Files
super6502/hw/super6502_fpga
Byron Lathi 61f6e53327 Updates based on fpga test
1. in SD mode, CMD0 does not have a response, so we specifically ignore
   it.

2. The penable signal was messed up, although it looks like this doesn't
   matter anyway

3. The SD clock should be out of phase from the data signal by 180
   degrees, so that we get max hold time
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