60 lines
1.6 KiB
Markdown
60 lines
1.6 KiB
Markdown
# PIC
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## Overview
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The PIC (Programmable Interrupt Controller) supports 256 edge or level
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triggered interrupts.
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Interrupts can only be rising edge or positive level trigger. Negative edge or
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low level trigger can be accomplished by inverting the input to this module.
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When an interrupt is triggered, it remains triggered until cleared with an
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`EOI`. Currently, only the highest priority interrupt can be cleared. This
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is bad design and will be fixed soon(tm).
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## Interface
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The PIC is controlled through two 8-bit registers, `CMD` and `DAT`.
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The upepr 3 bits of `CMD` control which register is accessed, and the lower 5
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bits control the byte select.
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`EOI` is a special case: when `CMD` is 0xFF, the highest priority interrupt is
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cleared.
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### CMD
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| [7:5] | [4:0] |
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|------------------ |------------- |
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| Register Address | Byte Select |
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### DAT
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| [7:0] |
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|----------------------- |
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| Data[8*Byte_sel +: 8] |
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## Registers
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### Register Map
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| Address | Read | Write |
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|--------- |------------ |-------- |
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| 0 | IRQ Number | ~ |
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| 1 | Enable | Enable |
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| 2 | Type | Type |
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### IRQ Number
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8 bit register outputs the highest priority interrupt currently active. When
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no interrupt is active, it will output 255.
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### Enable
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256 bit enable register. When bit _n_ is set to 1, the corresponding interrupt
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_n_.
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### Type
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256 bit type register. When bit _n_ is set to 0, the corresponding interrupt
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_n_ will be edge triggered. If the bit is set to 1, the interrupt will be level
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triggered. |