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edd13e9b71008ed36d7f1d4469bf896da0db6ce8
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Byron Lathi edd13e9b71 Remove debug information
2022-04-17 18:11:45 -05:00
hw
Reset bit count upon entering RXDATA
2022-04-14 11:20:48 -05:00
sw
Remove debug information
2022-04-17 18:11:45 -05:00
.gitlab-ci.yml
Update ci
2022-04-16 22:07:19 -05:00
Description
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5.5 MiB
Languages
SystemVerilog 47.7%
Verilog 41.8%
Python 4.8%
VHDL 2%
Assembly 2%
Other 1.6%