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eth: Update Alveo example design to use 32-bit MACs at 10G

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-11-05 23:42:03 -08:00
parent b97eb139ca
commit 0fe56c5390
45 changed files with 535 additions and 49 deletions
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15
src/eth/example/Alveo/fpga/rtl/fpga_au55.sv
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@@ -17,11 +17,19 @@ Authors:
*/
module fpga #
(
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter string VENDOR = "XILINX",
// device family
parameter string FAMILY = "virtexuplus",
// Board configuration
parameter QSFP_CNT = 2,
parameter UART_CNT = 3
parameter UART_CNT = 3,
// 10G/25G MAC configuration
parameter logic CFG_LOW_LATENCY = 1'b1,
parameter logic COMBINED_MAC_PCS = 1'b1,
parameter MAC_DATA_W = 64
)
(
/*
@@ -210,7 +218,10 @@ fpga_core #(
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
.GTY_CLK_CNT(GTY_CLK_CNT),
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
.MAC_DATA_W(MAC_DATA_W)
)
core_inst (
/*