axi: Add AXI lite register module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

rtl/axi/taxi_axil_register.f

@@ -0,0 +1,4 @@
+taxi_axil_register.sv
+taxi_axil_register_wr.sv
+taxi_axil_register_rd.sv
+taxi_axil_if.sv

rtl/axi/taxi_axil_register.sv

@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite register
+ */
+module taxi_axil_register #
+(
+    // AW channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter AW_REG_TYPE = 1,
+    // W channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter W_REG_TYPE = 1,
+    // B channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter B_REG_TYPE = 1,
+    // AR channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter AR_REG_TYPE = 1,
+    // R channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter R_REG_TYPE = 1
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-Lite slave interface
+     */
+    taxi_axil_if.wr_slv  s_axil_wr,
+    taxi_axil_if.rd_slv  s_axil_rd,
+
+    /*
+     * AXI4-Lite master interface
+     */
+    taxi_axil_if.wr_mst  m_axil_wr,
+    taxi_axil_if.rd_mst  m_axil_rd
+);
+
+taxi_axil_register_wr #(
+    .AW_REG_TYPE(AW_REG_TYPE),
+    .W_REG_TYPE(W_REG_TYPE),
+    .B_REG_TYPE(B_REG_TYPE)
+)
+axil_register_wr_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Lite slave interface
+     */
+    .s_axil_wr(s_axil_wr),
+
+    /*
+     * AXI4-Lite master interface
+     */
+    .m_axil_wr(m_axil_wr)
+);
+
+taxi_axil_register_rd #(
+    .AR_REG_TYPE(AR_REG_TYPE),
+    .R_REG_TYPE(R_REG_TYPE)
+)
+axil_register_rd_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Lite slave interface
+     */
+    .s_axil_rd(s_axil_rd),
+
+    /*
+     * AXI4-Lite master interface
+     */
+    .m_axil_rd(m_axil_rd)
+);
+
+endmodule
+
+`resetall

rtl/axi/taxi_axil_register_rd.sv

@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite register (read)
+ */
+module taxi_axil_register_rd #
+(
+    // AR channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter AR_REG_TYPE = 1,
+    // R channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter R_REG_TYPE = 1
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-Lite slave interface
+     */
+    taxi_axil_if.rd_slv  s_axil_rd,
+
+    /*
+     * AXI4-Lite master interface
+     */
+    taxi_axil_if.rd_mst  m_axil_rd
+);
+
+// extract parameters
+localparam DATA_W = s_axil_rd.DATA_W;
+localparam ADDR_W = s_axil_rd.ADDR_W;
+localparam STRB_W = s_axil_rd.STRB_W;
+localparam logic ARUSER_EN = s_axil_rd.ARUSER_EN && m_axil_rd.ARUSER_EN;
+localparam ARUSER_W = s_axil_rd.ARUSER_W;
+localparam logic RUSER_EN = s_axil_rd.RUSER_EN && m_axil_rd.RUSER_EN;
+localparam RUSER_W = s_axil_rd.RUSER_W;
+
+if (m_axil_rd.DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_rd.STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+// AR channel
+
+if (AR_REG_TYPE > 1) begin
+    // skid buffer, no bubble cycles
+
+    // datapath registers
+    logic                 s_axil_arready_reg = 1'b0;
+
+    logic [ADDR_W-1:0]    m_axil_araddr_reg   = '0;
+    logic [2:0]           m_axil_arprot_reg   = '0;
+    logic [ARUSER_W-1:0]  m_axil_aruser_reg   = '0;
+    logic                 m_axil_arvalid_reg  = 1'b0, m_axil_arvalid_next;
+
+    logic [ADDR_W-1:0]    temp_m_axil_araddr_reg   = '0;
+    logic [2:0]           temp_m_axil_arprot_reg   = '0;
+    logic [ARUSER_W-1:0]  temp_m_axil_aruser_reg   = '0;
+    logic                 temp_m_axil_arvalid_reg  = 1'b0, temp_m_axil_arvalid_next;
+
+    // datapath control
+    logic store_axil_ar_input_to_output;
+    logic store_axil_ar_input_to_temp;
+    logic store_axil_ar_temp_to_output;
+
+    assign s_axil_rd.arready  = s_axil_arready_reg;
+
+    assign m_axil_rd.araddr   = m_axil_araddr_reg;
+    assign m_axil_rd.arprot   = m_axil_arprot_reg;
+    assign m_axil_rd.aruser   = ARUSER_EN ? m_axil_aruser_reg : '0;
+    assign m_axil_rd.arvalid  = m_axil_arvalid_reg;
+
+    // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+    wire s_axil_arready_early = m_axil_rd.arready || (!temp_m_axil_arvalid_reg && (!m_axil_arvalid_reg || !s_axil_rd.arvalid));
+
+    always_comb begin
+        // transfer sink ready state to source
+        m_axil_arvalid_next = m_axil_arvalid_reg;
+        temp_m_axil_arvalid_next = temp_m_axil_arvalid_reg;
+
+        store_axil_ar_input_to_output = 1'b0;
+        store_axil_ar_input_to_temp = 1'b0;
+        store_axil_ar_temp_to_output = 1'b0;
+
+        if (s_axil_arready_reg) begin
+            // input is ready
+            if (m_axil_rd.arready || !m_axil_arvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                m_axil_arvalid_next = s_axil_rd.arvalid;
+                store_axil_ar_input_to_output = 1'b1;
+            end else begin
+                // output is not ready, store input in temp
+                temp_m_axil_arvalid_next = s_axil_rd.arvalid;
+                store_axil_ar_input_to_temp = 1'b1;
+            end
+        end else if (m_axil_rd.arready) begin
+            // input is not ready, but output is ready
+            m_axil_arvalid_next = temp_m_axil_arvalid_reg;
+            temp_m_axil_arvalid_next = 1'b0;
+            store_axil_ar_temp_to_output = 1'b1;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        s_axil_arready_reg <= s_axil_arready_early;
+        m_axil_arvalid_reg <= m_axil_arvalid_next;
+        temp_m_axil_arvalid_reg <= temp_m_axil_arvalid_next;
+
+        // datapath
+        if (store_axil_ar_input_to_output) begin
+            m_axil_araddr_reg <= s_axil_rd.araddr;
+            m_axil_arprot_reg <= s_axil_rd.arprot;
+            m_axil_aruser_reg <= s_axil_rd.aruser;
+        end else if (store_axil_ar_temp_to_output) begin
+            m_axil_araddr_reg <= temp_m_axil_araddr_reg;
+            m_axil_arprot_reg <= temp_m_axil_arprot_reg;
+            m_axil_aruser_reg <= temp_m_axil_aruser_reg;
+        end
+
+        if (store_axil_ar_input_to_temp) begin
+            temp_m_axil_araddr_reg <= s_axil_rd.araddr;
+            temp_m_axil_arprot_reg <= s_axil_rd.arprot;
+            temp_m_axil_aruser_reg <= s_axil_rd.aruser;
+        end
+
+        if (rst) begin
+            s_axil_arready_reg <= 1'b0;
+            m_axil_arvalid_reg <= 1'b0;
+            temp_m_axil_arvalid_reg <= 1'b0;
+        end
+    end
+
+end else if (AR_REG_TYPE == 1) begin
+    // simple register, inserts bubble cycles
+
+    // datapath registers
+    logic                 s_axil_arready_reg = 1'b0;
+
+    logic [ADDR_W-1:0]    m_axil_araddr_reg   = '0;
+    logic [2:0]           m_axil_arprot_reg   = '0;
+    logic [ARUSER_W-1:0]  m_axil_aruser_reg   = '0;
+    logic                 m_axil_arvalid_reg  = 1'b0, m_axil_arvalid_next;
+
+    // datapath control
+    logic store_axil_ar_input_to_output;
+
+    assign s_axil_rd.arready  = s_axil_arready_reg;
+
+    assign m_axil_rd.araddr   = m_axil_araddr_reg;
+    assign m_axil_rd.arprot   = m_axil_arprot_reg;
+    assign m_axil_rd.aruser   = ARUSER_EN ? m_axil_aruser_reg : '0;
+    assign m_axil_rd.arvalid  = m_axil_arvalid_reg;
+
+    // enable ready input next cycle if output buffer will be empty
+    wire s_axil_arready_early = !m_axil_arvalid_next;
+
+    always_comb begin
+        // transfer sink ready state to source
+        m_axil_arvalid_next = m_axil_arvalid_reg;
+
+        store_axil_ar_input_to_output = 1'b0;
+
+        if (s_axil_arready_reg) begin
+            m_axil_arvalid_next = s_axil_rd.arvalid;
+            store_axil_ar_input_to_output = 1'b1;
+        end else if (m_axil_rd.arready) begin
+            m_axil_arvalid_next = 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        s_axil_arready_reg <= s_axil_arready_early;
+        m_axil_arvalid_reg <= m_axil_arvalid_next;
+
+        // datapath
+        if (store_axil_ar_input_to_output) begin
+            m_axil_araddr_reg <= s_axil_rd.araddr;
+            m_axil_arprot_reg <= s_axil_rd.arprot;
+            m_axil_aruser_reg <= s_axil_rd.aruser;
+        end
+
+        if (rst) begin
+            s_axil_arready_reg <= 1'b0;
+            m_axil_arvalid_reg <= 1'b0;
+        end
+    end
+
+end else begin
+
+    // bypass AR channel
+    assign m_axil_rd.araddr = s_axil_rd.araddr;
+    assign m_axil_rd.arprot = s_axil_rd.arprot;
+    assign m_axil_rd.aruser = ARUSER_EN ? s_axil_rd.aruser : '0;
+    assign m_axil_rd.arvalid = s_axil_rd.arvalid;
+    assign s_axil_rd.arready = m_axil_rd.arready;
+
+end
+
+// R channel
+
+if (R_REG_TYPE > 1) begin
+    // skid buffer, no bubble cycles
+
+    // datapath registers
+    logic                m_axil_rready_reg = 1'b0;
+
+    logic [DATA_W-1:0]   s_axil_rdata_reg  = '0;
+    logic [1:0]          s_axil_rresp_reg  = 2'b0;
+    logic [RUSER_W-1:0]  s_axil_ruser_reg  = '0;
+    logic                s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
+
+    logic [DATA_W-1:0]   temp_s_axil_rdata_reg  = '0;
+    logic [1:0]          temp_s_axil_rresp_reg  = 2'b0;
+    logic [RUSER_W-1:0]  temp_s_axil_ruser_reg  = '0;
+    logic                temp_s_axil_rvalid_reg = 1'b0, temp_s_axil_rvalid_next;
+
+    // datapath control
+    logic store_axil_r_input_to_output;
+    logic store_axil_r_input_to_temp;
+    logic store_axil_r_temp_to_output;
+
+    assign m_axil_rd.rready = m_axil_rready_reg;
+
+    assign s_axil_rd.rdata  = s_axil_rdata_reg;
+    assign s_axil_rd.rresp  = s_axil_rresp_reg;
+    assign s_axil_rd.ruser  = RUSER_EN ? s_axil_ruser_reg : '0;
+    assign s_axil_rd.rvalid = s_axil_rvalid_reg;
+
+    // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+    wire m_axil_rready_early = s_axil_rd.rready || (!temp_s_axil_rvalid_reg && (!s_axil_rvalid_reg || !m_axil_rd.rvalid));
+
+    always_comb begin
+        // transfer sink ready state to source
+        s_axil_rvalid_next = s_axil_rvalid_reg;
+        temp_s_axil_rvalid_next = temp_s_axil_rvalid_reg;
+
+        store_axil_r_input_to_output = 1'b0;
+        store_axil_r_input_to_temp = 1'b0;
+        store_axil_r_temp_to_output = 1'b0;
+
+        if (m_axil_rready_reg) begin
+            // input is ready
+            if (s_axil_rd.rready || !s_axil_rvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                s_axil_rvalid_next = m_axil_rd.rvalid;
+                store_axil_r_input_to_output = 1'b1;
+            end else begin
+                // output is not ready, store input in temp
+                temp_s_axil_rvalid_next = m_axil_rd.rvalid;
+                store_axil_r_input_to_temp = 1'b1;
+            end
+        end else if (s_axil_rd.rready) begin
+            // input is not ready, but output is ready
+            s_axil_rvalid_next = temp_s_axil_rvalid_reg;
+            temp_s_axil_rvalid_next = 1'b0;
+            store_axil_r_temp_to_output = 1'b1;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        m_axil_rready_reg <= m_axil_rready_early;
+        s_axil_rvalid_reg <= s_axil_rvalid_next;
+        temp_s_axil_rvalid_reg <= temp_s_axil_rvalid_next;
+
+        // datapath
+        if (store_axil_r_input_to_output) begin
+            s_axil_rdata_reg <= m_axil_rd.rdata;
+            s_axil_rresp_reg <= m_axil_rd.rresp;
+            s_axil_ruser_reg <= m_axil_rd.ruser;
+        end else if (store_axil_r_temp_to_output) begin
+            s_axil_rdata_reg <= temp_s_axil_rdata_reg;
+            s_axil_rresp_reg <= temp_s_axil_rresp_reg;
+            s_axil_ruser_reg <= temp_s_axil_ruser_reg;
+        end
+
+        if (store_axil_r_input_to_temp) begin
+            temp_s_axil_rdata_reg <= m_axil_rd.rdata;
+            temp_s_axil_rresp_reg <= m_axil_rd.rresp;
+            temp_s_axil_ruser_reg <= m_axil_rd.ruser;
+        end
+
+        if (rst) begin
+            m_axil_rready_reg <= 1'b0;
+            s_axil_rvalid_reg <= 1'b0;
+            temp_s_axil_rvalid_reg <= 1'b0;
+        end
+    end
+
+end else if (R_REG_TYPE == 1) begin
+    // simple register, inserts bubble cycles
+
+    // datapath registers
+    logic                m_axil_rready_reg = 1'b0;
+
+    logic [DATA_W-1:0]   s_axil_rdata_reg  = '0;
+    logic [1:0]          s_axil_rresp_reg  = 2'b0;
+    logic [RUSER_W-1:0]  s_axil_ruser_reg  = '0;
+    logic                s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
+
+    // datapath control
+    logic store_axil_r_input_to_output;
+
+    assign m_axil_rd.rready = m_axil_rready_reg;
+
+    assign s_axil_rd.rdata  = s_axil_rdata_reg;
+    assign s_axil_rd.rresp  = s_axil_rresp_reg;
+    assign s_axil_rd.ruser  = RUSER_EN ? s_axil_ruser_reg : '0;
+    assign s_axil_rd.rvalid = s_axil_rvalid_reg;
+
+    // enable ready input next cycle if output buffer will be empty
+    wire m_axil_rready_early = !s_axil_rvalid_next;
+
+    always_comb begin
+        // transfer sink ready state to source
+        s_axil_rvalid_next = s_axil_rvalid_reg;
+
+        store_axil_r_input_to_output = 1'b0;
+
+        if (m_axil_rready_reg) begin
+            s_axil_rvalid_next = m_axil_rd.rvalid;
+            store_axil_r_input_to_output = 1'b1;
+        end else if (s_axil_rd.rready) begin
+            s_axil_rvalid_next = 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        m_axil_rready_reg <= m_axil_rready_early;
+        s_axil_rvalid_reg <= s_axil_rvalid_next;
+
+        // datapath
+        if (store_axil_r_input_to_output) begin
+            s_axil_rdata_reg <= m_axil_rd.rdata;
+            s_axil_rresp_reg <= m_axil_rd.rresp;
+            s_axil_ruser_reg <= m_axil_rd.ruser;
+        end
+
+        if (rst) begin
+            m_axil_rready_reg <= 1'b0;
+            s_axil_rvalid_reg <= 1'b0;
+        end
+    end
+
+end else begin
+
+    // bypass R channel
+    assign s_axil_rd.rdata = m_axil_rd.rdata;
+    assign s_axil_rd.rresp = m_axil_rd.rresp;
+    assign s_axil_rd.ruser = RUSER_EN ? m_axil_rd.ruser : '0;
+    assign s_axil_rd.rvalid = m_axil_rd.rvalid;
+    assign m_axil_rd.rready = s_axil_rd.rready;
+
+end
+
+endmodule
+
+`resetall

rtl/axi/taxi_axil_register_wr.sv

@@ -0,0 +1,522 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2018-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite register (write)
+ */
+module taxi_axil_register_wr #
+(
+    // AW channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter AW_REG_TYPE = 1,
+    // W channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter W_REG_TYPE = 1,
+    // B channel register type
+    // 0 to bypass, 1 for simple buffer
+    parameter B_REG_TYPE = 1
+)
+(
+    input  wire logic    clk,
+    input  wire logic    rst,
+
+    /*
+     * AXI4-Lite slave interface
+     */
+    taxi_axil_if.wr_slv  s_axil_wr,
+
+    /*
+     * AXI4-Lite master interface
+     */
+    taxi_axil_if.wr_mst  m_axil_wr
+);
+
+// extract parameters
+localparam DATA_W = s_axil_wr.DATA_W;
+localparam ADDR_W = s_axil_wr.ADDR_W;
+localparam STRB_W = s_axil_wr.STRB_W;
+localparam logic AWUSER_EN = s_axil_wr.AWUSER_EN && m_axil_wr.AWUSER_EN;
+localparam AWUSER_W = s_axil_wr.AWUSER_W;
+localparam logic WUSER_EN = s_axil_wr.WUSER_EN && m_axil_wr.WUSER_EN;
+localparam WUSER_W = s_axil_wr.WUSER_W;
+localparam logic BUSER_EN = s_axil_wr.BUSER_EN && m_axil_wr.BUSER_EN;
+localparam BUSER_W = s_axil_wr.BUSER_W;
+
+if (m_axil_wr.DATA_W != DATA_W)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+if (m_axil_wr.STRB_W != STRB_W)
+    $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
+
+// AW channel
+
+if (AW_REG_TYPE > 1) begin
+    // skid buffer, no bubble cycles
+
+    // datapath registers
+    logic                 s_axil_awready_reg = 1'b0;
+
+    logic [ADDR_W-1:0]    m_axil_awaddr_reg   = '0;
+    logic [2:0]           m_axil_awprot_reg   = '0;
+    logic [AWUSER_W-1:0]  m_axil_awuser_reg   = '0;
+    logic                 m_axil_awvalid_reg  = 1'b0, m_axil_awvalid_next;
+
+    logic [ADDR_W-1:0]    temp_m_axil_awaddr_reg   = '0;
+    logic [2:0]           temp_m_axil_awprot_reg   = '0;
+    logic [AWUSER_W-1:0]  temp_m_axil_awuser_reg   = '0;
+    logic                 temp_m_axil_awvalid_reg  = 1'b0, temp_m_axil_awvalid_next;
+
+    // datapath control
+    logic store_axil_aw_input_to_output;
+    logic store_axil_aw_input_to_temp;
+    logic store_axil_aw_temp_to_output;
+
+    assign s_axil_wr.awready  = s_axil_awready_reg;
+
+    assign m_axil_wr.awaddr   = m_axil_awaddr_reg;
+    assign m_axil_wr.awprot   = m_axil_awprot_reg;
+    assign m_axil_wr.awuser   = AWUSER_EN ? m_axil_awuser_reg : '0;
+    assign m_axil_wr.awvalid  = m_axil_awvalid_reg;
+
+    // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+    wire s_axil_awready_early = m_axil_wr.awready || (!temp_m_axil_awvalid_reg && (!m_axil_awvalid_reg || !s_axil_wr.awvalid));
+
+    always_comb begin
+        // transfer sink ready state to source
+        m_axil_awvalid_next = m_axil_awvalid_reg;
+        temp_m_axil_awvalid_next = temp_m_axil_awvalid_reg;
+
+        store_axil_aw_input_to_output = 1'b0;
+        store_axil_aw_input_to_temp = 1'b0;
+        store_axil_aw_temp_to_output = 1'b0;
+
+        if (s_axil_awready_reg) begin
+            // input is ready
+            if (m_axil_wr.awready || !m_axil_awvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                m_axil_awvalid_next = s_axil_wr.awvalid;
+                store_axil_aw_input_to_output = 1'b1;
+            end else begin
+                // output is not ready, store input in temp
+                temp_m_axil_awvalid_next = s_axil_wr.awvalid;
+                store_axil_aw_input_to_temp = 1'b1;
+            end
+        end else if (m_axil_wr.awready) begin
+            // input is not ready, but output is ready
+            m_axil_awvalid_next = temp_m_axil_awvalid_reg;
+            temp_m_axil_awvalid_next = 1'b0;
+            store_axil_aw_temp_to_output = 1'b1;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        s_axil_awready_reg <= s_axil_awready_early;
+        m_axil_awvalid_reg <= m_axil_awvalid_next;
+        temp_m_axil_awvalid_reg <= temp_m_axil_awvalid_next;
+
+        // datapath
+        if (store_axil_aw_input_to_output) begin
+            m_axil_awaddr_reg <= s_axil_wr.awaddr;
+            m_axil_awprot_reg <= s_axil_wr.awprot;
+            m_axil_awuser_reg <= s_axil_wr.awuser;
+        end else if (store_axil_aw_temp_to_output) begin
+            m_axil_awaddr_reg <= temp_m_axil_awaddr_reg;
+            m_axil_awprot_reg <= temp_m_axil_awprot_reg;
+            m_axil_awuser_reg <= temp_m_axil_awuser_reg;
+        end
+
+        if (store_axil_aw_input_to_temp) begin
+            temp_m_axil_awaddr_reg <= s_axil_wr.awaddr;
+            temp_m_axil_awprot_reg <= s_axil_wr.awprot;
+            temp_m_axil_awuser_reg <= s_axil_wr.awuser;
+        end
+
+        if (rst) begin
+            s_axil_awready_reg <= 1'b0;
+            m_axil_awvalid_reg <= 1'b0;
+            temp_m_axil_awvalid_reg <= 1'b0;
+        end
+    end
+
+end else if (AW_REG_TYPE == 1) begin
+    // simple register, inserts bubble cycles
+
+    // datapath registers
+    logic                 s_axil_awready_reg = 1'b0;
+
+    logic [ADDR_W-1:0]    m_axil_awaddr_reg   = '0;
+    logic [2:0]           m_axil_awprot_reg   = '0;
+    logic [AWUSER_W-1:0]  m_axil_awuser_reg   = '0;
+    logic                 m_axil_awvalid_reg  = 1'b0, m_axil_awvalid_next;
+
+    // datapath control
+    logic store_axil_aw_input_to_output;
+
+    assign s_axil_wr.awready  = s_axil_awready_reg;
+
+    assign m_axil_wr.awaddr   = m_axil_awaddr_reg;
+    assign m_axil_wr.awprot   = m_axil_awprot_reg;
+    assign m_axil_wr.awuser   = AWUSER_EN ? m_axil_awuser_reg : '0;
+    assign m_axil_wr.awvalid  = m_axil_awvalid_reg;
+
+    // enable ready input next cycle if output buffer will be empty
+    wire s_axil_awready_early = !m_axil_awvalid_next;
+
+    always_comb begin
+        // transfer sink ready state to source
+        m_axil_awvalid_next = m_axil_awvalid_reg;
+
+        store_axil_aw_input_to_output = 1'b0;
+
+        if (s_axil_awready_reg) begin
+            m_axil_awvalid_next = s_axil_wr.awvalid;
+            store_axil_aw_input_to_output = 1'b1;
+        end else if (m_axil_wr.awready) begin
+            m_axil_awvalid_next = 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        s_axil_awready_reg <= s_axil_awready_early;
+        m_axil_awvalid_reg <= m_axil_awvalid_next;
+
+        // datapath
+        if (store_axil_aw_input_to_output) begin
+            m_axil_awaddr_reg <= s_axil_wr.awaddr;
+            m_axil_awprot_reg <= s_axil_wr.awprot;
+            m_axil_awuser_reg <= s_axil_wr.awuser;
+        end
+
+        if (rst) begin
+            s_axil_awready_reg <= 1'b0;
+            m_axil_awvalid_reg <= 1'b0;
+        end
+    end
+
+end else begin
+
+    // bypass AW channel
+    assign m_axil_wr.awaddr = s_axil_wr.awaddr;
+    assign m_axil_wr.awprot = s_axil_wr.awprot;
+    assign m_axil_wr.awuser = AWUSER_EN ? s_axil_wr.awuser : '0;
+    assign m_axil_wr.awvalid = s_axil_wr.awvalid;
+    assign s_axil_wr.awready = m_axil_wr.awready;
+
+end
+
+// W channel
+
+if (W_REG_TYPE > 1) begin
+    // skid buffer, no bubble cycles
+
+    // datapath registers
+    logic                s_axil_wready_reg = 1'b0;
+
+    logic [DATA_W-1:0]   m_axil_wdata_reg  = '0;
+    logic [STRB_W-1:0]   m_axil_wstrb_reg  = '0;
+    logic [WUSER_W-1:0]  m_axil_wuser_reg  = '0;
+    logic                m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
+
+    logic [DATA_W-1:0]   temp_m_axil_wdata_reg  = '0;
+    logic [STRB_W-1:0]   temp_m_axil_wstrb_reg  = '0;
+    logic [WUSER_W-1:0]  temp_m_axil_wuser_reg  = '0;
+    logic                temp_m_axil_wvalid_reg = 1'b0, temp_m_axil_wvalid_next;
+
+    // datapath control
+    logic store_axil_w_input_to_output;
+    logic store_axil_w_input_to_temp;
+    logic store_axil_w_temp_to_output;
+
+    assign s_axil_wr.wready = s_axil_wready_reg;
+
+    assign m_axil_wr.wdata  = m_axil_wdata_reg;
+    assign m_axil_wr.wstrb  = m_axil_wstrb_reg;
+    assign m_axil_wr.wuser  = WUSER_EN ? m_axil_wuser_reg : '0;
+    assign m_axil_wr.wvalid = m_axil_wvalid_reg;
+
+    // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+    wire s_axil_wready_early = m_axil_wr.wready || (!temp_m_axil_wvalid_reg && (!m_axil_wvalid_reg || !s_axil_wr.wvalid));
+
+    always_comb begin
+        // transfer sink ready state to source
+        m_axil_wvalid_next = m_axil_wvalid_reg;
+        temp_m_axil_wvalid_next = temp_m_axil_wvalid_reg;
+
+        store_axil_w_input_to_output = 1'b0;
+        store_axil_w_input_to_temp = 1'b0;
+        store_axil_w_temp_to_output = 1'b0;
+
+        if (s_axil_wready_reg) begin
+            // input is ready
+            if (m_axil_wr.wready || !m_axil_wvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                m_axil_wvalid_next = s_axil_wr.wvalid;
+                store_axil_w_input_to_output = 1'b1;
+            end else begin
+                // output is not ready, store input in temp
+                temp_m_axil_wvalid_next = s_axil_wr.wvalid;
+                store_axil_w_input_to_temp = 1'b1;
+            end
+        end else if (m_axil_wr.wready) begin
+            // input is not ready, but output is ready
+            m_axil_wvalid_next = temp_m_axil_wvalid_reg;
+            temp_m_axil_wvalid_next = 1'b0;
+            store_axil_w_temp_to_output = 1'b1;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        s_axil_wready_reg <= s_axil_wready_early;
+        m_axil_wvalid_reg <= m_axil_wvalid_next;
+        temp_m_axil_wvalid_reg <= temp_m_axil_wvalid_next;
+
+        // datapath
+        if (store_axil_w_input_to_output) begin
+            m_axil_wdata_reg <= s_axil_wr.wdata;
+            m_axil_wstrb_reg <= s_axil_wr.wstrb;
+            m_axil_wuser_reg <= s_axil_wr.wuser;
+        end else if (store_axil_w_temp_to_output) begin
+            m_axil_wdata_reg <= temp_m_axil_wdata_reg;
+            m_axil_wstrb_reg <= temp_m_axil_wstrb_reg;
+            m_axil_wuser_reg <= temp_m_axil_wuser_reg;
+        end
+
+        if (store_axil_w_input_to_temp) begin
+            temp_m_axil_wdata_reg <= s_axil_wr.wdata;
+            temp_m_axil_wstrb_reg <= s_axil_wr.wstrb;
+            temp_m_axil_wuser_reg <= s_axil_wr.wuser;
+        end
+
+        if (rst) begin
+            s_axil_wready_reg <= 1'b0;
+            m_axil_wvalid_reg <= 1'b0;
+            temp_m_axil_wvalid_reg <= 1'b0;
+        end
+    end
+
+end else if (W_REG_TYPE == 1) begin
+    // simple register, inserts bubble cycles
+
+    // datapath registers
+    logic                s_axil_wready_reg = 1'b0;
+
+    logic [DATA_W-1:0]   m_axil_wdata_reg  = '0;
+    logic [STRB_W-1:0]   m_axil_wstrb_reg  = '0;
+    logic [WUSER_W-1:0]  m_axil_wuser_reg  = '0;
+    logic                m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
+
+    // datapath control
+    logic store_axil_w_input_to_output;
+
+    assign s_axil_wr.wready = s_axil_wready_reg;
+
+    assign m_axil_wr.wdata  = m_axil_wdata_reg;
+    assign m_axil_wr.wstrb  = m_axil_wstrb_reg;
+    assign m_axil_wr.wuser  = WUSER_EN ? m_axil_wuser_reg : '0;
+    assign m_axil_wr.wvalid = m_axil_wvalid_reg;
+
+    // enable ready input next cycle if output buffer will be empty
+    wire s_axil_wready_early = !m_axil_wvalid_next;
+
+    always_comb begin
+        // transfer sink ready state to source
+        m_axil_wvalid_next = m_axil_wvalid_reg;
+
+        store_axil_w_input_to_output = 1'b0;
+
+        if (s_axil_wready_reg) begin
+            m_axil_wvalid_next = s_axil_wr.wvalid;
+            store_axil_w_input_to_output = 1'b1;
+        end else if (m_axil_wr.wready) begin
+            m_axil_wvalid_next = 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        s_axil_wready_reg <= s_axil_wready_early;
+        m_axil_wvalid_reg <= m_axil_wvalid_next;
+
+        // datapath
+        if (store_axil_w_input_to_output) begin
+            m_axil_wdata_reg <= s_axil_wr.wdata;
+            m_axil_wstrb_reg <= s_axil_wr.wstrb;
+            m_axil_wuser_reg <= s_axil_wr.wuser;
+        end
+
+        if (rst) begin
+            s_axil_wready_reg <= 1'b0;
+            m_axil_wvalid_reg <= 1'b0;
+        end
+    end
+
+end else begin
+
+    // bypass W channel
+    assign m_axil_wr.wdata = s_axil_wr.wdata;
+    assign m_axil_wr.wstrb = s_axil_wr.wstrb;
+    assign m_axil_wr.wuser = WUSER_EN ? s_axil_wr.wuser : '0;
+    assign m_axil_wr.wvalid = s_axil_wr.wvalid;
+    assign s_axil_wr.wready = m_axil_wr.wready;
+
+end
+
+// B channel
+
+if (B_REG_TYPE > 1) begin
+    // skid buffer, no bubble cycles
+
+    // datapath registers
+    logic                m_axil_bready_reg = 1'b0;
+
+    logic [1:0]          s_axil_bresp_reg  = 2'b0;
+    logic [BUSER_W-1:0]  s_axil_buser_reg  = '0;
+    logic                s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
+
+    logic [1:0]          temp_s_axil_bresp_reg  = 2'b0;
+    logic [BUSER_W-1:0]  temp_s_axil_buser_reg  = '0;
+    logic                temp_s_axil_bvalid_reg = 1'b0, temp_s_axil_bvalid_next;
+
+    // datapath control
+    logic store_axil_b_input_to_output;
+    logic store_axil_b_input_to_temp;
+    logic store_axil_b_temp_to_output;
+
+    assign m_axil_wr.bready = m_axil_bready_reg;
+
+    assign s_axil_wr.bresp  = s_axil_bresp_reg;
+    assign s_axil_wr.buser  = BUSER_EN ? s_axil_buser_reg : '0;
+    assign s_axil_wr.bvalid = s_axil_bvalid_reg;
+
+    // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+    wire m_axil_bready_early = s_axil_wr.bready || (!temp_s_axil_bvalid_reg && (!s_axil_bvalid_reg || !m_axil_wr.bvalid));
+
+    always_comb begin
+        // transfer sink ready state to source
+        s_axil_bvalid_next = s_axil_bvalid_reg;
+        temp_s_axil_bvalid_next = temp_s_axil_bvalid_reg;
+
+        store_axil_b_input_to_output = 1'b0;
+        store_axil_b_input_to_temp = 1'b0;
+        store_axil_b_temp_to_output = 1'b0;
+
+        if (m_axil_bready_reg) begin
+            // input is ready
+            if (s_axil_wr.bready || !s_axil_bvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                s_axil_bvalid_next = m_axil_wr.bvalid;
+                store_axil_b_input_to_output = 1'b1;
+            end else begin
+                // output is not ready, store input in temp
+                temp_s_axil_bvalid_next = m_axil_wr.bvalid;
+                store_axil_b_input_to_temp = 1'b1;
+            end
+        end else if (s_axil_wr.bready) begin
+            // input is not ready, but output is ready
+            s_axil_bvalid_next = temp_s_axil_bvalid_reg;
+            temp_s_axil_bvalid_next = 1'b0;
+            store_axil_b_temp_to_output = 1'b1;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        m_axil_bready_reg <= m_axil_bready_early;
+        s_axil_bvalid_reg <= s_axil_bvalid_next;
+        temp_s_axil_bvalid_reg <= temp_s_axil_bvalid_next;
+
+        // datapath
+        if (store_axil_b_input_to_output) begin
+            s_axil_bresp_reg <= m_axil_wr.bresp;
+            s_axil_buser_reg <= m_axil_wr.buser;
+        end else if (store_axil_b_temp_to_output) begin
+            s_axil_bresp_reg <= temp_s_axil_bresp_reg;
+            s_axil_buser_reg <= temp_s_axil_buser_reg;
+        end
+
+        if (store_axil_b_input_to_temp) begin
+            temp_s_axil_bresp_reg <= m_axil_wr.bresp;
+            temp_s_axil_buser_reg <= m_axil_wr.buser;
+        end
+
+        if (rst) begin
+            m_axil_bready_reg <= 1'b0;
+            s_axil_bvalid_reg <= 1'b0;
+            temp_s_axil_bvalid_reg <= 1'b0;
+        end
+    end
+
+end else if (B_REG_TYPE == 1) begin
+    // simple register, inserts bubble cycles
+
+    // datapath registers
+    logic                m_axil_bready_reg = 1'b0;
+
+    logic [1:0]          s_axil_bresp_reg  = 2'b0;
+    logic [BUSER_W-1:0]  s_axil_buser_reg  = '0;
+    logic                s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
+
+    // datapath control
+    logic store_axil_b_input_to_output;
+
+    assign m_axil_wr.bready = m_axil_bready_reg;
+
+    assign s_axil_wr.bresp  = s_axil_bresp_reg;
+    assign s_axil_wr.buser  = BUSER_EN ? s_axil_buser_reg : '0;
+    assign s_axil_wr.bvalid = s_axil_bvalid_reg;
+
+    // enable ready input next cycle if output buffer will be empty
+    wire m_axil_bready_early = !s_axil_bvalid_next;
+
+    always_comb begin
+        // transfer sink ready state to source
+        s_axil_bvalid_next = s_axil_bvalid_reg;
+
+        store_axil_b_input_to_output = 1'b0;
+
+        if (m_axil_bready_reg) begin
+            s_axil_bvalid_next = m_axil_wr.bvalid;
+            store_axil_b_input_to_output = 1'b1;
+        end else if (s_axil_wr.bready) begin
+            s_axil_bvalid_next = 1'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        m_axil_bready_reg <= m_axil_bready_early;
+        s_axil_bvalid_reg <= s_axil_bvalid_next;
+
+        // datapath
+        if (store_axil_b_input_to_output) begin
+            s_axil_bresp_reg <= m_axil_wr.bresp;
+            s_axil_buser_reg <= m_axil_wr.buser;
+        end
+
+        if (rst) begin
+            m_axil_bready_reg <= 1'b0;
+            s_axil_bvalid_reg <= 1'b0;
+        end
+    end
+
+end else begin
+
+    // bypass B channel
+    assign s_axil_wr.bresp = m_axil_wr.bresp;
+    assign s_axil_wr.buser = BUSER_EN ? m_axil_wr.buser : '0;
+    assign s_axil_wr.bvalid = m_axil_wr.bvalid;
+    assign m_axil_wr.bready = s_axil_wr.bready;
+
+end
+
+endmodule
+
+`resetall

tb/axi/taxi_axil_register/Makefile

@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = taxi_axil_register
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/axi/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+REG_TYPE ?= 1
+
+# module parameters
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 32
+export PARAM_AWUSER_EN := 0
+export PARAM_AWUSER_W := 1
+export PARAM_WUSER_EN := 0
+export PARAM_WUSER_W := 1
+export PARAM_BUSER_EN := 0
+export PARAM_BUSER_W := 1
+export PARAM_ARUSER_EN := 0
+export PARAM_ARUSER_W := 1
+export PARAM_RUSER_EN := 0
+export PARAM_RUSER_W := 1
+export PARAM_AW_REG_TYPE := $(REG_TYPE)
+export PARAM_W_REG_TYPE := $(REG_TYPE)
+export PARAM_B_REG_TYPE := $(REG_TYPE)
+export PARAM_AR_REG_TYPE := $(REG_TYPE)
+export PARAM_R_REG_TYPE := $(REG_TYPE)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/axi/taxi_axil_register/test_taxi_axil_register.py

@@ -0,0 +1,243 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst)
+        self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.axil_master.write_if.aw_channel.set_pause_generator(generator())
+            self.axil_master.write_if.w_channel.set_pause_generator(generator())
+            self.axil_master.read_if.ar_channel.set_pause_generator(generator())
+            self.axil_ram.write_if.b_channel.set_pause_generator(generator())
+            self.axil_ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.axil_master.write_if.b_channel.set_pause_generator(generator())
+            self.axil_master.read_if.r_channel.set_pause_generator(generator())
+            self.axil_ram.write_if.aw_channel.set_pause_generator(generator())
+            self.axil_ram.write_if.w_channel.set_pause_generator(generator())
+            self.axil_ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master.write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram.write(addr-128, b'\xaa'*(length+256))
+
+            await tb.axil_master.write(addr, test_data)
+
+            tb.log.debug("%s", tb.axil_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axil_ram.read(addr, length) == test_data
+            assert tb.axil_ram.read(addr-1, 1) == b'\xaa'
+            assert tb.axil_ram.read(addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_master.write_if.byte_lanes
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*2):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram.write(addr, test_data)
+
+            data = await tb.axil_master.read(addr, length)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            length = random.randint(1, min(32, aperture))
+            addr = offset+random.randint(0, aperture-length)
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0)
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_write, run_test_read, run_stress_test]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("reg_type", [0, 1, 2])
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+def test_taxi_axil_register(request, data_w, reg_type):
+    dut = "taxi_axil_register"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "axi", f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 32
+    parameters['AWUSER_EN'] = 0
+    parameters['AWUSER_W'] = 1
+    parameters['WUSER_EN'] = 0
+    parameters['WUSER_W'] = 1
+    parameters['BUSER_EN'] = 0
+    parameters['BUSER_W'] = 1
+    parameters['ARUSER_EN'] = 0
+    parameters['ARUSER_W'] = 1
+    parameters['RUSER_EN'] = 0
+    parameters['RUSER_W'] = 1
+    parameters['AW_REG_TYPE'] = reg_type
+    parameters['W_REG_TYPE'] = reg_type
+    parameters['B_REG_TYPE'] = reg_type
+    parameters['AR_REG_TYPE'] = reg_type
+    parameters['R_REG_TYPE'] = reg_type
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/axi/taxi_axil_register/test_taxi_axil_register.sv

@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 lite register testbench
+ */
+module test_taxi_axil_register #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 32,
+    parameter ADDR_W = 32,
+    parameter logic AWUSER_EN = 1'b0,
+    parameter AWUSER_W = 1,
+    parameter logic WUSER_EN = 1'b0,
+    parameter WUSER_W = 1,
+    parameter logic BUSER_EN = 1'b0,
+    parameter BUSER_W = 1,
+    parameter logic ARUSER_EN = 1'b0,
+    parameter ARUSER_W = 1,
+    parameter logic RUSER_EN = 1'b0,
+    parameter RUSER_W = 1,
+    parameter AW_REG_TYPE = 1,
+    parameter W_REG_TYPE = 1,
+    parameter B_REG_TYPE = 1,
+    parameter AR_REG_TYPE = 1,
+    parameter R_REG_TYPE = 1
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axil_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W),
+    .AWUSER_EN(AWUSER_EN),
+    .AWUSER_W(AWUSER_W),
+    .WUSER_EN(WUSER_EN),
+    .WUSER_W(WUSER_W),
+    .BUSER_EN(BUSER_EN),
+    .BUSER_W(BUSER_W),
+    .ARUSER_EN(ARUSER_EN),
+    .ARUSER_W(ARUSER_W),
+    .RUSER_EN(RUSER_EN),
+    .RUSER_W(RUSER_W)
+) s_axil(), m_axil();
+
+taxi_axil_register #(
+    .AW_REG_TYPE(AW_REG_TYPE),
+    .W_REG_TYPE(W_REG_TYPE),
+    .B_REG_TYPE(B_REG_TYPE),
+    .AR_REG_TYPE(AR_REG_TYPE),
+    .R_REG_TYPE(R_REG_TYPE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Lite slave interface
+     */
+    .s_axil_wr(s_axil),
+    .s_axil_rd(s_axil),
+
+    /*
+     * AXI4-Lite master interface
+     */
+    .m_axil_wr(m_axil),
+    .m_axil_rd(m_axil)
+);
+
+endmodule
+
+`resetall