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axi: Add AXI lite register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
4
rtl/axi/taxi_axil_register.f
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4
rtl/axi/taxi_axil_register.f
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@@ -0,0 +1,4 @@
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taxi_axil_register.sv
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taxi_axil_register_wr.sv
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taxi_axil_register_rd.sv
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taxi_axil_if.sv
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94
rtl/axi/taxi_axil_register.sv
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94
rtl/axi/taxi_axil_register.sv
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@@ -0,0 +1,94 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite register
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*/
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module taxi_axil_register #
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(
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// AW channel register type
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// 0 to bypass, 1 for simple buffer
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parameter AW_REG_TYPE = 1,
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// W channel register type
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// 0 to bypass, 1 for simple buffer
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parameter W_REG_TYPE = 1,
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// B channel register type
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// 0 to bypass, 1 for simple buffer
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parameter B_REG_TYPE = 1,
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// AR channel register type
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// 0 to bypass, 1 for simple buffer
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parameter AR_REG_TYPE = 1,
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// R channel register type
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// 0 to bypass, 1 for simple buffer
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parameter R_REG_TYPE = 1
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Lite slave interface
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*/
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taxi_axil_if.wr_slv s_axil_wr,
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taxi_axil_if.rd_slv s_axil_rd,
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/*
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* AXI4-Lite master interface
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*/
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taxi_axil_if.wr_mst m_axil_wr,
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taxi_axil_if.rd_mst m_axil_rd
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);
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taxi_axil_register_wr #(
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.AW_REG_TYPE(AW_REG_TYPE),
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.W_REG_TYPE(W_REG_TYPE),
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.B_REG_TYPE(B_REG_TYPE)
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)
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axil_register_wr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Lite slave interface
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*/
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.s_axil_wr(s_axil_wr),
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/*
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* AXI4-Lite master interface
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*/
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.m_axil_wr(m_axil_wr)
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);
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taxi_axil_register_rd #(
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.AR_REG_TYPE(AR_REG_TYPE),
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.R_REG_TYPE(R_REG_TYPE)
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)
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axil_register_rd_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Lite slave interface
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*/
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.s_axil_rd(s_axil_rd),
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/*
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* AXI4-Lite master interface
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*/
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.m_axil_rd(m_axil_rd)
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);
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endmodule
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`resetall
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371
rtl/axi/taxi_axil_register_rd.sv
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371
rtl/axi/taxi_axil_register_rd.sv
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@@ -0,0 +1,371 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite register (read)
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*/
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module taxi_axil_register_rd #
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(
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// AR channel register type
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// 0 to bypass, 1 for simple buffer
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parameter AR_REG_TYPE = 1,
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// R channel register type
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// 0 to bypass, 1 for simple buffer
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parameter R_REG_TYPE = 1
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Lite slave interface
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*/
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taxi_axil_if.rd_slv s_axil_rd,
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/*
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* AXI4-Lite master interface
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*/
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taxi_axil_if.rd_mst m_axil_rd
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);
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// extract parameters
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localparam DATA_W = s_axil_rd.DATA_W;
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localparam ADDR_W = s_axil_rd.ADDR_W;
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localparam STRB_W = s_axil_rd.STRB_W;
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localparam logic ARUSER_EN = s_axil_rd.ARUSER_EN && m_axil_rd.ARUSER_EN;
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localparam ARUSER_W = s_axil_rd.ARUSER_W;
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localparam logic RUSER_EN = s_axil_rd.RUSER_EN && m_axil_rd.RUSER_EN;
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localparam RUSER_W = s_axil_rd.RUSER_W;
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if (m_axil_rd.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (m_axil_rd.STRB_W != STRB_W)
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$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
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// AR channel
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if (AR_REG_TYPE > 1) begin
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// skid buffer, no bubble cycles
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// datapath registers
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logic s_axil_arready_reg = 1'b0;
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logic [ADDR_W-1:0] m_axil_araddr_reg = '0;
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logic [2:0] m_axil_arprot_reg = '0;
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logic [ARUSER_W-1:0] m_axil_aruser_reg = '0;
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logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
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logic [ADDR_W-1:0] temp_m_axil_araddr_reg = '0;
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logic [2:0] temp_m_axil_arprot_reg = '0;
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logic [ARUSER_W-1:0] temp_m_axil_aruser_reg = '0;
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logic temp_m_axil_arvalid_reg = 1'b0, temp_m_axil_arvalid_next;
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// datapath control
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logic store_axil_ar_input_to_output;
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logic store_axil_ar_input_to_temp;
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logic store_axil_ar_temp_to_output;
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assign s_axil_rd.arready = s_axil_arready_reg;
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assign m_axil_rd.araddr = m_axil_araddr_reg;
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assign m_axil_rd.arprot = m_axil_arprot_reg;
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assign m_axil_rd.aruser = ARUSER_EN ? m_axil_aruser_reg : '0;
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assign m_axil_rd.arvalid = m_axil_arvalid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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wire s_axil_arready_early = m_axil_rd.arready || (!temp_m_axil_arvalid_reg && (!m_axil_arvalid_reg || !s_axil_rd.arvalid));
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always_comb begin
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// transfer sink ready state to source
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m_axil_arvalid_next = m_axil_arvalid_reg;
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temp_m_axil_arvalid_next = temp_m_axil_arvalid_reg;
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store_axil_ar_input_to_output = 1'b0;
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store_axil_ar_input_to_temp = 1'b0;
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store_axil_ar_temp_to_output = 1'b0;
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if (s_axil_arready_reg) begin
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// input is ready
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if (m_axil_rd.arready || !m_axil_arvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axil_arvalid_next = s_axil_rd.arvalid;
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store_axil_ar_input_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axil_arvalid_next = s_axil_rd.arvalid;
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store_axil_ar_input_to_temp = 1'b1;
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end
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end else if (m_axil_rd.arready) begin
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// input is not ready, but output is ready
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m_axil_arvalid_next = temp_m_axil_arvalid_reg;
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temp_m_axil_arvalid_next = 1'b0;
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store_axil_ar_temp_to_output = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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s_axil_arready_reg <= s_axil_arready_early;
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m_axil_arvalid_reg <= m_axil_arvalid_next;
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temp_m_axil_arvalid_reg <= temp_m_axil_arvalid_next;
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// datapath
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if (store_axil_ar_input_to_output) begin
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m_axil_araddr_reg <= s_axil_rd.araddr;
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m_axil_arprot_reg <= s_axil_rd.arprot;
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m_axil_aruser_reg <= s_axil_rd.aruser;
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end else if (store_axil_ar_temp_to_output) begin
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m_axil_araddr_reg <= temp_m_axil_araddr_reg;
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m_axil_arprot_reg <= temp_m_axil_arprot_reg;
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m_axil_aruser_reg <= temp_m_axil_aruser_reg;
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end
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if (store_axil_ar_input_to_temp) begin
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temp_m_axil_araddr_reg <= s_axil_rd.araddr;
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temp_m_axil_arprot_reg <= s_axil_rd.arprot;
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temp_m_axil_aruser_reg <= s_axil_rd.aruser;
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end
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if (rst) begin
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s_axil_arready_reg <= 1'b0;
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m_axil_arvalid_reg <= 1'b0;
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temp_m_axil_arvalid_reg <= 1'b0;
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end
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end
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end else if (AR_REG_TYPE == 1) begin
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// simple register, inserts bubble cycles
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// datapath registers
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logic s_axil_arready_reg = 1'b0;
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logic [ADDR_W-1:0] m_axil_araddr_reg = '0;
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logic [2:0] m_axil_arprot_reg = '0;
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logic [ARUSER_W-1:0] m_axil_aruser_reg = '0;
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logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
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// datapath control
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logic store_axil_ar_input_to_output;
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assign s_axil_rd.arready = s_axil_arready_reg;
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assign m_axil_rd.araddr = m_axil_araddr_reg;
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assign m_axil_rd.arprot = m_axil_arprot_reg;
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assign m_axil_rd.aruser = ARUSER_EN ? m_axil_aruser_reg : '0;
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assign m_axil_rd.arvalid = m_axil_arvalid_reg;
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// enable ready input next cycle if output buffer will be empty
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wire s_axil_arready_early = !m_axil_arvalid_next;
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always_comb begin
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// transfer sink ready state to source
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m_axil_arvalid_next = m_axil_arvalid_reg;
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store_axil_ar_input_to_output = 1'b0;
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if (s_axil_arready_reg) begin
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m_axil_arvalid_next = s_axil_rd.arvalid;
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store_axil_ar_input_to_output = 1'b1;
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end else if (m_axil_rd.arready) begin
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m_axil_arvalid_next = 1'b0;
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end
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end
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always_ff @(posedge clk) begin
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s_axil_arready_reg <= s_axil_arready_early;
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m_axil_arvalid_reg <= m_axil_arvalid_next;
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// datapath
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if (store_axil_ar_input_to_output) begin
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m_axil_araddr_reg <= s_axil_rd.araddr;
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m_axil_arprot_reg <= s_axil_rd.arprot;
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m_axil_aruser_reg <= s_axil_rd.aruser;
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end
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if (rst) begin
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s_axil_arready_reg <= 1'b0;
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m_axil_arvalid_reg <= 1'b0;
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end
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end
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end else begin
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// bypass AR channel
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assign m_axil_rd.araddr = s_axil_rd.araddr;
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assign m_axil_rd.arprot = s_axil_rd.arprot;
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assign m_axil_rd.aruser = ARUSER_EN ? s_axil_rd.aruser : '0;
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assign m_axil_rd.arvalid = s_axil_rd.arvalid;
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assign s_axil_rd.arready = m_axil_rd.arready;
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end
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// R channel
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if (R_REG_TYPE > 1) begin
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// skid buffer, no bubble cycles
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// datapath registers
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logic m_axil_rready_reg = 1'b0;
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logic [DATA_W-1:0] s_axil_rdata_reg = '0;
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logic [1:0] s_axil_rresp_reg = 2'b0;
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logic [RUSER_W-1:0] s_axil_ruser_reg = '0;
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logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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logic [DATA_W-1:0] temp_s_axil_rdata_reg = '0;
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logic [1:0] temp_s_axil_rresp_reg = 2'b0;
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logic [RUSER_W-1:0] temp_s_axil_ruser_reg = '0;
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logic temp_s_axil_rvalid_reg = 1'b0, temp_s_axil_rvalid_next;
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// datapath control
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logic store_axil_r_input_to_output;
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logic store_axil_r_input_to_temp;
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logic store_axil_r_temp_to_output;
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assign m_axil_rd.rready = m_axil_rready_reg;
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assign s_axil_rd.rdata = s_axil_rdata_reg;
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assign s_axil_rd.rresp = s_axil_rresp_reg;
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assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
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assign s_axil_rd.rvalid = s_axil_rvalid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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wire m_axil_rready_early = s_axil_rd.rready || (!temp_s_axil_rvalid_reg && (!s_axil_rvalid_reg || !m_axil_rd.rvalid));
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always_comb begin
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// transfer sink ready state to source
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s_axil_rvalid_next = s_axil_rvalid_reg;
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temp_s_axil_rvalid_next = temp_s_axil_rvalid_reg;
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store_axil_r_input_to_output = 1'b0;
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store_axil_r_input_to_temp = 1'b0;
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store_axil_r_temp_to_output = 1'b0;
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if (m_axil_rready_reg) begin
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// input is ready
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if (s_axil_rd.rready || !s_axil_rvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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s_axil_rvalid_next = m_axil_rd.rvalid;
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store_axil_r_input_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_s_axil_rvalid_next = m_axil_rd.rvalid;
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store_axil_r_input_to_temp = 1'b1;
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end
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end else if (s_axil_rd.rready) begin
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// input is not ready, but output is ready
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s_axil_rvalid_next = temp_s_axil_rvalid_reg;
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temp_s_axil_rvalid_next = 1'b0;
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store_axil_r_temp_to_output = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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m_axil_rready_reg <= m_axil_rready_early;
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s_axil_rvalid_reg <= s_axil_rvalid_next;
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temp_s_axil_rvalid_reg <= temp_s_axil_rvalid_next;
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// datapath
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if (store_axil_r_input_to_output) begin
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s_axil_rdata_reg <= m_axil_rd.rdata;
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s_axil_rresp_reg <= m_axil_rd.rresp;
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s_axil_ruser_reg <= m_axil_rd.ruser;
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end else if (store_axil_r_temp_to_output) begin
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s_axil_rdata_reg <= temp_s_axil_rdata_reg;
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s_axil_rresp_reg <= temp_s_axil_rresp_reg;
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s_axil_ruser_reg <= temp_s_axil_ruser_reg;
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end
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if (store_axil_r_input_to_temp) begin
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temp_s_axil_rdata_reg <= m_axil_rd.rdata;
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temp_s_axil_rresp_reg <= m_axil_rd.rresp;
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temp_s_axil_ruser_reg <= m_axil_rd.ruser;
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end
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if (rst) begin
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m_axil_rready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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temp_s_axil_rvalid_reg <= 1'b0;
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end
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end
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end else if (R_REG_TYPE == 1) begin
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// simple register, inserts bubble cycles
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// datapath registers
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logic m_axil_rready_reg = 1'b0;
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logic [DATA_W-1:0] s_axil_rdata_reg = '0;
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logic [1:0] s_axil_rresp_reg = 2'b0;
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logic [RUSER_W-1:0] s_axil_ruser_reg = '0;
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logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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// datapath control
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logic store_axil_r_input_to_output;
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assign m_axil_rd.rready = m_axil_rready_reg;
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|
||||
assign s_axil_rd.rdata = s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = s_axil_rresp_reg;
|
||||
assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
|
||||
assign s_axil_rd.rvalid = s_axil_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axil_rready_early = !s_axil_rvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg;
|
||||
|
||||
store_axil_r_input_to_output = 1'b0;
|
||||
|
||||
if (m_axil_rready_reg) begin
|
||||
s_axil_rvalid_next = m_axil_rd.rvalid;
|
||||
store_axil_r_input_to_output = 1'b1;
|
||||
end else if (s_axil_rd.rready) begin
|
||||
s_axil_rvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_rready_reg <= m_axil_rready_early;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_r_input_to_output) begin
|
||||
s_axil_rdata_reg <= m_axil_rd.rdata;
|
||||
s_axil_rresp_reg <= m_axil_rd.rresp;
|
||||
s_axil_ruser_reg <= m_axil_rd.ruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_rready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass R channel
|
||||
assign s_axil_rd.rdata = m_axil_rd.rdata;
|
||||
assign s_axil_rd.rresp = m_axil_rd.rresp;
|
||||
assign s_axil_rd.ruser = RUSER_EN ? m_axil_rd.ruser : '0;
|
||||
assign s_axil_rd.rvalid = m_axil_rd.rvalid;
|
||||
assign m_axil_rd.rready = s_axil_rd.rready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
522
rtl/axi/taxi_axil_register_wr.sv
Normal file
522
rtl/axi/taxi_axil_register_wr.sv
Normal file
@@ -0,0 +1,522 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite register (write)
|
||||
*/
|
||||
module taxi_axil_register_wr #
|
||||
(
|
||||
// AW channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter AW_REG_TYPE = 1,
|
||||
// W channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter W_REG_TYPE = 1,
|
||||
// B channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter B_REG_TYPE = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
taxi_axil_if.wr_slv s_axil_wr,
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
taxi_axil_if.wr_mst m_axil_wr
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axil_wr.DATA_W;
|
||||
localparam ADDR_W = s_axil_wr.ADDR_W;
|
||||
localparam STRB_W = s_axil_wr.STRB_W;
|
||||
localparam logic AWUSER_EN = s_axil_wr.AWUSER_EN && m_axil_wr.AWUSER_EN;
|
||||
localparam AWUSER_W = s_axil_wr.AWUSER_W;
|
||||
localparam logic WUSER_EN = s_axil_wr.WUSER_EN && m_axil_wr.WUSER_EN;
|
||||
localparam WUSER_W = s_axil_wr.WUSER_W;
|
||||
localparam logic BUSER_EN = s_axil_wr.BUSER_EN && m_axil_wr.BUSER_EN;
|
||||
localparam BUSER_W = s_axil_wr.BUSER_W;
|
||||
|
||||
if (m_axil_wr.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (m_axil_wr.STRB_W != STRB_W)
|
||||
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
|
||||
|
||||
// AW channel
|
||||
|
||||
if (AW_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_awready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_awaddr_reg = '0;
|
||||
logic [2:0] m_axil_awprot_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axil_awuser_reg = '0;
|
||||
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
|
||||
|
||||
logic [ADDR_W-1:0] temp_m_axil_awaddr_reg = '0;
|
||||
logic [2:0] temp_m_axil_awprot_reg = '0;
|
||||
logic [AWUSER_W-1:0] temp_m_axil_awuser_reg = '0;
|
||||
logic temp_m_axil_awvalid_reg = 1'b0, temp_m_axil_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_aw_input_to_output;
|
||||
logic store_axil_aw_input_to_temp;
|
||||
logic store_axil_aw_temp_to_output;
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
|
||||
assign m_axil_wr.awaddr = m_axil_awaddr_reg;
|
||||
assign m_axil_wr.awprot = m_axil_awprot_reg;
|
||||
assign m_axil_wr.awuser = AWUSER_EN ? m_axil_awuser_reg : '0;
|
||||
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axil_awready_early = m_axil_wr.awready || (!temp_m_axil_awvalid_reg && (!m_axil_awvalid_reg || !s_axil_wr.awvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_awvalid_next = m_axil_awvalid_reg;
|
||||
temp_m_axil_awvalid_next = temp_m_axil_awvalid_reg;
|
||||
|
||||
store_axil_aw_input_to_output = 1'b0;
|
||||
store_axil_aw_input_to_temp = 1'b0;
|
||||
store_axil_aw_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axil_awready_reg) begin
|
||||
// input is ready
|
||||
if (m_axil_wr.awready || !m_axil_awvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axil_awvalid_next = s_axil_wr.awvalid;
|
||||
store_axil_aw_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axil_awvalid_next = s_axil_wr.awvalid;
|
||||
store_axil_aw_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axil_wr.awready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axil_awvalid_next = temp_m_axil_awvalid_reg;
|
||||
temp_m_axil_awvalid_next = 1'b0;
|
||||
store_axil_aw_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_awready_reg <= s_axil_awready_early;
|
||||
m_axil_awvalid_reg <= m_axil_awvalid_next;
|
||||
temp_m_axil_awvalid_reg <= temp_m_axil_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_aw_input_to_output) begin
|
||||
m_axil_awaddr_reg <= s_axil_wr.awaddr;
|
||||
m_axil_awprot_reg <= s_axil_wr.awprot;
|
||||
m_axil_awuser_reg <= s_axil_wr.awuser;
|
||||
end else if (store_axil_aw_temp_to_output) begin
|
||||
m_axil_awaddr_reg <= temp_m_axil_awaddr_reg;
|
||||
m_axil_awprot_reg <= temp_m_axil_awprot_reg;
|
||||
m_axil_awuser_reg <= temp_m_axil_awuser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_aw_input_to_temp) begin
|
||||
temp_m_axil_awaddr_reg <= s_axil_wr.awaddr;
|
||||
temp_m_axil_awprot_reg <= s_axil_wr.awprot;
|
||||
temp_m_axil_awuser_reg <= s_axil_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
m_axil_awvalid_reg <= 1'b0;
|
||||
temp_m_axil_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (AW_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_awready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_awaddr_reg = '0;
|
||||
logic [2:0] m_axil_awprot_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axil_awuser_reg = '0;
|
||||
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_aw_input_to_output;
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
|
||||
assign m_axil_wr.awaddr = m_axil_awaddr_reg;
|
||||
assign m_axil_wr.awprot = m_axil_awprot_reg;
|
||||
assign m_axil_wr.awuser = AWUSER_EN ? m_axil_awuser_reg : '0;
|
||||
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axil_awready_early = !m_axil_awvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_awvalid_next = m_axil_awvalid_reg;
|
||||
|
||||
store_axil_aw_input_to_output = 1'b0;
|
||||
|
||||
if (s_axil_awready_reg) begin
|
||||
m_axil_awvalid_next = s_axil_wr.awvalid;
|
||||
store_axil_aw_input_to_output = 1'b1;
|
||||
end else if (m_axil_wr.awready) begin
|
||||
m_axil_awvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_awready_reg <= s_axil_awready_early;
|
||||
m_axil_awvalid_reg <= m_axil_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_aw_input_to_output) begin
|
||||
m_axil_awaddr_reg <= s_axil_wr.awaddr;
|
||||
m_axil_awprot_reg <= s_axil_wr.awprot;
|
||||
m_axil_awuser_reg <= s_axil_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
m_axil_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass AW channel
|
||||
assign m_axil_wr.awaddr = s_axil_wr.awaddr;
|
||||
assign m_axil_wr.awprot = s_axil_wr.awprot;
|
||||
assign m_axil_wr.awuser = AWUSER_EN ? s_axil_wr.awuser : '0;
|
||||
assign m_axil_wr.awvalid = s_axil_wr.awvalid;
|
||||
assign s_axil_wr.awready = m_axil_wr.awready;
|
||||
|
||||
end
|
||||
|
||||
// W channel
|
||||
|
||||
if (W_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axil_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axil_wstrb_reg = '0;
|
||||
logic [WUSER_W-1:0] m_axil_wuser_reg = '0;
|
||||
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
|
||||
|
||||
logic [DATA_W-1:0] temp_m_axil_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] temp_m_axil_wstrb_reg = '0;
|
||||
logic [WUSER_W-1:0] temp_m_axil_wuser_reg = '0;
|
||||
logic temp_m_axil_wvalid_reg = 1'b0, temp_m_axil_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_w_input_to_output;
|
||||
logic store_axil_w_input_to_temp;
|
||||
logic store_axil_w_temp_to_output;
|
||||
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
|
||||
assign m_axil_wr.wdata = m_axil_wdata_reg;
|
||||
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
|
||||
assign m_axil_wr.wuser = WUSER_EN ? m_axil_wuser_reg : '0;
|
||||
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axil_wready_early = m_axil_wr.wready || (!temp_m_axil_wvalid_reg && (!m_axil_wvalid_reg || !s_axil_wr.wvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_wvalid_next = m_axil_wvalid_reg;
|
||||
temp_m_axil_wvalid_next = temp_m_axil_wvalid_reg;
|
||||
|
||||
store_axil_w_input_to_output = 1'b0;
|
||||
store_axil_w_input_to_temp = 1'b0;
|
||||
store_axil_w_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axil_wready_reg) begin
|
||||
// input is ready
|
||||
if (m_axil_wr.wready || !m_axil_wvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axil_wvalid_next = s_axil_wr.wvalid;
|
||||
store_axil_w_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axil_wvalid_next = s_axil_wr.wvalid;
|
||||
store_axil_w_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axil_wr.wready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axil_wvalid_next = temp_m_axil_wvalid_reg;
|
||||
temp_m_axil_wvalid_next = 1'b0;
|
||||
store_axil_w_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_wready_reg <= s_axil_wready_early;
|
||||
m_axil_wvalid_reg <= m_axil_wvalid_next;
|
||||
temp_m_axil_wvalid_reg <= temp_m_axil_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_w_input_to_output) begin
|
||||
m_axil_wdata_reg <= s_axil_wr.wdata;
|
||||
m_axil_wstrb_reg <= s_axil_wr.wstrb;
|
||||
m_axil_wuser_reg <= s_axil_wr.wuser;
|
||||
end else if (store_axil_w_temp_to_output) begin
|
||||
m_axil_wdata_reg <= temp_m_axil_wdata_reg;
|
||||
m_axil_wstrb_reg <= temp_m_axil_wstrb_reg;
|
||||
m_axil_wuser_reg <= temp_m_axil_wuser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_w_input_to_temp) begin
|
||||
temp_m_axil_wdata_reg <= s_axil_wr.wdata;
|
||||
temp_m_axil_wstrb_reg <= s_axil_wr.wstrb;
|
||||
temp_m_axil_wuser_reg <= s_axil_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
m_axil_wvalid_reg <= 1'b0;
|
||||
temp_m_axil_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (W_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axil_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axil_wstrb_reg = '0;
|
||||
logic [WUSER_W-1:0] m_axil_wuser_reg = '0;
|
||||
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_w_input_to_output;
|
||||
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
|
||||
assign m_axil_wr.wdata = m_axil_wdata_reg;
|
||||
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
|
||||
assign m_axil_wr.wuser = WUSER_EN ? m_axil_wuser_reg : '0;
|
||||
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axil_wready_early = !m_axil_wvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_wvalid_next = m_axil_wvalid_reg;
|
||||
|
||||
store_axil_w_input_to_output = 1'b0;
|
||||
|
||||
if (s_axil_wready_reg) begin
|
||||
m_axil_wvalid_next = s_axil_wr.wvalid;
|
||||
store_axil_w_input_to_output = 1'b1;
|
||||
end else if (m_axil_wr.wready) begin
|
||||
m_axil_wvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_wready_reg <= s_axil_wready_early;
|
||||
m_axil_wvalid_reg <= m_axil_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_w_input_to_output) begin
|
||||
m_axil_wdata_reg <= s_axil_wr.wdata;
|
||||
m_axil_wstrb_reg <= s_axil_wr.wstrb;
|
||||
m_axil_wuser_reg <= s_axil_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
m_axil_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass W channel
|
||||
assign m_axil_wr.wdata = s_axil_wr.wdata;
|
||||
assign m_axil_wr.wstrb = s_axil_wr.wstrb;
|
||||
assign m_axil_wr.wuser = WUSER_EN ? s_axil_wr.wuser : '0;
|
||||
assign m_axil_wr.wvalid = s_axil_wr.wvalid;
|
||||
assign s_axil_wr.wready = m_axil_wr.wready;
|
||||
|
||||
end
|
||||
|
||||
// B channel
|
||||
|
||||
if (B_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_bready_reg = 1'b0;
|
||||
|
||||
logic [1:0] s_axil_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axil_buser_reg = '0;
|
||||
logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
|
||||
logic [1:0] temp_s_axil_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] temp_s_axil_buser_reg = '0;
|
||||
logic temp_s_axil_bvalid_reg = 1'b0, temp_s_axil_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_b_input_to_output;
|
||||
logic store_axil_b_input_to_temp;
|
||||
logic store_axil_b_temp_to_output;
|
||||
|
||||
assign m_axil_wr.bready = m_axil_bready_reg;
|
||||
|
||||
assign s_axil_wr.bresp = s_axil_bresp_reg;
|
||||
assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire m_axil_bready_early = s_axil_wr.bready || (!temp_s_axil_bvalid_reg && (!s_axil_bvalid_reg || !m_axil_wr.bvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg;
|
||||
temp_s_axil_bvalid_next = temp_s_axil_bvalid_reg;
|
||||
|
||||
store_axil_b_input_to_output = 1'b0;
|
||||
store_axil_b_input_to_temp = 1'b0;
|
||||
store_axil_b_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axil_bready_reg) begin
|
||||
// input is ready
|
||||
if (s_axil_wr.bready || !s_axil_bvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axil_bvalid_next = m_axil_wr.bvalid;
|
||||
store_axil_b_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axil_bvalid_next = m_axil_wr.bvalid;
|
||||
store_axil_b_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (s_axil_wr.bready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axil_bvalid_next = temp_s_axil_bvalid_reg;
|
||||
temp_s_axil_bvalid_next = 1'b0;
|
||||
store_axil_b_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_bready_reg <= m_axil_bready_early;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
temp_s_axil_bvalid_reg <= temp_s_axil_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_b_input_to_output) begin
|
||||
s_axil_bresp_reg <= m_axil_wr.bresp;
|
||||
s_axil_buser_reg <= m_axil_wr.buser;
|
||||
end else if (store_axil_b_temp_to_output) begin
|
||||
s_axil_bresp_reg <= temp_s_axil_bresp_reg;
|
||||
s_axil_buser_reg <= temp_s_axil_buser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_b_input_to_temp) begin
|
||||
temp_s_axil_bresp_reg <= m_axil_wr.bresp;
|
||||
temp_s_axil_buser_reg <= m_axil_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_bready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
temp_s_axil_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (B_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_bready_reg = 1'b0;
|
||||
|
||||
logic [1:0] s_axil_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axil_buser_reg = '0;
|
||||
logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_b_input_to_output;
|
||||
|
||||
assign m_axil_wr.bready = m_axil_bready_reg;
|
||||
|
||||
assign s_axil_wr.bresp = s_axil_bresp_reg;
|
||||
assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axil_bready_early = !s_axil_bvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg;
|
||||
|
||||
store_axil_b_input_to_output = 1'b0;
|
||||
|
||||
if (m_axil_bready_reg) begin
|
||||
s_axil_bvalid_next = m_axil_wr.bvalid;
|
||||
store_axil_b_input_to_output = 1'b1;
|
||||
end else if (s_axil_wr.bready) begin
|
||||
s_axil_bvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_bready_reg <= m_axil_bready_early;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_b_input_to_output) begin
|
||||
s_axil_bresp_reg <= m_axil_wr.bresp;
|
||||
s_axil_buser_reg <= m_axil_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_bready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass B channel
|
||||
assign s_axil_wr.bresp = m_axil_wr.bresp;
|
||||
assign s_axil_wr.buser = BUSER_EN ? m_axil_wr.buser : '0;
|
||||
assign s_axil_wr.bvalid = m_axil_wr.bvalid;
|
||||
assign m_axil_wr.bready = s_axil_wr.bready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user