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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-16 22:22:43 -08:00
parent 94dba88560
commit 1112545d0a
1 changed files with 21 additions and 0 deletions
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README.md
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@@ -36,6 +36,12 @@ To facilitate the dual-license model, contributions to the project can only be a
* Pipeline register
* Pipeline FIFO
* Ethernet
* 10/100 MII MAC
* 10/100 MII MAC + FIFO
* 10/100/1000 GMII MAC
* 10/100/1000 GMII MAC + FIFO
* 10/100/1000 RGMII MAC
* 10/100/1000 RGMII MAC + FIFO
* 1G MAC
* 1G MAC + FIFO
* 10G MAC
@@ -43,6 +49,21 @@ To facilitate the dual-license model, contributions to the project can only be a
* 10G MAC/PHY
* 10G MAC/PHY + FIFO
* 10G PHY
* MII PHY interface
* GMII PHY interface
* RGMII PHY interface
* General input/output
* Switch debouncer
* Generic IDDR
* Generic ODDR
* Source-synchronous DDR input
* Source-synchronous DDR differential input
* Source-synchronous DDR output
* Source-synchronous DDR differential output
* Source-synchronous SDR input
* Source-synchronous SDR differential input
* Source-synchronous SDR output
* Source-synchronous SDR differential output
* Linear-feedback shift register
* Parametrizable combinatorial LFSR/CRC module
* CRC computation module