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eth: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-02 16:11:07 -07:00
parent 76d4465081
commit 159c9d6241
45 changed files with 1561 additions and 1296 deletions
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16
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv
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@@ -39,19 +39,19 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_0_tx_p,
output wire logic [3:0] qsfp_0_tx_n,
input wire logic [3:0] qsfp_0_rx_p,
input wire logic [3:0] qsfp_0_rx_n,
output wire logic qsfp_0_tx_p[4],
output wire logic qsfp_0_tx_n[4],
input wire logic qsfp_0_rx_p[4],
input wire logic qsfp_0_rx_n[4],
input wire logic qsfp_0_mgt_refclk_p,
input wire logic qsfp_0_mgt_refclk_n,
input wire logic qsfp_0_modprs_l,
output wire logic qsfp_0_sel_l,
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
// input wire logic qsfp_1_mgt_refclk_p,
// input wire logic qsfp_1_mgt_refclk_n,
input wire logic qsfp_1_modprs_l,

103
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
View File

@@ -40,19 +40,19 @@ module fpga_core #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_0_tx_p,
output wire logic [3:0] qsfp_0_tx_n,
input wire logic [3:0] qsfp_0_rx_p,
input wire logic [3:0] qsfp_0_rx_n,
output wire logic qsfp_0_tx_p[4],
output wire logic qsfp_0_tx_n[4],
input wire logic qsfp_0_rx_p[4],
input wire logic qsfp_0_rx_n[4],
input wire logic qsfp_0_mgt_refclk_p,
input wire logic qsfp_0_mgt_refclk_n,
input wire logic qsfp_0_modprs_l,
output wire logic qsfp_0_sel_l,
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
// input wire logic qsfp_1_mgt_refclk_p,
// input wire logic qsfp_1_mgt_refclk_n,
input wire logic qsfp_1_modprs_l,
@@ -67,12 +67,12 @@ assign qsfp_0_sel_l = 1'b1;
assign qsfp_1_sel_l = 1'b1;
assign qsfp_reset_l = 1'b1;
wire [7:0] qsfp_tx_clk;
wire [7:0] qsfp_tx_rst;
wire [7:0] qsfp_rx_clk;
wire [7:0] qsfp_rx_rst;
wire qsfp_tx_clk[8];
wire qsfp_tx_rst[8];
wire qsfp_rx_clk[8];
wire qsfp_rx_rst[8];
wire [7:0] qsfp_rx_status;
wire qsfp_rx_status[8];
wire [1:0] qsfp_gtpowergood;
@@ -124,15 +124,20 @@ qsfp_sync_reset_inst (
.out(qsfp_rst)
);
wire [7:0] qsfp_tx_p;
wire [7:0] qsfp_tx_n;
wire [7:0] qsfp_rx_p = {qsfp_1_rx_p, qsfp_0_rx_p};
wire [7:0] qsfp_rx_n = {qsfp_1_rx_n, qsfp_0_rx_n};
wire qsfp_tx_p[8];
wire qsfp_tx_n[8];
wire qsfp_rx_p[8];
wire qsfp_rx_n[8];
assign qsfp_0_tx_p = qsfp_tx_p[3:0];
assign qsfp_0_tx_n = qsfp_tx_n[3:0];
assign qsfp_1_tx_p = qsfp_tx_p[7:4];
assign qsfp_1_tx_n = qsfp_tx_n[7:4];
assign qsfp_0_tx_p = qsfp_tx_p[4*0 +: 4];
assign qsfp_0_tx_n = qsfp_tx_n[4*0 +: 4];
assign qsfp_1_tx_p = qsfp_tx_p[4*1 +: 4];
assign qsfp_1_tx_n = qsfp_tx_n[4*1 +: 4];
assign qsfp_rx_p[4*0 +: 4] = qsfp_0_rx_p;
assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
@@ -199,12 +204,12 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(qsfp_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]),
.tx_clk(qsfp_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -221,24 +226,24 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -246,8 +251,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -292,7 +297,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -317,42 +322,42 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

69
src/eth/example/Alveo/fpga/rtl/fpga_au200.sv
View File

@@ -48,10 +48,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_0_p,
input wire logic qsfp0_mgt_refclk_0_n,
// input wire logic qsfp0_mgt_refclk_1_p,
@@ -64,10 +64,10 @@ module fpga #
// output wire logic qsfp0_refclk_reset,
// output wire logic [1:0] qsfp0_fs,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_0_p,
input wire logic qsfp1_mgt_refclk_0_n,
// input wire logic qsfp1_mgt_refclk_1_p,
@@ -215,10 +215,35 @@ assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
wire qsfp0_mgt_refclk_0;
wire qsfp1_mgt_refclk_0;
localparam PORT_CNT = 2;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_156mhz_ref_int = qsfp0_mgt_refclk_0;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_0_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -227,10 +252,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(3),
.UART_CNT(1),
.PORT_CNT(2),
.GTY_QUAD_CNT(2),
.GTY_CNT(2*4),
.GTY_CLK_CNT(2)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -260,13 +285,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_0_p, qsfp0_mgt_refclk_0_p}),
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_0_n, qsfp0_mgt_refclk_0_n}),
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk_0, qsfp0_mgt_refclk_0}),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell({qsfp1_modsell, qsfp0_modsell}),
.eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),

69
src/eth/example/Alveo/fpga/rtl/fpga_au280.sv
View File

@@ -41,10 +41,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_0_p,
input wire logic qsfp0_mgt_refclk_0_n,
// input wire logic qsfp0_mgt_refclk_1_p,
@@ -52,10 +52,10 @@ module fpga #
output wire logic qsfp0_refclk_oe_b,
output wire logic qsfp0_refclk_fs,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_0_p,
input wire logic qsfp1_mgt_refclk_0_n,
// input wire logic qsfp1_mgt_refclk_1_p,
@@ -178,10 +178,35 @@ assign qsfp0_refclk_fs = 1'b1;
assign qsfp1_refclk_oe_b = 1'b0;
assign qsfp1_refclk_fs = 1'b1;
wire qsfp0_mgt_refclk_0;
wire qsfp1_mgt_refclk_0;
localparam PORT_CNT = 2;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_156mhz_ref_int = qsfp0_mgt_refclk_0;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_0_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -190,10 +215,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(3),
.UART_CNT(1),
.PORT_CNT(2),
.GTY_QUAD_CNT(2),
.GTY_CNT(2*4),
.GTY_CLK_CNT(2)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -223,13 +248,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_0_p, qsfp0_mgt_refclk_0_p}),
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_0_n, qsfp0_mgt_refclk_0_n}),
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk_0, qsfp0_mgt_refclk_0}),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

61
src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv
View File

@@ -42,19 +42,19 @@ module fpga #
/*
* Ethernet: QSFP28
*/
// output wire logic [3:0] qsfp0_tx_p,
// output wire logic [3:0] qsfp0_tx_n,
// input wire logic [3:0] qsfp0_rx_p,
// input wire logic [3:0] qsfp0_rx_n,
// output wire logic qsfp0_tx_p[4],
// output wire logic qsfp0_tx_n[4],
// input wire logic qsfp0_rx_p[4],
// input wire logic qsfp0_rx_n[4],
// input wire logic qsfp0_mgt_refclk_0_p,
// input wire logic qsfp0_mgt_refclk_0_n,
// input wire logic qsfp0_mgt_refclk_1_p,
// input wire logic qsfp0_mgt_refclk_1_n,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_p,
input wire logic qsfp1_mgt_refclk_n
);
@@ -165,9 +165,28 @@ sync_reset_125mhz_inst (
.out(rst_125mhz_int)
);
wire qsfp1_mgt_refclk;
localparam PORT_CNT = QSFP_CNT;
localparam GTY_QUAD_CNT = 1;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_161mhz_ref_int = qsfp1_mgt_refclk;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp1_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = qsfp1_mgt_refclk_n;
assign clk_161mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -176,10 +195,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(2),
.UART_CNT(UART_CNT),
.PORT_CNT(QSFP_CNT),
.GTY_QUAD_CNT(1),
.GTY_CNT(1*4),
.GTY_CLK_CNT(1)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -209,13 +228,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p(qsfp1_tx_p),
.eth_gty_tx_n(qsfp1_tx_n),
.eth_gty_rx_p(qsfp1_rx_p),
.eth_gty_rx_n(qsfp1_rx_n),
.eth_gty_mgt_refclk_p(qsfp1_mgt_refclk_p),
.eth_gty_mgt_refclk_n(qsfp1_mgt_refclk_n),
.eth_gty_mgt_refclk_out(qsfp1_mgt_refclk),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

53
src/eth/example/Alveo/fpga/rtl/fpga_au50.sv
View File

@@ -41,10 +41,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_tx_p,
output wire logic [3:0] qsfp_tx_n,
input wire logic [3:0] qsfp_rx_p,
input wire logic [3:0] qsfp_rx_n,
output wire logic qsfp_tx_p[4],
output wire logic qsfp_tx_n[4],
input wire logic qsfp_rx_p[4],
input wire logic qsfp_rx_n[4],
input wire logic qsfp_mgt_refclk_0_p,
input wire logic qsfp_mgt_refclk_0_n
// input wire logic qsfp_mgt_refclk_1_p,
@@ -160,9 +160,28 @@ sync_reset_125mhz_inst (
// GPIO
assign hbm_cattrip = 1'b0;
wire qsfp_mgt_refclk_0;
localparam PORT_CNT = QSFP_CNT;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_161mhz_ref_int = qsfp_mgt_refclk_0;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp_mgt_refclk_0_n;
assign clk_161mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -171,10 +190,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(3),
.UART_CNT(UART_CNT),
.PORT_CNT(QSFP_CNT),
.GTY_QUAD_CNT(QSFP_CNT),
.GTY_CNT(QSFP_CNT*4),
.GTY_CLK_CNT(QSFP_CNT)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -204,13 +223,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p(qsfp_tx_p),
.eth_gty_tx_n(qsfp_tx_n),
.eth_gty_rx_p(qsfp_rx_p),
.eth_gty_rx_n(qsfp_rx_n),
.eth_gty_mgt_refclk_p(qsfp_mgt_refclk_0_p),
.eth_gty_mgt_refclk_n(qsfp_mgt_refclk_0_n),
.eth_gty_mgt_refclk_out(qsfp_mgt_refclk_0),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

69
src/eth/example/Alveo/fpga/rtl/fpga_au55.sv
View File

@@ -46,17 +46,17 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_p,
input wire logic qsfp0_mgt_refclk_n,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_p,
input wire logic qsfp1_mgt_refclk_n
);
@@ -170,10 +170,35 @@ sync_reset_125mhz_inst (
// GPIO
assign hbm_cattrip = 1'b0;
wire qsfp0_mgt_refclk;
wire qsfp1_mgt_refclk;
localparam PORT_CNT = QSFP_CNT;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_161mhz_ref_int = qsfp0_mgt_refclk;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_n;
assign clk_161mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -182,10 +207,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(3),
.UART_CNT(UART_CNT),
.PORT_CNT(QSFP_CNT),
.GTY_QUAD_CNT(QSFP_CNT),
.GTY_CNT(QSFP_CNT*4),
.GTY_CLK_CNT(QSFP_CNT)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -215,13 +240,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_p, qsfp0_mgt_refclk_p}),
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_n, qsfp0_mgt_refclk_n}),
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk, qsfp0_mgt_refclk}),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

86
src/eth/example/Alveo/fpga/rtl/fpga_core.sv
View File

@@ -57,13 +57,13 @@ module fpga_core #
/*
* Ethernet
*/
output wire logic [GTY_CNT-1:0] eth_gty_tx_p,
output wire logic [GTY_CNT-1:0] eth_gty_tx_n,
input wire logic [GTY_CNT-1:0] eth_gty_rx_p,
input wire logic [GTY_CNT-1:0] eth_gty_rx_n,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n,
output wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out,
output wire logic eth_gty_tx_p[GTY_CNT],
output wire logic eth_gty_tx_n[GTY_CNT],
input wire logic eth_gty_rx_p[GTY_CNT],
input wire logic eth_gty_rx_n[GTY_CNT],
input wire logic eth_gty_mgt_refclk_p[GTY_CLK_CNT],
input wire logic eth_gty_mgt_refclk_n[GTY_CLK_CNT],
output wire logic eth_gty_mgt_refclk_out[GTY_CLK_CNT],
output wire logic [PORT_CNT-1:0] eth_port_modsell,
output wire logic [PORT_CNT-1:0] eth_port_resetl,
@@ -221,23 +221,23 @@ assign eth_port_modsell = '1;
assign eth_port_resetl = '1;
assign eth_port_lpmode = '0;
wire [GTY_CNT-1:0] eth_gty_tx_clk;
wire [GTY_CNT-1:0] eth_gty_tx_rst;
wire eth_gty_tx_clk[GTY_CNT];
wire eth_gty_tx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_clk;
wire [GTY_CNT-1:0] eth_gty_rx_rst;
wire eth_gty_rx_clk[GTY_CNT];
wire eth_gty_rx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_status;
wire eth_gty_rx_status[GTY_CNT];
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
wire eth_gty_mgt_refclk[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
wire eth_gty_rst[GTY_CLK_CNT];
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
@@ -359,12 +359,12 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -381,24 +381,24 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -406,8 +406,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -452,7 +452,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -477,42 +477,42 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

63
src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv
View File

@@ -40,14 +40,14 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [1:0] dsfp0_tx_p,
output wire logic [1:0] dsfp0_tx_n,
input wire logic [1:0] dsfp0_rx_p,
input wire logic [1:0] dsfp0_rx_n,
output wire logic [1:0] dsfp1_tx_p,
output wire logic [1:0] dsfp1_tx_n,
input wire logic [1:0] dsfp1_rx_p,
input wire logic [1:0] dsfp1_rx_n,
output wire logic dsfp0_tx_p[2],
output wire logic dsfp0_tx_n[2],
input wire logic dsfp0_rx_p[2],
input wire logic dsfp0_rx_n[2],
output wire logic dsfp1_tx_p[2],
output wire logic dsfp1_tx_n[2],
input wire logic dsfp1_rx_p[2],
input wire logic dsfp1_rx_n[2],
input wire logic dsfp_mgt_refclk_p,
input wire logic dsfp_mgt_refclk_n
);
@@ -158,9 +158,32 @@ sync_reset_125mhz_inst (
.out(rst_125mhz_int)
);
wire dsfp_mgt_refclk;
localparam GTY_QUAD_CNT = 1;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_161mhz_ref_int = dsfp_mgt_refclk;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign dsfp0_tx_p = eth_gty_tx_p[2*0 +: 2];
assign dsfp0_tx_n = eth_gty_tx_n[2*0 +: 2];
assign eth_gty_rx_p[2*0 +: 2] = dsfp0_rx_p;
assign eth_gty_rx_n[2*0 +: 2] = dsfp0_rx_n;
assign dsfp1_tx_p = eth_gty_tx_p[2*1 +: 2];
assign dsfp1_tx_n = eth_gty_tx_n[2*1 +: 2];
assign eth_gty_rx_p[2*1 +: 2] = dsfp1_rx_p;
assign eth_gty_rx_n[2*1 +: 2] = dsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = dsfp_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = dsfp_mgt_refclk_n;
assign clk_161mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -170,9 +193,9 @@ fpga_core #(
.LED_CNT(2),
.UART_CNT(UART_CNT),
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(1),
.GTY_CNT(1*4),
.GTY_CLK_CNT(1)
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -202,13 +225,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p({dsfp1_tx_p, dsfp0_tx_p}),
.eth_gty_tx_n({dsfp1_tx_n, dsfp0_tx_n}),
.eth_gty_rx_p({dsfp1_rx_p, dsfp0_rx_p}),
.eth_gty_rx_n({dsfp1_rx_n, dsfp0_rx_n}),
.eth_gty_mgt_refclk_p(dsfp_mgt_refclk_p),
.eth_gty_mgt_refclk_n(dsfp_mgt_refclk_n),
.eth_gty_mgt_refclk_out(dsfp_mgt_refclk),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

14
src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -49,6 +49,9 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for clk in dut.eth_gty_mgt_refclk_p:
cocotb.start_soon(Clock(clk, 6.4, units="ns").start())
for inst in dut.gty_quad:
for ch in inst.mac_inst.ch:
gt_inst = ch.ch_inst.gt.gt_inst
@@ -88,8 +91,6 @@ class TB:
dut.eth_port_modprsl.setimmediatevalue(0)
dut.eth_port_intl.setimmediatevalue(0)
cocotb.start_soon(self._run_refclk())
async def init(self):
self.dut.rst_125mhz.setimmediatevalue(0)
@@ -107,15 +108,6 @@ class TB:
for k in range(10):
await RisingEdge(self.dut.clk_125mhz)
async def _run_refclk(self):
t = Timer(3.2, 'ns')
val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1
while True:
self.dut.eth_gty_mgt_refclk_p.value = val
await t
self.dut.eth_gty_mgt_refclk_p.value = 0
await t
async def mac_test(tb, source, sink):
tb.log.info("Test MAC")

158
src/eth/example/HTG9200/fpga/rtl/fpga.sv
View File

@@ -66,90 +66,90 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
input wire logic qsfp_1_mgt_refclk_p,
input wire logic qsfp_1_mgt_refclk_n,
output wire logic qsfp_1_resetl,
input wire logic qsfp_1_modprsl,
input wire logic qsfp_1_intl,
output wire logic [3:0] qsfp_2_tx_p,
output wire logic [3:0] qsfp_2_tx_n,
input wire logic [3:0] qsfp_2_rx_p,
input wire logic [3:0] qsfp_2_rx_n,
output wire logic qsfp_2_tx_p[4],
output wire logic qsfp_2_tx_n[4],
input wire logic qsfp_2_rx_p[4],
input wire logic qsfp_2_rx_n[4],
input wire logic qsfp_2_mgt_refclk_p,
input wire logic qsfp_2_mgt_refclk_n,
output wire logic qsfp_2_resetl,
input wire logic qsfp_2_modprsl,
input wire logic qsfp_2_intl,
output wire logic [3:0] qsfp_3_tx_p,
output wire logic [3:0] qsfp_3_tx_n,
input wire logic [3:0] qsfp_3_rx_p,
input wire logic [3:0] qsfp_3_rx_n,
output wire logic qsfp_3_tx_p[4],
output wire logic qsfp_3_tx_n[4],
input wire logic qsfp_3_rx_p[4],
input wire logic qsfp_3_rx_n[4],
input wire logic qsfp_3_mgt_refclk_p,
input wire logic qsfp_3_mgt_refclk_n,
output wire logic qsfp_3_resetl,
input wire logic qsfp_3_modprsl,
input wire logic qsfp_3_intl,
output wire logic [3:0] qsfp_4_tx_p,
output wire logic [3:0] qsfp_4_tx_n,
input wire logic [3:0] qsfp_4_rx_p,
input wire logic [3:0] qsfp_4_rx_n,
output wire logic qsfp_4_tx_p[4],
output wire logic qsfp_4_tx_n[4],
input wire logic qsfp_4_rx_p[4],
input wire logic qsfp_4_rx_n[4],
input wire logic qsfp_4_mgt_refclk_p,
input wire logic qsfp_4_mgt_refclk_n,
output wire logic qsfp_4_resetl,
input wire logic qsfp_4_modprsl,
input wire logic qsfp_4_intl,
output wire logic [3:0] qsfp_5_tx_p,
output wire logic [3:0] qsfp_5_tx_n,
input wire logic [3:0] qsfp_5_rx_p,
input wire logic [3:0] qsfp_5_rx_n,
output wire logic qsfp_5_tx_p[4],
output wire logic qsfp_5_tx_n[4],
input wire logic qsfp_5_rx_p[4],
input wire logic qsfp_5_rx_n[4],
input wire logic qsfp_5_mgt_refclk_p,
input wire logic qsfp_5_mgt_refclk_n,
output wire logic qsfp_5_resetl,
input wire logic qsfp_5_modprsl,
input wire logic qsfp_5_intl,
output wire logic [3:0] qsfp_6_tx_p,
output wire logic [3:0] qsfp_6_tx_n,
input wire logic [3:0] qsfp_6_rx_p,
input wire logic [3:0] qsfp_6_rx_n,
output wire logic qsfp_6_tx_p[4],
output wire logic qsfp_6_tx_n[4],
input wire logic qsfp_6_rx_p[4],
input wire logic qsfp_6_rx_n[4],
input wire logic qsfp_6_mgt_refclk_p,
input wire logic qsfp_6_mgt_refclk_n,
output wire logic qsfp_6_resetl,
input wire logic qsfp_6_modprsl,
input wire logic qsfp_6_intl,
output wire logic [3:0] qsfp_7_tx_p,
output wire logic [3:0] qsfp_7_tx_n,
input wire logic [3:0] qsfp_7_rx_p,
input wire logic [3:0] qsfp_7_rx_n,
output wire logic qsfp_7_tx_p[4],
output wire logic qsfp_7_tx_n[4],
input wire logic qsfp_7_rx_p[4],
input wire logic qsfp_7_rx_n[4],
input wire logic qsfp_7_mgt_refclk_p,
input wire logic qsfp_7_mgt_refclk_n,
output wire logic qsfp_7_resetl,
input wire logic qsfp_7_modprsl,
input wire logic qsfp_7_intl,
output wire logic [3:0] qsfp_8_tx_p,
output wire logic [3:0] qsfp_8_tx_n,
input wire logic [3:0] qsfp_8_rx_p,
input wire logic [3:0] qsfp_8_rx_n,
output wire logic qsfp_8_tx_p[4],
output wire logic qsfp_8_tx_n[4],
input wire logic qsfp_8_rx_p[4],
input wire logic qsfp_8_rx_n[4],
input wire logic qsfp_8_mgt_refclk_p,
input wire logic qsfp_8_mgt_refclk_n,
output wire logic qsfp_8_resetl,
input wire logic qsfp_8_modprsl,
input wire logic qsfp_8_intl,
output wire logic [3:0] qsfp_9_tx_p,
output wire logic [3:0] qsfp_9_tx_n,
input wire logic [3:0] qsfp_9_rx_p,
input wire logic [3:0] qsfp_9_rx_n,
output wire logic qsfp_9_tx_p[4],
output wire logic qsfp_9_tx_n[4],
input wire logic qsfp_9_rx_p[4],
input wire logic qsfp_9_rx_n[4],
input wire logic qsfp_9_mgt_refclk_p,
input wire logic qsfp_9_mgt_refclk_n,
output wire logic qsfp_9_resetl,
@@ -320,6 +320,14 @@ localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign clk_gty2_fdec = 1'b0;
assign clk_gty2_finc = 1'b0;
assign clk_gty2_oe_n = 1'b0;
@@ -328,6 +336,70 @@ assign clk_gty2_rst_n = !rst_125mhz_int;
wire eth_pll_locked = clk_gty2_lol_n;
assign qsfp_1_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp_1_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp_1_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp_1_rx_n;
assign qsfp_2_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp_2_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp_2_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp_2_rx_n;
assign qsfp_3_tx_p = eth_gty_tx_p[4*2 +: 4];
assign qsfp_3_tx_n = eth_gty_tx_n[4*2 +: 4];
assign eth_gty_rx_p[4*2 +: 4] = qsfp_3_rx_p;
assign eth_gty_rx_n[4*2 +: 4] = qsfp_3_rx_n;
assign qsfp_4_tx_p = eth_gty_tx_p[4*3 +: 4];
assign qsfp_4_tx_n = eth_gty_tx_n[4*3 +: 4];
assign eth_gty_rx_p[4*3 +: 4] = qsfp_4_rx_p;
assign eth_gty_rx_n[4*3 +: 4] = qsfp_4_rx_n;
assign qsfp_5_tx_p = eth_gty_tx_p[4*4 +: 4];
assign qsfp_5_tx_n = eth_gty_tx_n[4*4 +: 4];
assign eth_gty_rx_p[4*4 +: 4] = qsfp_5_rx_p;
assign eth_gty_rx_n[4*4 +: 4] = qsfp_5_rx_n;
assign qsfp_6_tx_p = eth_gty_tx_p[4*5 +: 4];
assign qsfp_6_tx_n = eth_gty_tx_n[4*5 +: 4];
assign eth_gty_rx_p[4*5 +: 4] = qsfp_6_rx_p;
assign eth_gty_rx_n[4*5 +: 4] = qsfp_6_rx_n;
assign qsfp_7_tx_p = eth_gty_tx_p[4*6 +: 4];
assign qsfp_7_tx_n = eth_gty_tx_n[4*6 +: 4];
assign eth_gty_rx_p[4*6 +: 4] = qsfp_7_rx_p;
assign eth_gty_rx_n[4*6 +: 4] = qsfp_7_rx_n;
assign qsfp_8_tx_p = eth_gty_tx_p[4*7 +: 4];
assign qsfp_8_tx_n = eth_gty_tx_n[4*7 +: 4];
assign eth_gty_rx_p[4*7 +: 4] = qsfp_8_rx_p;
assign eth_gty_rx_n[4*7 +: 4] = qsfp_8_rx_n;
assign qsfp_9_tx_p = eth_gty_tx_p[4*8 +: 4];
assign qsfp_9_tx_n = eth_gty_tx_n[4*8 +: 4];
assign eth_gty_rx_p[4*8 +: 4] = qsfp_9_rx_p;
assign eth_gty_rx_n[4*8 +: 4] = qsfp_9_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp_1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = qsfp_1_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[1] = qsfp_2_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[1] = qsfp_2_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[2] = qsfp_3_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[2] = qsfp_3_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[3] = qsfp_4_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[3] = qsfp_4_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[4] = qsfp_5_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[4] = qsfp_5_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[5] = qsfp_6_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[5] = qsfp_6_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[6] = qsfp_7_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[6] = qsfp_7_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[7] = qsfp_8_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[7] = qsfp_8_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[8] = qsfp_9_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[8] = qsfp_9_mgt_refclk_n;
fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
@@ -375,13 +447,13 @@ core_inst (
*/
.eth_pll_locked(eth_pll_locked),
.eth_gty_tx_p({qsfp_9_tx_p, qsfp_8_tx_p, qsfp_7_tx_p, qsfp_6_tx_p, qsfp_5_tx_p, qsfp_4_tx_p, qsfp_3_tx_p, qsfp_2_tx_p, qsfp_1_tx_p}),
.eth_gty_tx_n({qsfp_9_tx_n, qsfp_8_tx_n, qsfp_7_tx_n, qsfp_6_tx_n, qsfp_5_tx_n, qsfp_4_tx_n, qsfp_3_tx_n, qsfp_2_tx_n, qsfp_1_tx_n}),
.eth_gty_rx_p({qsfp_9_rx_p, qsfp_8_rx_p, qsfp_7_rx_p, qsfp_6_rx_p, qsfp_5_rx_p, qsfp_4_rx_p, qsfp_3_rx_p, qsfp_2_rx_p, qsfp_1_rx_p}),
.eth_gty_rx_n({qsfp_9_rx_n, qsfp_8_rx_n, qsfp_7_rx_n, qsfp_6_rx_n, qsfp_5_rx_n, qsfp_4_rx_n, qsfp_3_rx_n, qsfp_2_rx_n, qsfp_1_rx_n}),
.eth_gty_mgt_refclk_p({qsfp_9_mgt_refclk_p, qsfp_8_mgt_refclk_p, qsfp_7_mgt_refclk_p, qsfp_6_mgt_refclk_p, qsfp_5_mgt_refclk_p, qsfp_4_mgt_refclk_p, qsfp_3_mgt_refclk_p, qsfp_2_mgt_refclk_p, qsfp_1_mgt_refclk_p}),
.eth_gty_mgt_refclk_n({qsfp_9_mgt_refclk_n, qsfp_8_mgt_refclk_n, qsfp_7_mgt_refclk_n, qsfp_6_mgt_refclk_n, qsfp_5_mgt_refclk_n, qsfp_4_mgt_refclk_n, qsfp_3_mgt_refclk_n, qsfp_2_mgt_refclk_n, qsfp_1_mgt_refclk_n}),
.eth_gty_mgt_refclk_out(),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_resetl({qsfp_9_resetl, qsfp_8_resetl, qsfp_7_resetl, qsfp_6_resetl, qsfp_5_resetl, qsfp_4_resetl, qsfp_3_resetl, qsfp_2_resetl, qsfp_1_resetl}),
.eth_port_modprsl({qsfp_9_modprsl, qsfp_8_modprsl, qsfp_7_modprsl, qsfp_6_modprsl, qsfp_5_modprsl, qsfp_4_modprsl, qsfp_3_modprsl, qsfp_2_modprsl, qsfp_1_modprsl}),

248
src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv
View File

@@ -66,90 +66,90 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
input wire logic qsfp_1_mgt_refclk_p,
input wire logic qsfp_1_mgt_refclk_n,
output wire logic qsfp_1_resetl,
input wire logic qsfp_1_modprsl,
input wire logic qsfp_1_intl,
output wire logic [3:0] qsfp_2_tx_p,
output wire logic [3:0] qsfp_2_tx_n,
input wire logic [3:0] qsfp_2_rx_p,
input wire logic [3:0] qsfp_2_rx_n,
output wire logic qsfp_2_tx_p[4],
output wire logic qsfp_2_tx_n[4],
input wire logic qsfp_2_rx_p[4],
input wire logic qsfp_2_rx_n[4],
input wire logic qsfp_2_mgt_refclk_p,
input wire logic qsfp_2_mgt_refclk_n,
output wire logic qsfp_2_resetl,
input wire logic qsfp_2_modprsl,
input wire logic qsfp_2_intl,
output wire logic [3:0] qsfp_3_tx_p,
output wire logic [3:0] qsfp_3_tx_n,
input wire logic [3:0] qsfp_3_rx_p,
input wire logic [3:0] qsfp_3_rx_n,
output wire logic qsfp_3_tx_p[4],
output wire logic qsfp_3_tx_n[4],
input wire logic qsfp_3_rx_p[4],
input wire logic qsfp_3_rx_n[4],
input wire logic qsfp_3_mgt_refclk_p,
input wire logic qsfp_3_mgt_refclk_n,
output wire logic qsfp_3_resetl,
input wire logic qsfp_3_modprsl,
input wire logic qsfp_3_intl,
output wire logic [3:0] qsfp_4_tx_p,
output wire logic [3:0] qsfp_4_tx_n,
input wire logic [3:0] qsfp_4_rx_p,
input wire logic [3:0] qsfp_4_rx_n,
output wire logic qsfp_4_tx_p[4],
output wire logic qsfp_4_tx_n[4],
input wire logic qsfp_4_rx_p[4],
input wire logic qsfp_4_rx_n[4],
input wire logic qsfp_4_mgt_refclk_p,
input wire logic qsfp_4_mgt_refclk_n,
output wire logic qsfp_4_resetl,
input wire logic qsfp_4_modprsl,
input wire logic qsfp_4_intl,
output wire logic [3:0] qsfp_5_tx_p,
output wire logic [3:0] qsfp_5_tx_n,
input wire logic [3:0] qsfp_5_rx_p,
input wire logic [3:0] qsfp_5_rx_n,
output wire logic qsfp_5_tx_p[4],
output wire logic qsfp_5_tx_n[4],
input wire logic qsfp_5_rx_p[4],
input wire logic qsfp_5_rx_n[4],
input wire logic qsfp_5_mgt_refclk_p,
input wire logic qsfp_5_mgt_refclk_n,
output wire logic qsfp_5_resetl,
input wire logic qsfp_5_modprsl,
input wire logic qsfp_5_intl,
output wire logic [3:0] qsfp_6_tx_p,
output wire logic [3:0] qsfp_6_tx_n,
input wire logic [3:0] qsfp_6_rx_p,
input wire logic [3:0] qsfp_6_rx_n,
output wire logic qsfp_6_tx_p[4],
output wire logic qsfp_6_tx_n[4],
input wire logic qsfp_6_rx_p[4],
input wire logic qsfp_6_rx_n[4],
input wire logic qsfp_6_mgt_refclk_p,
input wire logic qsfp_6_mgt_refclk_n,
output wire logic qsfp_6_resetl,
input wire logic qsfp_6_modprsl,
input wire logic qsfp_6_intl,
output wire logic [3:0] qsfp_7_tx_p,
output wire logic [3:0] qsfp_7_tx_n,
input wire logic [3:0] qsfp_7_rx_p,
input wire logic [3:0] qsfp_7_rx_n,
output wire logic qsfp_7_tx_p[4],
output wire logic qsfp_7_tx_n[4],
input wire logic qsfp_7_rx_p[4],
input wire logic qsfp_7_rx_n[4],
input wire logic qsfp_7_mgt_refclk_p,
input wire logic qsfp_7_mgt_refclk_n,
output wire logic qsfp_7_resetl,
input wire logic qsfp_7_modprsl,
input wire logic qsfp_7_intl,
output wire logic [3:0] qsfp_8_tx_p,
output wire logic [3:0] qsfp_8_tx_n,
input wire logic [3:0] qsfp_8_rx_p,
input wire logic [3:0] qsfp_8_rx_n,
output wire logic qsfp_8_tx_p[4],
output wire logic qsfp_8_tx_n[4],
input wire logic qsfp_8_rx_p[4],
input wire logic qsfp_8_rx_n[4],
input wire logic qsfp_8_mgt_refclk_p,
input wire logic qsfp_8_mgt_refclk_n,
output wire logic qsfp_8_resetl,
input wire logic qsfp_8_modprsl,
input wire logic qsfp_8_intl,
output wire logic [3:0] qsfp_9_tx_p,
output wire logic [3:0] qsfp_9_tx_n,
input wire logic [3:0] qsfp_9_rx_p,
input wire logic [3:0] qsfp_9_rx_n,
output wire logic qsfp_9_tx_p[4],
output wire logic qsfp_9_tx_n[4],
input wire logic qsfp_9_rx_p[4],
input wire logic qsfp_9_rx_n[4],
input wire logic qsfp_9_mgt_refclk_p,
input wire logic qsfp_9_mgt_refclk_n,
output wire logic qsfp_9_resetl,
@@ -159,10 +159,10 @@ module fpga #
/*
* Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter
*/
output wire logic [3:0] fmc_qsfp_1_tx_p,
output wire logic [3:0] fmc_qsfp_1_tx_n,
input wire logic [3:0] fmc_qsfp_1_rx_p,
input wire logic [3:0] fmc_qsfp_1_rx_n,
output wire logic fmc_qsfp_1_tx_p[4],
output wire logic fmc_qsfp_1_tx_n[4],
input wire logic fmc_qsfp_1_rx_p[4],
input wire logic fmc_qsfp_1_rx_n[4],
input wire logic fmc_qsfp_1_mgt_refclk_p,
input wire logic fmc_qsfp_1_mgt_refclk_n,
output wire logic fmc_qsfp_1_modsell,
@@ -171,10 +171,10 @@ module fpga #
input wire logic fmc_qsfp_1_intl,
output wire logic fmc_qsfp_1_lpmode,
output wire logic [3:0] fmc_qsfp_2_tx_p,
output wire logic [3:0] fmc_qsfp_2_tx_n,
input wire logic [3:0] fmc_qsfp_2_rx_p,
input wire logic [3:0] fmc_qsfp_2_rx_n,
output wire logic fmc_qsfp_2_tx_p[4],
output wire logic fmc_qsfp_2_tx_n[4],
input wire logic fmc_qsfp_2_rx_p[4],
input wire logic fmc_qsfp_2_rx_n[4],
input wire logic fmc_qsfp_2_mgt_refclk_p,
input wire logic fmc_qsfp_2_mgt_refclk_n,
output wire logic fmc_qsfp_2_modsell,
@@ -183,10 +183,10 @@ module fpga #
input wire logic fmc_qsfp_2_intl,
output wire logic fmc_qsfp_2_lpmode,
output wire logic [3:0] fmc_qsfp_3_tx_p,
output wire logic [3:0] fmc_qsfp_3_tx_n,
input wire logic [3:0] fmc_qsfp_3_rx_p,
input wire logic [3:0] fmc_qsfp_3_rx_n,
output wire logic fmc_qsfp_3_tx_p[4],
output wire logic fmc_qsfp_3_tx_n[4],
input wire logic fmc_qsfp_3_rx_p[4],
input wire logic fmc_qsfp_3_rx_n[4],
input wire logic fmc_qsfp_3_mgt_refclk_p,
input wire logic fmc_qsfp_3_mgt_refclk_n,
output wire logic fmc_qsfp_3_modsell,
@@ -195,10 +195,10 @@ module fpga #
input wire logic fmc_qsfp_3_intl,
output wire logic fmc_qsfp_3_lpmode,
output wire logic [3:0] fmc_qsfp_4_tx_p,
output wire logic [3:0] fmc_qsfp_4_tx_n,
input wire logic [3:0] fmc_qsfp_4_rx_p,
input wire logic [3:0] fmc_qsfp_4_rx_n,
output wire logic fmc_qsfp_4_tx_p[4],
output wire logic fmc_qsfp_4_tx_n[4],
input wire logic fmc_qsfp_4_rx_p[4],
input wire logic fmc_qsfp_4_rx_n[4],
input wire logic fmc_qsfp_4_mgt_refclk_p,
input wire logic fmc_qsfp_4_mgt_refclk_n,
output wire logic fmc_qsfp_4_modsell,
@@ -207,10 +207,10 @@ module fpga #
input wire logic fmc_qsfp_4_intl,
output wire logic fmc_qsfp_4_lpmode,
output wire logic [3:0] fmc_qsfp_5_tx_p,
output wire logic [3:0] fmc_qsfp_5_tx_n,
input wire logic [3:0] fmc_qsfp_5_rx_p,
input wire logic [3:0] fmc_qsfp_5_rx_n,
output wire logic fmc_qsfp_5_tx_p[4],
output wire logic fmc_qsfp_5_tx_n[4],
input wire logic fmc_qsfp_5_rx_p[4],
input wire logic fmc_qsfp_5_rx_n[4],
input wire logic fmc_qsfp_5_mgt_refclk_p,
input wire logic fmc_qsfp_5_mgt_refclk_n,
output wire logic fmc_qsfp_5_modsell,
@@ -219,10 +219,10 @@ module fpga #
input wire logic fmc_qsfp_5_intl,
output wire logic fmc_qsfp_5_lpmode,
output wire logic [3:0] fmc_qsfp_6_tx_p,
output wire logic [3:0] fmc_qsfp_6_tx_n,
input wire logic [3:0] fmc_qsfp_6_rx_p,
input wire logic [3:0] fmc_qsfp_6_rx_n,
output wire logic fmc_qsfp_6_tx_p[4],
output wire logic fmc_qsfp_6_tx_n[4],
input wire logic fmc_qsfp_6_rx_p[4],
input wire logic fmc_qsfp_6_rx_n[4],
input wire logic fmc_qsfp_6_mgt_refclk_p,
input wire logic fmc_qsfp_6_mgt_refclk_n,
output wire logic fmc_qsfp_6_modsell,
@@ -405,14 +405,20 @@ localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign clk_gty2_fdec = 1'b0;
assign clk_gty2_finc = 1'b0;
assign clk_gty2_oe_n = 1'b0;
assign clk_gty2_sync_n = 1'b1;
assign clk_gty2_rst_n = !rst_125mhz_int;
wire [PORT_CNT-1:0] eth_gty_mgt_refclk_out;
// forward MGT ref clock to PLL on FMC+ board
OBUFDS obufds_fmc_refclk_inst (
.I(eth_gty_mgt_refclk_out[0]),
@@ -434,6 +440,112 @@ assign fmc_clk_rst_n = !rst_125mhz_int;
wire eth_pll_locked = clk_gty2_lol_n && fmc_clk_lol_n;
assign qsfp_1_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp_1_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp_1_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp_1_rx_n;
assign qsfp_2_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp_2_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp_2_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp_2_rx_n;
assign qsfp_3_tx_p = eth_gty_tx_p[4*2 +: 4];
assign qsfp_3_tx_n = eth_gty_tx_n[4*2 +: 4];
assign eth_gty_rx_p[4*2 +: 4] = qsfp_3_rx_p;
assign eth_gty_rx_n[4*2 +: 4] = qsfp_3_rx_n;
assign qsfp_4_tx_p = eth_gty_tx_p[4*3 +: 4];
assign qsfp_4_tx_n = eth_gty_tx_n[4*3 +: 4];
assign eth_gty_rx_p[4*3 +: 4] = qsfp_4_rx_p;
assign eth_gty_rx_n[4*3 +: 4] = qsfp_4_rx_n;
assign qsfp_5_tx_p = eth_gty_tx_p[4*4 +: 4];
assign qsfp_5_tx_n = eth_gty_tx_n[4*4 +: 4];
assign eth_gty_rx_p[4*4 +: 4] = qsfp_5_rx_p;
assign eth_gty_rx_n[4*4 +: 4] = qsfp_5_rx_n;
assign qsfp_6_tx_p = eth_gty_tx_p[4*5 +: 4];
assign qsfp_6_tx_n = eth_gty_tx_n[4*5 +: 4];
assign eth_gty_rx_p[4*5 +: 4] = qsfp_6_rx_p;
assign eth_gty_rx_n[4*5 +: 4] = qsfp_6_rx_n;
assign qsfp_7_tx_p = eth_gty_tx_p[4*6 +: 4];
assign qsfp_7_tx_n = eth_gty_tx_n[4*6 +: 4];
assign eth_gty_rx_p[4*6 +: 4] = qsfp_7_rx_p;
assign eth_gty_rx_n[4*6 +: 4] = qsfp_7_rx_n;
assign qsfp_8_tx_p = eth_gty_tx_p[4*7 +: 4];
assign qsfp_8_tx_n = eth_gty_tx_n[4*7 +: 4];
assign eth_gty_rx_p[4*7 +: 4] = qsfp_8_rx_p;
assign eth_gty_rx_n[4*7 +: 4] = qsfp_8_rx_n;
assign qsfp_9_tx_p = eth_gty_tx_p[4*8 +: 4];
assign qsfp_9_tx_n = eth_gty_tx_n[4*8 +: 4];
assign eth_gty_rx_p[4*8 +: 4] = qsfp_9_rx_p;
assign eth_gty_rx_n[4*8 +: 4] = qsfp_9_rx_n;
assign fmc_qsfp_1_tx_p = eth_gty_tx_p[4*9 +: 4];
assign fmc_qsfp_1_tx_n = eth_gty_tx_n[4*9 +: 4];
assign eth_gty_rx_p[4*9 +: 4] = fmc_qsfp_1_rx_p;
assign eth_gty_rx_n[4*9 +: 4] = fmc_qsfp_1_rx_n;
assign fmc_qsfp_2_tx_p = eth_gty_tx_p[4*10 +: 4];
assign fmc_qsfp_2_tx_n = eth_gty_tx_n[4*10 +: 4];
assign eth_gty_rx_p[4*10 +: 4] = fmc_qsfp_2_rx_p;
assign eth_gty_rx_n[4*10 +: 4] = fmc_qsfp_2_rx_n;
assign fmc_qsfp_3_tx_p = eth_gty_tx_p[4*11 +: 4];
assign fmc_qsfp_3_tx_n = eth_gty_tx_n[4*11 +: 4];
assign eth_gty_rx_p[4*11 +: 4] = fmc_qsfp_3_rx_p;
assign eth_gty_rx_n[4*11 +: 4] = fmc_qsfp_3_rx_n;
assign fmc_qsfp_4_tx_p = eth_gty_tx_p[4*12 +: 4];
assign fmc_qsfp_4_tx_n = eth_gty_tx_n[4*12 +: 4];
assign eth_gty_rx_p[4*12 +: 4] = fmc_qsfp_4_rx_p;
assign eth_gty_rx_n[4*12 +: 4] = fmc_qsfp_4_rx_n;
assign fmc_qsfp_5_tx_p = eth_gty_tx_p[4*13 +: 4];
assign fmc_qsfp_5_tx_n = eth_gty_tx_n[4*13 +: 4];
assign eth_gty_rx_p[4*13 +: 4] = fmc_qsfp_5_rx_p;
assign eth_gty_rx_n[4*13 +: 4] = fmc_qsfp_5_rx_n;
assign fmc_qsfp_6_tx_p = eth_gty_tx_p[4*14 +: 4];
assign fmc_qsfp_6_tx_n = eth_gty_tx_n[4*14 +: 4];
assign eth_gty_rx_p[4*14 +: 4] = fmc_qsfp_6_rx_p;
assign eth_gty_rx_n[4*14 +: 4] = fmc_qsfp_6_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp_1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = qsfp_1_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[1] = qsfp_2_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[1] = qsfp_2_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[2] = qsfp_3_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[2] = qsfp_3_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[3] = qsfp_4_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[3] = qsfp_4_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[4] = qsfp_5_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[4] = qsfp_5_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[5] = qsfp_6_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[5] = qsfp_6_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[6] = qsfp_7_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[6] = qsfp_7_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[7] = qsfp_8_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[7] = qsfp_8_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[8] = qsfp_9_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[8] = qsfp_9_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[9] = fmc_qsfp_1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[9] = fmc_qsfp_1_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[10] = fmc_qsfp_2_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[10] = fmc_qsfp_2_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[11] = fmc_qsfp_3_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[11] = fmc_qsfp_3_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[12] = fmc_qsfp_4_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[12] = fmc_qsfp_4_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[13] = fmc_qsfp_5_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[13] = fmc_qsfp_5_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[14] = fmc_qsfp_6_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[14] = fmc_qsfp_6_mgt_refclk_n;
fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
@@ -481,12 +593,12 @@ core_inst (
*/
.eth_pll_locked(eth_pll_locked),
.eth_gty_tx_p({fmc_qsfp_6_tx_p, fmc_qsfp_5_tx_p, fmc_qsfp_4_tx_p, fmc_qsfp_3_tx_p, fmc_qsfp_2_tx_p, fmc_qsfp_1_tx_p, qsfp_9_tx_p, qsfp_8_tx_p, qsfp_7_tx_p, qsfp_6_tx_p, qsfp_5_tx_p, qsfp_4_tx_p, qsfp_3_tx_p, qsfp_2_tx_p, qsfp_1_tx_p}),
.eth_gty_tx_n({fmc_qsfp_6_tx_n, fmc_qsfp_5_tx_n, fmc_qsfp_4_tx_n, fmc_qsfp_3_tx_n, fmc_qsfp_2_tx_n, fmc_qsfp_1_tx_n, qsfp_9_tx_n, qsfp_8_tx_n, qsfp_7_tx_n, qsfp_6_tx_n, qsfp_5_tx_n, qsfp_4_tx_n, qsfp_3_tx_n, qsfp_2_tx_n, qsfp_1_tx_n}),
.eth_gty_rx_p({fmc_qsfp_6_rx_p, fmc_qsfp_5_rx_p, fmc_qsfp_4_rx_p, fmc_qsfp_3_rx_p, fmc_qsfp_2_rx_p, fmc_qsfp_1_rx_p, qsfp_9_rx_p, qsfp_8_rx_p, qsfp_7_rx_p, qsfp_6_rx_p, qsfp_5_rx_p, qsfp_4_rx_p, qsfp_3_rx_p, qsfp_2_rx_p, qsfp_1_rx_p}),
.eth_gty_rx_n({fmc_qsfp_6_rx_n, fmc_qsfp_5_rx_n, fmc_qsfp_4_rx_n, fmc_qsfp_3_rx_n, fmc_qsfp_2_rx_n, fmc_qsfp_1_rx_n, qsfp_9_rx_n, qsfp_8_rx_n, qsfp_7_rx_n, qsfp_6_rx_n, qsfp_5_rx_n, qsfp_4_rx_n, qsfp_3_rx_n, qsfp_2_rx_n, qsfp_1_rx_n}),
.eth_gty_mgt_refclk_p({fmc_qsfp_6_mgt_refclk_p, fmc_qsfp_5_mgt_refclk_p, fmc_qsfp_4_mgt_refclk_p, fmc_qsfp_3_mgt_refclk_p, fmc_qsfp_2_mgt_refclk_p, fmc_qsfp_1_mgt_refclk_p, qsfp_9_mgt_refclk_p, qsfp_8_mgt_refclk_p, qsfp_7_mgt_refclk_p, qsfp_6_mgt_refclk_p, qsfp_5_mgt_refclk_p, qsfp_4_mgt_refclk_p, qsfp_3_mgt_refclk_p, qsfp_2_mgt_refclk_p, qsfp_1_mgt_refclk_p}),
.eth_gty_mgt_refclk_n({fmc_qsfp_6_mgt_refclk_n, fmc_qsfp_5_mgt_refclk_n, fmc_qsfp_4_mgt_refclk_n, fmc_qsfp_3_mgt_refclk_n, fmc_qsfp_2_mgt_refclk_n, fmc_qsfp_1_mgt_refclk_n, qsfp_9_mgt_refclk_n, qsfp_8_mgt_refclk_n, qsfp_7_mgt_refclk_n, qsfp_6_mgt_refclk_n, qsfp_5_mgt_refclk_n, qsfp_4_mgt_refclk_n, qsfp_3_mgt_refclk_n, qsfp_2_mgt_refclk_n, qsfp_1_mgt_refclk_n}),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_resetl({fmc_qsfp_6_resetl, fmc_qsfp_5_resetl, fmc_qsfp_4_resetl, fmc_qsfp_3_resetl, fmc_qsfp_2_resetl, fmc_qsfp_1_resetl, qsfp_9_resetl, qsfp_8_resetl, qsfp_7_resetl, qsfp_6_resetl, qsfp_5_resetl, qsfp_4_resetl, qsfp_3_resetl, qsfp_2_resetl, qsfp_1_resetl}),

86
src/eth/example/HTG9200/fpga/rtl/fpga_core.sv
View File

@@ -63,13 +63,13 @@ module fpga_core #
*/
input wire logic eth_pll_locked,
output wire logic [GTY_CNT-1:0] eth_gty_tx_p,
output wire logic [GTY_CNT-1:0] eth_gty_tx_n,
input wire logic [GTY_CNT-1:0] eth_gty_rx_p,
input wire logic [GTY_CNT-1:0] eth_gty_rx_n,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n,
output wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out,
output wire logic eth_gty_tx_p[GTY_CNT],
output wire logic eth_gty_tx_n[GTY_CNT],
input wire logic eth_gty_rx_p[GTY_CNT],
input wire logic eth_gty_rx_n[GTY_CNT],
input wire logic eth_gty_mgt_refclk_p[GTY_CLK_CNT],
input wire logic eth_gty_mgt_refclk_n[GTY_CLK_CNT],
output wire logic eth_gty_mgt_refclk_out[GTY_CLK_CNT],
output wire logic [PORT_CNT-1:0] eth_port_resetl,
input wire logic [PORT_CNT-1:0] eth_port_modprsl,
@@ -289,23 +289,23 @@ xfcp_mod_i2c_inst (
wire eth_reset = SIM ? 1'b0 : (si5341_i2c_busy || !eth_pll_locked);
assign eth_port_resetl = {PORT_CNT{~eth_reset}};
wire [GTY_CNT-1:0] eth_gty_tx_clk;
wire [GTY_CNT-1:0] eth_gty_tx_rst;
wire eth_gty_tx_clk[GTY_CNT];
wire eth_gty_tx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_clk;
wire [GTY_CNT-1:0] eth_gty_rx_rst;
wire eth_gty_rx_clk[GTY_CNT];
wire eth_gty_rx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_status;
wire eth_gty_rx_status[GTY_CNT];
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
wire eth_gty_mgt_refclk[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
wire eth_gty_rst[GTY_CLK_CNT];
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
@@ -456,12 +456,12 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -478,24 +478,24 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -503,8 +503,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -549,7 +549,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -574,42 +574,42 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

14
src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -49,6 +49,9 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for clk in dut.eth_gty_mgt_refclk_p:
cocotb.start_soon(Clock(clk, 6.206, units="ns").start())
for inst in dut.gty_quad:
for ch in inst.mac_inst.ch:
gt_inst = ch.ch_inst.gt.gt_inst
@@ -91,8 +94,6 @@ class TB:
dut.eth_port_modprsl.setimmediatevalue(0)
dut.eth_port_intl.setimmediatevalue(0)
cocotb.start_soon(self._run_refclk())
async def init(self):
self.dut.rst_125mhz.setimmediatevalue(0)
@@ -110,15 +111,6 @@ class TB:
for k in range(10):
await RisingEdge(self.dut.clk_125mhz)
async def _run_refclk(self):
t = Timer(3.102, 'ns')
val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1
while True:
self.dut.eth_gty_mgt_refclk_p.value = val
await t
self.dut.eth_gty_mgt_refclk_p.value = 0
await t
async def mac_test(tb, source, sink):
tb.log.info("Test MAC")

86
src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv
View File

@@ -65,13 +65,13 @@ module fpga_core #
/*
* Ethernet: QSFP28
*/
output wire logic [GTY_CNT-1:0] eth_gty_tx_p,
output wire logic [GTY_CNT-1:0] eth_gty_tx_n,
input wire logic [GTY_CNT-1:0] eth_gty_rx_p,
input wire logic [GTY_CNT-1:0] eth_gty_rx_n,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n,
output wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out,
output wire logic eth_gty_tx_p[GTY_CNT],
output wire logic eth_gty_tx_n[GTY_CNT],
input wire logic eth_gty_rx_p[GTY_CNT],
input wire logic eth_gty_rx_n[GTY_CNT],
input wire logic eth_gty_mgt_refclk_p[GTY_CLK_CNT],
input wire logic eth_gty_mgt_refclk_n[GTY_CLK_CNT],
output wire logic eth_gty_mgt_refclk_out[GTY_CLK_CNT],
output wire logic [PORT_CNT-1:0] eth_port_resetl,
input wire logic [PORT_CNT-1:0] eth_port_modprsl,
@@ -246,23 +246,23 @@ xfcp_mod_axil_inst (
wire eth_reset = SIM ? 1'b0 : rst_125mhz;
assign eth_port_resetl = {PORT_CNT{~eth_reset}};
wire [GTY_CNT-1:0] eth_gty_tx_clk;
wire [GTY_CNT-1:0] eth_gty_tx_rst;
wire eth_gty_tx_clk[GTY_CNT];
wire eth_gty_tx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_clk;
wire [GTY_CNT-1:0] eth_gty_rx_rst;
wire eth_gty_rx_clk[GTY_CNT];
wire eth_gty_rx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_status;
wire eth_gty_rx_status[GTY_CNT];
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
wire eth_gty_mgt_refclk[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
wire eth_gty_rst[GTY_CLK_CNT];
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
@@ -387,12 +387,12 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -409,24 +409,24 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -434,8 +434,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -480,7 +480,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -505,42 +505,42 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

8
src/eth/example/HTG_ZRF8/fpga/rtl/fpga_em.sv
View File

@@ -63,10 +63,10 @@ module fpga #
// output wire logic [9:0] fmc_la_p,
// output wire logic [9:0] fmc_la_n,
output wire logic [7:0] fmc_dp_c2m_p,
output wire logic [7:0] fmc_dp_c2m_n,
input wire logic [7:0] fmc_dp_m2c_p,
input wire logic [7:0] fmc_dp_m2c_n,
output wire logic fmc_dp_c2m_p[8],
output wire logic fmc_dp_c2m_n[8],
input wire logic fmc_dp_m2c_p[8],
input wire logic fmc_dp_m2c_n[8],
input wire logic fmc_mgt_refclk_0_0_p,
input wire logic fmc_mgt_refclk_0_0_n,
input wire logic fmc_mgt_refclk_1_0_p,

8
src/eth/example/HTG_ZRF8/fpga/rtl/fpga_r2.sv
View File

@@ -77,10 +77,10 @@ module fpga #
output wire logic fmc_qsfp_resetl,
output wire logic fmc_qsfp_lpmode,
output wire logic [7:0] fmc_dp_c2m_p,
output wire logic [7:0] fmc_dp_c2m_n,
input wire logic [7:0] fmc_dp_m2c_p,
input wire logic [7:0] fmc_dp_m2c_n,
output wire logic fmc_dp_c2m_p[8],
output wire logic fmc_dp_c2m_n[8],
input wire logic fmc_dp_m2c_p[8],
input wire logic fmc_dp_m2c_n[8],
input wire logic fmc_mgt_refclk_0_0_p,
input wire logic fmc_mgt_refclk_0_0_n,
input wire logic fmc_mgt_refclk_1_0_p,

14
src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -49,6 +49,9 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for clk in dut.eth_gty_mgt_refclk_p:
cocotb.start_soon(Clock(clk, 6.206, units="ns").start())
for inst in dut.uut.gty_quad:
for ch in inst.mac_inst.ch:
gt_inst = ch.ch_inst.gt.gt_inst
@@ -91,8 +94,6 @@ class TB:
dut.i2c_sda_i.setimmediatevalue(1)
dut.sw.setimmediatevalue(0)
cocotb.start_soon(self._run_refclk())
async def init(self):
self.dut.rst_125mhz.setimmediatevalue(0)
@@ -116,15 +117,6 @@ class TB:
for k in range(10):
await RisingEdge(self.dut.clk_125mhz)
async def _run_refclk(self):
t = Timer(3.102, 'ns')
val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1
while True:
self.dut.eth_gty_mgt_refclk_p.value = val
await t
self.dut.eth_gty_mgt_refclk_p.value = 0
await t
async def mac_test(tb, source, sink):
tb.log.info("Test MAC")

14
src/eth/example/HTG_ZRF8/fpga/tb/fpga_core/test_fpga_core.sv
View File

@@ -59,13 +59,13 @@ logic uart_cts;
logic uart_rst_n;
logic uart_suspend_n;
logic [GTY_CNT-1:0] eth_gty_tx_p;
logic [GTY_CNT-1:0] eth_gty_tx_n;
logic [GTY_CNT-1:0] eth_gty_rx_p;
logic [GTY_CNT-1:0] eth_gty_rx_n;
logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p;
logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n;
logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out;
logic eth_gty_tx_p[GTY_CNT];
logic eth_gty_tx_n[GTY_CNT];
logic eth_gty_rx_p[GTY_CNT];
logic eth_gty_rx_n[GTY_CNT];
logic eth_gty_mgt_refclk_p[GTY_CLK_CNT];
logic eth_gty_mgt_refclk_n[GTY_CLK_CNT];
logic eth_gty_mgt_refclk_out[GTY_CLK_CNT];
logic [PORT_CNT-1:0] eth_port_resetl;
logic [PORT_CNT-1:0] eth_port_modprsl;

12
src/eth/example/KCU105/fpga/rtl/fpga.sv
View File

@@ -69,10 +69,10 @@ module fpga #
/*
* Ethernet: SFP+
*/
input wire logic [1:0] sfp_rx_p,
input wire logic [1:0] sfp_rx_n,
output wire logic [1:0] sfp_tx_p,
output wire logic [1:0] sfp_tx_n,
input wire logic sfp_rx_p[2],
input wire logic sfp_rx_n[2],
output wire logic sfp_tx_p[2],
output wire logic sfp_tx_n[2],
input wire logic sfp_mgt_refclk_0_p,
input wire logic sfp_mgt_refclk_0_n,
@@ -352,8 +352,8 @@ eth_pcspma (
);
// SFP+
wire [1:0] sfp_tx_p_int;
wire [1:0] sfp_tx_n_int;
wire sfp_tx_p_int[2];
wire sfp_tx_n_int[2];
wire sfp0_gmii_clk_int;
wire sfp0_gmii_rst_int;

74
src/eth/example/KCU105/fpga/rtl/fpga_core.sv
View File

@@ -71,10 +71,10 @@ module fpga_core #
/*
* Ethernet: SFP+
*/
input wire logic [1:0] sfp_rx_p,
input wire logic [1:0] sfp_rx_n,
output wire logic [1:0] sfp_tx_p,
output wire logic [1:0] sfp_tx_n,
input wire logic sfp_rx_p[2],
input wire logic sfp_rx_n[2],
output wire logic sfp_tx_p[2],
output wire logic sfp_tx_n[2],
input wire logic sfp_mgt_refclk_0_p,
input wire logic sfp_mgt_refclk_0_n,
@@ -472,12 +472,12 @@ if (SFP_RATE == 0) begin : sfp_mac
end else begin : sfp_mac
wire [1:0] sfp_tx_clk;
wire [1:0] sfp_tx_rst;
wire [1:0] sfp_rx_clk;
wire [1:0] sfp_rx_rst;
wire sfp_tx_clk[2];
wire sfp_tx_rst[2];
wire sfp_rx_clk[2];
wire sfp_rx_rst[2];
wire [1:0] sfp_rx_status;
wire sfp_rx_status[2];
wire sfp_gtpowergood;
@@ -597,12 +597,12 @@ end else begin : sfp_mac
* MAC clocks
*/
.rx_clk(sfp_rx_clk),
.rx_rst_in('0),
.rx_rst_in('{2{1'b0}}),
.rx_rst_out(sfp_rx_rst),
.tx_clk(sfp_tx_clk),
.tx_rst_in('0),
.tx_rst_in('{2{1'b0}}),
.tx_rst_out(sfp_tx_rst),
.ptp_sample_clk('0),
.ptp_sample_clk('{2{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -619,24 +619,24 @@ end else begin : sfp_mac
* PTP clock
*/
.tx_ptp_ts('{2{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{2{1'b0}}),
.rx_ptp_ts('{2{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{2{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{2{1'b0}}),
.tx_lfc_resend('{2{1'b0}}),
.rx_lfc_en('{2{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{2{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{2{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{2{1'b0}}),
.rx_pfc_en('{2{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{2{'0}}),
@@ -644,8 +644,8 @@ end else begin : sfp_mac
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{2{1'b0}}),
.tx_pause_req('{2{1'b0}}),
.tx_pause_ack(),
/*
@@ -690,7 +690,7 @@ end else begin : sfp_mac
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{2{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -715,42 +715,42 @@ end else begin : sfp_mac
*/
.cfg_tx_max_pkt_len('{2{16'd9218}}),
.cfg_tx_ifg('{2{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{2{1'b1}}),
.cfg_rx_max_pkt_len('{2{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{2{1'b1}}),
.cfg_tx_prbs31_enable('{2{1'b0}}),
.cfg_rx_prbs31_enable('{2{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{2{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{2{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{2{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{2{1'b0}}),
.cfg_mcf_rx_eth_src('{2{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{2{1'b0}}),
.cfg_mcf_rx_eth_type('{2{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{2{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{2{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{2{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{2{1'b1}}),
.cfg_mcf_rx_forward('{2{1'b0}}),
.cfg_mcf_rx_enable('{2{1'b0}}),
.cfg_tx_lfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{2{16'h8808}}),
.cfg_tx_lfc_opcode('{2{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{2{1'b0}}),
.cfg_tx_lfc_quanta('{2{16'hffff}}),
.cfg_tx_lfc_refresh('{2{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{2{16'h8808}}),
.cfg_tx_pfc_opcode('{2{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{2{1'b0}}),
.cfg_tx_pfc_quanta('{2{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{2{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{2{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{2{1'b0}}),
.cfg_rx_pfc_opcode('{2{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{2{1'b0}})
);
for (genvar n = 0; n < 2; n = n + 1) begin : sfp_ch

92
src/eth/example/KR260/fpga/rtl/fpga_core.sv
View File

@@ -338,12 +338,12 @@ if (SFP_RATE == 0) begin : sfp_mac
end else begin : sfp_mac
wire sfp_tx_clk;
wire sfp_tx_rst;
wire sfp_rx_clk;
wire sfp_rx_rst;
wire sfp_tx_clk[1];
wire sfp_tx_rst[1];
wire sfp_rx_clk[1];
wire sfp_rx_rst[1];
wire sfp_rx_status;
wire sfp_rx_status[1];
wire sfp_gtpowergood;
@@ -395,6 +395,16 @@ end else begin : sfp_mac
.out(sfp_rst)
);
wire eth_gty_tx_p[1];
wire eth_gty_tx_n[1];
wire eth_gty_rx_p[1];
wire eth_gty_rx_n[1];
assign sfp_tx_p = eth_gty_tx_p[0];
assign sfp_tx_n = eth_gty_tx_n[0];
assign eth_gty_rx_p[0] = sfp_rx_p;
assign eth_gty_rx_n[0] = sfp_rx_n;
taxi_eth_mac_25g_us #(
.SIM(SIM),
.VENDOR(VENDOR),
@@ -448,21 +458,21 @@ end else begin : sfp_mac
/*
* Serial data
*/
.xcvr_txp(sfp_tx_p),
.xcvr_txn(sfp_tx_n),
.xcvr_rxp(sfp_rx_p),
.xcvr_rxn(sfp_rx_n),
.xcvr_txp(eth_gty_tx_p),
.xcvr_txn(eth_gty_tx_n),
.xcvr_rxp(eth_gty_rx_p),
.xcvr_rxn(eth_gty_rx_n),
/*
* MAC clocks
*/
.rx_clk(sfp_rx_clk),
.rx_rst_in('0),
.rx_rst_in('{1{1'b0}}),
.rx_rst_out(sfp_rx_rst),
.tx_clk(sfp_tx_clk),
.tx_rst_in('0),
.tx_rst_in('{1{1'b0}}),
.tx_rst_out(sfp_tx_rst),
.ptp_sample_clk('0),
.ptp_sample_clk('{1{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -479,24 +489,24 @@ end else begin : sfp_mac
* PTP clock
*/
.tx_ptp_ts('{1{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{1{1'b0}}),
.rx_ptp_ts('{1{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{1{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{1{1'b0}}),
.tx_lfc_resend('{1{1'b0}}),
.rx_lfc_en('{1{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{1{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{1{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{1{1'b0}}),
.rx_pfc_en('{1{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{1{'0}}),
@@ -504,8 +514,8 @@ end else begin : sfp_mac
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{1{1'b0}}),
.tx_pause_req('{1{1'b0}}),
.tx_pause_ack(),
/*
@@ -550,7 +560,7 @@ end else begin : sfp_mac
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{1{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -575,42 +585,42 @@ end else begin : sfp_mac
*/
.cfg_tx_max_pkt_len('{1{16'd9218}}),
.cfg_tx_ifg('{1{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{1{1'b1}}),
.cfg_rx_max_pkt_len('{1{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{1{1'b1}}),
.cfg_tx_prbs31_enable('{1{1'b0}}),
.cfg_rx_prbs31_enable('{1{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{1{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{1{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{1{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{1{1'b0}}),
.cfg_mcf_rx_eth_src('{1{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{1{1'b0}}),
.cfg_mcf_rx_eth_type('{1{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{1{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{1{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{1{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{1{1'b1}}),
.cfg_mcf_rx_forward('{1{1'b0}}),
.cfg_mcf_rx_enable('{1{1'b0}}),
.cfg_tx_lfc_eth_dst('{1{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{1{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{1{16'h8808}}),
.cfg_tx_lfc_opcode('{1{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{1{1'b0}}),
.cfg_tx_lfc_quanta('{1{16'hffff}}),
.cfg_tx_lfc_refresh('{1{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{1{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{1{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{1{16'h8808}}),
.cfg_tx_pfc_opcode('{1{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{1{1'b0}}),
.cfg_tx_pfc_quanta('{1{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{1{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{1{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{1{1'b0}}),
.cfg_rx_pfc_opcode('{1{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{1{1'b0}})
);
taxi_axis_async_fifo #(
@@ -627,15 +637,15 @@ end else begin : sfp_mac
/*
* AXI4-Stream input (sink)
*/
.s_clk(sfp_rx_clk),
.s_rst(sfp_rx_rst),
.s_clk(sfp_rx_clk[0]),
.s_rst(sfp_rx_rst[0]),
.s_axis(axis_sfp_rx[0]),
/*
* AXI4-Stream output (source)
*/
.m_clk(sfp_tx_clk),
.m_rst(sfp_tx_rst),
.m_clk(sfp_tx_clk[0]),
.m_rst(sfp_tx_rst[0]),
.m_axis(axis_sfp_tx[0]),
/*

16
src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga.sv
View File

@@ -33,10 +33,10 @@ module fpga #
/*
* Ethernet: SFP+
*/
output wire logic [3:0] qsfp_0_tx_p,
output wire logic [3:0] qsfp_0_tx_n,
input wire logic [3:0] qsfp_0_rx_p,
input wire logic [3:0] qsfp_0_rx_n,
output wire logic qsfp_0_tx_p[4],
output wire logic qsfp_0_tx_n[4],
input wire logic qsfp_0_rx_p[4],
input wire logic qsfp_0_rx_n[4],
input wire logic qsfp_mgt_refclk_p,
input wire logic qsfp_mgt_refclk_n,
output wire logic qsfp_0_modsell,
@@ -45,10 +45,10 @@ module fpga #
input wire logic qsfp_0_intl,
output wire logic qsfp_0_lpmode,
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
output wire logic qsfp_1_modsell,
output wire logic qsfp_1_resetl,
input wire logic qsfp_1_modprsl,

103
src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv
View File

@@ -40,10 +40,10 @@ module fpga_core #
/*
* Ethernet: SFP+
*/
output wire logic [3:0] qsfp_0_tx_p,
output wire logic [3:0] qsfp_0_tx_n,
input wire logic [3:0] qsfp_0_rx_p,
input wire logic [3:0] qsfp_0_rx_n,
output wire logic qsfp_0_tx_p[4],
output wire logic qsfp_0_tx_n[4],
input wire logic qsfp_0_rx_p[4],
input wire logic qsfp_0_rx_n[4],
input wire logic qsfp_mgt_refclk_p,
input wire logic qsfp_mgt_refclk_n,
output wire logic qsfp_mgt_refclk_out,
@@ -53,10 +53,10 @@ module fpga_core #
input wire logic qsfp_0_intl,
output wire logic qsfp_0_lpmode,
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
output wire logic qsfp_1_modsell,
output wire logic qsfp_1_resetl,
input wire logic qsfp_1_modprsl,
@@ -73,12 +73,12 @@ assign qsfp_1_modsell = 1'b0;
assign qsfp_1_resetl = 1'b1;
assign qsfp_1_lpmode = 1'b0;
wire [7:0] qsfp_tx_clk;
wire [7:0] qsfp_tx_rst;
wire [7:0] qsfp_rx_clk;
wire [7:0] qsfp_rx_rst;
wire qsfp_tx_clk[8];
wire qsfp_tx_rst[8];
wire qsfp_rx_clk[8];
wire qsfp_rx_rst[8];
wire [7:0] qsfp_rx_status;
wire qsfp_rx_status[8];
assign qsfp_led_green[0] = qsfp_rx_status[0];
assign qsfp_led_orange[0] = 1'b0;
@@ -139,15 +139,20 @@ qsfp_sync_reset_inst (
.out(qsfp_rst)
);
wire [7:0] qsfp_tx_p;
wire [7:0] qsfp_tx_n;
wire [7:0] qsfp_rx_p = {qsfp_1_rx_p, qsfp_0_rx_p};
wire [7:0] qsfp_rx_n = {qsfp_1_rx_n, qsfp_0_rx_n};
wire qsfp_tx_p[8];
wire qsfp_tx_n[8];
wire qsfp_rx_p[8];
wire qsfp_rx_n[8];
assign qsfp_0_tx_p = qsfp_tx_p[3:0];
assign qsfp_0_tx_n = qsfp_tx_n[3:0];
assign qsfp_1_tx_p = qsfp_tx_p[7:4];
assign qsfp_1_tx_n = qsfp_tx_n[7:4];
assign qsfp_0_tx_p = qsfp_tx_p[4*0 +: 4];
assign qsfp_0_tx_n = qsfp_tx_n[4*0 +: 4];
assign qsfp_1_tx_p = qsfp_tx_p[4*1 +: 4];
assign qsfp_1_tx_n = qsfp_tx_n[4*1 +: 4];
assign qsfp_rx_p[4*0 +: 4] = qsfp_0_rx_p;
assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
@@ -218,12 +223,12 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(qsfp_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]),
.tx_clk(qsfp_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -240,24 +245,24 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -265,8 +270,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -311,7 +316,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -336,42 +341,42 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

96
src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv
View File

@@ -26,38 +26,38 @@ module fpga_core #
* Clock: 125MHz
* Synchronous reset
*/
input wire logic clk_125mhz,
input wire logic rst_125mhz,
input wire logic clk_125mhz,
input wire logic rst_125mhz,
/*
* GPIO
*/
output wire logic [1:0][1:0] sfp_led,
output wire logic [1:0] sma_led,
output wire logic [1:0] sfp_led[2],
output wire logic [1:0] sma_led,
/*
* Ethernet: SFP+
*/
input wire logic [1:0] sfp_rx_p,
input wire logic [1:0] sfp_rx_n,
output wire logic [1:0] sfp_tx_p,
output wire logic [1:0] sfp_tx_n,
input wire logic sfp_mgt_refclk_p,
input wire logic sfp_mgt_refclk_n,
output wire logic sfp_mgt_refclk_out,
output wire logic [1:0] sfp_tx_disable,
input wire logic [1:0] sfp_npres,
input wire logic [1:0] sfp_los,
output wire logic [1:0] sfp_rs
input wire logic sfp_rx_p[2],
input wire logic sfp_rx_n[2],
output wire logic sfp_tx_p[2],
output wire logic sfp_tx_n[2],
input wire logic sfp_mgt_refclk_p,
input wire logic sfp_mgt_refclk_n,
output wire logic sfp_mgt_refclk_out,
output wire logic [1:0] sfp_tx_disable,
input wire logic [1:0] sfp_npres,
input wire logic [1:0] sfp_los,
output wire logic [1:0] sfp_rs
);
// SFP+
wire [1:0] sfp_tx_clk;
wire [1:0] sfp_tx_rst;
wire [1:0] sfp_rx_clk;
wire [1:0] sfp_rx_rst;
wire sfp_tx_clk[2];
wire sfp_tx_rst[2];
wire sfp_rx_clk[2];
wire sfp_rx_rst[2];
wire [1:0] sfp_rx_status;
wire sfp_rx_status[2];
assign sfp_led[0][0] = sfp_rx_status[0];
assign sfp_led[0][1] = 1'b0;
@@ -199,12 +199,12 @@ sfp_mac_inst (
* MAC clocks
*/
.rx_clk(sfp_rx_clk),
.rx_rst_in('0),
.rx_rst_in('{2{1'b0}}),
.rx_rst_out(sfp_rx_rst),
.tx_clk(sfp_tx_clk),
.tx_rst_in('0),
.tx_rst_in('{2{1'b0}}),
.tx_rst_out(sfp_tx_rst),
.ptp_sample_clk('0),
.ptp_sample_clk('{2{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -221,24 +221,24 @@ sfp_mac_inst (
* PTP clock
*/
.tx_ptp_ts('{2{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{2{1'b0}}),
.rx_ptp_ts('{2{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{2{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{2{1'b0}}),
.tx_lfc_resend('{2{1'b0}}),
.rx_lfc_en('{2{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{2{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{2{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{2{1'b0}}),
.rx_pfc_en('{2{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{2{'0}}),
@@ -246,8 +246,8 @@ sfp_mac_inst (
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{2{1'b0}}),
.tx_pause_req('{2{1'b0}}),
.tx_pause_ack(),
/*
@@ -292,7 +292,7 @@ sfp_mac_inst (
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{2{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -317,42 +317,42 @@ sfp_mac_inst (
*/
.cfg_tx_max_pkt_len('{2{16'd9218}}),
.cfg_tx_ifg('{2{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{2{1'b1}}),
.cfg_rx_max_pkt_len('{2{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{2{1'b1}}),
.cfg_tx_prbs31_enable('{2{1'b0}}),
.cfg_rx_prbs31_enable('{2{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{2{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{2{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{2{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{2{1'b0}}),
.cfg_mcf_rx_eth_src('{2{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{2{1'b0}}),
.cfg_mcf_rx_eth_type('{2{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{2{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{2{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{2{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{2{1'b1}}),
.cfg_mcf_rx_forward('{2{1'b0}}),
.cfg_mcf_rx_enable('{2{1'b0}}),
.cfg_tx_lfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{2{16'h8808}}),
.cfg_tx_lfc_opcode('{2{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{2{1'b0}}),
.cfg_tx_lfc_quanta('{2{16'hffff}}),
.cfg_tx_lfc_refresh('{2{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{2{16'h8808}}),
.cfg_tx_pfc_opcode('{2{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{2{1'b0}}),
.cfg_tx_pfc_quanta('{2{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{2{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{2{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{2{1'b0}}),
.cfg_rx_pfc_opcode('{2{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{2{1'b0}})
);
for (genvar n = 0; n < 2; n = n + 1) begin : sfp_ch

28
src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_k35.sv
View File

@@ -25,28 +25,28 @@ module fpga #
/*
* Clock: 100MHz LVDS
*/
input wire logic clk_100mhz_p,
input wire logic clk_100mhz_n,
input wire logic clk_100mhz_p,
input wire logic clk_100mhz_n,
/*
* GPIO
*/
output wire logic [1:0][1:0] sfp_led,
output wire logic [1:0] sma_led,
output wire logic [1:0] sfp_led[2],
output wire logic [1:0] sma_led,
/*
* Ethernet: SFP+
*/
input wire logic [1:0] sfp_rx_p,
input wire logic [1:0] sfp_rx_n,
output wire logic [1:0] sfp_tx_p,
output wire logic [1:0] sfp_tx_n,
input wire logic sfp_mgt_refclk_p,
input wire logic sfp_mgt_refclk_n,
output wire logic [1:0] sfp_tx_disable,
input wire logic [1:0] sfp_npres,
input wire logic [1:0] sfp_los,
output wire logic [1:0] sfp_rs
input wire logic sfp_rx_p[2],
input wire logic sfp_rx_n[2],
output wire logic sfp_tx_p[2],
output wire logic sfp_tx_n[2],
input wire logic sfp_mgt_refclk_p,
input wire logic sfp_mgt_refclk_n,
output wire logic [1:0] sfp_tx_disable,
input wire logic [1:0] sfp_npres,
input wire logic [1:0] sfp_los,
output wire logic [1:0] sfp_rs
);
// Clock and reset

24
src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_k3p.sv
View File

@@ -25,22 +25,22 @@ module fpga #
/*
* GPIO
*/
output wire logic [1:0][1:0] sfp_led,
output wire logic [1:0] sma_led,
output wire logic [1:0] sfp_led[2],
output wire logic [1:0] sma_led,
/*
* Ethernet: SFP+
*/
input wire logic [1:0] sfp_rx_p,
input wire logic [1:0] sfp_rx_n,
output wire logic [1:0] sfp_tx_p,
output wire logic [1:0] sfp_tx_n,
input wire logic sfp_mgt_refclk_p,
input wire logic sfp_mgt_refclk_n,
output wire logic [1:0] sfp_tx_disable,
input wire logic [1:0] sfp_npres,
input wire logic [1:0] sfp_los,
output wire logic [1:0] sfp_rs
input wire logic sfp_rx_p[2],
input wire logic sfp_rx_n[2],
output wire logic sfp_tx_p[2],
output wire logic sfp_tx_n[2],
input wire logic sfp_mgt_refclk_p,
input wire logic sfp_mgt_refclk_n,
output wire logic [1:0] sfp_tx_disable,
input wire logic [1:0] sfp_npres,
input wire logic [1:0] sfp_los,
output wire logic [1:0] sfp_rs
);
// Clock and reset

8
src/eth/example/VCU108/fpga/rtl/fpga.sv
View File

@@ -64,10 +64,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
input wire logic [3:0] qsfp_rx_p,
input wire logic [3:0] qsfp_rx_n,
output wire logic [3:0] qsfp_tx_p,
output wire logic [3:0] qsfp_tx_n,
input wire logic qsfp_rx_p[4],
input wire logic qsfp_rx_n[4],
output wire logic qsfp_tx_p[4],
output wire logic qsfp_tx_n[4],
input wire logic qsfp_mgt_refclk_0_p,
input wire logic qsfp_mgt_refclk_0_n,
// input wire logic qsfp_mgt_refclk_1_p,

83
src/eth/example/VCU108/fpga/rtl/fpga_core.sv
View File

@@ -66,10 +66,10 @@ module fpga_core #
/*
* Ethernet: QSFP28
*/
input wire logic [3:0] qsfp_rx_p,
input wire logic [3:0] qsfp_rx_n,
output wire logic [3:0] qsfp_tx_p,
output wire logic [3:0] qsfp_tx_n,
input wire logic qsfp_rx_p[4],
input wire logic qsfp_rx_n[4],
output wire logic qsfp_tx_p[4],
output wire logic qsfp_tx_n[4],
input wire logic qsfp_mgt_refclk_0_p,
input wire logic qsfp_mgt_refclk_0_n,
// input wire logic qsfp_mgt_refclk_1_p,
@@ -282,14 +282,21 @@ assign qsfp_modsell = 1'b0;
assign qsfp_resetl = 1'b1;
assign qsfp_lpmode = 1'b0;
wire [3:0] qsfp_tx_clk;
wire [3:0] qsfp_tx_rst;
wire [3:0] qsfp_rx_clk;
wire [3:0] qsfp_rx_rst;
wire qsfp_tx_clk[4];
wire qsfp_tx_rst[4];
wire qsfp_rx_clk[4];
wire qsfp_rx_rst[4];
wire [3:0] qsfp_rx_status;
wire qsfp_rx_status[4];
assign led = {qsfp_rx_status, qsfp_rx_rst};
assign led[0] = qsfp_rx_rst[0];
assign led[1] = qsfp_rx_rst[1];
assign led[2] = qsfp_rx_rst[2];
assign led[3] = qsfp_rx_rst[3];
assign led[4] = qsfp_rx_status[0];
assign led[5] = qsfp_rx_status[1];
assign led[6] = qsfp_rx_status[2];
assign led[7] = qsfp_rx_status[3];
wire qsfp_gtpowergood;
@@ -408,12 +415,12 @@ qsfp_mac_inst (
* MAC clocks
*/
.rx_clk(qsfp_rx_clk),
.rx_rst_in('0),
.rx_rst_in('{4{1'b0}}),
.rx_rst_out(qsfp_rx_rst),
.tx_clk(qsfp_tx_clk),
.tx_rst_in('0),
.tx_rst_in('{4{1'b0}}),
.tx_rst_out(qsfp_tx_rst),
.ptp_sample_clk('0),
.ptp_sample_clk('{4{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -430,24 +437,24 @@ qsfp_mac_inst (
* PTP clock
*/
.tx_ptp_ts('{4{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{4{1'b0}}),
.rx_ptp_ts('{4{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{4{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{4{1'b0}}),
.tx_lfc_resend('{4{1'b0}}),
.rx_lfc_en('{4{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{4{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{4{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{4{1'b0}}),
.rx_pfc_en('{4{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{4{'0}}),
@@ -455,8 +462,8 @@ qsfp_mac_inst (
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{4{1'b0}}),
.tx_pause_req('{4{1'b0}}),
.tx_pause_ack(),
/*
@@ -501,7 +508,7 @@ qsfp_mac_inst (
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{4{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -526,42 +533,42 @@ qsfp_mac_inst (
*/
.cfg_tx_max_pkt_len('{4{16'd9218}}),
.cfg_tx_ifg('{4{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{4{1'b1}}),
.cfg_rx_max_pkt_len('{4{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{4{1'b1}}),
.cfg_tx_prbs31_enable('{4{1'b0}}),
.cfg_rx_prbs31_enable('{4{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{4{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{4{1'b0}}),
.cfg_mcf_rx_eth_src('{4{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{4{1'b0}}),
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{4{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{4{1'b1}}),
.cfg_mcf_rx_forward('{4{1'b0}}),
.cfg_mcf_rx_enable('{4{1'b0}}),
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
.cfg_tx_lfc_opcode('{4{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{4{1'b0}}),
.cfg_tx_lfc_quanta('{4{16'hffff}}),
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
.cfg_tx_pfc_opcode('{4{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{4{1'b0}}),
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{4{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{4{1'b0}}),
.cfg_rx_pfc_opcode('{4{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{4{1'b0}})
);
for (genvar n = 0; n < 4; n = n + 1) begin : qsfp_ch

16
src/eth/example/VCU118/fpga/rtl/fpga.sv
View File

@@ -72,10 +72,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_0_p,
input wire logic qsfp1_mgt_refclk_0_n,
// input wire logic qsfp1_mgt_refclk_1_p,
@@ -88,10 +88,10 @@ module fpga #
input wire logic qsfp1_intl,
output wire logic qsfp1_lpmode,
output wire logic [3:0] qsfp2_tx_p,
output wire logic [3:0] qsfp2_tx_n,
input wire logic [3:0] qsfp2_rx_p,
input wire logic [3:0] qsfp2_rx_n,
output wire logic qsfp2_tx_p[4],
output wire logic qsfp2_tx_n[4],
input wire logic qsfp2_rx_p[4],
input wire logic qsfp2_rx_n[4],
// input wire logic qsfp2_mgt_refclk_0_p,
// input wire logic qsfp2_mgt_refclk_0_n,
// input wire logic qsfp2_mgt_refclk_1_p,

108
src/eth/example/VCU118/fpga/rtl/fpga_core.sv
View File

@@ -70,10 +70,10 @@ module fpga_core #
/*
* Ethernet: QSFP28
*/
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_mgt_refclk_0_p,
input wire logic qsfp1_mgt_refclk_0_n,
// input wire logic qsfp1_mgt_refclk_1_p,
@@ -86,10 +86,10 @@ module fpga_core #
input wire logic qsfp1_intl,
output wire logic qsfp1_lpmode,
input wire logic [3:0] qsfp2_rx_p,
input wire logic [3:0] qsfp2_rx_n,
output wire logic [3:0] qsfp2_tx_p,
output wire logic [3:0] qsfp2_tx_n,
input wire logic qsfp2_rx_p[4],
input wire logic qsfp2_rx_n[4],
output wire logic qsfp2_tx_p[4],
output wire logic qsfp2_tx_n[4],
// input wire logic qsfp2_mgt_refclk_0_p,
// input wire logic qsfp2_mgt_refclk_0_n,
// input wire logic qsfp2_mgt_refclk_1_p,
@@ -462,14 +462,16 @@ assign qsfp2_modsell = 1'b0;
assign qsfp2_resetl = 1'b1;
assign qsfp2_lpmode = 1'b0;
wire [7:0] qsfp_tx_clk;
wire [7:0] qsfp_tx_rst;
wire [7:0] qsfp_rx_clk;
wire [7:0] qsfp_rx_rst;
wire qsfp_tx_clk[8];
wire qsfp_tx_rst[8];
wire qsfp_rx_clk[8];
wire qsfp_rx_rst[8];
wire [7:0] qsfp_rx_status;
wire qsfp_rx_status[8];
assign led = qsfp_rx_status;
for (genvar n = 0; n < 8; n = n + 1) begin
assign led[n] = qsfp_rx_status[n];
end
wire [1:0] qsfp_gtpowergood;
@@ -520,15 +522,21 @@ qsfp_sync_reset_inst (
.out(qsfp_rst)
);
wire [7:0] qsfp_tx_p;
wire [7:0] qsfp_tx_n;
wire [7:0] qsfp_rx_p = {qsfp2_rx_p, qsfp1_rx_p};
wire [7:0] qsfp_rx_n = {qsfp2_rx_n, qsfp1_rx_n};
wire qsfp_tx_p[8];
wire qsfp_tx_n[8];
wire qsfp_rx_p[8];
wire qsfp_rx_n[8];
assign qsfp1_tx_p = qsfp_tx_p[4*0 +: 4];
assign qsfp1_tx_n = qsfp_tx_n[4*0 +: 4];
assign qsfp2_tx_p = qsfp_tx_p[4*1 +: 4];
assign qsfp2_tx_n = qsfp_tx_n[4*1 +: 4];
assign qsfp_rx_p[4*0 +: 4] = qsfp1_rx_p;
assign qsfp_rx_n[4*0 +: 4] = qsfp1_rx_n;
assign qsfp_rx_p[4*1 +: 4] = qsfp2_rx_p;
assign qsfp_rx_n[4*1 +: 4] = qsfp2_rx_n;
assign qsfp1_tx_p = qsfp_tx_p[3:0];
assign qsfp1_tx_n = qsfp_tx_n[3:0];
assign qsfp2_tx_p = qsfp_tx_p[7:4];
assign qsfp2_tx_n = qsfp_tx_n[7:4];
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"};
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"};
@@ -604,12 +612,12 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(qsfp_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]),
.tx_clk(qsfp_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -626,24 +634,24 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -651,8 +659,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -697,7 +705,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -722,42 +730,42 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

219
src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv
View File

@@ -19,118 +19,67 @@ module fpga_core #
(
parameter logic SIM = 1'b0,
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtexuplus"
parameter string FAMILY = "virtexuplus",
parameter PORT_CNT = 4,
parameter GTY_QUAD_CNT = PORT_CNT,
parameter GTY_CNT = GTY_QUAD_CNT*4,
parameter GTY_CLK_CNT = GTY_QUAD_CNT
)
(
/*
* Clock: 125 MHz
* Synchronous reset
*/
input wire logic clk_125mhz,
input wire logic rst_125mhz,
input wire logic clk_125mhz,
input wire logic rst_125mhz,
/*
* GPIO
*/
output wire logic led,
output wire logic led,
/*
* UART: 3000000 bps, 8N1
*/
input wire logic uart_rxd,
output wire logic uart_txd,
input wire logic uart_rxd,
output wire logic uart_txd,
/*
* I2C
*/
input wire logic eeprom_i2c_scl_i,
output wire logic eeprom_i2c_scl_o,
input wire logic eeprom_i2c_sda_i,
output wire logic eeprom_i2c_sda_o,
input wire logic eeprom_i2c_scl_i,
output wire logic eeprom_i2c_scl_o,
input wire logic eeprom_i2c_sda_i,
output wire logic eeprom_i2c_sda_o,
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
input wire logic qsfp0_mgt_refclk_b0_p,
input wire logic qsfp0_mgt_refclk_b0_n,
output wire logic eth_gty_tx_p[GTY_CNT],
output wire logic eth_gty_tx_n[GTY_CNT],
input wire logic eth_gty_rx_p[GTY_CNT],
input wire logic eth_gty_rx_n[GTY_CNT],
input wire logic eth_gty_mgt_refclk_p[GTY_CLK_CNT],
input wire logic eth_gty_mgt_refclk_n[GTY_CLK_CNT],
output wire logic eth_gty_mgt_refclk_out[GTY_CLK_CNT],
output wire logic qsfp0_resetl,
input wire logic qsfp0_modprsl,
input wire logic qsfp0_intl,
output wire logic qsfp0_lpmode,
output wire logic [PORT_CNT-1:0] eth_port_resetl,
input wire logic [PORT_CNT-1:0] eth_port_modprsl,
input wire logic [PORT_CNT-1:0] eth_port_intl,
output wire logic [PORT_CNT-1:0] eth_port_lpmode,
input wire logic qsfp0_i2c_scl_i,
output wire logic qsfp0_i2c_scl_o,
input wire logic qsfp0_i2c_sda_i,
output wire logic qsfp0_i2c_sda_o,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
input wire logic qsfp1_mgt_refclk_b0_p,
input wire logic qsfp1_mgt_refclk_b0_n,
output wire logic qsfp1_resetl,
input wire logic qsfp1_modprsl,
input wire logic qsfp1_intl,
output wire logic qsfp1_lpmode,
input wire logic qsfp1_i2c_scl_i,
output wire logic qsfp1_i2c_scl_o,
input wire logic qsfp1_i2c_sda_i,
output wire logic qsfp1_i2c_sda_o,
output wire logic [3:0] qsfp2_tx_p,
output wire logic [3:0] qsfp2_tx_n,
input wire logic [3:0] qsfp2_rx_p,
input wire logic [3:0] qsfp2_rx_n,
input wire logic qsfp2_mgt_refclk_b0_p,
input wire logic qsfp2_mgt_refclk_b0_n,
output wire logic qsfp2_resetl,
input wire logic qsfp2_modprsl,
input wire logic qsfp2_intl,
output wire logic qsfp2_lpmode,
input wire logic qsfp2_i2c_scl_i,
output wire logic qsfp2_i2c_scl_o,
input wire logic qsfp2_i2c_sda_i,
output wire logic qsfp2_i2c_sda_o,
output wire logic [3:0] qsfp3_tx_p,
output wire logic [3:0] qsfp3_tx_n,
input wire logic [3:0] qsfp3_rx_p,
input wire logic [3:0] qsfp3_rx_n,
input wire logic qsfp3_mgt_refclk_b0_p,
input wire logic qsfp3_mgt_refclk_b0_n,
output wire logic qsfp3_resetl,
input wire logic qsfp3_modprsl,
input wire logic qsfp3_intl,
output wire logic qsfp3_lpmode,
input wire logic qsfp3_i2c_scl_i,
output wire logic qsfp3_i2c_scl_o,
input wire logic qsfp3_i2c_sda_i,
output wire logic qsfp3_i2c_sda_o
input wire logic [PORT_CNT-1:0] eth_port_i2c_scl_i,
output wire logic [PORT_CNT-1:0] eth_port_i2c_scl_o,
input wire logic [PORT_CNT-1:0] eth_port_i2c_sda_i,
output wire logic [PORT_CNT-1:0] eth_port_i2c_sda_o
);
assign eeprom_i2c_scl_o = 1'b1;
assign eeprom_i2c_sda_o = 1'b1;
assign qsfp0_i2c_scl_o = 1'b1;
assign qsfp0_i2c_sda_o = 1'b1;
assign qsfp1_i2c_scl_o = 1'b1;
assign qsfp1_i2c_sda_o = 1'b1;
assign qsfp2_i2c_scl_o = 1'b1;
assign qsfp2_i2c_sda_o = 1'b1;
assign qsfp3_i2c_scl_o = 1'b1;
assign qsfp3_i2c_sda_o = 1'b1;
assign eth_port_i2c_scl_o = '1;
assign eth_port_i2c_sda_o = '1;
// XFCP
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
@@ -211,7 +160,7 @@ xfcp_stats_inst (
.s_axis_stat(axis_stat)
);
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[4]();
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[GTY_QUAD_CNT]();
taxi_axis_arb_mux #(
.S_COUNT($size(axis_eth_stat)),
@@ -235,52 +184,26 @@ stat_mux_inst (
);
// QSFP28
assign qsfp0_resetl = 1'b1;
assign qsfp0_lpmode = 1'b0;
assign qsfp1_resetl = 1'b1;
assign qsfp1_lpmode = 1'b0;
assign qsfp2_resetl = 1'b1;
assign qsfp2_lpmode = 1'b0;
assign qsfp3_resetl = 1'b1;
assign qsfp3_lpmode = 1'b0;
assign eth_port_resetl = '1;
assign eth_port_lpmode = '0;
localparam GTY_QUAD_CNT = 4;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire [GTY_CNT-1:0] eth_gty_tx_p;
wire [GTY_CNT-1:0] eth_gty_tx_n;
wire [GTY_CNT-1:0] eth_gty_rx_p = {qsfp3_rx_p, qsfp2_rx_p, qsfp1_rx_p, qsfp0_rx_p};
wire [GTY_CNT-1:0] eth_gty_rx_n = {qsfp3_rx_n, qsfp2_rx_n, qsfp1_rx_n, qsfp0_rx_n};
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p = {qsfp3_mgt_refclk_b0_p, qsfp2_mgt_refclk_b0_p, qsfp1_mgt_refclk_b0_p, qsfp0_mgt_refclk_b0_p};
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n = {qsfp3_mgt_refclk_b0_n, qsfp2_mgt_refclk_b0_n, qsfp1_mgt_refclk_b0_n, qsfp0_mgt_refclk_b0_n};
assign qsfp0_tx_p = eth_gty_tx_p[3:0];
assign qsfp0_tx_n = eth_gty_tx_n[3:0];
assign qsfp1_tx_p = eth_gty_tx_p[7:4];
assign qsfp1_tx_n = eth_gty_tx_n[7:4];
assign qsfp2_tx_p = eth_gty_tx_p[11:8];
assign qsfp2_tx_n = eth_gty_tx_n[11:8];
assign qsfp3_tx_p = eth_gty_tx_p[15:12];
assign qsfp3_tx_n = eth_gty_tx_n[15:12];
wire [GTY_CNT-1:0] eth_gty_tx_clk;
wire [GTY_CNT-1:0] eth_gty_tx_rst;
wire eth_gty_tx_clk[GTY_CNT];
wire eth_gty_tx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_clk;
wire [GTY_CNT-1:0] eth_gty_rx_rst;
wire eth_gty_rx_clk[GTY_CNT];
wire eth_gty_rx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_status;
wire eth_gty_rx_status[GTY_CNT];
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
wire eth_gty_mgt_refclk[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
wire eth_gty_rst[GTY_CLK_CNT];
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
@@ -417,12 +340,12 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -439,24 +362,24 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -464,8 +387,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -510,7 +433,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -535,42 +458,42 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

160
src/eth/example/XUPP3R/fpga/rtl/fpga_xupp3r.sv
View File

@@ -50,10 +50,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_b0_p,
input wire logic qsfp0_mgt_refclk_b0_n,
// input wire logic qsfp0_mgt_refclk_b1_p,
@@ -69,10 +69,10 @@ module fpga #
inout wire logic qsfp0_i2c_scl,
inout wire logic qsfp0_i2c_sda,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_b0_p,
input wire logic qsfp1_mgt_refclk_b0_n,
// input wire logic qsfp1_mgt_refclk_b1_p,
@@ -88,10 +88,10 @@ module fpga #
inout wire logic qsfp1_i2c_scl,
inout wire logic qsfp1_i2c_sda,
output wire logic [3:0] qsfp2_tx_p,
output wire logic [3:0] qsfp2_tx_n,
input wire logic [3:0] qsfp2_rx_p,
input wire logic [3:0] qsfp2_rx_n,
output wire logic qsfp2_tx_p[4],
output wire logic qsfp2_tx_n[4],
input wire logic qsfp2_rx_p[4],
input wire logic qsfp2_rx_n[4],
input wire logic qsfp2_mgt_refclk_b0_p,
input wire logic qsfp2_mgt_refclk_b0_n,
// input wire logic qsfp2_mgt_refclk_b2_p,
@@ -107,10 +107,10 @@ module fpga #
inout wire logic qsfp2_i2c_scl,
inout wire logic qsfp2_i2c_sda,
output wire logic [3:0] qsfp3_tx_p,
output wire logic [3:0] qsfp3_tx_n,
input wire logic [3:0] qsfp3_rx_p,
input wire logic [3:0] qsfp3_rx_n,
output wire logic qsfp3_tx_p[4],
output wire logic qsfp3_tx_n[4],
input wire logic qsfp3_rx_p[4],
input wire logic qsfp3_rx_n[4],
input wire logic qsfp3_mgt_refclk_b0_p,
input wire logic qsfp3_mgt_refclk_b0_n,
// input wire logic qsfp3_mgt_refclk_b3_p,
@@ -336,10 +336,56 @@ assign qsfp2_i2c_sda = qsfp2_i2c_sda_o_reg ? 1'bz : 1'b0;
assign qsfp3_i2c_scl = qsfp3_i2c_scl_o_reg ? 1'bz : 1'b0;
assign qsfp3_i2c_sda = qsfp3_i2c_sda_o_reg ? 1'bz : 1'b0;
localparam PORT_CNT = 4;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign qsfp2_tx_p = eth_gty_tx_p[4*2 +: 4];
assign qsfp2_tx_n = eth_gty_tx_n[4*2 +: 4];
assign eth_gty_rx_p[4*2 +: 4] = qsfp2_rx_p;
assign eth_gty_rx_n[4*2 +: 4] = qsfp2_rx_n;
assign qsfp3_tx_p = eth_gty_tx_p[4*3 +: 4];
assign qsfp3_tx_n = eth_gty_tx_n[4*3 +: 4];
assign eth_gty_rx_p[4*3 +: 4] = qsfp3_rx_p;
assign eth_gty_rx_n[4*3 +: 4] = qsfp3_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[2] = qsfp2_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[2] = qsfp2_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[3] = qsfp3_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[3] = qsfp3_mgt_refclk_b0_n;
fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY)
.FAMILY(FAMILY),
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -371,73 +417,23 @@ core_inst (
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_p(qsfp0_tx_p),
.qsfp0_tx_n(qsfp0_tx_n),
.qsfp0_rx_p(qsfp0_rx_p),
.qsfp0_rx_n(qsfp0_rx_n),
.qsfp0_mgt_refclk_b0_p(qsfp0_mgt_refclk_b0_p),
.qsfp0_mgt_refclk_b0_n(qsfp0_mgt_refclk_b0_n),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.qsfp0_modprsl(qsfp0_modprsl_int),
.qsfp0_resetl(qsfp0_resetl),
.qsfp0_intl(qsfp0_intl_int),
.qsfp0_lpmode(qsfp0_lpmode),
.eth_port_resetl({qsfp3_resetl, qsfp2_resetl, qsfp1_resetl, qsfp0_resetl}),
.eth_port_modprsl({qsfp3_modprsl, qsfp2_modprsl, qsfp1_modprsl, qsfp0_modprsl}),
.eth_port_intl({qsfp3_intl, qsfp2_intl, qsfp1_intl, qsfp0_intl}),
.eth_port_lpmode({qsfp3_lpmode, qsfp2_lpmode, qsfp1_lpmode, qsfp0_lpmode}),
.qsfp0_i2c_scl_i(qsfp0_i2c_scl_i),
.qsfp0_i2c_scl_o(qsfp0_i2c_scl_o),
.qsfp0_i2c_sda_i(qsfp0_i2c_sda_i),
.qsfp0_i2c_sda_o(qsfp0_i2c_sda_o),
.qsfp1_tx_p(qsfp1_tx_p),
.qsfp1_tx_n(qsfp1_tx_n),
.qsfp1_rx_p(qsfp1_rx_p),
.qsfp1_rx_n(qsfp1_rx_n),
.qsfp1_mgt_refclk_b0_p(qsfp1_mgt_refclk_b0_p),
.qsfp1_mgt_refclk_b0_n(qsfp1_mgt_refclk_b0_n),
.qsfp1_modprsl(qsfp1_modprsl_int),
.qsfp1_resetl(qsfp1_resetl),
.qsfp1_intl(qsfp1_intl_int),
.qsfp1_lpmode(qsfp1_lpmode),
.qsfp1_i2c_scl_i(qsfp1_i2c_scl_i),
.qsfp1_i2c_scl_o(qsfp1_i2c_scl_o),
.qsfp1_i2c_sda_i(qsfp1_i2c_sda_i),
.qsfp1_i2c_sda_o(qsfp1_i2c_sda_o),
.qsfp2_tx_p(qsfp2_tx_p),
.qsfp2_tx_n(qsfp2_tx_n),
.qsfp2_rx_p(qsfp2_rx_p),
.qsfp2_rx_n(qsfp2_rx_n),
.qsfp2_mgt_refclk_b0_p(qsfp2_mgt_refclk_b0_p),
.qsfp2_mgt_refclk_b0_n(qsfp2_mgt_refclk_b0_n),
.qsfp2_modprsl(qsfp2_modprsl_int),
.qsfp2_resetl(qsfp2_resetl),
.qsfp2_intl(qsfp2_intl_int),
.qsfp2_lpmode(qsfp2_lpmode),
.qsfp2_i2c_scl_i(qsfp2_i2c_scl_i),
.qsfp2_i2c_scl_o(qsfp2_i2c_scl_o),
.qsfp2_i2c_sda_i(qsfp2_i2c_sda_i),
.qsfp2_i2c_sda_o(qsfp2_i2c_sda_o),
.qsfp3_tx_p(qsfp3_tx_p),
.qsfp3_tx_n(qsfp3_tx_n),
.qsfp3_rx_p(qsfp3_rx_p),
.qsfp3_rx_n(qsfp3_rx_n),
.qsfp3_mgt_refclk_b0_p(qsfp3_mgt_refclk_b0_p),
.qsfp3_mgt_refclk_b0_n(qsfp3_mgt_refclk_b0_n),
.qsfp3_modprsl(qsfp3_modprsl_int),
.qsfp3_resetl(qsfp3_resetl),
.qsfp3_intl(qsfp3_intl_int),
.qsfp3_lpmode(qsfp3_lpmode),
.qsfp3_i2c_scl_i(qsfp3_i2c_scl_i),
.qsfp3_i2c_scl_o(qsfp3_i2c_scl_o),
.qsfp3_i2c_sda_i(qsfp3_i2c_sda_i),
.qsfp3_i2c_sda_o(qsfp3_i2c_sda_o)
.eth_port_i2c_scl_i({qsfp3_i2c_scl_i, qsfp2_i2c_scl_i, qsfp1_i2c_scl_i, qsfp0_i2c_scl_i}),
.eth_port_i2c_scl_o({qsfp3_i2c_scl_o, qsfp2_i2c_scl_o, qsfp1_i2c_scl_o, qsfp0_i2c_scl_o}),
.eth_port_i2c_sda_i({qsfp3_i2c_sda_i, qsfp2_i2c_sda_i, qsfp1_i2c_sda_i, qsfp0_i2c_sda_i}),
.eth_port_i2c_sda_o({qsfp3_i2c_sda_o, qsfp2_i2c_sda_o, qsfp1_i2c_sda_o, qsfp0_i2c_sda_o})
);
endmodule

160
src/eth/example/XUPP3R/fpga/rtl/fpga_xusp3s.sv
View File

@@ -50,10 +50,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_b0_p,
input wire logic qsfp0_mgt_refclk_b0_n,
// input wire logic qsfp0_mgt_refclk_b1_p,
@@ -69,10 +69,10 @@ module fpga #
inout wire logic qsfp0_i2c_scl,
inout wire logic qsfp0_i2c_sda,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_b0_p,
input wire logic qsfp1_mgt_refclk_b0_n,
// input wire logic qsfp1_mgt_refclk_b1_p,
@@ -88,10 +88,10 @@ module fpga #
inout wire logic qsfp1_i2c_scl,
inout wire logic qsfp1_i2c_sda,
output wire logic [3:0] qsfp2_tx_p,
output wire logic [3:0] qsfp2_tx_n,
input wire logic [3:0] qsfp2_rx_p,
input wire logic [3:0] qsfp2_rx_n,
output wire logic qsfp2_tx_p[4],
output wire logic qsfp2_tx_n[4],
input wire logic qsfp2_rx_p[4],
input wire logic qsfp2_rx_n[4],
input wire logic qsfp2_mgt_refclk_b0_p,
input wire logic qsfp2_mgt_refclk_b0_n,
// input wire logic qsfp2_mgt_refclk_b2_p,
@@ -107,10 +107,10 @@ module fpga #
inout wire logic qsfp2_i2c_scl,
inout wire logic qsfp2_i2c_sda,
output wire logic [3:0] qsfp3_tx_p,
output wire logic [3:0] qsfp3_tx_n,
input wire logic [3:0] qsfp3_rx_p,
input wire logic [3:0] qsfp3_rx_n,
output wire logic qsfp3_tx_p[4],
output wire logic qsfp3_tx_n[4],
input wire logic qsfp3_rx_p[4],
input wire logic qsfp3_rx_n[4],
input wire logic qsfp3_mgt_refclk_b0_p,
input wire logic qsfp3_mgt_refclk_b0_n,
// input wire logic qsfp3_mgt_refclk_b3_p,
@@ -336,10 +336,56 @@ assign qsfp2_i2c_sda = qsfp2_i2c_sda_o_reg ? 1'bz : 1'b0;
assign qsfp3_i2c_scl = qsfp3_i2c_scl_o_reg ? 1'bz : 1'b0;
assign qsfp3_i2c_sda = qsfp3_i2c_sda_o_reg ? 1'bz : 1'b0;
localparam PORT_CNT = 4;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign qsfp2_tx_p = eth_gty_tx_p[4*2 +: 4];
assign qsfp2_tx_n = eth_gty_tx_n[4*2 +: 4];
assign eth_gty_rx_p[4*2 +: 4] = qsfp2_rx_p;
assign eth_gty_rx_n[4*2 +: 4] = qsfp2_rx_n;
assign qsfp3_tx_p = eth_gty_tx_p[4*3 +: 4];
assign qsfp3_tx_n = eth_gty_tx_n[4*3 +: 4];
assign eth_gty_rx_p[4*3 +: 4] = qsfp3_rx_p;
assign eth_gty_rx_n[4*3 +: 4] = qsfp3_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[2] = qsfp2_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[2] = qsfp2_mgt_refclk_b0_n;
assign eth_gty_mgt_refclk_p[3] = qsfp3_mgt_refclk_b0_p;
assign eth_gty_mgt_refclk_n[3] = qsfp3_mgt_refclk_b0_n;
fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY)
.FAMILY(FAMILY),
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -371,73 +417,23 @@ core_inst (
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_p(qsfp0_tx_p),
.qsfp0_tx_n(qsfp0_tx_n),
.qsfp0_rx_p(qsfp0_rx_p),
.qsfp0_rx_n(qsfp0_rx_n),
.qsfp0_mgt_refclk_b0_p(qsfp0_mgt_refclk_b0_p),
.qsfp0_mgt_refclk_b0_n(qsfp0_mgt_refclk_b0_n),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.qsfp0_modprsl(qsfp0_modprsl_int),
.qsfp0_resetl(qsfp0_resetl),
.qsfp0_intl(qsfp0_intl_int),
.qsfp0_lpmode(qsfp0_lpmode),
.eth_port_resetl({qsfp3_resetl, qsfp2_resetl, qsfp1_resetl, qsfp0_resetl}),
.eth_port_modprsl({qsfp3_modprsl, qsfp2_modprsl, qsfp1_modprsl, qsfp0_modprsl}),
.eth_port_intl({qsfp3_intl, qsfp2_intl, qsfp1_intl, qsfp0_intl}),
.eth_port_lpmode({qsfp3_lpmode, qsfp2_lpmode, qsfp1_lpmode, qsfp0_lpmode}),
.qsfp0_i2c_scl_i(qsfp0_i2c_scl_i),
.qsfp0_i2c_scl_o(qsfp0_i2c_scl_o),
.qsfp0_i2c_sda_i(qsfp0_i2c_sda_i),
.qsfp0_i2c_sda_o(qsfp0_i2c_sda_o),
.qsfp1_tx_p(qsfp1_tx_p),
.qsfp1_tx_n(qsfp1_tx_n),
.qsfp1_rx_p(qsfp1_rx_p),
.qsfp1_rx_n(qsfp1_rx_n),
.qsfp1_mgt_refclk_b0_p(qsfp1_mgt_refclk_b0_p),
.qsfp1_mgt_refclk_b0_n(qsfp1_mgt_refclk_b0_n),
.qsfp1_modprsl(qsfp1_modprsl_int),
.qsfp1_resetl(qsfp1_resetl),
.qsfp1_intl(qsfp1_intl_int),
.qsfp1_lpmode(qsfp1_lpmode),
.qsfp1_i2c_scl_i(qsfp1_i2c_scl_i),
.qsfp1_i2c_scl_o(qsfp1_i2c_scl_o),
.qsfp1_i2c_sda_i(qsfp1_i2c_sda_i),
.qsfp1_i2c_sda_o(qsfp1_i2c_sda_o),
.qsfp2_tx_p(qsfp2_tx_p),
.qsfp2_tx_n(qsfp2_tx_n),
.qsfp2_rx_p(qsfp2_rx_p),
.qsfp2_rx_n(qsfp2_rx_n),
.qsfp2_mgt_refclk_b0_p(qsfp2_mgt_refclk_b0_p),
.qsfp2_mgt_refclk_b0_n(qsfp2_mgt_refclk_b0_n),
.qsfp2_modprsl(qsfp2_modprsl_int),
.qsfp2_resetl(qsfp2_resetl),
.qsfp2_intl(qsfp2_intl_int),
.qsfp2_lpmode(qsfp2_lpmode),
.qsfp2_i2c_scl_i(qsfp2_i2c_scl_i),
.qsfp2_i2c_scl_o(qsfp2_i2c_scl_o),
.qsfp2_i2c_sda_i(qsfp2_i2c_sda_i),
.qsfp2_i2c_sda_o(qsfp2_i2c_sda_o),
.qsfp3_tx_p(qsfp3_tx_p),
.qsfp3_tx_n(qsfp3_tx_n),
.qsfp3_rx_p(qsfp3_rx_p),
.qsfp3_rx_n(qsfp3_rx_n),
.qsfp3_mgt_refclk_b0_p(qsfp3_mgt_refclk_b0_p),
.qsfp3_mgt_refclk_b0_n(qsfp3_mgt_refclk_b0_n),
.qsfp3_modprsl(qsfp3_modprsl_int),
.qsfp3_resetl(qsfp3_resetl),
.qsfp3_intl(qsfp3_intl_int),
.qsfp3_lpmode(qsfp3_lpmode),
.qsfp3_i2c_scl_i(qsfp3_i2c_scl_i),
.qsfp3_i2c_scl_o(qsfp3_i2c_scl_o),
.qsfp3_i2c_sda_i(qsfp3_i2c_sda_i),
.qsfp3_i2c_sda_o(qsfp3_i2c_sda_o)
.eth_port_i2c_scl_i({qsfp3_i2c_scl_i, qsfp2_i2c_scl_i, qsfp1_i2c_scl_i, qsfp0_i2c_scl_i}),
.eth_port_i2c_scl_o({qsfp3_i2c_scl_o, qsfp2_i2c_scl_o, qsfp1_i2c_scl_o, qsfp0_i2c_scl_o}),
.eth_port_i2c_sda_i({qsfp3_i2c_sda_i, qsfp2_i2c_sda_i, qsfp1_i2c_sda_i, qsfp0_i2c_sda_i}),
.eth_port_i2c_sda_o({qsfp3_i2c_sda_o, qsfp2_i2c_sda_o, qsfp1_i2c_sda_o, qsfp0_i2c_sda_o})
);
endmodule

4
src/eth/example/XUPP3R/fpga/tb/fpga_core/Makefile
View File

@@ -41,6 +41,10 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
export PARAM_SIM := "1'b1"
export PARAM_VENDOR := "\"XILINX\""
export PARAM_FAMILY := "\"virtexuplus\""
export PARAM_PORT_CNT := 4
export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT)
export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) )))
export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT)
ifeq ($(SIM), icarus)
PLUSARGS += -fst

11
src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -42,10 +42,6 @@ class TB:
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp0_mgt_refclk_b0_p, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp1_mgt_refclk_b0_p, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp2_mgt_refclk_b0_p, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp3_mgt_refclk_b0_p, 3.102, units="ns").start())
self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)
@@ -53,6 +49,9 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for clk in dut.eth_gty_mgt_refclk_p:
cocotb.start_soon(Clock(clk, 3.102, units="ns").start())
for inst in dut.gty_quad:
for ch in inst.mac_inst.ch:
gt_inst = ch.ch_inst.gt.gt_inst
@@ -216,6 +215,10 @@ def test_fpga_core(request):
parameters['SIM'] = "1'b1"
parameters['VENDOR'] = "\"XILINX\""
parameters['FAMILY'] = "\"virtexuplus\""
parameters['PORT_CNT'] = 4
parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT']
parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4
parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT']
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

12
src/eth/example/ZCU102/fpga/rtl/fpga.sv
View File

@@ -57,10 +57,10 @@ module fpga #
/*
* Ethernet: SFP+
*/
input wire logic [3:0] sfp_rx_p,
input wire logic [3:0] sfp_rx_n,
output wire logic [3:0] sfp_tx_p,
output wire logic [3:0] sfp_tx_n,
input wire logic sfp_rx_p[4],
input wire logic sfp_rx_n[4],
output wire logic sfp_tx_p[4],
output wire logic sfp_tx_n[4],
input wire logic sfp_mgt_refclk_0_p,
input wire logic sfp_mgt_refclk_0_n,
output wire logic [3:0] sfp_tx_disable_b
@@ -243,8 +243,8 @@ sync_signal_inst (
wire [7:0] led_int;
// SFP+
wire [3:0] sfp_tx_p_int;
wire [3:0] sfp_tx_n_int;
wire sfp_tx_p_int[4];
wire sfp_tx_n_int[4];
wire sfp0_gmii_clk_int;
wire sfp0_gmii_rst_int;

74
src/eth/example/ZCU102/fpga/rtl/fpga_core.sv
View File

@@ -56,10 +56,10 @@ module fpga_core #
/*
* Ethernet: SFP+
*/
input wire logic [3:0] sfp_rx_p,
input wire logic [3:0] sfp_rx_n,
output wire logic [3:0] sfp_tx_p,
output wire logic [3:0] sfp_tx_n,
input wire logic sfp_rx_p[4],
input wire logic sfp_rx_n[4],
output wire logic sfp_tx_p[4],
output wire logic sfp_tx_n[4],
input wire logic sfp_mgt_refclk_0_p,
input wire logic sfp_mgt_refclk_0_n,
@@ -559,12 +559,12 @@ if (SFP_RATE == 0) begin : sfp_mac
end else begin : sfp_mac
wire [3:0] sfp_tx_clk;
wire [3:0] sfp_tx_rst;
wire [3:0] sfp_rx_clk;
wire [3:0] sfp_rx_rst;
wire sfp_tx_clk[4];
wire sfp_tx_rst[4];
wire sfp_rx_clk[4];
wire sfp_rx_rst[4];
wire [3:0] sfp_rx_status;
wire sfp_rx_status[4];
wire sfp_gtpowergood;
@@ -683,12 +683,12 @@ end else begin : sfp_mac
* MAC clocks
*/
.rx_clk(sfp_rx_clk),
.rx_rst_in('0),
.rx_rst_in('{4{1'b0}}),
.rx_rst_out(sfp_rx_rst),
.tx_clk(sfp_tx_clk),
.tx_rst_in('0),
.tx_rst_in('{4{1'b0}}),
.tx_rst_out(sfp_tx_rst),
.ptp_sample_clk('0),
.ptp_sample_clk('{4{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -705,24 +705,24 @@ end else begin : sfp_mac
* PTP clock
*/
.tx_ptp_ts('{4{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{4{1'b0}}),
.rx_ptp_ts('{4{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{4{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{4{1'b0}}),
.tx_lfc_resend('{4{1'b0}}),
.rx_lfc_en('{4{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{4{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{4{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{4{1'b0}}),
.rx_pfc_en('{4{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{4{'0}}),
@@ -730,8 +730,8 @@ end else begin : sfp_mac
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{4{1'b0}}),
.tx_pause_req('{4{1'b0}}),
.tx_pause_ack(),
/*
@@ -776,7 +776,7 @@ end else begin : sfp_mac
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{4{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -801,42 +801,42 @@ end else begin : sfp_mac
*/
.cfg_tx_max_pkt_len('{4{16'd9218}}),
.cfg_tx_ifg('{4{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{4{1'b1}}),
.cfg_rx_max_pkt_len('{4{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{4{1'b1}}),
.cfg_tx_prbs31_enable('{4{1'b0}}),
.cfg_rx_prbs31_enable('{4{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{4{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{4{1'b0}}),
.cfg_mcf_rx_eth_src('{4{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{4{1'b0}}),
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{4{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{4{1'b1}}),
.cfg_mcf_rx_forward('{4{1'b0}}),
.cfg_mcf_rx_enable('{4{1'b0}}),
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
.cfg_tx_lfc_opcode('{4{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{4{1'b0}}),
.cfg_tx_lfc_quanta('{4{16'hffff}}),
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
.cfg_tx_pfc_opcode('{4{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{4{1'b0}}),
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{4{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{4{1'b0}}),
.cfg_rx_pfc_opcode('{4{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{4{1'b0}})
);
for (genvar n = 0; n < 4; n = n + 1) begin : sfp_ch

12
src/eth/example/ZCU106/fpga/rtl/fpga.sv
View File

@@ -61,10 +61,10 @@ module fpga #
/*
* Ethernet: SFP+
*/
input wire logic [1:0] sfp_rx_p,
input wire logic [1:0] sfp_rx_n,
output wire logic [1:0] sfp_tx_p,
output wire logic [1:0] sfp_tx_n,
input wire logic sfp_rx_p[2],
input wire logic sfp_rx_n[2],
output wire logic sfp_tx_p[2],
output wire logic sfp_tx_n[2],
input wire logic sfp_mgt_refclk_0_p,
input wire logic sfp_mgt_refclk_0_n,
output wire logic [1:0] sfp_tx_disable_b
@@ -240,8 +240,8 @@ sync_signal_inst (
wire [7:0] led_int;
// SFP+
wire [1:0] sfp_tx_p_int;
wire [1:0] sfp_tx_n_int;
wire sfp_tx_p_int[2];
wire sfp_tx_n_int[2];
wire sfp0_gmii_clk_int;
wire sfp0_gmii_rst_int;

74
src/eth/example/ZCU106/fpga/rtl/fpga_core.sv
View File

@@ -60,10 +60,10 @@ module fpga_core #
/*
* Ethernet: SFP+
*/
input wire logic [1:0] sfp_rx_p,
input wire logic [1:0] sfp_rx_n,
output wire logic [1:0] sfp_tx_p,
output wire logic [1:0] sfp_tx_n,
input wire logic sfp_rx_p[2],
input wire logic sfp_rx_n[2],
output wire logic sfp_tx_p[2],
output wire logic sfp_tx_n[2],
input wire logic sfp_mgt_refclk_0_p,
input wire logic sfp_mgt_refclk_0_n,
@@ -373,12 +373,12 @@ if (SFP_RATE == 0) begin : sfp_mac
end else begin : sfp_mac
wire [1:0] sfp_tx_clk;
wire [1:0] sfp_tx_rst;
wire [1:0] sfp_rx_clk;
wire [1:0] sfp_rx_rst;
wire sfp_tx_clk[2];
wire sfp_tx_rst[2];
wire sfp_rx_clk[2];
wire sfp_rx_rst[2];
wire [1:0] sfp_rx_status;
wire sfp_rx_status[2];
wire sfp_gtpowergood;
@@ -499,12 +499,12 @@ end else begin : sfp_mac
* MAC clocks
*/
.rx_clk(sfp_rx_clk),
.rx_rst_in('0),
.rx_rst_in('{2{1'b0}}),
.rx_rst_out(sfp_rx_rst),
.tx_clk(sfp_tx_clk),
.tx_rst_in('0),
.tx_rst_in('{2{1'b0}}),
.tx_rst_out(sfp_tx_rst),
.ptp_sample_clk('0),
.ptp_sample_clk('{2{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -521,24 +521,24 @@ end else begin : sfp_mac
* PTP clock
*/
.tx_ptp_ts('{2{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{2{1'b0}}),
.rx_ptp_ts('{2{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{2{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{2{1'b0}}),
.tx_lfc_resend('{2{1'b0}}),
.rx_lfc_en('{2{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{2{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{2{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{2{1'b0}}),
.rx_pfc_en('{2{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{2{'0}}),
@@ -546,8 +546,8 @@ end else begin : sfp_mac
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{2{1'b0}}),
.tx_pause_req('{2{1'b0}}),
.tx_pause_ack(),
/*
@@ -592,7 +592,7 @@ end else begin : sfp_mac
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{2{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -617,42 +617,42 @@ end else begin : sfp_mac
*/
.cfg_tx_max_pkt_len('{2{16'd9218}}),
.cfg_tx_ifg('{2{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{2{1'b1}}),
.cfg_rx_max_pkt_len('{2{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{2{1'b1}}),
.cfg_tx_prbs31_enable('{2{1'b0}}),
.cfg_rx_prbs31_enable('{2{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{2{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{2{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{2{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{2{1'b0}}),
.cfg_mcf_rx_eth_src('{2{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{2{1'b0}}),
.cfg_mcf_rx_eth_type('{2{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{2{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{2{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{2{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{2{1'b1}}),
.cfg_mcf_rx_forward('{2{1'b0}}),
.cfg_mcf_rx_enable('{2{1'b0}}),
.cfg_tx_lfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{2{16'h8808}}),
.cfg_tx_lfc_opcode('{2{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{2{1'b0}}),
.cfg_tx_lfc_quanta('{2{16'hffff}}),
.cfg_tx_lfc_refresh('{2{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{2{16'h8808}}),
.cfg_tx_pfc_opcode('{2{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{2{1'b0}}),
.cfg_tx_pfc_quanta('{2{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{2{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{2{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{2{1'b0}}),
.cfg_rx_pfc_opcode('{2{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{2{1'b0}})
);
for (genvar n = 0; n < 2; n = n + 1) begin : sfp_ch

8
src/eth/example/ZCU111/fpga/rtl/fpga.sv
View File

@@ -67,10 +67,10 @@ module fpga #
/*
* Ethernet: SFP+
*/
input wire logic [3:0] sfp_rx_p,
input wire logic [3:0] sfp_rx_n,
output wire logic [3:0] sfp_tx_p,
output wire logic [3:0] sfp_tx_n,
input wire logic sfp_rx_p[4],
input wire logic sfp_rx_n[4],
output wire logic sfp_tx_p[4],
output wire logic sfp_tx_n[4],
input wire logic sfp_mgt_refclk_0_p,
input wire logic sfp_mgt_refclk_0_n,
output wire logic [3:0] sfp_tx_disable_b,

74
src/eth/example/ZCU111/fpga/rtl/fpga_core.sv
View File

@@ -72,10 +72,10 @@ module fpga_core #
/*
* Ethernet: SFP+
*/
input wire logic [3:0] sfp_rx_p,
input wire logic [3:0] sfp_rx_n,
output wire logic [3:0] sfp_tx_p,
output wire logic [3:0] sfp_tx_n,
input wire logic sfp_rx_p[4],
input wire logic sfp_rx_n[4],
output wire logic sfp_tx_p[4],
output wire logic sfp_tx_n[4],
input wire logic sfp_mgt_refclk_0_p,
input wire logic sfp_mgt_refclk_0_n,
@@ -276,12 +276,12 @@ xfcp_mod_axil_inst (
// SFP+
assign sfp_tx_disable_b = '1;
wire [3:0] sfp_tx_clk;
wire [3:0] sfp_tx_rst;
wire [3:0] sfp_rx_clk;
wire [3:0] sfp_rx_rst;
wire sfp_tx_clk[4];
wire sfp_tx_rst[4];
wire sfp_rx_clk[4];
wire sfp_rx_rst[4];
wire [3:0] sfp_rx_status;
wire sfp_rx_status[4];
wire sfp_gtpowergood;
@@ -399,12 +399,12 @@ sfp_mac_inst (
* MAC clocks
*/
.rx_clk(sfp_rx_clk),
.rx_rst_in('0),
.rx_rst_in('{4{1'b0}}),
.rx_rst_out(sfp_rx_rst),
.tx_clk(sfp_tx_clk),
.tx_rst_in('0),
.tx_rst_in('{4{1'b0}}),
.tx_rst_out(sfp_tx_rst),
.ptp_sample_clk('0),
.ptp_sample_clk('{4{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -421,24 +421,24 @@ sfp_mac_inst (
* PTP clock
*/
.tx_ptp_ts('{4{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{4{1'b0}}),
.rx_ptp_ts('{4{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{4{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{4{1'b0}}),
.tx_lfc_resend('{4{1'b0}}),
.rx_lfc_en('{4{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{4{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{4{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{4{1'b0}}),
.rx_pfc_en('{4{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{4{'0}}),
@@ -446,8 +446,8 @@ sfp_mac_inst (
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{4{1'b0}}),
.tx_pause_req('{4{1'b0}}),
.tx_pause_ack(),
/*
@@ -492,7 +492,7 @@ sfp_mac_inst (
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{4{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -517,42 +517,42 @@ sfp_mac_inst (
*/
.cfg_tx_max_pkt_len('{4{16'd9218}}),
.cfg_tx_ifg('{4{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{4{1'b1}}),
.cfg_rx_max_pkt_len('{4{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{4{1'b1}}),
.cfg_tx_prbs31_enable('{4{1'b0}}),
.cfg_rx_prbs31_enable('{4{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{4{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{4{1'b0}}),
.cfg_mcf_rx_eth_src('{4{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{4{1'b0}}),
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{4{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{4{1'b1}}),
.cfg_mcf_rx_forward('{4{1'b0}}),
.cfg_mcf_rx_enable('{4{1'b0}}),
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
.cfg_tx_lfc_opcode('{4{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{4{1'b0}}),
.cfg_tx_lfc_quanta('{4{16'hffff}}),
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
.cfg_tx_pfc_opcode('{4{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{4{1'b0}}),
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{4{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{4{1'b0}}),
.cfg_rx_pfc_opcode('{4{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{4{1'b0}})
);
for (genvar n = 0; n < 4; n = n + 1) begin : sfp_ch

8
src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.sv
View File

@@ -61,10 +61,10 @@ logic uart_txd;
logic uart_rts;
logic uart_cts;
logic [3:0] sfp_rx_p;
logic [3:0] sfp_rx_n;
logic [3:0] sfp_tx_p;
logic [3:0] sfp_tx_n;
logic sfp_rx_p[4];
logic sfp_rx_n[4];
logic sfp_tx_p[4];
logic sfp_tx_n[4];
logic sfp_mgt_refclk_0_p;
logic sfp_mgt_refclk_0_n;

16
src/eth/example/fb2CG/fpga/rtl/fpga.sv
View File

@@ -44,10 +44,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_0_tx_p,
output wire logic [3:0] qsfp_0_tx_n,
input wire logic [3:0] qsfp_0_rx_p,
input wire logic [3:0] qsfp_0_rx_n,
output wire logic qsfp_0_tx_p[4],
output wire logic qsfp_0_tx_n[4],
input wire logic qsfp_0_rx_p[4],
input wire logic qsfp_0_rx_n[4],
input wire logic qsfp_0_mgt_refclk_p,
input wire logic qsfp_0_mgt_refclk_n,
input wire logic qsfp_0_mod_prsnt_n,
@@ -55,10 +55,10 @@ module fpga #
output wire logic qsfp_0_lp_mode,
input wire logic qsfp_0_intr_n,
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
input wire logic qsfp_1_mgt_refclk_p,
input wire logic qsfp_1_mgt_refclk_n,
input wire logic qsfp_1_mod_prsnt_n,

124
src/eth/example/fb2CG/fpga/rtl/fpga_core.sv
View File

@@ -41,10 +41,10 @@ module fpga_core #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_0_tx_p,
output wire logic [3:0] qsfp_0_tx_n,
input wire logic [3:0] qsfp_0_rx_p,
input wire logic [3:0] qsfp_0_rx_n,
output wire logic qsfp_0_tx_p[4],
output wire logic qsfp_0_tx_n[4],
input wire logic qsfp_0_rx_p[4],
input wire logic qsfp_0_rx_n[4],
input wire logic qsfp_0_mgt_refclk_p,
input wire logic qsfp_0_mgt_refclk_n,
input wire logic qsfp_0_mod_prsnt_n,
@@ -52,10 +52,10 @@ module fpga_core #
output wire logic qsfp_0_lp_mode,
input wire logic qsfp_0_intr_n,
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
input wire logic qsfp_1_mgt_refclk_p,
input wire logic qsfp_1_mgt_refclk_n,
input wire logic qsfp_1_mod_prsnt_n,
@@ -93,14 +93,17 @@ assign qsfp_0_lp_mode = 1'b0;
assign qsfp_1_reset_n = 1'b1;
assign qsfp_1_lp_mode = 1'b0;
wire [7:0] qsfp_tx_clk;
wire [7:0] qsfp_tx_rst;
wire [7:0] qsfp_rx_clk;
wire [7:0] qsfp_rx_rst;
wire qsfp_tx_clk[8];
wire qsfp_tx_rst[8];
wire qsfp_rx_clk[8];
wire qsfp_rx_rst[8];
wire [7:0] qsfp_rx_status;
wire qsfp_rx_status[8];
for (genvar n = 0; n < 8; n = n + 1) begin
assign led_g[n] = qsfp_rx_status[n];
end
assign led_g = qsfp_rx_status;
assign led_r = '0;
assign led_bmc = '0;
assign led_exp = '1;
@@ -112,13 +115,18 @@ taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[8]();
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[8]();
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_qsfp_stat[2]();
wire [1:0] qsfp_mgt_refclk_p = {qsfp_1_mgt_refclk_p, qsfp_0_mgt_refclk_p};
wire [1:0] qsfp_mgt_refclk_n = {qsfp_1_mgt_refclk_n, qsfp_0_mgt_refclk_n};
wire qsfp_mgt_refclk_p[2];
wire qsfp_mgt_refclk_n[2];
wire [1:0] qsfp_mgt_refclk;
wire [1:0] qsfp_mgt_refclk_bufg;
assign qsfp_mgt_refclk_p[0] = qsfp_0_mgt_refclk_p;
assign qsfp_mgt_refclk_n[0] = qsfp_0_mgt_refclk_n;
assign qsfp_mgt_refclk_p[1] = qsfp_1_mgt_refclk_p;
assign qsfp_mgt_refclk_n[1] = qsfp_1_mgt_refclk_n;
wire [1:0] qsfp_rst;
wire qsfp_mgt_refclk[2];
wire qsfp_mgt_refclk_bufg[2];
wire qsfp_rst[2];
for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk
@@ -162,20 +170,24 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk
);
end
wire qsfp_tx_p[8];
wire qsfp_tx_n[8];
wire qsfp_rx_p[8];
wire qsfp_rx_n[8];
wire [7:0] qsfp_tx_p;
wire [7:0] qsfp_tx_n;
wire [7:0] qsfp_rx_p = {qsfp_1_rx_p, qsfp_0_rx_p};
wire [7:0] qsfp_rx_n = {qsfp_1_rx_n, qsfp_0_rx_n};
assign qsfp_0_tx_p = qsfp_tx_p[4*0 +: 4];
assign qsfp_0_tx_n = qsfp_tx_n[4*0 +: 4];
assign qsfp_1_tx_p = qsfp_tx_p[4*1 +: 4];
assign qsfp_1_tx_n = qsfp_tx_n[4*1 +: 4];
assign qsfp_0_tx_p = qsfp_tx_p[3:0];
assign qsfp_0_tx_n = qsfp_tx_n[3:0];
assign qsfp_1_tx_p = qsfp_tx_p[7:4];
assign qsfp_1_tx_n = qsfp_tx_n[7:4];
assign qsfp_rx_p[4*0 +: 4] = qsfp_0_rx_p;
assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
localparam CLK = n;
localparam CLK = 4;
localparam CNT = 4;
taxi_eth_mac_25g_us #(
@@ -239,12 +251,12 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(qsfp_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]),
.tx_clk(qsfp_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -261,24 +273,24 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -286,8 +298,8 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -332,7 +344,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -357,42 +369,42 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end