example: Build all MAC variants for ZCU106

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/example/ZCU106/fpga/fpga_10g/config.tcl

@@ -12,6 +12,10 @@ set params [dict create]
 # 0 for 1G, 1 for 10G
 dict set params SFP_RATE "1"
 
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+
 # apply parameters to top-level
 set param_list {}
 dict for {name value} $params {

src/eth/example/ZCU106/fpga/fpga_10g_async/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu7ev-ffvc1156-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+

src/eth/example/ZCU106/fpga/fpga_10g_async/config.tcl

@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# SFP+ rate
+# 0 for 1G, 1 for 10G
+dict set params SFP_RATE "1"
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "0"
+dict set params COMBINED_MAC_PCS "1"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/ZCU106/fpga/fpga_10g_split/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu7ev-ffvc1156-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+

src/eth/example/ZCU106/fpga/fpga_10g_split/config.tcl

@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# SFP+ rate
+# 0 for 1G, 1 for 10G
+dict set params SFP_RATE "1"
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "0"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/ZCU106/fpga/fpga_10g_split_async/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu7ev-ffvc1156-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+

src/eth/example/ZCU106/fpga/fpga_10g_split_async/config.tcl

@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# SFP+ rate
+# 0 for 1G, 1 for 10G
+dict set params SFP_RATE "1"
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "0"
+dict set params COMBINED_MAC_PCS "0"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/ZCU106/fpga/fpga_1g/config.tcl

@@ -12,6 +12,10 @@ set params [dict create]
 # 0 for 1G, 1 for 10G
 dict set params SFP_RATE "0"
 
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+
 # apply parameters to top-level
 set param_list {}
 dict for {name value} $params {

src/eth/example/ZCU106/fpga/rtl/fpga.sv

@@ -24,7 +24,10 @@ module fpga #
     // device family
     parameter string FAMILY = "zynquplus",
     // SFP rate selection (0 for 1G, 1 for 10G)
-    parameter logic SFP_RATE = 1'b1
+    parameter logic SFP_RATE = 1'b1,
+    // 10G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1
 )
 (
     /*
@@ -425,7 +428,9 @@ fpga_core #(
     .SIM(SIM),
     .VENDOR(VENDOR),
     .FAMILY(FAMILY),
-    .SFP_RATE(SFP_RATE)
+    .SFP_RATE(SFP_RATE),
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS)
 )
 core_inst (
     /*

src/eth/example/ZCU106/fpga/rtl/fpga_core.sv

@@ -24,7 +24,10 @@ module fpga_core #
     // device family
     parameter string FAMILY = "zynquplus",
     // SFP rate selection (0 for 1G, 1 for 10G)
-    parameter logic SFP_RATE = 1'b1
+    parameter logic SFP_RATE = 1'b1,
+    // 10G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1
 )
 (
     /*
@@ -433,12 +436,13 @@ end else begin : sfp_mac
         .CNT(2),
 
         // GT config
-        .CFG_LOW_LATENCY(1),
+        .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
 
         // GT type
         .GT_TYPE("GTH"),
 
         // PHY parameters
+        .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
         .PADDING_EN(1'b1),
         .DIC_EN(1'b1),
         .MIN_FRAME_LEN(64),