sync: Set ASYNC_REG in HDL instead of TCL

Signed-off-by: Alex Forencich <alex@alexforencich.com>

rtl/sync/taxi_sync_reset.sv

@@ -28,7 +28,7 @@ module taxi_sync_reset #
     output wire logic  out
 );
 
-(* srl_style = "register" *)
+(* async_reg="true", srl_style="register", shreg_extract="no" *)
 logic [N-1:0] sync_reg = '1;
 
 assign out = sync_reg[N-1];

rtl/sync/taxi_sync_signal.sv

@@ -29,7 +29,7 @@ module taxi_sync_signal #(
     output wire logic [WIDTH-1:0]  out
 );
 
-(* srl_style = "register" *)
+(* async_reg="true", srl_style="register", shreg_extract="no" *)
 logic [WIDTH-1:0] sync_reg[N-1:0];
 
 assign out = sync_reg[N-1];

syn/vivado/taxi_sync_reset.tcl

@@ -14,6 +14,5 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_sync_reset || REF_
     # reset synchronization
     set reset_ffs [get_cells -quiet -hier "sync_reg_reg[*]" -filter "PARENT == $inst"]
 
-    set_property ASYNC_REG TRUE $reset_ffs
     set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
 }

syn/vivado/taxi_sync_signal.tcl

@@ -11,6 +11,5 @@
 foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_sync_signal || REF_NAME == taxi_sync_signal)}] {
     puts "Inserting timing constraints for taxi_sync_signal instance $inst"
 
-    set_property ASYNC_REG TRUE [get_cells -hier "sync_reg_reg[*][*]" -filter "PARENT == $inst"]
     set_false_path -to [get_cells -hier "sync_reg_reg[0][*]" -filter "PARENT == $inst"]
 }