example: Update example designs

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-12-07 16:28:40 -08:00 · 2025-04-28 17:12:55 -07:00
parent d43569a92a
commit 577c572c5d
49 changed files with 85 additions and 85 deletions
--- a/example/ADM_PCIE_9V3/fpga/fpga/Makefile
+++ b/example/ADM_PCIE_9V3/fpga/fpga/Makefile
@@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl

 # Configuration
 # CONFIG_TCL_FILES = ./config.tcl
--- a/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile
+++ b/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile
@@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl

 # Configuration
 # CONFIG_TCL_FILES = ./config.tcl
--- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
@@ -48,11 +48,11 @@ class TB:

        for inst in dut.gty_quad:
            for ch in inst.mac_inst.ch:
-                cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
-                cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())

-                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        dut.user_sw.setimmediatevalue(0)

--- a/example/Alveo/fpga/fpga_AU200/Makefile
+++ b/example/Alveo/fpga/fpga_AU200/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU200_10g/Makefile
+++ b/example/Alveo/fpga/fpga_AU200_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU250/Makefile
+++ b/example/Alveo/fpga/fpga_AU250/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU250_10g/Makefile
+++ b/example/Alveo/fpga/fpga_AU250_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU280/Makefile
+++ b/example/Alveo/fpga/fpga_AU280/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU280_10g/Makefile
+++ b/example/Alveo/fpga/fpga_AU280_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU45N/Makefile
+++ b/example/Alveo/fpga/fpga_AU45N/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU45N_10g/Makefile
+++ b/example/Alveo/fpga/fpga_AU45N_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU50/Makefile
+++ b/example/Alveo/fpga/fpga_AU50/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU50_10g/Makefile
+++ b/example/Alveo/fpga/fpga_AU50_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU55C/Makefile
+++ b/example/Alveo/fpga/fpga_AU55C/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU55C_10g/Makefile
+++ b/example/Alveo/fpga/fpga_AU55C_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU55N/Makefile
+++ b/example/Alveo/fpga/fpga_AU55N/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_AU55N_10g/Makefile
+++ b/example/Alveo/fpga/fpga_AU55N_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_VCU1525/Makefile
+++ b/example/Alveo/fpga/fpga_VCU1525/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_VCU1525_10g/Makefile
+++ b/example/Alveo/fpga/fpga_VCU1525_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_X3522/Makefile
+++ b/example/Alveo/fpga/fpga_X3522/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/fpga_X3522_10g/Makefile
+++ b/example/Alveo/fpga/fpga_X3522_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
@@ -51,11 +51,11 @@ class TB:

        for inst in dut.gty_quad:
            for ch in inst.mac_inst.ch:
-                cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
-                cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())

-                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        dut.sw.setimmediatevalue(0)
        dut.eth_port_modprsl.setimmediatevalue(0)
--- a/example/KCU105/fpga/fpga_10g/Makefile
+++ b/example/KCU105/fpga/fpga_10g/Makefile
@@ -32,7 +32,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
 IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
-IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_156.tcl
+IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl

 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
--- a/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
@@ -71,11 +71,11 @@ class TB:
            cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start())

            for ch in dut.sfp_mac.sfp_mac_inst.ch:
-                cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start())
-                cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start())

-                self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-                self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+                self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+                self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
        self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
--- a/example/KR260/fpga/fpga_10g/Makefile
+++ b/example/KR260/fpga/fpga_10g/Makefile
@@ -29,7 +29,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl

 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
--- a/example/KR260/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/KR260/fpga/tb/fpga_core/test_fpga_core.py
@@ -60,11 +60,11 @@ class TB:

            ch = dut.sfp_mac.sfp_mac_inst.ch[0]

-            cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start())
-            cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start())
+            cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start())
+            cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start())

-            self.sfp_source = BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)
-            self.sfp_sink = BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True)
+            self.sfp_source = BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True)
+            self.sfp_sink = BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True)

        cocotb.start_soon(self._run_clk())

--- a/example/Nexus_K3P_Q/fpga/fpga/Makefile
+++ b/example/Nexus_K3P_Q/fpga/fpga/Makefile
@@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl

 # Configuration
 # CONFIG_TCL_FILES = ./config.tcl
--- a/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile
+++ b/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile
@@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl

 # Configuration
 # CONFIG_TCL_FILES = ./config.tcl
--- a/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py
@@ -48,11 +48,11 @@ class TB:

        for inst in dut.gty_quad:
            for ch in inst.mac_inst.ch:
-                cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
-                cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())

-                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        dut.qsfp_0_modprsl.setimmediatevalue(0)
        dut.qsfp_0_intl.setimmediatevalue(0)
--- a/example/Nexus_K3P_S/fpga/fpga_K35/Makefile
+++ b/example/Nexus_K3P_S/fpga/fpga_K35/Makefile
@@ -27,7 +27,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_161.tcl

 # Configuration
 # CONFIG_TCL_FILES = ./config.tcl
--- a/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile
+++ b/example/Nexus_K3P_S/fpga/fpga_K3P/Makefile
@@ -27,7 +27,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl

 # Configuration
 # CONFIG_TCL_FILES = ./config.tcl
--- a/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile
+++ b/example/Nexus_K3P_S/fpga/fpga_K3P_10g/Makefile
@@ -27,7 +27,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl

 # Configuration
 # CONFIG_TCL_FILES = ./config.tcl
--- a/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py
@@ -47,11 +47,11 @@ class TB:
        self.sfp_sinks = []

        for ch in dut.sfp_mac_inst.ch:
-            cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
-            cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
+            cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
+            cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())

-            self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-            self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+            self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+            self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        dut.sfp_npres.setimmediatevalue(0)
        dut.sfp_los.setimmediatevalue(0)
--- a/example/VCU108/fpga/fpga/Makefile
+++ b/example/VCU108/fpga/fpga/Makefile
@@ -32,7 +32,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
 IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
-IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl
+IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl

 include ../common/vivado.mk

--- a/example/VCU108/fpga/fpga_10g/Makefile
+++ b/example/VCU108/fpga/fpga_10g/Makefile
@@ -32,7 +32,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
 IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
-IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl
+IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl

 include ../common/vivado.mk

--- a/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
@@ -58,11 +58,11 @@ class TB:
        self.qsfp_sinks = []

        for ch in dut.qsfp_mac_inst.ch:
-            cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
-            cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
+            cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
+            cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())

-            self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-            self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+            self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+            self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        dut.phy_gmii_clk_en.setimmediatevalue(1)

--- a/example/VCU118/fpga/fpga/Makefile
+++ b/example/VCU118/fpga/fpga/Makefile
@@ -33,7 +33,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
 IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
-IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl
+IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl

 include ../common/vivado.mk

--- a/example/VCU118/fpga/fpga_10g/Makefile
+++ b/example/VCU118/fpga/fpga_10g/Makefile
@@ -33,7 +33,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
 IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
-IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl
+IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl

 include ../common/vivado.mk

--- a/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
@@ -59,11 +59,11 @@ class TB:

        for inst in dut.gty_quad:
            for ch in inst.mac_inst.ch:
-                cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
-                cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())

-                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        dut.phy_gmii_clk_en.setimmediatevalue(1)

--- a/example/ZCU102/fpga/fpga_10g/Makefile
+++ b/example/ZCU102/fpga/fpga_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl

 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
--- a/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
@@ -77,11 +77,11 @@ class TB:
            cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start())

            for ch in dut.sfp_mac.sfp_mac_inst.ch:
-                cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start())
-                cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start())

-                self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-                self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+                self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+                self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        self.uart_source = UartSource(dut.uart_rxd, baud=2000000, bits=8, stop_bits=1)
        self.uart_sink = UartSink(dut.uart_txd, baud=2000000, bits=8, stop_bits=1)
--- a/example/ZCU106/fpga/fpga_10g/Makefile
+++ b/example/ZCU106/fpga/fpga_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gth_10g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gth_10g_156.tcl

 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
--- a/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
@@ -65,11 +65,11 @@ class TB:
            cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start())

            for ch in dut.sfp_mac.sfp_mac_inst.ch:
-                cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start())
-                cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start())

-                self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-                self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+                self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+                self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        self.uart_source = UartSource(dut.uart_rxd, baud=2000000, bits=8, stop_bits=1)
        self.uart_sink = UartSink(dut.uart_txd, baud=2000000, bits=8, stop_bits=1)
--- a/example/ZCU111/fpga/fpga/Makefile
+++ b/example/ZCU111/fpga/fpga/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/ZCU111/fpga/fpga_10g/Makefile
+++ b/example/ZCU111/fpga/fpga_10g/Makefile
@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl

 # Configuration
 #CONFIG_TCL_FILES = ./config.tcl
--- a/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py
@@ -49,11 +49,11 @@ class TB:
        cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start())

        for ch in dut.sfp_mac_inst.ch:
-            cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start())
-            cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start())
+            cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start())
+            cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start())

-            self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-            self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+            self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+            self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
        self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)
--- a/example/fb2CG/fpga/fpga/Makefile
+++ b/example/fb2CG/fpga/fpga/Makefile
@@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl

 # Configuration
 # CONFIG_TCL_FILES = ./config.tcl
--- a/example/fb2CG/fpga/fpga_10g/Makefile
+++ b/example/fb2CG/fpga/fpga_10g/Makefile
@@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl

 # IP
-IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl

 # Configuration
 # CONFIG_TCL_FILES = ./config.tcl
--- a/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
@@ -49,11 +49,11 @@ class TB:

        for inst in dut.gty_quad:
            for ch in inst.mac_inst.ch:
-                cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
-                cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
+                cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())

-                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
-                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+                self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+                self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))

        dut.qsfp_0_mod_prsnt_n.setimmediatevalue(0)
        dut.qsfp_0_intr_n.setimmediatevalue(0)