sync: Set ASYNC_REG in HDL instead of TCL

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-28 20:03:38 -07:00
parent 577c572c5d
commit 3401e069d1
4 changed files with 2 additions and 4 deletions

View File

@@ -28,7 +28,7 @@ module taxi_sync_reset #
output wire logic out
);
(* srl_style = "register" *)
(* async_reg="true", srl_style="register", shreg_extract="no" *)
logic [N-1:0] sync_reg = '1;
assign out = sync_reg[N-1];

View File

@@ -29,7 +29,7 @@ module taxi_sync_signal #(
output wire logic [WIDTH-1:0] out
);
(* srl_style = "register" *)
(* async_reg="true", srl_style="register", shreg_extract="no" *)
logic [WIDTH-1:0] sync_reg[N-1:0];
assign out = sync_reg[N-1];