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prim: Add arbiter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
155
rtl/prim/taxi_arbiter.sv
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155
rtl/prim/taxi_arbiter.sv
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@@ -0,0 +1,155 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Arbiter module
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*/
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module taxi_arbiter #
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(
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parameter PORTS = 4,
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// select round robin arbitration
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parameter logic ARB_ROUND_ROBIN = 1'b1,
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// blocking arbiter enable
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parameter logic ARB_BLOCK = 1'b1,
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// block on acknowledge assert when nonzero, request deassert when 0
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parameter logic ARB_BLOCK_ACK = 1'b0,
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// LSB priority selection
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parameter logic LSB_HIGH_PRIO = 1'b0
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)
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(
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input wire logic clk,
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input wire logic rst,
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input wire logic [PORTS-1:0] req,
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input wire logic [PORTS-1:0] ack,
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output wire logic grant_valid,
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output wire logic [PORTS-1:0] grant,
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output wire logic [$clog2(PORTS)-1:0] grant_index
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);
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localparam CL_PORTS = $clog2(PORTS);
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logic [PORTS-1:0] grant_reg = 'd0, grant_next;
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logic grant_valid_reg = 1'b0, grant_valid_next;
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logic [CL_PORTS-1:0] grant_index_reg = 'd0, grant_index_next;
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assign grant_valid = grant_valid_reg;
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assign grant = grant_reg;
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assign grant_index = grant_index_reg;
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wire req_valid;
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wire [CL_PORTS-1:0] req_index;
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wire [PORTS-1:0] req_mask;
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taxi_penc #(
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.WIDTH(PORTS),
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.LSB_HIGH_PRIO(LSB_HIGH_PRIO)
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)
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penc_inst (
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.input_mask(req),
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.output_valid(req_valid),
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.output_index(req_index),
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.output_mask(req_mask)
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);
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logic [PORTS-1:0] mask_reg = 'd0, mask_next;
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wire masked_req_valid;
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wire [CL_PORTS-1:0] masked_req_index;
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wire [PORTS-1:0] masked_req_mask;
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if (ARB_ROUND_ROBIN) begin
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taxi_penc #(
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.WIDTH(PORTS),
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.LSB_HIGH_PRIO(LSB_HIGH_PRIO)
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)
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penc_masked (
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.input_mask(req & mask_reg),
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.output_valid(masked_req_valid),
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.output_index(masked_req_index),
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.output_mask(masked_req_mask)
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);
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end else begin
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assign masked_req_valid = 1'b0;
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assign masked_req_index = '0;
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assign masked_req_mask = '0;
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end
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always_comb begin
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grant_next = 'd0;
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grant_valid_next = 1'b0;
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grant_index_next = 'd0;
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mask_next = mask_reg;
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if (ARB_BLOCK && !ARB_BLOCK_ACK && ((grant_reg & req) != 0)) begin
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// granted req still asserted; hold it
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grant_valid_next = grant_valid_reg;
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grant_next = grant_reg;
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grant_index_next = grant_index_reg;
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end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && ((grant_reg & ack) == 0)) begin
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// granted req not yet acknowledged; hold it
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grant_valid_next = grant_valid_reg;
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grant_next = grant_reg;
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grant_index_next = grant_index_reg;
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end else if (req_valid) begin
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if (ARB_ROUND_ROBIN) begin
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if (masked_req_valid) begin
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grant_valid_next = 1'b1;
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grant_next = masked_req_mask;
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grant_index_next = masked_req_index;
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if (LSB_HIGH_PRIO) begin
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mask_next = {PORTS{1'b1}} << (masked_req_index + 1);
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end else begin
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mask_next = {PORTS{1'b1}} >> ((CL_PORTS+1)'(PORTS) - masked_req_index);
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end
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end else begin
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grant_valid_next = 1;
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grant_next = req_mask;
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grant_index_next = req_index;
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if (LSB_HIGH_PRIO) begin
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mask_next = {PORTS{1'b1}} << (req_index + 1);
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end else begin
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mask_next = {PORTS{1'b1}} >> ((CL_PORTS+1)'(PORTS) - req_index);
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end
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end
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end else begin
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grant_valid_next = 1'b1;
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grant_next = req_mask;
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grant_index_next = req_index;
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end
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end
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end
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always_ff @(posedge clk) begin
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grant_reg <= grant_next;
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grant_valid_reg <= grant_valid_next;
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grant_index_reg <= grant_index_next;
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mask_reg <= mask_next;
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if (rst) begin
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grant_reg <= 'd0;
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grant_valid_reg <= 1'b0;
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grant_index_reg <= 'd0;
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mask_reg <= 'd0;
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end
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end
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endmodule
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`resetall
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50
tb/prim/taxi_arbiter/Makefile
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50
tb/prim/taxi_arbiter/Makefile
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@@ -0,0 +1,50 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = taxi_arbiter
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = $(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += ../../../rtl/prim/$(DUT).sv
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VERILOG_SOURCES += ../../../rtl/prim/taxi_penc.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_PORTS := 32
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export PARAM_ARM_ROUND_ROBIN := "1'b1"
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export PARAM_ARM_BLOCK := "1'b1"
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export PARAM_ARM_BLOCK_ACK := "1'b0"
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export PARAM_LSB_HIGH_PRIO := "1'b0"
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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335
tb/prim/taxi_arbiter/test_taxi_arbiter.py
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335
tb/prim/taxi_arbiter/test_taxi_arbiter.py
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@@ -0,0 +1,335 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2020-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import logging
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import os
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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dut.req.setimmediatevalue(0)
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dut.ack.setimmediatevalue(0)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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@cocotb.test()
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async def run_single_bit(dut):
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tb = TB(dut)
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round_robin = bool(int(dut.ARB_ROUND_ROBIN.value))
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lsb_high_prio = bool(int(dut.LSB_HIGH_PRIO.value))
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await tb.reset()
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if lsb_high_prio:
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prev_index = 31
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else:
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prev_index = 0
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for i in range(32):
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lst = [i]
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k = 0
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for y in lst:
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k = k | 1 << y
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tb.log.info("Request: 0x%08x", k)
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dut.req.value = k
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await RisingEdge(dut.clk)
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dut.req.value = 0
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await RisingEdge(dut.clk)
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if round_robin:
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if lsb_high_prio:
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# emulate round robin
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lst2 = [x for x in lst if x > prev_index]
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if len(lst2) == 0:
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lst2 = lst
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g = min(lst2)
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else:
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# emulate round robin
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lst2 = [x for x in lst if x < prev_index]
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if len(lst2) == 0:
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lst2 = lst
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g = max(lst2)
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else:
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if lsb_high_prio:
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g = min(lst)
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else:
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g = max(lst)
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tb.log.info("Grant (mask): 0x%08x", int(dut.grant.value))
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tb.log.info("Grant (index): %d", int(dut.grant_index.value))
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assert int(dut.grant.value) == 1 << g
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assert int(dut.grant_index.value) == g
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prev_index = int(g)
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def run_cycle(dut):
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tb = TB(dut)
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round_robin = bool(int(dut.ARB_ROUND_ROBIN.value))
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lsb_high_prio = bool(int(dut.LSB_HIGH_PRIO.value))
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await tb.reset()
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if lsb_high_prio:
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prev_index = 31
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else:
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prev_index = 0
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for i in range(32):
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lst = [0, 5, 10, 15, 20, 25, 30]
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k = 0
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for y in lst:
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k = k | 1 << y
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tb.log.info("Request: 0x%08x", k)
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dut.req.value = k
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await RisingEdge(dut.clk)
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dut.req.value = 0
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await RisingEdge(dut.clk)
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if round_robin:
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if lsb_high_prio:
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# emulate round robin
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lst2 = [x for x in lst if x > prev_index]
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if len(lst2) == 0:
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lst2 = lst
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g = min(lst2)
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else:
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# emulate round robin
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lst2 = [x for x in lst if x < prev_index]
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if len(lst2) == 0:
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lst2 = lst
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g = max(lst2)
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else:
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if lsb_high_prio:
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g = min(lst)
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else:
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g = max(lst)
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tb.log.info("Grant (mask): 0x%08x", int(dut.grant.value))
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tb.log.info("Grant (index): %d", int(dut.grant_index.value))
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assert int(dut.grant.value) == 1 << g
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assert int(dut.grant_index.value) == g
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prev_index = int(g)
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def run_two_bits(dut):
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tb = TB(dut)
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round_robin = bool(int(dut.ARB_ROUND_ROBIN.value))
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lsb_high_prio = bool(int(dut.LSB_HIGH_PRIO.value))
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await tb.reset()
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if lsb_high_prio:
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prev_index = 31
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else:
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prev_index = 0
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for i in range(32):
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for j in range(32):
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lst = [i, j]
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k = 0
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for y in lst:
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k = k | 1 << y
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tb.log.info("Request: 0x%08x", k)
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dut.req.value = k
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await RisingEdge(dut.clk)
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dut.req.value = 0
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await RisingEdge(dut.clk)
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if round_robin:
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if lsb_high_prio:
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# emulate round robin
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lst2 = [x for x in lst if x > prev_index]
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if len(lst2) == 0:
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lst2 = lst
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g = min(lst2)
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else:
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# emulate round robin
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lst2 = [x for x in lst if x < prev_index]
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if len(lst2) == 0:
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lst2 = lst
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g = max(lst2)
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else:
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if lsb_high_prio:
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g = min(lst)
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else:
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g = max(lst)
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tb.log.info("Grant (mask): 0x%08x", int(dut.grant.value))
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tb.log.info("Grant (index): %d", int(dut.grant_index.value))
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assert int(dut.grant.value) == 1 << g
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assert int(dut.grant_index.value) == g
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prev_index = int(g)
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def run_five_bits(dut):
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tb = TB(dut)
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round_robin = bool(int(dut.ARB_ROUND_ROBIN.value))
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lsb_high_prio = bool(int(dut.LSB_HIGH_PRIO.value))
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await tb.reset()
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if lsb_high_prio:
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prev_index = 31
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else:
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prev_index = 0
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for i in range(32):
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lst = [(i*x) % 32 for x in [1, 3, 5, 7, 11]]
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k = 0
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for y in lst:
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k = k | 1 << y
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tb.log.info("Request: 0x%08x", k)
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dut.req.value = k
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await RisingEdge(dut.clk)
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dut.req.value = 0
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await RisingEdge(dut.clk)
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if round_robin:
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if lsb_high_prio:
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# emulate round robin
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lst2 = [x for x in lst if x > prev_index]
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if len(lst2) == 0:
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lst2 = lst
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g = min(lst2)
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else:
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# emulate round robin
|
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lst2 = [x for x in lst if x < prev_index]
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if len(lst2) == 0:
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lst2 = lst
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g = max(lst2)
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else:
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if lsb_high_prio:
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g = min(lst)
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else:
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g = max(lst)
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tb.log.info("Grant (mask): 0x%08x", int(dut.grant.value))
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tb.log.info("Grant (index): %d", int(dut.grant_index.value))
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assert int(dut.grant.value) == 1 << g
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assert int(dut.grant_index.value) == g
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prev_index = int(g)
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await RisingEdge(dut.clk)
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# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("lsb_high_prio", [0, 1])
|
||||
@pytest.mark.parametrize("round_robin", [0, 1])
|
||||
def test_taxi_arbiter(request, round_robin, lsb_high_prio):
|
||||
dut = "taxi_arbiter"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, "prim", f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "prim", "taxi_penc.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['PORTS'] = 32
|
||||
parameters['ARB_ROUND_ROBIN'] = f"1'b{round_robin}"
|
||||
parameters['ARB_BLOCK'] = "1'b1"
|
||||
parameters['ARB_BLOCK_ACK'] = "1'b0"
|
||||
parameters['LSB_HIGH_PRIO'] = f"1'b{lsb_high_prio}"
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Reference in New Issue
Block a user