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cndm: Move control registers out of port module

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-03 13:31:16 -08:00
parent 191f7940b3
commit 4d8f0cfece
4 changed files with 467 additions and 307 deletions
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201
src/cndm/rtl/cndm_micro_cpl_wr.sv
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@@ -20,6 +20,17 @@ module cndm_micro_cpl_wr
input wire logic clk,
input wire logic rst,
/*
* Control register interface
*/
taxi_axil_if.wr_slv s_axil_ctrl_wr,
taxi_axil_if.rd_slv s_axil_ctrl_rd,
/*
* Datapath control register interface
*/
taxi_apb_if.slv s_apb_dp_ctrl,
/*
* DMA
*/
@@ -27,19 +38,169 @@ module cndm_micro_cpl_wr
taxi_dma_desc_if.sts_snk dma_wr_desc_sts,
taxi_dma_ram_if.rd_slv dma_ram_rd,
input wire logic txcq_en,
input wire logic [3:0] txcq_size,
input wire logic [63:0] txcq_base_addr,
output wire logic [15:0] txcq_prod,
input wire logic rxcq_en,
input wire logic [3:0] rxcq_size,
input wire logic [63:0] rxcq_base_addr,
output wire logic [15:0] rxcq_prod,
taxi_axis_if.snk axis_cpl[2],
output wire logic irq
);
localparam AXIL_ADDR_W = s_axil_ctrl_wr.ADDR_W;
localparam AXIL_DATA_W = s_axil_ctrl_wr.DATA_W;
localparam APB_ADDR_W = s_apb_dp_ctrl.ADDR_W;
localparam APB_DATA_W = s_apb_dp_ctrl.DATA_W;
logic txcq_en_reg = '0;
logic [3:0] txcq_size_reg = '0;
logic [63:0] txcq_base_addr_reg = '0;
logic rxcq_en_reg = '0;
logic [3:0] rxcq_size_reg = '0;
logic [63:0] rxcq_base_addr_reg = '0;
logic [15:0] txcq_prod_ptr_reg = '0;
logic [15:0] rxcq_prod_ptr_reg = '0;
logic s_axil_ctrl_awready_reg = 1'b0;
logic s_axil_ctrl_wready_reg = 1'b0;
logic s_axil_ctrl_bvalid_reg = 1'b0;
logic s_axil_ctrl_arready_reg = 1'b0;
logic [AXIL_DATA_W-1:0] s_axil_ctrl_rdata_reg = '0;
logic s_axil_ctrl_rvalid_reg = 1'b0;
assign s_axil_ctrl_wr.awready = s_axil_ctrl_awready_reg;
assign s_axil_ctrl_wr.wready = s_axil_ctrl_wready_reg;
assign s_axil_ctrl_wr.bresp = '0;
assign s_axil_ctrl_wr.buser = '0;
assign s_axil_ctrl_wr.bvalid = s_axil_ctrl_bvalid_reg;
assign s_axil_ctrl_rd.arready = s_axil_ctrl_arready_reg;
assign s_axil_ctrl_rd.rdata = s_axil_ctrl_rdata_reg;
assign s_axil_ctrl_rd.rresp = '0;
assign s_axil_ctrl_rd.ruser = '0;
assign s_axil_ctrl_rd.rvalid = s_axil_ctrl_rvalid_reg;
logic s_apb_dp_ctrl_pready_reg = 1'b0;
logic [AXIL_DATA_W-1:0] s_apb_dp_ctrl_prdata_reg = '0;
assign s_apb_dp_ctrl.pready = s_apb_dp_ctrl_pready_reg;
assign s_apb_dp_ctrl.prdata = s_apb_dp_ctrl_prdata_reg;
assign s_apb_dp_ctrl.pslverr = 1'b0;
assign s_apb_dp_ctrl.pruser = '0;
assign s_apb_dp_ctrl.pbuser = '0;
always_ff @(posedge clk) begin
s_axil_ctrl_awready_reg <= 1'b0;
s_axil_ctrl_wready_reg <= 1'b0;
s_axil_ctrl_bvalid_reg <= s_axil_ctrl_bvalid_reg && !s_axil_ctrl_wr.bready;
s_axil_ctrl_arready_reg <= 1'b0;
s_axil_ctrl_rvalid_reg <= s_axil_ctrl_rvalid_reg && !s_axil_ctrl_rd.rready;
s_apb_dp_ctrl_pready_reg <= 1'b0;
if (s_axil_ctrl_wr.awvalid && s_axil_ctrl_wr.wvalid && !s_axil_ctrl_bvalid_reg) begin
s_axil_ctrl_awready_reg <= 1'b1;
s_axil_ctrl_wready_reg <= 1'b1;
s_axil_ctrl_bvalid_reg <= 1'b1;
// case ({s_axil_ctrl_wr.awaddr[9:2], 2'b00})
// 10'h000: begin
// txcq_en_reg <= s_axil_ctrl_wr.wdata[0];
// txcq_size_reg <= s_axil_ctrl_wr.wdata[19:16];
// end
// 10'h008: txcq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata;
// 10'h00c: txcq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata;
// 10'h100: begin
// rxcq_en_reg <= s_axil_ctrl_wr.wdata[0];
// rxcq_size_reg <= s_axil_ctrl_wr.wdata[19:16];
// end
// 10'h108: rxcq_base_addr_reg[31:0] <= s_axil_ctrl_wr.wdata;
// 10'h10c: rxcq_base_addr_reg[63:32] <= s_axil_ctrl_wr.wdata;
// default: begin end
// endcase
end
if (s_axil_ctrl_rd.arvalid && !s_axil_ctrl_rvalid_reg) begin
s_axil_ctrl_rdata_reg <= '0;
s_axil_ctrl_arready_reg <= 1'b1;
s_axil_ctrl_rvalid_reg <= 1'b1;
// case ({s_axil_ctrl_rd.araddr[9:2], 2'b00})
// 10'h000: begin
// s_axil_ctrl_rdata_reg[0] <= txcq_en_reg;
// s_axil_ctrl_rdata_reg[19:16] <= txcq_size_reg;
// end
// 10'h004: s_axil_ctrl_rdata_reg[15:0] <= txcq_prod_ptr_reg;
// 10'h008: s_axil_ctrl_rdata_reg <= txcq_base_addr_reg[31:0];
// 10'h00c: s_axil_ctrl_rdata_reg <= txcq_base_addr_reg[63:32];
// 10'h100: begin
// s_axil_ctrl_rdata_reg[0] <= rxcq_en_reg;
// s_axil_ctrl_rdata_reg[19:16] <= rxcq_size_reg;
// end
// 10'h104: s_axil_ctrl_rdata_reg[15:0] <= rxcq_prod_ptr_reg;
// 10'h108: s_axil_ctrl_rdata_reg <= rxcq_base_addr_reg[31:0];
// 10'h10c: s_axil_ctrl_rdata_reg <= rxcq_base_addr_reg[63:32];
// default: begin end
// endcase
end
if (s_apb_dp_ctrl.penable && s_apb_dp_ctrl.psel && !s_apb_dp_ctrl_pready_reg) begin
s_apb_dp_ctrl_pready_reg <= 1'b1;
s_apb_dp_ctrl_prdata_reg <= '0;
if (s_apb_dp_ctrl.pwrite) begin
case ({s_apb_dp_ctrl.paddr[9:2], 2'b00})
10'h000: begin
txcq_en_reg <= s_apb_dp_ctrl.pwdata[0];
txcq_size_reg <= s_apb_dp_ctrl.pwdata[19:16];
end
10'h008: txcq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata;
10'h00c: txcq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata;
10'h100: begin
rxcq_en_reg <= s_apb_dp_ctrl.pwdata[0];
rxcq_size_reg <= s_apb_dp_ctrl.pwdata[19:16];
end
10'h108: rxcq_base_addr_reg[31:0] <= s_apb_dp_ctrl.pwdata;
10'h10c: rxcq_base_addr_reg[63:32] <= s_apb_dp_ctrl.pwdata;
default: begin end
endcase
end
case ({s_apb_dp_ctrl.paddr[9:2], 2'b00})
10'h000: begin
s_apb_dp_ctrl_prdata_reg[0] <= txcq_en_reg;
s_apb_dp_ctrl_prdata_reg[19:16] <= txcq_size_reg;
end
10'h004: s_apb_dp_ctrl_prdata_reg[15:0] <= txcq_prod_ptr_reg;
10'h008: s_apb_dp_ctrl_prdata_reg <= txcq_base_addr_reg[31:0];
10'h00c: s_apb_dp_ctrl_prdata_reg <= txcq_base_addr_reg[63:32];
10'h100: begin
s_apb_dp_ctrl_prdata_reg[0] <= rxcq_en_reg;
s_apb_dp_ctrl_prdata_reg[19:16] <= rxcq_size_reg;
end
10'h104: s_apb_dp_ctrl_prdata_reg[15:0] <= rxcq_prod_ptr_reg;
10'h108: s_apb_dp_ctrl_prdata_reg <= rxcq_base_addr_reg[31:0];
10'h10c: s_apb_dp_ctrl_prdata_reg <= rxcq_base_addr_reg[63:32];
default: begin end
endcase
end
if (rst) begin
s_axil_ctrl_awready_reg <= 1'b0;
s_axil_ctrl_wready_reg <= 1'b0;
s_axil_ctrl_bvalid_reg <= 1'b0;
s_axil_ctrl_arready_reg <= 1'b0;
s_axil_ctrl_rvalid_reg <= 1'b0;
s_apb_dp_ctrl_pready_reg <= 1'b0;
end
end
taxi_axis_if #(
.DATA_W(axis_cpl[0].DATA_W),
.KEEP_EN(axis_cpl[0].KEEP_EN),
@@ -62,16 +223,10 @@ typedef enum logic [1:0] {
state_t state_reg = STATE_IDLE;
logic [15:0] txcq_prod_ptr_reg = '0;
logic [15:0] rxcq_prod_ptr_reg = '0;
logic phase_tag_reg = 1'b0;
logic irq_reg = 1'b0;
assign txcq_prod = txcq_prod_ptr_reg;
assign rxcq_prod = rxcq_prod_ptr_reg;
assign irq = irq_reg;
always_ff @(posedge clk) begin
@@ -90,11 +245,11 @@ always_ff @(posedge clk) begin
dma_wr_desc_req.req_user <= '0;
dma_wr_desc_req.req_valid <= dma_wr_desc_req.req_valid && !dma_wr_desc_req.req_ready;
if (!txcq_en) begin
if (!txcq_en_reg) begin
txcq_prod_ptr_reg <= '0;
end
if (!rxcq_en) begin
if (!rxcq_en_reg) begin
rxcq_prod_ptr_reg <= '0;
end
@@ -105,11 +260,11 @@ always_ff @(posedge clk) begin
dma_wr_desc_req.req_src_addr <= '0;
if (cpl_comb.tid == 0) begin
dma_wr_desc_req.req_dst_addr <= txcq_base_addr + 64'(16'(txcq_prod_ptr_reg & ({16{1'b1}} >> (16 - txcq_size))) * 16);
phase_tag_reg <= !txcq_prod_ptr_reg[txcq_size];
dma_wr_desc_req.req_dst_addr <= txcq_base_addr_reg + 64'(16'(txcq_prod_ptr_reg & ({16{1'b1}} >> (16 - txcq_size_reg))) * 16);
phase_tag_reg <= !txcq_prod_ptr_reg[txcq_size_reg];
if (cpl_comb.tvalid && !cpl_comb.tready) begin
txcq_prod_ptr_reg <= txcq_prod_ptr_reg + 1;
if (txcq_en) begin
if (txcq_en_reg) begin
dma_wr_desc_req.req_valid <= 1'b1;
state_reg <= STATE_WRITE_DATA;
end else begin
@@ -117,11 +272,11 @@ always_ff @(posedge clk) begin
end
end
end else begin
dma_wr_desc_req.req_dst_addr <= rxcq_base_addr + 64'(16'(rxcq_prod_ptr_reg & ({16{1'b1}} >> (16 - rxcq_size))) * 16);
phase_tag_reg <= !rxcq_prod_ptr_reg[rxcq_size];
dma_wr_desc_req.req_dst_addr <= rxcq_base_addr_reg + 64'(16'(rxcq_prod_ptr_reg & ({16{1'b1}} >> (16 - rxcq_size_reg))) * 16);
phase_tag_reg <= !rxcq_prod_ptr_reg[rxcq_size_reg];
if (cpl_comb.tvalid && !cpl_comb.tready) begin
rxcq_prod_ptr_reg <= rxcq_prod_ptr_reg + 1;
if (rxcq_en) begin
if (rxcq_en_reg) begin
dma_wr_desc_req.req_valid <= 1'b1;
state_reg <= STATE_WRITE_DATA;
end else begin