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example: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-28 17:12:55 -07:00
parent d43569a92a
commit 577c572c5d
49 changed files with 85 additions and 85 deletions
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2
example/ADM_PCIE_9V3/fpga/fpga/Makefile
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@@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
# Configuration
# CONFIG_TCL_FILES = ./config.tcl

2
example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile
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@@ -28,7 +28,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
# Configuration
# CONFIG_TCL_FILES = ./config.tcl

8
example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
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@@ -48,11 +48,11 @@ class TB:
for inst in dut.gty_quad:
for ch in inst.mac_inst.ch:
cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))
dut.user_sw.setimmediatevalue(0)