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example: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-28 17:12:55 -07:00
parent d43569a92a
commit 577c572c5d
49 changed files with 85 additions and 85 deletions
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2
example/ZCU111/fpga/fpga/Makefile
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@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_156.tcl
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
# Configuration
#CONFIG_TCL_FILES = ./config.tcl

2
example/ZCU111/fpga/fpga_10g/Makefile
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@@ -31,7 +31,7 @@ XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_156.tcl
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_156.tcl
# Configuration
#CONFIG_TCL_FILES = ./config.tcl

8
example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py
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@@ -49,11 +49,11 @@ class TB:
cocotb.start_soon(Clock(dut.sfp_mgt_refclk_0_p, 6.4, units="ns").start())
for ch in dut.sfp_mac_inst.ch:
cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 6.4, units="ns").start())
cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 6.4, units="ns").start())
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 6.4, units="ns").start())
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 6.4, units="ns").start())
self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
self.sfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
self.sfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))
self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)