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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
1
src/axi/lib/taxi
Symbolic link
1
src/axi/lib/taxi
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../../../
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257
src/axi/rtl/taxi_axi_if.sv
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257
src/axi/rtl/taxi_axi_if.sv
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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interface taxi_axi_if #(
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// Width of data bus in bits
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parameter DATA_W = 32,
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// Width of address bus in bits
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parameter ADDR_W = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_W = (DATA_W/8),
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// Width of ID signal
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parameter ID_W = 8,
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// Use awuser signal
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parameter logic AWUSER_EN = 1'b0,
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// Width of awuser signal
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parameter AWUSER_W = 1,
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// Use wuser signal
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parameter logic WUSER_EN = 1'b0,
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// Width of wuser signal
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parameter WUSER_W = 1,
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// Use buser signal
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parameter logic BUSER_EN = 1'b0,
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// Width of buser signal
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parameter BUSER_W = 1,
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// Use aruser signal
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parameter logic ARUSER_EN = 1'b0,
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// Width of aruser signal
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parameter ARUSER_W = 1,
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// Use ruser signal
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parameter logic RUSER_EN = 1'b0,
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// Width of ruser signal
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parameter RUSER_W = 1
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)
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();
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// AW
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logic [ID_W-1:0] awid;
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logic [ADDR_W-1:0] awaddr;
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logic [7:0] awlen;
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logic [2:0] awsize;
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logic [1:0] awburst;
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logic awlock;
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logic [3:0] awcache;
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logic [2:0] awprot;
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logic [3:0] awqos;
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logic [3:0] awregion;
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logic [AWUSER_W-1:0] awuser;
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logic awvalid;
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logic awready;
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// W
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logic [DATA_W-1:0] wdata;
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logic [STRB_W-1:0] wstrb;
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logic wlast;
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logic [WUSER_W-1:0] wuser;
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logic wvalid;
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logic wready;
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// B
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logic [ID_W-1:0] bid;
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logic [1:0] bresp;
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logic [BUSER_W-1:0] buser;
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logic bvalid;
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logic bready;
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// AR
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logic [ID_W-1:0] arid;
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logic [ADDR_W-1:0] araddr;
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logic [7:0] arlen;
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logic [2:0] arsize;
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logic [1:0] arburst;
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logic arlock;
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logic [3:0] arcache;
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logic [2:0] arprot;
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logic [3:0] arqos;
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logic [3:0] arregion;
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logic [ARUSER_W-1:0] aruser;
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logic arvalid;
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logic arready;
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// R
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logic [ID_W-1:0] rid;
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logic [DATA_W-1:0] rdata;
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logic [1:0] rresp;
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logic rlast;
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logic [RUSER_W-1:0] ruser;
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logic rvalid;
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logic rready;
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modport wr_mst (
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// AW
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output awid,
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output awaddr,
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output awlen,
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output awsize,
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output awburst,
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output awlock,
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output awcache,
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output awprot,
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output awqos,
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output awregion,
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output awuser,
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output awvalid,
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input awready,
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// W
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output wdata,
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output wstrb,
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output wlast,
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output wuser,
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output wvalid,
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input wready,
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// B
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input bid,
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input bresp,
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input buser,
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input bvalid,
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output bready
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);
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modport rd_mst (
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// AR
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output arid,
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output araddr,
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output arlen,
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output arsize,
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output arburst,
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output arlock,
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output arcache,
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output arprot,
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output arqos,
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output arregion,
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output aruser,
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output arvalid,
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input arready,
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// R
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input rid,
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input rdata,
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input rresp,
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input rlast,
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input ruser,
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input rvalid,
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output rready
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);
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modport wr_slv (
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// AW
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input awid,
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input awaddr,
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input awlen,
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input awsize,
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input awburst,
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input awlock,
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input awcache,
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input awprot,
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input awqos,
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input awregion,
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input awuser,
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input awvalid,
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output awready,
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// W
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input wdata,
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input wstrb,
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input wlast,
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input wuser,
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input wvalid,
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output wready,
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// B
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output bid,
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output bresp,
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output buser,
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output bvalid,
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input bready
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);
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modport rd_slv (
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// AR
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input arid,
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input araddr,
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input arlen,
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input arsize,
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input arburst,
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input arlock,
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input arcache,
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input arprot,
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input arqos,
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input arregion,
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input aruser,
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input arvalid,
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output arready,
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// R
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output rid,
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output rdata,
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output rresp,
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output rlast,
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output ruser,
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output rvalid,
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input rready
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);
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modport wr_mon (
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// AW
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input awid,
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input awaddr,
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input awlen,
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input awsize,
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input awburst,
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input awlock,
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input awcache,
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input awprot,
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input awqos,
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input awregion,
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input awuser,
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input awvalid,
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input awready,
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// W
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input wdata,
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input wstrb,
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input wlast,
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input wuser,
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input wvalid,
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input wready,
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// B
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input bid,
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input bresp,
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input buser,
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input bvalid,
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input bready
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);
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modport rd_mon (
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// AR
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input arid,
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input araddr,
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input arlen,
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input arsize,
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input arburst,
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input arlock,
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input arcache,
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input arprot,
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input arqos,
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input arregion,
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input aruser,
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input arvalid,
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input arready,
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// R
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input rid,
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input rdata,
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input rresp,
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input rlast,
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input ruser,
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input rvalid,
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input rready
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);
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endinterface
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327
src/axi/rtl/taxi_axi_ram.sv
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327
src/axi/rtl/taxi_axi_ram.sv
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@@ -0,0 +1,327 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 RAM
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*/
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module taxi_axi_ram #
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(
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// Width of address bus in bits
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parameter ADDR_W = 16,
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// Extra pipeline register on output
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parameter logic PIPELINE_OUTPUT = 1'b0
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4 slave interface
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*/
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taxi_axi_if.wr_slv s_axi_wr,
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taxi_axi_if.rd_slv s_axi_rd
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);
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// extract parameters
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localparam DATA_W = s_axi_wr.DATA_W;
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localparam STRB_W = s_axi_wr.STRB_W;
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localparam WR_ID_W = s_axi_wr.ID_W;
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localparam RD_ID_W = s_axi_rd.ID_W;
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localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
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localparam BYTE_LANES = STRB_W;
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localparam BYTE_W = DATA_W/BYTE_LANES;
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// check configuration
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if (BYTE_W * STRB_W != DATA_W)
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$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
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if (2**$clog2(BYTE_LANES) != BYTE_LANES)
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$fatal(0, "Error: AXI byte lane count must be even power of two (instance %m)");
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if (s_axi_wr.DATA_W != s_axi_rd.DATA_W)
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$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
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if (s_axi_wr.ADDR_W < ADDR_W || s_axi_rd.ADDR_W < ADDR_W)
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$fatal(0, "Error: AXI address width is insufficient (instance %m)");
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localparam [0:0]
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READ_STATE_IDLE = 1'd0,
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READ_STATE_BURST = 1'd1;
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logic [0:0] read_state_reg = READ_STATE_IDLE, read_state_next;
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localparam [1:0]
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WRITE_STATE_IDLE = 2'd0,
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WRITE_STATE_BURST = 2'd1,
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WRITE_STATE_RESP = 2'd2;
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logic [1:0] write_state_reg = WRITE_STATE_IDLE, write_state_next;
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logic mem_wr_en;
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logic mem_rd_en;
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logic [WR_ID_W-1:0] write_id_reg = '0, write_id_next;
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logic [ADDR_W-1:0] write_addr_reg = '0, write_addr_next;
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logic [7:0] write_count_reg = 8'd0, write_count_next;
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logic [2:0] write_size_reg = 3'd0, write_size_next;
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logic [1:0] write_burst_reg = 2'd0, write_burst_next;
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logic [RD_ID_W-1:0] read_id_reg = '0, read_id_next;
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logic [ADDR_W-1:0] read_addr_reg = '0, read_addr_next;
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logic [7:0] read_count_reg = 8'd0, read_count_next;
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logic [2:0] read_size_reg = 3'd0, read_size_next;
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logic [1:0] read_burst_reg = 2'd0, read_burst_next;
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logic s_axi_awready_reg = 1'b0, s_axi_awready_next;
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logic s_axi_wready_reg = 1'b0, s_axi_wready_next;
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logic [WR_ID_W-1:0] s_axi_bid_reg = '0, s_axi_bid_next;
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logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
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logic s_axi_arready_reg = 1'b0, s_axi_arready_next;
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logic [RD_ID_W-1:0] s_axi_rid_reg = '0, s_axi_rid_next;
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logic [DATA_W-1:0] s_axi_rdata_reg = '0, s_axi_rdata_next;
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logic s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
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logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
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logic [RD_ID_W-1:0] s_axi_rid_pipe_reg = '0;
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logic [DATA_W-1:0] s_axi_rdata_pipe_reg = '0;
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logic s_axi_rlast_pipe_reg = 1'b0;
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logic s_axi_rvalid_pipe_reg = 1'b0;
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// (* RAM_STYLE="BLOCK" *)
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logic [DATA_W-1:0] mem[2**VALID_ADDR_W];
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wire [VALID_ADDR_W-1:0] read_addr_valid = VALID_ADDR_W'(read_addr_reg >> (ADDR_W - VALID_ADDR_W));
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wire [VALID_ADDR_W-1:0] write_addr_valid = VALID_ADDR_W'(write_addr_reg >> (ADDR_W - VALID_ADDR_W));
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assign s_axi_wr.awready = s_axi_awready_reg;
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assign s_axi_wr.wready = s_axi_wready_reg;
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assign s_axi_wr.bid = s_axi_bid_reg;
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assign s_axi_wr.bresp = 2'b00;
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assign s_axi_wr.bvalid = s_axi_bvalid_reg;
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assign s_axi_rd.arready = s_axi_arready_reg;
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assign s_axi_rd.rid = PIPELINE_OUTPUT ? s_axi_rid_pipe_reg : s_axi_rid_reg;
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assign s_axi_rd.rdata = PIPELINE_OUTPUT ? s_axi_rdata_pipe_reg : s_axi_rdata_reg;
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assign s_axi_rd.rresp = 2'b00;
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assign s_axi_rd.rlast = PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : s_axi_rlast_reg;
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assign s_axi_rd.rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg;
|
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|
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initial begin
|
||||
// two nested loops for smaller number of iterations per loop
|
||||
// workaround for synthesizer complaints about large loop counts
|
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for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin
|
||||
for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin
|
||||
mem[j] = '0;
|
||||
end
|
||||
end
|
||||
end
|
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|
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always_comb begin
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write_state_next = WRITE_STATE_IDLE;
|
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|
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mem_wr_en = 1'b0;
|
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|
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write_id_next = write_id_reg;
|
||||
write_addr_next = write_addr_reg;
|
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write_count_next = write_count_reg;
|
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write_size_next = write_size_reg;
|
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write_burst_next = write_burst_reg;
|
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|
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s_axi_awready_next = 1'b0;
|
||||
s_axi_wready_next = 1'b0;
|
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s_axi_bid_next = s_axi_bid_reg;
|
||||
s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_wr.bready;
|
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|
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case (write_state_reg)
|
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WRITE_STATE_IDLE: begin
|
||||
s_axi_awready_next = 1'b1;
|
||||
|
||||
if (s_axi_wr.awready && s_axi_wr.awvalid) begin
|
||||
write_id_next = s_axi_wr.awid;
|
||||
write_addr_next = ADDR_W'(s_axi_wr.awaddr);
|
||||
write_count_next = s_axi_wr.awlen;
|
||||
write_size_next = s_axi_wr.awsize <= 3'($clog2(STRB_W)) ? s_axi_wr.awsize : 3'($clog2(STRB_W));
|
||||
write_burst_next = s_axi_wr.awburst;
|
||||
|
||||
s_axi_awready_next = 1'b0;
|
||||
s_axi_wready_next = 1'b1;
|
||||
write_state_next = WRITE_STATE_BURST;
|
||||
end else begin
|
||||
write_state_next = WRITE_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
WRITE_STATE_BURST: begin
|
||||
s_axi_wready_next = 1'b1;
|
||||
|
||||
if (s_axi_wr.wready && s_axi_wr.wvalid) begin
|
||||
mem_wr_en = 1'b1;
|
||||
if (write_burst_reg != 2'b00) begin
|
||||
write_addr_next = write_addr_reg + (1 << write_size_reg);
|
||||
end
|
||||
write_count_next = write_count_reg - 1;
|
||||
if (write_count_reg > 0) begin
|
||||
write_state_next = WRITE_STATE_BURST;
|
||||
end else begin
|
||||
s_axi_wready_next = 1'b0;
|
||||
if (s_axi_wr.bready || !s_axi_wr.bvalid) begin
|
||||
s_axi_bid_next = write_id_reg;
|
||||
s_axi_bvalid_next = 1'b1;
|
||||
s_axi_awready_next = 1'b1;
|
||||
write_state_next = WRITE_STATE_IDLE;
|
||||
end else begin
|
||||
write_state_next = WRITE_STATE_RESP;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
write_state_next = WRITE_STATE_BURST;
|
||||
end
|
||||
end
|
||||
WRITE_STATE_RESP: begin
|
||||
if (s_axi_wr.bready || !s_axi_wr.bvalid) begin
|
||||
s_axi_bid_next = write_id_reg;
|
||||
s_axi_bvalid_next = 1'b1;
|
||||
s_axi_awready_next = 1'b1;
|
||||
write_state_next = WRITE_STATE_IDLE;
|
||||
end else begin
|
||||
write_state_next = WRITE_STATE_RESP;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
write_state_next = WRITE_STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
write_state_reg <= write_state_next;
|
||||
|
||||
write_id_reg <= write_id_next;
|
||||
write_addr_reg <= write_addr_next;
|
||||
write_count_reg <= write_count_next;
|
||||
write_size_reg <= write_size_next;
|
||||
write_burst_reg <= write_burst_next;
|
||||
|
||||
s_axi_awready_reg <= s_axi_awready_next;
|
||||
s_axi_wready_reg <= s_axi_wready_next;
|
||||
s_axi_bid_reg <= s_axi_bid_next;
|
||||
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
||||
|
||||
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
|
||||
if (mem_wr_en & s_axi_wr.wstrb[i]) begin
|
||||
mem[write_addr_valid][BYTE_W*i +: BYTE_W] <= s_axi_wr.wdata[BYTE_W*i +: BYTE_W];
|
||||
end
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
write_state_reg <= WRITE_STATE_IDLE;
|
||||
|
||||
s_axi_awready_reg <= 1'b0;
|
||||
s_axi_wready_reg <= 1'b0;
|
||||
s_axi_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
read_state_next = READ_STATE_IDLE;
|
||||
|
||||
mem_rd_en = 1'b0;
|
||||
|
||||
s_axi_rid_next = s_axi_rid_reg;
|
||||
s_axi_rlast_next = s_axi_rlast_reg;
|
||||
s_axi_rvalid_next = s_axi_rvalid_reg && !(s_axi_rd.rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg));
|
||||
|
||||
read_id_next = read_id_reg;
|
||||
read_addr_next = read_addr_reg;
|
||||
read_count_next = read_count_reg;
|
||||
read_size_next = read_size_reg;
|
||||
read_burst_next = read_burst_reg;
|
||||
|
||||
s_axi_arready_next = 1'b0;
|
||||
|
||||
case (read_state_reg)
|
||||
READ_STATE_IDLE: begin
|
||||
s_axi_arready_next = 1'b1;
|
||||
|
||||
if (s_axi_rd.arready && s_axi_rd.arvalid) begin
|
||||
read_id_next = s_axi_rd.arid;
|
||||
read_addr_next = ADDR_W'(s_axi_rd.araddr);
|
||||
read_count_next = s_axi_rd.arlen;
|
||||
read_size_next = s_axi_rd.arsize <= 3'($clog2(STRB_W)) ? s_axi_rd.arsize : 3'($clog2(STRB_W));
|
||||
read_burst_next = s_axi_rd.arburst;
|
||||
|
||||
s_axi_arready_next = 1'b0;
|
||||
read_state_next = READ_STATE_BURST;
|
||||
end else begin
|
||||
read_state_next = READ_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
READ_STATE_BURST: begin
|
||||
if (s_axi_rd.rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg) || !s_axi_rvalid_reg) begin
|
||||
mem_rd_en = 1'b1;
|
||||
s_axi_rvalid_next = 1'b1;
|
||||
s_axi_rid_next = read_id_reg;
|
||||
s_axi_rlast_next = read_count_reg == 0;
|
||||
if (read_burst_reg != 2'b00) begin
|
||||
read_addr_next = read_addr_reg + (1 << read_size_reg);
|
||||
end
|
||||
read_count_next = read_count_reg - 1;
|
||||
if (read_count_reg > 0) begin
|
||||
read_state_next = READ_STATE_BURST;
|
||||
end else begin
|
||||
s_axi_arready_next = 1'b1;
|
||||
read_state_next = READ_STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
read_state_next = READ_STATE_BURST;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
read_state_reg <= read_state_next;
|
||||
|
||||
read_id_reg <= read_id_next;
|
||||
read_addr_reg <= read_addr_next;
|
||||
read_count_reg <= read_count_next;
|
||||
read_size_reg <= read_size_next;
|
||||
read_burst_reg <= read_burst_next;
|
||||
|
||||
s_axi_arready_reg <= s_axi_arready_next;
|
||||
s_axi_rid_reg <= s_axi_rid_next;
|
||||
s_axi_rlast_reg <= s_axi_rlast_next;
|
||||
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
||||
|
||||
if (mem_rd_en) begin
|
||||
s_axi_rdata_reg <= mem[read_addr_valid];
|
||||
end
|
||||
|
||||
if (!s_axi_rvalid_pipe_reg || s_axi_rd.rready) begin
|
||||
s_axi_rid_pipe_reg <= s_axi_rid_reg;
|
||||
s_axi_rdata_pipe_reg <= s_axi_rdata_reg;
|
||||
s_axi_rlast_pipe_reg <= s_axi_rlast_reg;
|
||||
s_axi_rvalid_pipe_reg <= s_axi_rvalid_reg;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
read_state_reg <= READ_STATE_IDLE;
|
||||
|
||||
s_axi_arready_reg <= 1'b0;
|
||||
s_axi_rvalid_reg <= 1'b0;
|
||||
s_axi_rvalid_pipe_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
4
src/axi/rtl/taxi_axi_register.f
Normal file
4
src/axi/rtl/taxi_axi_register.f
Normal file
@@ -0,0 +1,4 @@
|
||||
taxi_axi_register.sv
|
||||
taxi_axi_register_wr.sv
|
||||
taxi_axi_register_rd.sv
|
||||
taxi_axi_if.sv
|
||||
94
src/axi/rtl/taxi_axi_register.sv
Normal file
94
src/axi/rtl/taxi_axi_register.sv
Normal file
@@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 register
|
||||
*/
|
||||
module taxi_axi_register #
|
||||
(
|
||||
// AW channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter AW_REG_TYPE = 1,
|
||||
// W channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter W_REG_TYPE = 2,
|
||||
// B channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter B_REG_TYPE = 1,
|
||||
// AR channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter AR_REG_TYPE = 1,
|
||||
// R channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter R_REG_TYPE = 2
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
taxi_axi_if.wr_slv s_axi_wr,
|
||||
taxi_axi_if.rd_slv s_axi_rd,
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
taxi_axi_if.wr_mst m_axi_wr,
|
||||
taxi_axi_if.rd_mst m_axi_rd
|
||||
);
|
||||
|
||||
taxi_axi_register_wr #(
|
||||
.AW_REG_TYPE(AW_REG_TYPE),
|
||||
.W_REG_TYPE(W_REG_TYPE),
|
||||
.B_REG_TYPE(B_REG_TYPE)
|
||||
)
|
||||
axi_register_wr_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
.s_axi_wr(s_axi_wr),
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
.m_axi_wr(m_axi_wr)
|
||||
);
|
||||
|
||||
taxi_axi_register_rd #(
|
||||
.AR_REG_TYPE(AR_REG_TYPE),
|
||||
.R_REG_TYPE(R_REG_TYPE)
|
||||
)
|
||||
axi_register_rd_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
.s_axi_rd(s_axi_rd),
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
.m_axi_rd(m_axi_rd)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
472
src/axi/rtl/taxi_axi_register_rd.sv
Normal file
472
src/axi/rtl/taxi_axi_register_rd.sv
Normal file
@@ -0,0 +1,472 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 register (read)
|
||||
*/
|
||||
module taxi_axi_register_rd #
|
||||
(
|
||||
// AR channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter AR_REG_TYPE = 1,
|
||||
// R channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter R_REG_TYPE = 2
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
taxi_axi_if.rd_slv s_axi_rd,
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
taxi_axi_if.rd_mst m_axi_rd
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axi_rd.DATA_W;
|
||||
localparam ADDR_W = s_axi_rd.ADDR_W;
|
||||
localparam STRB_W = s_axi_rd.STRB_W;
|
||||
localparam ID_W = s_axi_rd.ID_W;
|
||||
localparam logic ARUSER_EN = s_axi_rd.ARUSER_EN && m_axi_rd.ARUSER_EN;
|
||||
localparam ARUSER_W = s_axi_rd.ARUSER_W;
|
||||
localparam logic RUSER_EN = s_axi_rd.RUSER_EN && m_axi_rd.RUSER_EN;
|
||||
localparam RUSER_W = s_axi_rd.RUSER_W;
|
||||
|
||||
if (m_axi_rd.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (m_axi_rd.STRB_W != STRB_W)
|
||||
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
|
||||
|
||||
// AR channel
|
||||
|
||||
if (AR_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_arready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] m_axi_arid_reg = '0;
|
||||
logic [ADDR_W-1:0] m_axi_araddr_reg = '0;
|
||||
logic [7:0] m_axi_arlen_reg = '0;
|
||||
logic [2:0] m_axi_arsize_reg = '0;
|
||||
logic [1:0] m_axi_arburst_reg = '0;
|
||||
logic m_axi_arlock_reg = '0;
|
||||
logic [3:0] m_axi_arcache_reg = '0;
|
||||
logic [2:0] m_axi_arprot_reg = '0;
|
||||
logic [3:0] m_axi_arqos_reg = '0;
|
||||
logic [3:0] m_axi_arregion_reg = '0;
|
||||
logic [ARUSER_W-1:0] m_axi_aruser_reg = '0;
|
||||
logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
|
||||
|
||||
logic [ID_W-1:0] temp_m_axi_arid_reg = '0;
|
||||
logic [ADDR_W-1:0] temp_m_axi_araddr_reg = '0;
|
||||
logic [7:0] temp_m_axi_arlen_reg = '0;
|
||||
logic [2:0] temp_m_axi_arsize_reg = '0;
|
||||
logic [1:0] temp_m_axi_arburst_reg = '0;
|
||||
logic temp_m_axi_arlock_reg = '0;
|
||||
logic [3:0] temp_m_axi_arcache_reg = '0;
|
||||
logic [2:0] temp_m_axi_arprot_reg = '0;
|
||||
logic [3:0] temp_m_axi_arqos_reg = '0;
|
||||
logic [3:0] temp_m_axi_arregion_reg = '0;
|
||||
logic [ARUSER_W-1:0] temp_m_axi_aruser_reg = '0;
|
||||
logic temp_m_axi_arvalid_reg = 1'b0, temp_m_axi_arvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_ar_input_to_output;
|
||||
logic store_axi_ar_input_to_temp;
|
||||
logic store_axi_ar_temp_to_output;
|
||||
|
||||
assign s_axi_rd.arready = s_axi_arready_reg;
|
||||
|
||||
assign m_axi_rd.arid = m_axi_arid_reg;
|
||||
assign m_axi_rd.araddr = m_axi_araddr_reg;
|
||||
assign m_axi_rd.arlen = m_axi_arlen_reg;
|
||||
assign m_axi_rd.arsize = m_axi_arsize_reg;
|
||||
assign m_axi_rd.arburst = m_axi_arburst_reg;
|
||||
assign m_axi_rd.arlock = m_axi_arlock_reg;
|
||||
assign m_axi_rd.arcache = m_axi_arcache_reg;
|
||||
assign m_axi_rd.arprot = m_axi_arprot_reg;
|
||||
assign m_axi_rd.arqos = m_axi_arqos_reg;
|
||||
assign m_axi_rd.arregion = m_axi_arregion_reg;
|
||||
assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0;
|
||||
assign m_axi_rd.arvalid = m_axi_arvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axi_arready_early = m_axi_rd.arready || (!temp_m_axi_arvalid_reg && (!m_axi_arvalid_reg || !s_axi_rd.arvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_arvalid_next = m_axi_arvalid_reg;
|
||||
temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg;
|
||||
|
||||
store_axi_ar_input_to_output = 1'b0;
|
||||
store_axi_ar_input_to_temp = 1'b0;
|
||||
store_axi_ar_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axi_arready_reg) begin
|
||||
// input is ready
|
||||
if (m_axi_rd.arready || !m_axi_arvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axi_arvalid_next = s_axi_rd.arvalid;
|
||||
store_axi_ar_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axi_arvalid_next = s_axi_rd.arvalid;
|
||||
store_axi_ar_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axi_rd.arready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axi_arvalid_next = temp_m_axi_arvalid_reg;
|
||||
temp_m_axi_arvalid_next = 1'b0;
|
||||
store_axi_ar_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_arready_reg <= s_axi_arready_early;
|
||||
m_axi_arvalid_reg <= m_axi_arvalid_next;
|
||||
temp_m_axi_arvalid_reg <= temp_m_axi_arvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_ar_input_to_output) begin
|
||||
m_axi_arid_reg <= s_axi_rd.arid;
|
||||
m_axi_araddr_reg <= s_axi_rd.araddr;
|
||||
m_axi_arlen_reg <= s_axi_rd.arlen;
|
||||
m_axi_arsize_reg <= s_axi_rd.arsize;
|
||||
m_axi_arburst_reg <= s_axi_rd.arburst;
|
||||
m_axi_arlock_reg <= s_axi_rd.arlock;
|
||||
m_axi_arcache_reg <= s_axi_rd.arcache;
|
||||
m_axi_arprot_reg <= s_axi_rd.arprot;
|
||||
m_axi_arqos_reg <= s_axi_rd.arqos;
|
||||
m_axi_arregion_reg <= s_axi_rd.arregion;
|
||||
m_axi_aruser_reg <= s_axi_rd.aruser;
|
||||
end else if (store_axi_ar_temp_to_output) begin
|
||||
m_axi_arid_reg <= temp_m_axi_arid_reg;
|
||||
m_axi_araddr_reg <= temp_m_axi_araddr_reg;
|
||||
m_axi_arlen_reg <= temp_m_axi_arlen_reg;
|
||||
m_axi_arsize_reg <= temp_m_axi_arsize_reg;
|
||||
m_axi_arburst_reg <= temp_m_axi_arburst_reg;
|
||||
m_axi_arlock_reg <= temp_m_axi_arlock_reg;
|
||||
m_axi_arcache_reg <= temp_m_axi_arcache_reg;
|
||||
m_axi_arprot_reg <= temp_m_axi_arprot_reg;
|
||||
m_axi_arqos_reg <= temp_m_axi_arqos_reg;
|
||||
m_axi_arregion_reg <= temp_m_axi_arregion_reg;
|
||||
m_axi_aruser_reg <= temp_m_axi_aruser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_ar_input_to_temp) begin
|
||||
temp_m_axi_arid_reg <= s_axi_rd.arid;
|
||||
temp_m_axi_araddr_reg <= s_axi_rd.araddr;
|
||||
temp_m_axi_arlen_reg <= s_axi_rd.arlen;
|
||||
temp_m_axi_arsize_reg <= s_axi_rd.arsize;
|
||||
temp_m_axi_arburst_reg <= s_axi_rd.arburst;
|
||||
temp_m_axi_arlock_reg <= s_axi_rd.arlock;
|
||||
temp_m_axi_arcache_reg <= s_axi_rd.arcache;
|
||||
temp_m_axi_arprot_reg <= s_axi_rd.arprot;
|
||||
temp_m_axi_arqos_reg <= s_axi_rd.arqos;
|
||||
temp_m_axi_arregion_reg <= s_axi_rd.arregion;
|
||||
temp_m_axi_aruser_reg <= s_axi_rd.aruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_arready_reg <= 1'b0;
|
||||
m_axi_arvalid_reg <= 1'b0;
|
||||
temp_m_axi_arvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (AR_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_arready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] m_axi_arid_reg = '0;
|
||||
logic [ADDR_W-1:0] m_axi_araddr_reg = '0;
|
||||
logic [7:0] m_axi_arlen_reg = '0;
|
||||
logic [2:0] m_axi_arsize_reg = '0;
|
||||
logic [1:0] m_axi_arburst_reg = '0;
|
||||
logic m_axi_arlock_reg = '0;
|
||||
logic [3:0] m_axi_arcache_reg = '0;
|
||||
logic [2:0] m_axi_arprot_reg = '0;
|
||||
logic [3:0] m_axi_arqos_reg = '0;
|
||||
logic [3:0] m_axi_arregion_reg = '0;
|
||||
logic [ARUSER_W-1:0] m_axi_aruser_reg = '0;
|
||||
logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_ar_input_to_output;
|
||||
|
||||
assign s_axi_rd.arready = s_axi_arready_reg;
|
||||
|
||||
assign m_axi_rd.arid = m_axi_arid_reg;
|
||||
assign m_axi_rd.araddr = m_axi_araddr_reg;
|
||||
assign m_axi_rd.arlen = m_axi_arlen_reg;
|
||||
assign m_axi_rd.arsize = m_axi_arsize_reg;
|
||||
assign m_axi_rd.arburst = m_axi_arburst_reg;
|
||||
assign m_axi_rd.arlock = m_axi_arlock_reg;
|
||||
assign m_axi_rd.arcache = m_axi_arcache_reg;
|
||||
assign m_axi_rd.arprot = m_axi_arprot_reg;
|
||||
assign m_axi_rd.arqos = m_axi_arqos_reg;
|
||||
assign m_axi_rd.arregion = m_axi_arregion_reg;
|
||||
assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0;
|
||||
assign m_axi_rd.arvalid = m_axi_arvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axi_arready_early = !m_axi_arvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_arvalid_next = m_axi_arvalid_reg;
|
||||
|
||||
store_axi_ar_input_to_output = 1'b0;
|
||||
|
||||
if (s_axi_arready_reg) begin
|
||||
m_axi_arvalid_next = s_axi_rd.arvalid;
|
||||
store_axi_ar_input_to_output = 1'b1;
|
||||
end else if (m_axi_rd.arready) begin
|
||||
m_axi_arvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_arready_reg <= s_axi_arready_early;
|
||||
m_axi_arvalid_reg <= m_axi_arvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_ar_input_to_output) begin
|
||||
m_axi_arid_reg <= s_axi_rd.arid;
|
||||
m_axi_araddr_reg <= s_axi_rd.araddr;
|
||||
m_axi_arlen_reg <= s_axi_rd.arlen;
|
||||
m_axi_arsize_reg <= s_axi_rd.arsize;
|
||||
m_axi_arburst_reg <= s_axi_rd.arburst;
|
||||
m_axi_arlock_reg <= s_axi_rd.arlock;
|
||||
m_axi_arcache_reg <= s_axi_rd.arcache;
|
||||
m_axi_arprot_reg <= s_axi_rd.arprot;
|
||||
m_axi_arqos_reg <= s_axi_rd.arqos;
|
||||
m_axi_arregion_reg <= s_axi_rd.arregion;
|
||||
m_axi_aruser_reg <= s_axi_rd.aruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_arready_reg <= 1'b0;
|
||||
m_axi_arvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass AR channel
|
||||
assign m_axi_rd.arid = s_axi_rd.arid;
|
||||
assign m_axi_rd.araddr = s_axi_rd.araddr;
|
||||
assign m_axi_rd.arlen = s_axi_rd.arlen;
|
||||
assign m_axi_rd.arsize = s_axi_rd.arsize;
|
||||
assign m_axi_rd.arburst = s_axi_rd.arburst;
|
||||
assign m_axi_rd.arlock = s_axi_rd.arlock;
|
||||
assign m_axi_rd.arcache = s_axi_rd.arcache;
|
||||
assign m_axi_rd.arprot = s_axi_rd.arprot;
|
||||
assign m_axi_rd.arqos = s_axi_rd.arqos;
|
||||
assign m_axi_rd.arregion = s_axi_rd.arregion;
|
||||
assign m_axi_rd.aruser = ARUSER_EN ? s_axi_rd.aruser : '0;
|
||||
assign m_axi_rd.arvalid = s_axi_rd.arvalid;
|
||||
assign s_axi_rd.arready = m_axi_rd.arready;
|
||||
|
||||
end
|
||||
|
||||
// R channel
|
||||
|
||||
if (R_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axi_rready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] s_axi_rid_reg = '0;
|
||||
logic [DATA_W-1:0] s_axi_rdata_reg = '0;
|
||||
logic [1:0] s_axi_rresp_reg = 2'b0;
|
||||
logic s_axi_rlast_reg = 1'b0;
|
||||
logic [RUSER_W-1:0] s_axi_ruser_reg = '0;
|
||||
logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
|
||||
|
||||
logic [ID_W-1:0] temp_s_axi_rid_reg = '0;
|
||||
logic [DATA_W-1:0] temp_s_axi_rdata_reg = '0;
|
||||
logic [1:0] temp_s_axi_rresp_reg = 2'b0;
|
||||
logic temp_s_axi_rlast_reg = 1'b0;
|
||||
logic [RUSER_W-1:0] temp_s_axi_ruser_reg = '0;
|
||||
logic temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_r_input_to_output;
|
||||
logic store_axi_r_input_to_temp;
|
||||
logic store_axi_r_temp_to_output;
|
||||
|
||||
assign m_axi_rd.rready = m_axi_rready_reg;
|
||||
|
||||
assign s_axi_rd.rid = s_axi_rid_reg;
|
||||
assign s_axi_rd.rdata = s_axi_rdata_reg;
|
||||
assign s_axi_rd.rresp = s_axi_rresp_reg;
|
||||
assign s_axi_rd.rlast = s_axi_rlast_reg;
|
||||
assign s_axi_rd.ruser = RUSER_EN ? s_axi_ruser_reg : '0;
|
||||
assign s_axi_rd.rvalid = s_axi_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire m_axi_rready_early = s_axi_rd.rready || (!temp_s_axi_rvalid_reg && (!s_axi_rvalid_reg || !m_axi_rd.rvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axi_rvalid_next = s_axi_rvalid_reg;
|
||||
temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;
|
||||
|
||||
store_axi_r_input_to_output = 1'b0;
|
||||
store_axi_r_input_to_temp = 1'b0;
|
||||
store_axi_r_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axi_rready_reg) begin
|
||||
// input is ready
|
||||
if (s_axi_rd.rready || !s_axi_rvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axi_rvalid_next = m_axi_rd.rvalid;
|
||||
store_axi_r_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axi_rvalid_next = m_axi_rd.rvalid;
|
||||
store_axi_r_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (s_axi_rd.rready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axi_rvalid_next = temp_s_axi_rvalid_reg;
|
||||
temp_s_axi_rvalid_next = 1'b0;
|
||||
store_axi_r_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axi_rready_reg <= m_axi_rready_early;
|
||||
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
||||
temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_r_input_to_output) begin
|
||||
s_axi_rid_reg <= m_axi_rd.rid;
|
||||
s_axi_rdata_reg <= m_axi_rd.rdata;
|
||||
s_axi_rresp_reg <= m_axi_rd.rresp;
|
||||
s_axi_rlast_reg <= m_axi_rd.rlast;
|
||||
s_axi_ruser_reg <= m_axi_rd.ruser;
|
||||
end else if (store_axi_r_temp_to_output) begin
|
||||
s_axi_rid_reg <= temp_s_axi_rid_reg;
|
||||
s_axi_rdata_reg <= temp_s_axi_rdata_reg;
|
||||
s_axi_rresp_reg <= temp_s_axi_rresp_reg;
|
||||
s_axi_rlast_reg <= temp_s_axi_rlast_reg;
|
||||
s_axi_ruser_reg <= temp_s_axi_ruser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_r_input_to_temp) begin
|
||||
temp_s_axi_rid_reg <= m_axi_rd.rid;
|
||||
temp_s_axi_rdata_reg <= m_axi_rd.rdata;
|
||||
temp_s_axi_rresp_reg <= m_axi_rd.rresp;
|
||||
temp_s_axi_rlast_reg <= m_axi_rd.rlast;
|
||||
temp_s_axi_ruser_reg <= m_axi_rd.ruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axi_rready_reg <= 1'b0;
|
||||
s_axi_rvalid_reg <= 1'b0;
|
||||
temp_s_axi_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (R_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axi_rready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] s_axi_rid_reg = '0;
|
||||
logic [DATA_W-1:0] s_axi_rdata_reg = '0;
|
||||
logic [1:0] s_axi_rresp_reg = 2'b0;
|
||||
logic s_axi_rlast_reg = 1'b0;
|
||||
logic [RUSER_W-1:0] s_axi_ruser_reg = '0;
|
||||
logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_r_input_to_output;
|
||||
|
||||
assign m_axi_rd.rready = m_axi_rready_reg;
|
||||
|
||||
assign s_axi_rd.rid = s_axi_rid_reg;
|
||||
assign s_axi_rd.rdata = s_axi_rdata_reg;
|
||||
assign s_axi_rd.rresp = s_axi_rresp_reg;
|
||||
assign s_axi_rd.rlast = s_axi_rlast_reg;
|
||||
assign s_axi_rd.ruser = RUSER_EN ? s_axi_ruser_reg : '0;
|
||||
assign s_axi_rd.rvalid = s_axi_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axi_rready_early = !s_axi_rvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axi_rvalid_next = s_axi_rvalid_reg;
|
||||
|
||||
store_axi_r_input_to_output = 1'b0;
|
||||
|
||||
if (m_axi_rready_reg) begin
|
||||
s_axi_rvalid_next = m_axi_rd.rvalid;
|
||||
store_axi_r_input_to_output = 1'b1;
|
||||
end else if (s_axi_rd.rready) begin
|
||||
s_axi_rvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axi_rready_reg <= m_axi_rready_early;
|
||||
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_r_input_to_output) begin
|
||||
s_axi_rid_reg <= m_axi_rd.rid;
|
||||
s_axi_rdata_reg <= m_axi_rd.rdata;
|
||||
s_axi_rresp_reg <= m_axi_rd.rresp;
|
||||
s_axi_rlast_reg <= m_axi_rd.rlast;
|
||||
s_axi_ruser_reg <= m_axi_rd.ruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axi_rready_reg <= 1'b0;
|
||||
s_axi_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass R channel
|
||||
assign s_axi_rd.rid = m_axi_rd.rid;
|
||||
assign s_axi_rd.rdata = m_axi_rd.rdata;
|
||||
assign s_axi_rd.rresp = m_axi_rd.rresp;
|
||||
assign s_axi_rd.rlast = m_axi_rd.rlast;
|
||||
assign s_axi_rd.ruser = RUSER_EN ? m_axi_rd.ruser : '0;
|
||||
assign s_axi_rd.rvalid = m_axi_rd.rvalid;
|
||||
assign m_axi_rd.rready = s_axi_rd.rready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
623
src/axi/rtl/taxi_axi_register_wr.sv
Normal file
623
src/axi/rtl/taxi_axi_register_wr.sv
Normal file
@@ -0,0 +1,623 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 register (write)
|
||||
*/
|
||||
module taxi_axi_register_wr #
|
||||
(
|
||||
// AW channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter AW_REG_TYPE = 1,
|
||||
// W channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter W_REG_TYPE = 2,
|
||||
// B channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter B_REG_TYPE = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
taxi_axi_if.wr_slv s_axi_wr,
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
taxi_axi_if.wr_mst m_axi_wr
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axi_wr.DATA_W;
|
||||
localparam ADDR_W = s_axi_wr.ADDR_W;
|
||||
localparam STRB_W = s_axi_wr.STRB_W;
|
||||
localparam ID_W = s_axi_wr.ID_W;
|
||||
localparam logic AWUSER_EN = s_axi_wr.AWUSER_EN && m_axi_wr.AWUSER_EN;
|
||||
localparam AWUSER_W = s_axi_wr.AWUSER_W;
|
||||
localparam logic WUSER_EN = s_axi_wr.WUSER_EN && m_axi_wr.WUSER_EN;
|
||||
localparam WUSER_W = s_axi_wr.WUSER_W;
|
||||
localparam logic BUSER_EN = s_axi_wr.BUSER_EN && m_axi_wr.BUSER_EN;
|
||||
localparam BUSER_W = s_axi_wr.BUSER_W;
|
||||
|
||||
if (m_axi_wr.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (m_axi_wr.STRB_W != STRB_W)
|
||||
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
|
||||
|
||||
// AW channel
|
||||
|
||||
if (AW_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_awready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] m_axi_awid_reg = '0;
|
||||
logic [ADDR_W-1:0] m_axi_awaddr_reg = '0;
|
||||
logic [7:0] m_axi_awlen_reg = '0;
|
||||
logic [2:0] m_axi_awsize_reg = '0;
|
||||
logic [1:0] m_axi_awburst_reg = '0;
|
||||
logic m_axi_awlock_reg = '0;
|
||||
logic [3:0] m_axi_awcache_reg = '0;
|
||||
logic [2:0] m_axi_awprot_reg = '0;
|
||||
logic [3:0] m_axi_awqos_reg = '0;
|
||||
logic [3:0] m_axi_awregion_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axi_awuser_reg = '0;
|
||||
logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
|
||||
|
||||
logic [ID_W-1:0] temp_m_axi_awid_reg = '0;
|
||||
logic [ADDR_W-1:0] temp_m_axi_awaddr_reg = '0;
|
||||
logic [7:0] temp_m_axi_awlen_reg = '0;
|
||||
logic [2:0] temp_m_axi_awsize_reg = '0;
|
||||
logic [1:0] temp_m_axi_awburst_reg = '0;
|
||||
logic temp_m_axi_awlock_reg = '0;
|
||||
logic [3:0] temp_m_axi_awcache_reg = '0;
|
||||
logic [2:0] temp_m_axi_awprot_reg = '0;
|
||||
logic [3:0] temp_m_axi_awqos_reg = '0;
|
||||
logic [3:0] temp_m_axi_awregion_reg = '0;
|
||||
logic [AWUSER_W-1:0] temp_m_axi_awuser_reg = '0;
|
||||
logic temp_m_axi_awvalid_reg = 1'b0, temp_m_axi_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_aw_input_to_output;
|
||||
logic store_axi_aw_input_to_temp;
|
||||
logic store_axi_aw_temp_to_output;
|
||||
|
||||
assign s_axi_wr.awready = s_axi_awready_reg;
|
||||
|
||||
assign m_axi_wr.awid = m_axi_awid_reg;
|
||||
assign m_axi_wr.awaddr = m_axi_awaddr_reg;
|
||||
assign m_axi_wr.awlen = m_axi_awlen_reg;
|
||||
assign m_axi_wr.awsize = m_axi_awsize_reg;
|
||||
assign m_axi_wr.awburst = m_axi_awburst_reg;
|
||||
assign m_axi_wr.awlock = m_axi_awlock_reg;
|
||||
assign m_axi_wr.awcache = m_axi_awcache_reg;
|
||||
assign m_axi_wr.awprot = m_axi_awprot_reg;
|
||||
assign m_axi_wr.awqos = m_axi_awqos_reg;
|
||||
assign m_axi_wr.awregion = m_axi_awregion_reg;
|
||||
assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0;
|
||||
assign m_axi_wr.awvalid = m_axi_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axi_awready_early = m_axi_wr.awready || (!temp_m_axi_awvalid_reg && (!m_axi_awvalid_reg || !s_axi_wr.awvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_awvalid_next = m_axi_awvalid_reg;
|
||||
temp_m_axi_awvalid_next = temp_m_axi_awvalid_reg;
|
||||
|
||||
store_axi_aw_input_to_output = 1'b0;
|
||||
store_axi_aw_input_to_temp = 1'b0;
|
||||
store_axi_aw_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axi_awready_reg) begin
|
||||
// input is ready
|
||||
if (m_axi_wr.awready || !m_axi_awvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axi_awvalid_next = s_axi_wr.awvalid;
|
||||
store_axi_aw_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axi_awvalid_next = s_axi_wr.awvalid;
|
||||
store_axi_aw_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axi_wr.awready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axi_awvalid_next = temp_m_axi_awvalid_reg;
|
||||
temp_m_axi_awvalid_next = 1'b0;
|
||||
store_axi_aw_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_awready_reg <= s_axi_awready_early;
|
||||
m_axi_awvalid_reg <= m_axi_awvalid_next;
|
||||
temp_m_axi_awvalid_reg <= temp_m_axi_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_aw_input_to_output) begin
|
||||
m_axi_awid_reg <= s_axi_wr.awid;
|
||||
m_axi_awaddr_reg <= s_axi_wr.awaddr;
|
||||
m_axi_awlen_reg <= s_axi_wr.awlen;
|
||||
m_axi_awsize_reg <= s_axi_wr.awsize;
|
||||
m_axi_awburst_reg <= s_axi_wr.awburst;
|
||||
m_axi_awlock_reg <= s_axi_wr.awlock;
|
||||
m_axi_awcache_reg <= s_axi_wr.awcache;
|
||||
m_axi_awprot_reg <= s_axi_wr.awprot;
|
||||
m_axi_awqos_reg <= s_axi_wr.awqos;
|
||||
m_axi_awregion_reg <= s_axi_wr.awregion;
|
||||
m_axi_awuser_reg <= s_axi_wr.awuser;
|
||||
end else if (store_axi_aw_temp_to_output) begin
|
||||
m_axi_awid_reg <= temp_m_axi_awid_reg;
|
||||
m_axi_awaddr_reg <= temp_m_axi_awaddr_reg;
|
||||
m_axi_awlen_reg <= temp_m_axi_awlen_reg;
|
||||
m_axi_awsize_reg <= temp_m_axi_awsize_reg;
|
||||
m_axi_awburst_reg <= temp_m_axi_awburst_reg;
|
||||
m_axi_awlock_reg <= temp_m_axi_awlock_reg;
|
||||
m_axi_awcache_reg <= temp_m_axi_awcache_reg;
|
||||
m_axi_awprot_reg <= temp_m_axi_awprot_reg;
|
||||
m_axi_awqos_reg <= temp_m_axi_awqos_reg;
|
||||
m_axi_awregion_reg <= temp_m_axi_awregion_reg;
|
||||
m_axi_awuser_reg <= temp_m_axi_awuser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_aw_input_to_temp) begin
|
||||
temp_m_axi_awid_reg <= s_axi_wr.awid;
|
||||
temp_m_axi_awaddr_reg <= s_axi_wr.awaddr;
|
||||
temp_m_axi_awlen_reg <= s_axi_wr.awlen;
|
||||
temp_m_axi_awsize_reg <= s_axi_wr.awsize;
|
||||
temp_m_axi_awburst_reg <= s_axi_wr.awburst;
|
||||
temp_m_axi_awlock_reg <= s_axi_wr.awlock;
|
||||
temp_m_axi_awcache_reg <= s_axi_wr.awcache;
|
||||
temp_m_axi_awprot_reg <= s_axi_wr.awprot;
|
||||
temp_m_axi_awqos_reg <= s_axi_wr.awqos;
|
||||
temp_m_axi_awregion_reg <= s_axi_wr.awregion;
|
||||
temp_m_axi_awuser_reg <= s_axi_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_awready_reg <= 1'b0;
|
||||
m_axi_awvalid_reg <= 1'b0;
|
||||
temp_m_axi_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (AW_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_awready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] m_axi_awid_reg = '0;
|
||||
logic [ADDR_W-1:0] m_axi_awaddr_reg = '0;
|
||||
logic [7:0] m_axi_awlen_reg = '0;
|
||||
logic [2:0] m_axi_awsize_reg = '0;
|
||||
logic [1:0] m_axi_awburst_reg = '0;
|
||||
logic m_axi_awlock_reg = '0;
|
||||
logic [3:0] m_axi_awcache_reg = '0;
|
||||
logic [2:0] m_axi_awprot_reg = '0;
|
||||
logic [3:0] m_axi_awqos_reg = '0;
|
||||
logic [3:0] m_axi_awregion_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axi_awuser_reg = '0;
|
||||
logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_aw_input_to_output;
|
||||
|
||||
assign s_axi_wr.awready = s_axi_awready_reg;
|
||||
|
||||
assign m_axi_wr.awid = m_axi_awid_reg;
|
||||
assign m_axi_wr.awaddr = m_axi_awaddr_reg;
|
||||
assign m_axi_wr.awlen = m_axi_awlen_reg;
|
||||
assign m_axi_wr.awsize = m_axi_awsize_reg;
|
||||
assign m_axi_wr.awburst = m_axi_awburst_reg;
|
||||
assign m_axi_wr.awlock = m_axi_awlock_reg;
|
||||
assign m_axi_wr.awcache = m_axi_awcache_reg;
|
||||
assign m_axi_wr.awprot = m_axi_awprot_reg;
|
||||
assign m_axi_wr.awqos = m_axi_awqos_reg;
|
||||
assign m_axi_wr.awregion = m_axi_awregion_reg;
|
||||
assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0;
|
||||
assign m_axi_wr.awvalid = m_axi_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axi_awready_eawly = !m_axi_awvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_awvalid_next = m_axi_awvalid_reg;
|
||||
|
||||
store_axi_aw_input_to_output = 1'b0;
|
||||
|
||||
if (s_axi_awready_reg) begin
|
||||
m_axi_awvalid_next = s_axi_wr.awvalid;
|
||||
store_axi_aw_input_to_output = 1'b1;
|
||||
end else if (m_axi_wr.awready) begin
|
||||
m_axi_awvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_awready_reg <= s_axi_awready_eawly;
|
||||
m_axi_awvalid_reg <= m_axi_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_aw_input_to_output) begin
|
||||
m_axi_awid_reg <= s_axi_wr.awid;
|
||||
m_axi_awaddr_reg <= s_axi_wr.awaddr;
|
||||
m_axi_awlen_reg <= s_axi_wr.awlen;
|
||||
m_axi_awsize_reg <= s_axi_wr.awsize;
|
||||
m_axi_awburst_reg <= s_axi_wr.awburst;
|
||||
m_axi_awlock_reg <= s_axi_wr.awlock;
|
||||
m_axi_awcache_reg <= s_axi_wr.awcache;
|
||||
m_axi_awprot_reg <= s_axi_wr.awprot;
|
||||
m_axi_awqos_reg <= s_axi_wr.awqos;
|
||||
m_axi_awregion_reg <= s_axi_wr.awregion;
|
||||
m_axi_awuser_reg <= s_axi_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_awready_reg <= 1'b0;
|
||||
m_axi_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass AW channel
|
||||
assign m_axi_wr.awid = s_axi_wr.awid;
|
||||
assign m_axi_wr.awaddr = s_axi_wr.awaddr;
|
||||
assign m_axi_wr.awlen = s_axi_wr.awlen;
|
||||
assign m_axi_wr.awsize = s_axi_wr.awsize;
|
||||
assign m_axi_wr.awburst = s_axi_wr.awburst;
|
||||
assign m_axi_wr.awlock = s_axi_wr.awlock;
|
||||
assign m_axi_wr.awcache = s_axi_wr.awcache;
|
||||
assign m_axi_wr.awprot = s_axi_wr.awprot;
|
||||
assign m_axi_wr.awqos = s_axi_wr.awqos;
|
||||
assign m_axi_wr.awregion = s_axi_wr.awregion;
|
||||
assign m_axi_wr.awuser = AWUSER_EN ? s_axi_wr.awuser : '0;
|
||||
assign m_axi_wr.awvalid = s_axi_wr.awvalid;
|
||||
assign s_axi_wr.awready = m_axi_wr.awready;
|
||||
|
||||
end
|
||||
|
||||
// W channel
|
||||
|
||||
if (W_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axi_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axi_wstrb_reg = '0;
|
||||
logic m_axi_wlast_reg = 1'b0;
|
||||
logic [WUSER_W-1:0] m_axi_wuser_reg = '0;
|
||||
logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
|
||||
|
||||
logic [DATA_W-1:0] temp_m_axi_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] temp_m_axi_wstrb_reg = '0;
|
||||
logic temp_m_axi_wlast_reg = 1'b0;
|
||||
logic [WUSER_W-1:0] temp_m_axi_wuser_reg = '0;
|
||||
logic temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_w_input_to_output;
|
||||
logic store_axi_w_input_to_temp;
|
||||
logic store_axi_w_temp_to_output;
|
||||
|
||||
assign s_axi_wr.wready = s_axi_wready_reg;
|
||||
|
||||
assign m_axi_wr.wdata = m_axi_wdata_reg;
|
||||
assign m_axi_wr.wstrb = m_axi_wstrb_reg;
|
||||
assign m_axi_wr.wlast = m_axi_wlast_reg;
|
||||
assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0;
|
||||
assign m_axi_wr.wvalid = m_axi_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axi_wready_early = m_axi_wr.wready || (!temp_m_axi_wvalid_reg && (!m_axi_wvalid_reg || !s_axi_wr.wvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_wvalid_next = m_axi_wvalid_reg;
|
||||
temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
|
||||
|
||||
store_axi_w_input_to_output = 1'b0;
|
||||
store_axi_w_input_to_temp = 1'b0;
|
||||
store_axi_w_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axi_wready_reg) begin
|
||||
// input is ready
|
||||
if (m_axi_wr.wready || !m_axi_wvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axi_wvalid_next = s_axi_wr.wvalid;
|
||||
store_axi_w_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axi_wvalid_next = s_axi_wr.wvalid;
|
||||
store_axi_w_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axi_wr.wready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axi_wvalid_next = temp_m_axi_wvalid_reg;
|
||||
temp_m_axi_wvalid_next = 1'b0;
|
||||
store_axi_w_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_wready_reg <= s_axi_wready_early;
|
||||
m_axi_wvalid_reg <= m_axi_wvalid_next;
|
||||
temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_w_input_to_output) begin
|
||||
m_axi_wdata_reg <= s_axi_wr.wdata;
|
||||
m_axi_wstrb_reg <= s_axi_wr.wstrb;
|
||||
m_axi_wlast_reg <= s_axi_wr.wlast;
|
||||
m_axi_wuser_reg <= s_axi_wr.wuser;
|
||||
end else if (store_axi_w_temp_to_output) begin
|
||||
m_axi_wdata_reg <= temp_m_axi_wdata_reg;
|
||||
m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
|
||||
m_axi_wlast_reg <= temp_m_axi_wlast_reg;
|
||||
m_axi_wuser_reg <= temp_m_axi_wuser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_w_input_to_temp) begin
|
||||
temp_m_axi_wdata_reg <= s_axi_wr.wdata;
|
||||
temp_m_axi_wstrb_reg <= s_axi_wr.wstrb;
|
||||
temp_m_axi_wlast_reg <= s_axi_wr.wlast;
|
||||
temp_m_axi_wuser_reg <= s_axi_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_wready_reg <= 1'b0;
|
||||
m_axi_wvalid_reg <= 1'b0;
|
||||
temp_m_axi_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (W_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axi_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axi_wstrb_reg = '0;
|
||||
logic m_axi_wlast_reg = 1'b0;
|
||||
logic [WUSER_W-1:0] m_axi_wuser_reg = '0;
|
||||
logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_w_input_to_output;
|
||||
|
||||
assign s_axi_wr.wready = s_axi_wready_reg;
|
||||
|
||||
assign m_axi_wr.wdata = m_axi_wdata_reg;
|
||||
assign m_axi_wr.wstrb = m_axi_wstrb_reg;
|
||||
assign m_axi_wr.wlast = m_axi_wlast_reg;
|
||||
assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0;
|
||||
assign m_axi_wr.wvalid = m_axi_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axi_wready_ewly = !m_axi_wvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_wvalid_next = m_axi_wvalid_reg;
|
||||
|
||||
store_axi_w_input_to_output = 1'b0;
|
||||
|
||||
if (s_axi_wready_reg) begin
|
||||
m_axi_wvalid_next = s_axi_wr.wvalid;
|
||||
store_axi_w_input_to_output = 1'b1;
|
||||
end else if (m_axi_wr.wready) begin
|
||||
m_axi_wvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_wready_reg <= s_axi_wready_ewly;
|
||||
m_axi_wvalid_reg <= m_axi_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_w_input_to_output) begin
|
||||
m_axi_wdata_reg <= s_axi_wr.wdata;
|
||||
m_axi_wstrb_reg <= s_axi_wr.wstrb;
|
||||
m_axi_wlast_reg <= s_axi_wr.wlast;
|
||||
m_axi_wuser_reg <= s_axi_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_wready_reg <= 1'b0;
|
||||
m_axi_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass W channel
|
||||
assign m_axi_wr.wdata = s_axi_wr.wdata;
|
||||
assign m_axi_wr.wstrb = s_axi_wr.wstrb;
|
||||
assign m_axi_wr.wlast = s_axi_wr.wlast;
|
||||
assign m_axi_wr.wuser = WUSER_EN ? s_axi_wr.wuser : '0;
|
||||
assign m_axi_wr.wvalid = s_axi_wr.wvalid;
|
||||
assign s_axi_wr.wready = m_axi_wr.wready;
|
||||
|
||||
end
|
||||
|
||||
// B channel
|
||||
|
||||
if (B_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axi_bready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] s_axi_bid_reg = '0;
|
||||
logic [1:0] s_axi_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axi_buser_reg = '0;
|
||||
logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
|
||||
|
||||
logic [ID_W-1:0] temp_s_axi_bid_reg = '0;
|
||||
logic [1:0] temp_s_axi_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] temp_s_axi_buser_reg = '0;
|
||||
logic temp_s_axi_bvalid_reg = 1'b0, temp_s_axi_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_b_input_to_output;
|
||||
logic store_axi_b_input_to_temp;
|
||||
logic store_axi_b_temp_to_output;
|
||||
|
||||
assign m_axi_wr.bready = m_axi_bready_reg;
|
||||
|
||||
assign s_axi_wr.bid = s_axi_bid_reg;
|
||||
assign s_axi_wr.bresp = s_axi_bresp_reg;
|
||||
assign s_axi_wr.buser = BUSER_EN ? s_axi_buser_reg : '0;
|
||||
assign s_axi_wr.bvalid = s_axi_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire m_axi_bready_early = s_axi_wr.bready || (!temp_s_axi_bvalid_reg && (!s_axi_bvalid_reg || !m_axi_wr.bvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axi_bvalid_next = s_axi_bvalid_reg;
|
||||
temp_s_axi_bvalid_next = temp_s_axi_bvalid_reg;
|
||||
|
||||
store_axi_b_input_to_output = 1'b0;
|
||||
store_axi_b_input_to_temp = 1'b0;
|
||||
store_axi_b_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axi_bready_reg) begin
|
||||
// input is ready
|
||||
if (s_axi_wr.bready || !s_axi_bvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axi_bvalid_next = m_axi_wr.bvalid;
|
||||
store_axi_b_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axi_bvalid_next = m_axi_wr.bvalid;
|
||||
store_axi_b_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (s_axi_wr.bready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axi_bvalid_next = temp_s_axi_bvalid_reg;
|
||||
temp_s_axi_bvalid_next = 1'b0;
|
||||
store_axi_b_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axi_bready_reg <= m_axi_bready_early;
|
||||
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
||||
temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_b_input_to_output) begin
|
||||
s_axi_bid_reg <= m_axi_wr.bid;
|
||||
s_axi_bresp_reg <= m_axi_wr.bresp;
|
||||
s_axi_buser_reg <= m_axi_wr.buser;
|
||||
end else if (store_axi_b_temp_to_output) begin
|
||||
s_axi_bid_reg <= temp_s_axi_bid_reg;
|
||||
s_axi_bresp_reg <= temp_s_axi_bresp_reg;
|
||||
s_axi_buser_reg <= temp_s_axi_buser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_b_input_to_temp) begin
|
||||
temp_s_axi_bid_reg <= m_axi_wr.bid;
|
||||
temp_s_axi_bresp_reg <= m_axi_wr.bresp;
|
||||
temp_s_axi_buser_reg <= m_axi_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axi_bready_reg <= 1'b0;
|
||||
s_axi_bvalid_reg <= 1'b0;
|
||||
temp_s_axi_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (B_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axi_bready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] s_axi_bid_reg = '0;
|
||||
logic [1:0] s_axi_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axi_buser_reg = '0;
|
||||
logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_b_input_to_output;
|
||||
|
||||
assign m_axi_wr.bready = m_axi_bready_reg;
|
||||
|
||||
assign s_axi_wr.bid = s_axi_bid_reg;
|
||||
assign s_axi_wr.bresp = s_axi_bresp_reg;
|
||||
assign s_axi_wr.buser = BUSER_EN ? s_axi_buser_reg : '0;
|
||||
assign s_axi_wr.bvalid = s_axi_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axi_bready_early = !s_axi_bvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axi_bvalid_next = s_axi_bvalid_reg;
|
||||
|
||||
store_axi_b_input_to_output = 1'b0;
|
||||
|
||||
if (m_axi_bready_reg) begin
|
||||
s_axi_bvalid_next = m_axi_wr.bvalid;
|
||||
store_axi_b_input_to_output = 1'b1;
|
||||
end else if (s_axi_wr.bready) begin
|
||||
s_axi_bvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axi_bready_reg <= m_axi_bready_early;
|
||||
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_b_input_to_output) begin
|
||||
s_axi_bid_reg <= m_axi_wr.bid;
|
||||
s_axi_bresp_reg <= m_axi_wr.bresp;
|
||||
s_axi_buser_reg <= m_axi_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axi_bready_reg <= 1'b0;
|
||||
s_axi_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass B channel
|
||||
assign s_axi_wr.bid = m_axi_wr.bid;
|
||||
assign s_axi_wr.bresp = m_axi_wr.bresp;
|
||||
assign s_axi_wr.buser = BUSER_EN ? m_axi_wr.buser : '0;
|
||||
assign s_axi_wr.bvalid = m_axi_wr.bvalid;
|
||||
assign m_axi_wr.bready = s_axi_wr.bready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
284
src/axi/rtl/taxi_axil_dp_ram.sv
Normal file
284
src/axi/rtl/taxi_axil_dp_ram.sv
Normal file
@@ -0,0 +1,284 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Lite dual-port RAM
|
||||
*/
|
||||
module taxi_axil_dp_ram #
|
||||
(
|
||||
// Width of address bus in bits
|
||||
parameter ADDR_W = 16,
|
||||
// Extra pipeline register on output
|
||||
parameter logic PIPELINE_OUTPUT = 1'b0
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Port A
|
||||
*/
|
||||
input wire logic a_clk,
|
||||
input wire logic a_rst,
|
||||
taxi_axil_if.wr_slv s_axil_wr_a,
|
||||
taxi_axil_if.rd_slv s_axil_rd_a,
|
||||
|
||||
/*
|
||||
* Port B
|
||||
*/
|
||||
input wire logic b_clk,
|
||||
input wire logic b_rst,
|
||||
taxi_axil_if.wr_slv s_axil_wr_b,
|
||||
taxi_axil_if.rd_slv s_axil_rd_b
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axil_wr_a.DATA_W;
|
||||
localparam STRB_W = s_axil_wr_a.STRB_W;
|
||||
|
||||
localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
|
||||
localparam BYTE_LANES = STRB_W;
|
||||
localparam BYTE_W = DATA_W/BYTE_LANES;
|
||||
|
||||
// check configuration
|
||||
if (BYTE_W * STRB_W != DATA_W)
|
||||
$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
|
||||
|
||||
if (2**$clog2(BYTE_LANES) != BYTE_LANES)
|
||||
$fatal(0, "Error: AXI word width must be even power of two (instance %m)");
|
||||
|
||||
if (s_axil_wr_a.DATA_W != s_axil_rd_a.DATA_W || s_axil_wr_b.DATA_W != s_axil_rd_b.DATA_W || s_axil_wr_a.DATA_W != s_axil_wr_b.DATA_W)
|
||||
$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
|
||||
|
||||
if (s_axil_wr_a.ADDR_W < ADDR_W || s_axil_wr_a.ADDR_W < ADDR_W || s_axil_rd_b.ADDR_W < ADDR_W || s_axil_rd_b.ADDR_W < ADDR_W)
|
||||
$fatal(0, "Error: AXI address width is insufficient (instance %m)");
|
||||
|
||||
logic read_eligible_a;
|
||||
logic write_eligible_a;
|
||||
|
||||
logic read_eligible_b;
|
||||
logic write_eligible_b;
|
||||
|
||||
logic mem_wr_en_a;
|
||||
logic mem_rd_en_a;
|
||||
|
||||
logic mem_wr_en_b;
|
||||
logic mem_rd_en_b;
|
||||
|
||||
logic last_read_a_reg = 1'b0, last_read_a_next;
|
||||
logic last_read_b_reg = 1'b0, last_read_b_next;
|
||||
|
||||
logic s_axil_a_awready_reg = 1'b0, s_axil_a_awready_next;
|
||||
logic s_axil_a_wready_reg = 1'b0, s_axil_a_wready_next;
|
||||
logic s_axil_a_bvalid_reg = 1'b0, s_axil_a_bvalid_next;
|
||||
logic s_axil_a_arready_reg = 1'b0, s_axil_a_arready_next;
|
||||
logic [DATA_W-1:0] s_axil_a_rdata_reg = '0, s_axil_a_rdata_next;
|
||||
logic s_axil_a_rvalid_reg = 1'b0, s_axil_a_rvalid_next;
|
||||
logic [DATA_W-1:0] s_axil_a_rdata_pipe_reg = '0;
|
||||
logic s_axil_a_rvalid_pipe_reg = 1'b0;
|
||||
|
||||
logic s_axil_b_awready_reg = 1'b0, s_axil_b_awready_next;
|
||||
logic s_axil_b_wready_reg = 1'b0, s_axil_b_wready_next;
|
||||
logic s_axil_b_bvalid_reg = 1'b0, s_axil_b_bvalid_next;
|
||||
logic s_axil_b_arready_reg = 1'b0, s_axil_b_arready_next;
|
||||
logic [DATA_W-1:0] s_axil_b_rdata_reg = '0, s_axil_b_rdata_next;
|
||||
logic s_axil_b_rvalid_reg = 1'b0, s_axil_b_rvalid_next;
|
||||
logic [DATA_W-1:0] s_axil_b_rdata_pipe_reg = '0;
|
||||
logic s_axil_b_rvalid_pipe_reg = 1'b0;
|
||||
|
||||
// verilator lint_off MULTIDRIVEN
|
||||
// (* RAM_STYLE="BLOCK" *)
|
||||
logic [DATA_W-1:0] mem[2**VALID_ADDR_W];
|
||||
// verilator lint_on MULTIDRIVEN
|
||||
|
||||
wire [VALID_ADDR_W-1:0] s_axil_a_awaddr_valid = VALID_ADDR_W'(s_axil_wr_a.awaddr >> (ADDR_W - VALID_ADDR_W));
|
||||
wire [VALID_ADDR_W-1:0] s_axil_a_araddr_valid = VALID_ADDR_W'(s_axil_rd_a.araddr >> (ADDR_W - VALID_ADDR_W));
|
||||
|
||||
wire [VALID_ADDR_W-1:0] s_axil_b_awaddr_valid = VALID_ADDR_W'(s_axil_wr_b.awaddr >> (ADDR_W - VALID_ADDR_W));
|
||||
wire [VALID_ADDR_W-1:0] s_axil_b_araddr_valid = VALID_ADDR_W'(s_axil_rd_b.araddr >> (ADDR_W - VALID_ADDR_W));
|
||||
|
||||
assign s_axil_wr_a.awready = s_axil_a_awready_reg;
|
||||
assign s_axil_wr_a.wready = s_axil_a_wready_reg;
|
||||
assign s_axil_wr_a.bresp = 2'b00;
|
||||
assign s_axil_wr_a.bvalid = s_axil_a_bvalid_reg;
|
||||
|
||||
assign s_axil_rd_a.arready = s_axil_a_arready_reg;
|
||||
assign s_axil_rd_a.rdata = PIPELINE_OUTPUT ? s_axil_a_rdata_pipe_reg : s_axil_a_rdata_reg;
|
||||
assign s_axil_rd_a.rresp = 2'b00;
|
||||
assign s_axil_rd_a.rvalid = PIPELINE_OUTPUT ? s_axil_a_rvalid_pipe_reg : s_axil_a_rvalid_reg;
|
||||
|
||||
assign s_axil_wr_b.awready = s_axil_b_awready_reg;
|
||||
assign s_axil_wr_b.wready = s_axil_b_wready_reg;
|
||||
assign s_axil_wr_b.bresp = 2'b00;
|
||||
assign s_axil_wr_b.bvalid = s_axil_b_bvalid_reg;
|
||||
|
||||
assign s_axil_rd_b.arready = s_axil_b_arready_reg;
|
||||
assign s_axil_rd_b.rdata = PIPELINE_OUTPUT ? s_axil_b_rdata_pipe_reg : s_axil_b_rdata_reg;
|
||||
assign s_axil_rd_b.rresp = 2'b00;
|
||||
assign s_axil_rd_b.rvalid = PIPELINE_OUTPUT ? s_axil_b_rvalid_pipe_reg : s_axil_b_rvalid_reg;
|
||||
|
||||
initial begin
|
||||
// two nested loops for smaller number of iterations per loop
|
||||
// workaround for synthesizer complaints about large loop counts
|
||||
for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin
|
||||
for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin
|
||||
mem[j] = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
mem_wr_en_a = 1'b0;
|
||||
mem_rd_en_a = 1'b0;
|
||||
|
||||
last_read_a_next = last_read_a_reg;
|
||||
|
||||
s_axil_a_awready_next = 1'b0;
|
||||
s_axil_a_wready_next = 1'b0;
|
||||
s_axil_a_bvalid_next = s_axil_a_bvalid_reg && !s_axil_wr_a.bready;
|
||||
|
||||
s_axil_a_arready_next = 1'b0;
|
||||
s_axil_a_rvalid_next = s_axil_a_rvalid_reg && !(s_axil_rd_a.rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg));
|
||||
|
||||
write_eligible_a = s_axil_wr_a.awvalid && s_axil_wr_a.wvalid && (!s_axil_wr_a.bvalid || s_axil_wr_a.bready) && (!s_axil_wr_a.awready && !s_axil_wr_a.wready);
|
||||
read_eligible_a = s_axil_rd_a.arvalid && (!s_axil_rd_a.rvalid || s_axil_rd_a.rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg)) && (!s_axil_rd_a.arready);
|
||||
|
||||
if (write_eligible_a && (!read_eligible_a || last_read_a_reg)) begin
|
||||
last_read_a_next = 1'b0;
|
||||
|
||||
s_axil_a_awready_next = 1'b1;
|
||||
s_axil_a_wready_next = 1'b1;
|
||||
s_axil_a_bvalid_next = 1'b1;
|
||||
|
||||
mem_wr_en_a = 1'b1;
|
||||
end else if (read_eligible_a) begin
|
||||
last_read_a_next = 1'b1;
|
||||
|
||||
s_axil_a_arready_next = 1'b1;
|
||||
s_axil_a_rvalid_next = 1'b1;
|
||||
|
||||
mem_rd_en_a = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge a_clk) begin
|
||||
last_read_a_reg <= last_read_a_next;
|
||||
|
||||
s_axil_a_awready_reg <= s_axil_a_awready_next;
|
||||
s_axil_a_wready_reg <= s_axil_a_wready_next;
|
||||
s_axil_a_bvalid_reg <= s_axil_a_bvalid_next;
|
||||
|
||||
s_axil_a_arready_reg <= s_axil_a_arready_next;
|
||||
s_axil_a_rvalid_reg <= s_axil_a_rvalid_next;
|
||||
|
||||
if (mem_rd_en_a) begin
|
||||
s_axil_a_rdata_reg <= mem[s_axil_a_araddr_valid];
|
||||
end else begin
|
||||
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
|
||||
if (mem_wr_en_a && s_axil_wr_a.wstrb[i]) begin
|
||||
mem[s_axil_a_awaddr_valid][BYTE_W*i +: BYTE_W] <= s_axil_wr_a.wdata[BYTE_W*i +: BYTE_W];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if (!s_axil_a_rvalid_pipe_reg || s_axil_rd_a.rready) begin
|
||||
s_axil_a_rdata_pipe_reg <= s_axil_a_rdata_reg;
|
||||
s_axil_a_rvalid_pipe_reg <= s_axil_a_rvalid_reg;
|
||||
end
|
||||
|
||||
if (a_rst) begin
|
||||
last_read_a_reg <= 1'b0;
|
||||
|
||||
s_axil_a_awready_reg <= 1'b0;
|
||||
s_axil_a_wready_reg <= 1'b0;
|
||||
s_axil_a_bvalid_reg <= 1'b0;
|
||||
|
||||
s_axil_a_arready_reg <= 1'b0;
|
||||
s_axil_a_rvalid_reg <= 1'b0;
|
||||
s_axil_a_rvalid_pipe_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
mem_wr_en_b = 1'b0;
|
||||
mem_rd_en_b = 1'b0;
|
||||
|
||||
last_read_b_next = last_read_b_reg;
|
||||
|
||||
s_axil_b_awready_next = 1'b0;
|
||||
s_axil_b_wready_next = 1'b0;
|
||||
s_axil_b_bvalid_next = s_axil_b_bvalid_reg && !s_axil_wr_b.bready;
|
||||
|
||||
s_axil_b_arready_next = 1'b0;
|
||||
s_axil_b_rvalid_next = s_axil_b_rvalid_reg && !(s_axil_rd_b.rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg));
|
||||
|
||||
write_eligible_b = s_axil_wr_b.awvalid && s_axil_wr_b.wvalid && (!s_axil_wr_b.bvalid || s_axil_wr_b.bready) && (!s_axil_wr_b.awready && !s_axil_wr_b.wready);
|
||||
read_eligible_b = s_axil_rd_b.arvalid && (!s_axil_rd_b.rvalid || s_axil_rd_b.rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg)) && (!s_axil_rd_b.arready);
|
||||
|
||||
if (write_eligible_b && (!read_eligible_b || last_read_b_reg)) begin
|
||||
last_read_b_next = 1'b0;
|
||||
|
||||
s_axil_b_awready_next = 1'b1;
|
||||
s_axil_b_wready_next = 1'b1;
|
||||
s_axil_b_bvalid_next = 1'b1;
|
||||
|
||||
mem_wr_en_b = 1'b1;
|
||||
end else if (read_eligible_b) begin
|
||||
last_read_b_next = 1'b1;
|
||||
|
||||
s_axil_b_arready_next = 1'b1;
|
||||
s_axil_b_rvalid_next = 1'b1;
|
||||
|
||||
mem_rd_en_b = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge b_clk) begin
|
||||
last_read_b_reg <= last_read_b_next;
|
||||
|
||||
s_axil_b_awready_reg <= s_axil_b_awready_next;
|
||||
s_axil_b_wready_reg <= s_axil_b_wready_next;
|
||||
s_axil_b_bvalid_reg <= s_axil_b_bvalid_next;
|
||||
|
||||
s_axil_b_arready_reg <= s_axil_b_arready_next;
|
||||
s_axil_b_rvalid_reg <= s_axil_b_rvalid_next;
|
||||
|
||||
if (mem_rd_en_b) begin
|
||||
s_axil_b_rdata_reg <= mem[s_axil_b_araddr_valid];
|
||||
end else begin
|
||||
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
|
||||
if (mem_wr_en_b && s_axil_wr_b.wstrb[i]) begin
|
||||
mem[s_axil_b_awaddr_valid][BYTE_W*i +: BYTE_W] <= s_axil_wr_b.wdata[BYTE_W*i +: BYTE_W];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if (!s_axil_b_rvalid_pipe_reg || s_axil_rd_b.rready) begin
|
||||
s_axil_b_rdata_pipe_reg <= s_axil_b_rdata_reg;
|
||||
s_axil_b_rvalid_pipe_reg <= s_axil_b_rvalid_reg;
|
||||
end
|
||||
|
||||
if (b_rst) begin
|
||||
last_read_b_reg <= 1'b0;
|
||||
|
||||
s_axil_b_awready_reg <= 1'b0;
|
||||
s_axil_b_wready_reg <= 1'b0;
|
||||
s_axil_b_bvalid_reg <= 1'b0;
|
||||
|
||||
s_axil_b_arready_reg <= 1'b0;
|
||||
s_axil_b_rvalid_reg <= 1'b0;
|
||||
s_axil_b_rvalid_pipe_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
175
src/axi/rtl/taxi_axil_if.sv
Normal file
175
src/axi/rtl/taxi_axil_if.sv
Normal file
@@ -0,0 +1,175 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
interface taxi_axil_if #(
|
||||
// Width of data bus in bits
|
||||
parameter DATA_W = 32,
|
||||
// Width of address bus in bits
|
||||
parameter ADDR_W = 32,
|
||||
// Width of wstrb (width of data bus in words)
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
// Use awuser signal
|
||||
parameter logic AWUSER_EN = 1'b0,
|
||||
// Width of awuser signal
|
||||
parameter AWUSER_W = 1,
|
||||
// Use wuser signal
|
||||
parameter logic WUSER_EN = 1'b0,
|
||||
// Width of wuser signal
|
||||
parameter WUSER_W = 1,
|
||||
// Use buser signal
|
||||
parameter logic BUSER_EN = 1'b0,
|
||||
// Width of buser signal
|
||||
parameter BUSER_W = 1,
|
||||
// Use aruser signal
|
||||
parameter logic ARUSER_EN = 1'b0,
|
||||
// Width of aruser signal
|
||||
parameter ARUSER_W = 1,
|
||||
// Use ruser signal
|
||||
parameter logic RUSER_EN = 1'b0,
|
||||
// Width of ruser signal
|
||||
parameter RUSER_W = 1
|
||||
)
|
||||
();
|
||||
// AW
|
||||
logic [ADDR_W-1:0] awaddr;
|
||||
logic [2:0] awprot;
|
||||
logic [AWUSER_W-1:0] awuser;
|
||||
logic awvalid;
|
||||
logic awready;
|
||||
// W
|
||||
logic [DATA_W-1:0] wdata;
|
||||
logic [STRB_W-1:0] wstrb;
|
||||
logic [WUSER_W-1:0] wuser;
|
||||
logic wvalid;
|
||||
logic wready;
|
||||
// B
|
||||
logic [1:0] bresp;
|
||||
logic [BUSER_W-1:0] buser;
|
||||
logic bvalid;
|
||||
logic bready;
|
||||
// AR
|
||||
logic [ADDR_W-1:0] araddr;
|
||||
logic [2:0] arprot;
|
||||
logic [ARUSER_W-1:0] aruser;
|
||||
logic arvalid;
|
||||
logic arready;
|
||||
// R
|
||||
logic [DATA_W-1:0] rdata;
|
||||
logic [1:0] rresp;
|
||||
logic [RUSER_W-1:0] ruser;
|
||||
logic rvalid;
|
||||
logic rready;
|
||||
|
||||
modport wr_mst (
|
||||
// AW
|
||||
output awaddr,
|
||||
output awprot,
|
||||
output awuser,
|
||||
output awvalid,
|
||||
input awready,
|
||||
// W
|
||||
output wdata,
|
||||
output wstrb,
|
||||
output wuser,
|
||||
output wvalid,
|
||||
input wready,
|
||||
// B
|
||||
input bresp,
|
||||
input buser,
|
||||
input bvalid,
|
||||
output bready
|
||||
);
|
||||
|
||||
modport rd_mst (
|
||||
// AR
|
||||
output araddr,
|
||||
output arprot,
|
||||
output aruser,
|
||||
output arvalid,
|
||||
input arready,
|
||||
// R
|
||||
input rdata,
|
||||
input rresp,
|
||||
input ruser,
|
||||
input rvalid,
|
||||
output rready
|
||||
);
|
||||
|
||||
modport wr_slv (
|
||||
// AW
|
||||
input awaddr,
|
||||
input awprot,
|
||||
input awuser,
|
||||
input awvalid,
|
||||
output awready,
|
||||
// W
|
||||
input wdata,
|
||||
input wstrb,
|
||||
input wuser,
|
||||
input wvalid,
|
||||
output wready,
|
||||
// B
|
||||
output bresp,
|
||||
output buser,
|
||||
output bvalid,
|
||||
input bready
|
||||
);
|
||||
|
||||
modport rd_slv (
|
||||
// AR
|
||||
input araddr,
|
||||
input arprot,
|
||||
input aruser,
|
||||
input arvalid,
|
||||
output arready,
|
||||
// R
|
||||
output rdata,
|
||||
output rresp,
|
||||
output ruser,
|
||||
output rvalid,
|
||||
input rready
|
||||
);
|
||||
|
||||
modport wr_mon (
|
||||
// AW
|
||||
input awaddr,
|
||||
input awprot,
|
||||
input awuser,
|
||||
input awvalid,
|
||||
input awready,
|
||||
// W
|
||||
input wdata,
|
||||
input wstrb,
|
||||
input wuser,
|
||||
input wvalid,
|
||||
input wready,
|
||||
// B
|
||||
input bresp,
|
||||
input buser,
|
||||
input bvalid,
|
||||
input bready
|
||||
);
|
||||
|
||||
modport rd_mon (
|
||||
// AR
|
||||
input araddr,
|
||||
input arprot,
|
||||
input aruser,
|
||||
input arvalid,
|
||||
input arready,
|
||||
// R
|
||||
input rdata,
|
||||
input rresp,
|
||||
input ruser,
|
||||
input rvalid,
|
||||
input rready
|
||||
);
|
||||
|
||||
endinterface
|
||||
165
src/axi/rtl/taxi_axil_ram.sv
Normal file
165
src/axi/rtl/taxi_axil_ram.sv
Normal file
@@ -0,0 +1,165 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Lite RAM
|
||||
*/
|
||||
module taxi_axil_ram #
|
||||
(
|
||||
// Width of address bus in bits
|
||||
parameter ADDR_W = 16,
|
||||
// Extra pipeline register on output
|
||||
parameter logic PIPELINE_OUTPUT = 1'b0
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
taxi_axil_if.wr_slv s_axil_wr,
|
||||
taxi_axil_if.rd_slv s_axil_rd
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axil_wr.DATA_W;
|
||||
localparam STRB_W = s_axil_wr.STRB_W;
|
||||
|
||||
localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
|
||||
localparam BYTE_LANES = STRB_W;
|
||||
localparam BYTE_W = DATA_W/BYTE_LANES;
|
||||
|
||||
// check configuration
|
||||
if (BYTE_W * STRB_W != DATA_W)
|
||||
$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
|
||||
|
||||
if (2**$clog2(BYTE_LANES) != BYTE_LANES)
|
||||
$fatal(0, "Error: AXI byte lane count must be even power of two (instance %m)");
|
||||
|
||||
if (s_axil_wr.DATA_W != s_axil_rd.DATA_W)
|
||||
$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
|
||||
|
||||
if (s_axil_wr.ADDR_W < ADDR_W || s_axil_rd.ADDR_W < ADDR_W)
|
||||
$fatal(0, "Error: AXI address width is insufficient (instance %m)");
|
||||
|
||||
logic mem_wr_en;
|
||||
logic mem_rd_en;
|
||||
|
||||
logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
|
||||
logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
|
||||
logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
logic s_axil_arready_reg = 1'b0, s_axil_arready_next;
|
||||
logic [DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next;
|
||||
logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
|
||||
logic [DATA_W-1:0] s_axil_rdata_pipe_reg = '0;
|
||||
logic s_axil_rvalid_pipe_reg = 1'b0;
|
||||
|
||||
// (* RAM_STYLE="BLOCK" *)
|
||||
logic [DATA_W-1:0] mem[2**VALID_ADDR_W];
|
||||
|
||||
wire [VALID_ADDR_W-1:0] s_axil_awaddr_valid = VALID_ADDR_W'(s_axil_wr.awaddr >> (ADDR_W - VALID_ADDR_W));
|
||||
wire [VALID_ADDR_W-1:0] s_axil_araddr_valid = VALID_ADDR_W'(s_axil_rd.araddr >> (ADDR_W - VALID_ADDR_W));
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
assign s_axil_wr.bresp = 2'b00;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
assign s_axil_rd.arready = s_axil_arready_reg;
|
||||
assign s_axil_rd.rdata = PIPELINE_OUTPUT ? s_axil_rdata_pipe_reg : s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = 2'b00;
|
||||
assign s_axil_rd.rvalid = PIPELINE_OUTPUT ? s_axil_rvalid_pipe_reg : s_axil_rvalid_reg;
|
||||
|
||||
initial begin
|
||||
// two nested loops for smaller number of iterations per loop
|
||||
// workaround for synthesizer complaints about large loop counts
|
||||
for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin
|
||||
for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin
|
||||
mem[j] = '0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
mem_wr_en = 1'b0;
|
||||
|
||||
s_axil_awready_next = 1'b0;
|
||||
s_axil_wready_next = 1'b0;
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
|
||||
|
||||
if (s_axil_wr.awvalid && s_axil_wr.wvalid && (!s_axil_wr.bvalid || s_axil_wr.bready) && (!s_axil_wr.awready && !s_axil_wr.wready)) begin
|
||||
s_axil_awready_next = 1'b1;
|
||||
s_axil_wready_next = 1'b1;
|
||||
s_axil_bvalid_next = 1'b1;
|
||||
|
||||
mem_wr_en = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_awready_reg <= s_axil_awready_next;
|
||||
s_axil_wready_reg <= s_axil_wready_next;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
|
||||
if (mem_wr_en && s_axil_wr.wstrb[i]) begin
|
||||
mem[s_axil_awaddr_valid][BYTE_W*i +: BYTE_W] <= s_axil_wr.wdata[BYTE_W*i +: BYTE_W];
|
||||
end
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
mem_rd_en = 1'b0;
|
||||
|
||||
s_axil_arready_next = 1'b0;
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg && !(s_axil_rd.rready || (PIPELINE_OUTPUT && !s_axil_rvalid_pipe_reg));
|
||||
|
||||
if (s_axil_rd.arvalid && (!s_axil_rd.rvalid || s_axil_rd.rready || (PIPELINE_OUTPUT && !s_axil_rvalid_pipe_reg)) && (!s_axil_rd.arready)) begin
|
||||
s_axil_arready_next = 1'b1;
|
||||
s_axil_rvalid_next = 1'b1;
|
||||
|
||||
mem_rd_en = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_arready_reg <= s_axil_arready_next;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
if (mem_rd_en) begin
|
||||
s_axil_rdata_reg <= mem[s_axil_araddr_valid];
|
||||
end
|
||||
|
||||
if (!s_axil_rvalid_pipe_reg || s_axil_rd.rready) begin
|
||||
s_axil_rdata_pipe_reg <= s_axil_rdata_reg;
|
||||
s_axil_rvalid_pipe_reg <= s_axil_rvalid_reg;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
s_axil_rvalid_pipe_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
4
src/axi/rtl/taxi_axil_register.f
Normal file
4
src/axi/rtl/taxi_axil_register.f
Normal file
@@ -0,0 +1,4 @@
|
||||
taxi_axil_register.sv
|
||||
taxi_axil_register_wr.sv
|
||||
taxi_axil_register_rd.sv
|
||||
taxi_axil_if.sv
|
||||
94
src/axi/rtl/taxi_axil_register.sv
Normal file
94
src/axi/rtl/taxi_axil_register.sv
Normal file
@@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite register
|
||||
*/
|
||||
module taxi_axil_register #
|
||||
(
|
||||
// AW channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter AW_REG_TYPE = 1,
|
||||
// W channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter W_REG_TYPE = 1,
|
||||
// B channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter B_REG_TYPE = 1,
|
||||
// AR channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter AR_REG_TYPE = 1,
|
||||
// R channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter R_REG_TYPE = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
taxi_axil_if.wr_slv s_axil_wr,
|
||||
taxi_axil_if.rd_slv s_axil_rd,
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
taxi_axil_if.wr_mst m_axil_wr,
|
||||
taxi_axil_if.rd_mst m_axil_rd
|
||||
);
|
||||
|
||||
taxi_axil_register_wr #(
|
||||
.AW_REG_TYPE(AW_REG_TYPE),
|
||||
.W_REG_TYPE(W_REG_TYPE),
|
||||
.B_REG_TYPE(B_REG_TYPE)
|
||||
)
|
||||
axil_register_wr_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axil_wr(s_axil_wr),
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
.m_axil_wr(m_axil_wr)
|
||||
);
|
||||
|
||||
taxi_axil_register_rd #(
|
||||
.AR_REG_TYPE(AR_REG_TYPE),
|
||||
.R_REG_TYPE(R_REG_TYPE)
|
||||
)
|
||||
axil_register_rd_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axil_rd(s_axil_rd),
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
.m_axil_rd(m_axil_rd)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
371
src/axi/rtl/taxi_axil_register_rd.sv
Normal file
371
src/axi/rtl/taxi_axil_register_rd.sv
Normal file
@@ -0,0 +1,371 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite register (read)
|
||||
*/
|
||||
module taxi_axil_register_rd #
|
||||
(
|
||||
// AR channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter AR_REG_TYPE = 1,
|
||||
// R channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter R_REG_TYPE = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
taxi_axil_if.rd_slv s_axil_rd,
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
taxi_axil_if.rd_mst m_axil_rd
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axil_rd.DATA_W;
|
||||
localparam ADDR_W = s_axil_rd.ADDR_W;
|
||||
localparam STRB_W = s_axil_rd.STRB_W;
|
||||
localparam logic ARUSER_EN = s_axil_rd.ARUSER_EN && m_axil_rd.ARUSER_EN;
|
||||
localparam ARUSER_W = s_axil_rd.ARUSER_W;
|
||||
localparam logic RUSER_EN = s_axil_rd.RUSER_EN && m_axil_rd.RUSER_EN;
|
||||
localparam RUSER_W = s_axil_rd.RUSER_W;
|
||||
|
||||
if (m_axil_rd.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (m_axil_rd.STRB_W != STRB_W)
|
||||
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
|
||||
|
||||
// AR channel
|
||||
|
||||
if (AR_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_arready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_araddr_reg = '0;
|
||||
logic [2:0] m_axil_arprot_reg = '0;
|
||||
logic [ARUSER_W-1:0] m_axil_aruser_reg = '0;
|
||||
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
|
||||
|
||||
logic [ADDR_W-1:0] temp_m_axil_araddr_reg = '0;
|
||||
logic [2:0] temp_m_axil_arprot_reg = '0;
|
||||
logic [ARUSER_W-1:0] temp_m_axil_aruser_reg = '0;
|
||||
logic temp_m_axil_arvalid_reg = 1'b0, temp_m_axil_arvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_ar_input_to_output;
|
||||
logic store_axil_ar_input_to_temp;
|
||||
logic store_axil_ar_temp_to_output;
|
||||
|
||||
assign s_axil_rd.arready = s_axil_arready_reg;
|
||||
|
||||
assign m_axil_rd.araddr = m_axil_araddr_reg;
|
||||
assign m_axil_rd.arprot = m_axil_arprot_reg;
|
||||
assign m_axil_rd.aruser = ARUSER_EN ? m_axil_aruser_reg : '0;
|
||||
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axil_arready_early = m_axil_rd.arready || (!temp_m_axil_arvalid_reg && (!m_axil_arvalid_reg || !s_axil_rd.arvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_arvalid_next = m_axil_arvalid_reg;
|
||||
temp_m_axil_arvalid_next = temp_m_axil_arvalid_reg;
|
||||
|
||||
store_axil_ar_input_to_output = 1'b0;
|
||||
store_axil_ar_input_to_temp = 1'b0;
|
||||
store_axil_ar_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axil_arready_reg) begin
|
||||
// input is ready
|
||||
if (m_axil_rd.arready || !m_axil_arvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axil_arvalid_next = s_axil_rd.arvalid;
|
||||
store_axil_ar_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axil_arvalid_next = s_axil_rd.arvalid;
|
||||
store_axil_ar_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axil_rd.arready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axil_arvalid_next = temp_m_axil_arvalid_reg;
|
||||
temp_m_axil_arvalid_next = 1'b0;
|
||||
store_axil_ar_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_arready_reg <= s_axil_arready_early;
|
||||
m_axil_arvalid_reg <= m_axil_arvalid_next;
|
||||
temp_m_axil_arvalid_reg <= temp_m_axil_arvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_ar_input_to_output) begin
|
||||
m_axil_araddr_reg <= s_axil_rd.araddr;
|
||||
m_axil_arprot_reg <= s_axil_rd.arprot;
|
||||
m_axil_aruser_reg <= s_axil_rd.aruser;
|
||||
end else if (store_axil_ar_temp_to_output) begin
|
||||
m_axil_araddr_reg <= temp_m_axil_araddr_reg;
|
||||
m_axil_arprot_reg <= temp_m_axil_arprot_reg;
|
||||
m_axil_aruser_reg <= temp_m_axil_aruser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_ar_input_to_temp) begin
|
||||
temp_m_axil_araddr_reg <= s_axil_rd.araddr;
|
||||
temp_m_axil_arprot_reg <= s_axil_rd.arprot;
|
||||
temp_m_axil_aruser_reg <= s_axil_rd.aruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
m_axil_arvalid_reg <= 1'b0;
|
||||
temp_m_axil_arvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (AR_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_arready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_araddr_reg = '0;
|
||||
logic [2:0] m_axil_arprot_reg = '0;
|
||||
logic [ARUSER_W-1:0] m_axil_aruser_reg = '0;
|
||||
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_ar_input_to_output;
|
||||
|
||||
assign s_axil_rd.arready = s_axil_arready_reg;
|
||||
|
||||
assign m_axil_rd.araddr = m_axil_araddr_reg;
|
||||
assign m_axil_rd.arprot = m_axil_arprot_reg;
|
||||
assign m_axil_rd.aruser = ARUSER_EN ? m_axil_aruser_reg : '0;
|
||||
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axil_arready_early = !m_axil_arvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_arvalid_next = m_axil_arvalid_reg;
|
||||
|
||||
store_axil_ar_input_to_output = 1'b0;
|
||||
|
||||
if (s_axil_arready_reg) begin
|
||||
m_axil_arvalid_next = s_axil_rd.arvalid;
|
||||
store_axil_ar_input_to_output = 1'b1;
|
||||
end else if (m_axil_rd.arready) begin
|
||||
m_axil_arvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_arready_reg <= s_axil_arready_early;
|
||||
m_axil_arvalid_reg <= m_axil_arvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_ar_input_to_output) begin
|
||||
m_axil_araddr_reg <= s_axil_rd.araddr;
|
||||
m_axil_arprot_reg <= s_axil_rd.arprot;
|
||||
m_axil_aruser_reg <= s_axil_rd.aruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
m_axil_arvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass AR channel
|
||||
assign m_axil_rd.araddr = s_axil_rd.araddr;
|
||||
assign m_axil_rd.arprot = s_axil_rd.arprot;
|
||||
assign m_axil_rd.aruser = ARUSER_EN ? s_axil_rd.aruser : '0;
|
||||
assign m_axil_rd.arvalid = s_axil_rd.arvalid;
|
||||
assign s_axil_rd.arready = m_axil_rd.arready;
|
||||
|
||||
end
|
||||
|
||||
// R channel
|
||||
|
||||
if (R_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_rready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] s_axil_rdata_reg = '0;
|
||||
logic [1:0] s_axil_rresp_reg = 2'b0;
|
||||
logic [RUSER_W-1:0] s_axil_ruser_reg = '0;
|
||||
logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
|
||||
|
||||
logic [DATA_W-1:0] temp_s_axil_rdata_reg = '0;
|
||||
logic [1:0] temp_s_axil_rresp_reg = 2'b0;
|
||||
logic [RUSER_W-1:0] temp_s_axil_ruser_reg = '0;
|
||||
logic temp_s_axil_rvalid_reg = 1'b0, temp_s_axil_rvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_r_input_to_output;
|
||||
logic store_axil_r_input_to_temp;
|
||||
logic store_axil_r_temp_to_output;
|
||||
|
||||
assign m_axil_rd.rready = m_axil_rready_reg;
|
||||
|
||||
assign s_axil_rd.rdata = s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = s_axil_rresp_reg;
|
||||
assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
|
||||
assign s_axil_rd.rvalid = s_axil_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire m_axil_rready_early = s_axil_rd.rready || (!temp_s_axil_rvalid_reg && (!s_axil_rvalid_reg || !m_axil_rd.rvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg;
|
||||
temp_s_axil_rvalid_next = temp_s_axil_rvalid_reg;
|
||||
|
||||
store_axil_r_input_to_output = 1'b0;
|
||||
store_axil_r_input_to_temp = 1'b0;
|
||||
store_axil_r_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axil_rready_reg) begin
|
||||
// input is ready
|
||||
if (s_axil_rd.rready || !s_axil_rvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axil_rvalid_next = m_axil_rd.rvalid;
|
||||
store_axil_r_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axil_rvalid_next = m_axil_rd.rvalid;
|
||||
store_axil_r_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (s_axil_rd.rready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axil_rvalid_next = temp_s_axil_rvalid_reg;
|
||||
temp_s_axil_rvalid_next = 1'b0;
|
||||
store_axil_r_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_rready_reg <= m_axil_rready_early;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
temp_s_axil_rvalid_reg <= temp_s_axil_rvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_r_input_to_output) begin
|
||||
s_axil_rdata_reg <= m_axil_rd.rdata;
|
||||
s_axil_rresp_reg <= m_axil_rd.rresp;
|
||||
s_axil_ruser_reg <= m_axil_rd.ruser;
|
||||
end else if (store_axil_r_temp_to_output) begin
|
||||
s_axil_rdata_reg <= temp_s_axil_rdata_reg;
|
||||
s_axil_rresp_reg <= temp_s_axil_rresp_reg;
|
||||
s_axil_ruser_reg <= temp_s_axil_ruser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_r_input_to_temp) begin
|
||||
temp_s_axil_rdata_reg <= m_axil_rd.rdata;
|
||||
temp_s_axil_rresp_reg <= m_axil_rd.rresp;
|
||||
temp_s_axil_ruser_reg <= m_axil_rd.ruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_rready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
temp_s_axil_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (R_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_rready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] s_axil_rdata_reg = '0;
|
||||
logic [1:0] s_axil_rresp_reg = 2'b0;
|
||||
logic [RUSER_W-1:0] s_axil_ruser_reg = '0;
|
||||
logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_r_input_to_output;
|
||||
|
||||
assign m_axil_rd.rready = m_axil_rready_reg;
|
||||
|
||||
assign s_axil_rd.rdata = s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = s_axil_rresp_reg;
|
||||
assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
|
||||
assign s_axil_rd.rvalid = s_axil_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axil_rready_early = !s_axil_rvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg;
|
||||
|
||||
store_axil_r_input_to_output = 1'b0;
|
||||
|
||||
if (m_axil_rready_reg) begin
|
||||
s_axil_rvalid_next = m_axil_rd.rvalid;
|
||||
store_axil_r_input_to_output = 1'b1;
|
||||
end else if (s_axil_rd.rready) begin
|
||||
s_axil_rvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_rready_reg <= m_axil_rready_early;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_r_input_to_output) begin
|
||||
s_axil_rdata_reg <= m_axil_rd.rdata;
|
||||
s_axil_rresp_reg <= m_axil_rd.rresp;
|
||||
s_axil_ruser_reg <= m_axil_rd.ruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_rready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass R channel
|
||||
assign s_axil_rd.rdata = m_axil_rd.rdata;
|
||||
assign s_axil_rd.rresp = m_axil_rd.rresp;
|
||||
assign s_axil_rd.ruser = RUSER_EN ? m_axil_rd.ruser : '0;
|
||||
assign s_axil_rd.rvalid = m_axil_rd.rvalid;
|
||||
assign m_axil_rd.rready = s_axil_rd.rready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
522
src/axi/rtl/taxi_axil_register_wr.sv
Normal file
522
src/axi/rtl/taxi_axil_register_wr.sv
Normal file
@@ -0,0 +1,522 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite register (write)
|
||||
*/
|
||||
module taxi_axil_register_wr #
|
||||
(
|
||||
// AW channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter AW_REG_TYPE = 1,
|
||||
// W channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter W_REG_TYPE = 1,
|
||||
// B channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter B_REG_TYPE = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
taxi_axil_if.wr_slv s_axil_wr,
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
taxi_axil_if.wr_mst m_axil_wr
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axil_wr.DATA_W;
|
||||
localparam ADDR_W = s_axil_wr.ADDR_W;
|
||||
localparam STRB_W = s_axil_wr.STRB_W;
|
||||
localparam logic AWUSER_EN = s_axil_wr.AWUSER_EN && m_axil_wr.AWUSER_EN;
|
||||
localparam AWUSER_W = s_axil_wr.AWUSER_W;
|
||||
localparam logic WUSER_EN = s_axil_wr.WUSER_EN && m_axil_wr.WUSER_EN;
|
||||
localparam WUSER_W = s_axil_wr.WUSER_W;
|
||||
localparam logic BUSER_EN = s_axil_wr.BUSER_EN && m_axil_wr.BUSER_EN;
|
||||
localparam BUSER_W = s_axil_wr.BUSER_W;
|
||||
|
||||
if (m_axil_wr.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (m_axil_wr.STRB_W != STRB_W)
|
||||
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
|
||||
|
||||
// AW channel
|
||||
|
||||
if (AW_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_awready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_awaddr_reg = '0;
|
||||
logic [2:0] m_axil_awprot_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axil_awuser_reg = '0;
|
||||
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
|
||||
|
||||
logic [ADDR_W-1:0] temp_m_axil_awaddr_reg = '0;
|
||||
logic [2:0] temp_m_axil_awprot_reg = '0;
|
||||
logic [AWUSER_W-1:0] temp_m_axil_awuser_reg = '0;
|
||||
logic temp_m_axil_awvalid_reg = 1'b0, temp_m_axil_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_aw_input_to_output;
|
||||
logic store_axil_aw_input_to_temp;
|
||||
logic store_axil_aw_temp_to_output;
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
|
||||
assign m_axil_wr.awaddr = m_axil_awaddr_reg;
|
||||
assign m_axil_wr.awprot = m_axil_awprot_reg;
|
||||
assign m_axil_wr.awuser = AWUSER_EN ? m_axil_awuser_reg : '0;
|
||||
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axil_awready_early = m_axil_wr.awready || (!temp_m_axil_awvalid_reg && (!m_axil_awvalid_reg || !s_axil_wr.awvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_awvalid_next = m_axil_awvalid_reg;
|
||||
temp_m_axil_awvalid_next = temp_m_axil_awvalid_reg;
|
||||
|
||||
store_axil_aw_input_to_output = 1'b0;
|
||||
store_axil_aw_input_to_temp = 1'b0;
|
||||
store_axil_aw_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axil_awready_reg) begin
|
||||
// input is ready
|
||||
if (m_axil_wr.awready || !m_axil_awvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axil_awvalid_next = s_axil_wr.awvalid;
|
||||
store_axil_aw_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axil_awvalid_next = s_axil_wr.awvalid;
|
||||
store_axil_aw_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axil_wr.awready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axil_awvalid_next = temp_m_axil_awvalid_reg;
|
||||
temp_m_axil_awvalid_next = 1'b0;
|
||||
store_axil_aw_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_awready_reg <= s_axil_awready_early;
|
||||
m_axil_awvalid_reg <= m_axil_awvalid_next;
|
||||
temp_m_axil_awvalid_reg <= temp_m_axil_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_aw_input_to_output) begin
|
||||
m_axil_awaddr_reg <= s_axil_wr.awaddr;
|
||||
m_axil_awprot_reg <= s_axil_wr.awprot;
|
||||
m_axil_awuser_reg <= s_axil_wr.awuser;
|
||||
end else if (store_axil_aw_temp_to_output) begin
|
||||
m_axil_awaddr_reg <= temp_m_axil_awaddr_reg;
|
||||
m_axil_awprot_reg <= temp_m_axil_awprot_reg;
|
||||
m_axil_awuser_reg <= temp_m_axil_awuser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_aw_input_to_temp) begin
|
||||
temp_m_axil_awaddr_reg <= s_axil_wr.awaddr;
|
||||
temp_m_axil_awprot_reg <= s_axil_wr.awprot;
|
||||
temp_m_axil_awuser_reg <= s_axil_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
m_axil_awvalid_reg <= 1'b0;
|
||||
temp_m_axil_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (AW_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_awready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_awaddr_reg = '0;
|
||||
logic [2:0] m_axil_awprot_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axil_awuser_reg = '0;
|
||||
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_aw_input_to_output;
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
|
||||
assign m_axil_wr.awaddr = m_axil_awaddr_reg;
|
||||
assign m_axil_wr.awprot = m_axil_awprot_reg;
|
||||
assign m_axil_wr.awuser = AWUSER_EN ? m_axil_awuser_reg : '0;
|
||||
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axil_awready_early = !m_axil_awvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_awvalid_next = m_axil_awvalid_reg;
|
||||
|
||||
store_axil_aw_input_to_output = 1'b0;
|
||||
|
||||
if (s_axil_awready_reg) begin
|
||||
m_axil_awvalid_next = s_axil_wr.awvalid;
|
||||
store_axil_aw_input_to_output = 1'b1;
|
||||
end else if (m_axil_wr.awready) begin
|
||||
m_axil_awvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_awready_reg <= s_axil_awready_early;
|
||||
m_axil_awvalid_reg <= m_axil_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_aw_input_to_output) begin
|
||||
m_axil_awaddr_reg <= s_axil_wr.awaddr;
|
||||
m_axil_awprot_reg <= s_axil_wr.awprot;
|
||||
m_axil_awuser_reg <= s_axil_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
m_axil_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass AW channel
|
||||
assign m_axil_wr.awaddr = s_axil_wr.awaddr;
|
||||
assign m_axil_wr.awprot = s_axil_wr.awprot;
|
||||
assign m_axil_wr.awuser = AWUSER_EN ? s_axil_wr.awuser : '0;
|
||||
assign m_axil_wr.awvalid = s_axil_wr.awvalid;
|
||||
assign s_axil_wr.awready = m_axil_wr.awready;
|
||||
|
||||
end
|
||||
|
||||
// W channel
|
||||
|
||||
if (W_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axil_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axil_wstrb_reg = '0;
|
||||
logic [WUSER_W-1:0] m_axil_wuser_reg = '0;
|
||||
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
|
||||
|
||||
logic [DATA_W-1:0] temp_m_axil_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] temp_m_axil_wstrb_reg = '0;
|
||||
logic [WUSER_W-1:0] temp_m_axil_wuser_reg = '0;
|
||||
logic temp_m_axil_wvalid_reg = 1'b0, temp_m_axil_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_w_input_to_output;
|
||||
logic store_axil_w_input_to_temp;
|
||||
logic store_axil_w_temp_to_output;
|
||||
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
|
||||
assign m_axil_wr.wdata = m_axil_wdata_reg;
|
||||
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
|
||||
assign m_axil_wr.wuser = WUSER_EN ? m_axil_wuser_reg : '0;
|
||||
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axil_wready_early = m_axil_wr.wready || (!temp_m_axil_wvalid_reg && (!m_axil_wvalid_reg || !s_axil_wr.wvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_wvalid_next = m_axil_wvalid_reg;
|
||||
temp_m_axil_wvalid_next = temp_m_axil_wvalid_reg;
|
||||
|
||||
store_axil_w_input_to_output = 1'b0;
|
||||
store_axil_w_input_to_temp = 1'b0;
|
||||
store_axil_w_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axil_wready_reg) begin
|
||||
// input is ready
|
||||
if (m_axil_wr.wready || !m_axil_wvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axil_wvalid_next = s_axil_wr.wvalid;
|
||||
store_axil_w_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axil_wvalid_next = s_axil_wr.wvalid;
|
||||
store_axil_w_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axil_wr.wready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axil_wvalid_next = temp_m_axil_wvalid_reg;
|
||||
temp_m_axil_wvalid_next = 1'b0;
|
||||
store_axil_w_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_wready_reg <= s_axil_wready_early;
|
||||
m_axil_wvalid_reg <= m_axil_wvalid_next;
|
||||
temp_m_axil_wvalid_reg <= temp_m_axil_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_w_input_to_output) begin
|
||||
m_axil_wdata_reg <= s_axil_wr.wdata;
|
||||
m_axil_wstrb_reg <= s_axil_wr.wstrb;
|
||||
m_axil_wuser_reg <= s_axil_wr.wuser;
|
||||
end else if (store_axil_w_temp_to_output) begin
|
||||
m_axil_wdata_reg <= temp_m_axil_wdata_reg;
|
||||
m_axil_wstrb_reg <= temp_m_axil_wstrb_reg;
|
||||
m_axil_wuser_reg <= temp_m_axil_wuser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_w_input_to_temp) begin
|
||||
temp_m_axil_wdata_reg <= s_axil_wr.wdata;
|
||||
temp_m_axil_wstrb_reg <= s_axil_wr.wstrb;
|
||||
temp_m_axil_wuser_reg <= s_axil_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
m_axil_wvalid_reg <= 1'b0;
|
||||
temp_m_axil_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (W_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axil_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axil_wstrb_reg = '0;
|
||||
logic [WUSER_W-1:0] m_axil_wuser_reg = '0;
|
||||
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_w_input_to_output;
|
||||
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
|
||||
assign m_axil_wr.wdata = m_axil_wdata_reg;
|
||||
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
|
||||
assign m_axil_wr.wuser = WUSER_EN ? m_axil_wuser_reg : '0;
|
||||
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axil_wready_early = !m_axil_wvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_wvalid_next = m_axil_wvalid_reg;
|
||||
|
||||
store_axil_w_input_to_output = 1'b0;
|
||||
|
||||
if (s_axil_wready_reg) begin
|
||||
m_axil_wvalid_next = s_axil_wr.wvalid;
|
||||
store_axil_w_input_to_output = 1'b1;
|
||||
end else if (m_axil_wr.wready) begin
|
||||
m_axil_wvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_wready_reg <= s_axil_wready_early;
|
||||
m_axil_wvalid_reg <= m_axil_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_w_input_to_output) begin
|
||||
m_axil_wdata_reg <= s_axil_wr.wdata;
|
||||
m_axil_wstrb_reg <= s_axil_wr.wstrb;
|
||||
m_axil_wuser_reg <= s_axil_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
m_axil_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass W channel
|
||||
assign m_axil_wr.wdata = s_axil_wr.wdata;
|
||||
assign m_axil_wr.wstrb = s_axil_wr.wstrb;
|
||||
assign m_axil_wr.wuser = WUSER_EN ? s_axil_wr.wuser : '0;
|
||||
assign m_axil_wr.wvalid = s_axil_wr.wvalid;
|
||||
assign s_axil_wr.wready = m_axil_wr.wready;
|
||||
|
||||
end
|
||||
|
||||
// B channel
|
||||
|
||||
if (B_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_bready_reg = 1'b0;
|
||||
|
||||
logic [1:0] s_axil_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axil_buser_reg = '0;
|
||||
logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
|
||||
logic [1:0] temp_s_axil_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] temp_s_axil_buser_reg = '0;
|
||||
logic temp_s_axil_bvalid_reg = 1'b0, temp_s_axil_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_b_input_to_output;
|
||||
logic store_axil_b_input_to_temp;
|
||||
logic store_axil_b_temp_to_output;
|
||||
|
||||
assign m_axil_wr.bready = m_axil_bready_reg;
|
||||
|
||||
assign s_axil_wr.bresp = s_axil_bresp_reg;
|
||||
assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire m_axil_bready_early = s_axil_wr.bready || (!temp_s_axil_bvalid_reg && (!s_axil_bvalid_reg || !m_axil_wr.bvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg;
|
||||
temp_s_axil_bvalid_next = temp_s_axil_bvalid_reg;
|
||||
|
||||
store_axil_b_input_to_output = 1'b0;
|
||||
store_axil_b_input_to_temp = 1'b0;
|
||||
store_axil_b_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axil_bready_reg) begin
|
||||
// input is ready
|
||||
if (s_axil_wr.bready || !s_axil_bvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axil_bvalid_next = m_axil_wr.bvalid;
|
||||
store_axil_b_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axil_bvalid_next = m_axil_wr.bvalid;
|
||||
store_axil_b_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (s_axil_wr.bready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axil_bvalid_next = temp_s_axil_bvalid_reg;
|
||||
temp_s_axil_bvalid_next = 1'b0;
|
||||
store_axil_b_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_bready_reg <= m_axil_bready_early;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
temp_s_axil_bvalid_reg <= temp_s_axil_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_b_input_to_output) begin
|
||||
s_axil_bresp_reg <= m_axil_wr.bresp;
|
||||
s_axil_buser_reg <= m_axil_wr.buser;
|
||||
end else if (store_axil_b_temp_to_output) begin
|
||||
s_axil_bresp_reg <= temp_s_axil_bresp_reg;
|
||||
s_axil_buser_reg <= temp_s_axil_buser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_b_input_to_temp) begin
|
||||
temp_s_axil_bresp_reg <= m_axil_wr.bresp;
|
||||
temp_s_axil_buser_reg <= m_axil_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_bready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
temp_s_axil_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (B_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_bready_reg = 1'b0;
|
||||
|
||||
logic [1:0] s_axil_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axil_buser_reg = '0;
|
||||
logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_b_input_to_output;
|
||||
|
||||
assign m_axil_wr.bready = m_axil_bready_reg;
|
||||
|
||||
assign s_axil_wr.bresp = s_axil_bresp_reg;
|
||||
assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axil_bready_early = !s_axil_bvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg;
|
||||
|
||||
store_axil_b_input_to_output = 1'b0;
|
||||
|
||||
if (m_axil_bready_reg) begin
|
||||
s_axil_bvalid_next = m_axil_wr.bvalid;
|
||||
store_axil_b_input_to_output = 1'b1;
|
||||
end else if (s_axil_wr.bready) begin
|
||||
s_axil_bvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_bready_reg <= m_axil_bready_early;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_b_input_to_output) begin
|
||||
s_axil_bresp_reg <= m_axil_wr.bresp;
|
||||
s_axil_buser_reg <= m_axil_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_bready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass B channel
|
||||
assign s_axil_wr.bresp = m_axil_wr.bresp;
|
||||
assign s_axil_wr.buser = BUSER_EN ? m_axil_wr.buser : '0;
|
||||
assign s_axil_wr.bvalid = m_axil_wr.bvalid;
|
||||
assign m_axil_wr.bready = s_axil_wr.bready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
54
src/axi/tb/taxi_axi_ram/Makefile
Normal file
54
src/axi/tb/taxi_axi_ram/Makefile
Normal file
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axi_ram
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axi_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 16
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_PIPELINE_OUTPUT := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
243
src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.py
Normal file
243
src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.py
Normal file
@@ -0,0 +1,243 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiBus, AxiMaster
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.axi_master = AxiMaster(AxiBus.from_entity(dut.s_axi), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axi_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axi_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axi_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axi_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axi_master.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axi_master.write_if.byte_lanes
|
||||
max_burst_size = tb.axi_master.write_if.max_burst_size
|
||||
|
||||
if size is None:
|
||||
size = max_burst_size
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in list(range(1, byte_lanes*2))+[1024]:
|
||||
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
|
||||
tb.log.info("length %d, offset %d, size %d", length, offset, size)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axi_master.write(addr-4, b'\xaa'*(length+8))
|
||||
|
||||
await tb.axi_master.write(addr, test_data, size=size)
|
||||
|
||||
data = await tb.axi_master.read(addr-1, length+2)
|
||||
|
||||
assert data.data == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axi_master.write_if.byte_lanes
|
||||
max_burst_size = tb.axi_master.write_if.max_burst_size
|
||||
|
||||
if size is None:
|
||||
size = max_burst_size
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in list(range(1, byte_lanes*2))+[1024]:
|
||||
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
|
||||
tb.log.info("length %d, offset %d, size %d", length, offset, size)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axi_master.write(addr, test_data)
|
||||
|
||||
data = await tb.axi_master.read(addr, length, size=size)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(512, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0).join()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
data_width = len(cocotb.top.s_axi.wdata)
|
||||
byte_lanes = data_width // 8
|
||||
max_burst_size = (byte_lanes-1).bit_length()
|
||||
|
||||
for test in [run_test_write, run_test_read]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("size", [None]+list(range(max_burst_size)))
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axi_ram(request, data_w):
|
||||
dut = "taxi_axi_ram"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axi_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 16
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['ID_W'] = 8
|
||||
parameters['PIPELINE_OUTPUT'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
57
src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.sv
Normal file
57
src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.sv
Normal file
@@ -0,0 +1,57 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 RAM testbench
|
||||
*/
|
||||
module test_taxi_axi_ram #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 16,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter ID_W = 8,
|
||||
parameter PIPELINE_OUTPUT = 0
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axi_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W+16),
|
||||
.STRB_W(STRB_W),
|
||||
.ID_W(ID_W)
|
||||
) s_axi();
|
||||
|
||||
taxi_axi_ram #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axi_wr(s_axi),
|
||||
.s_axi_rd(s_axi)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
72
src/axi/tb/taxi_axi_register/Makefile
Normal file
72
src/axi/tb/taxi_axi_register/Makefile
Normal file
@@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axi_register
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
REG_TYPE ?= 1
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 32
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_AWUSER_EN := 0
|
||||
export PARAM_AWUSER_W := 1
|
||||
export PARAM_WUSER_EN := 0
|
||||
export PARAM_WUSER_W := 1
|
||||
export PARAM_BUSER_EN := 0
|
||||
export PARAM_BUSER_W := 1
|
||||
export PARAM_ARUSER_EN := 0
|
||||
export PARAM_ARUSER_W := 1
|
||||
export PARAM_RUSER_EN := 0
|
||||
export PARAM_RUSER_W := 1
|
||||
export PARAM_AW_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_W_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_B_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_AR_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_R_REG_TYPE := $(REG_TYPE)
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
265
src/axi/tb/taxi_axi_register/test_taxi_axi_register.py
Normal file
265
src/axi/tb/taxi_axi_register/test_taxi_axi_register.py
Normal file
@@ -0,0 +1,265 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiBus, AxiMaster, AxiRam
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.axi_master = AxiMaster(AxiBus.from_entity(dut.s_axi), dut.clk, dut.rst)
|
||||
self.axi_ram = AxiRam(AxiBus.from_entity(dut.m_axi), dut.clk, dut.rst, size=2**16)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axi_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axi_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axi_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
self.axi_ram.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axi_ram.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axi_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axi_master.read_if.r_channel.set_pause_generator(generator())
|
||||
self.axi_ram.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axi_ram.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axi_ram.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axi_master.write_if.byte_lanes
|
||||
max_burst_size = tb.axi_master.write_if.max_burst_size
|
||||
|
||||
if size is None:
|
||||
size = max_burst_size
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in list(range(1, byte_lanes*2))+[1024]:
|
||||
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
|
||||
tb.log.info("length %d, offset %d, size %d", length, offset, size)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axi_ram.write(addr-128, b'\xaa'*(length+256))
|
||||
|
||||
await tb.axi_master.write(addr, test_data, size=size)
|
||||
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
assert tb.axi_ram.read(addr, length) == test_data
|
||||
assert tb.axi_ram.read(addr-1, 1) == b'\xaa'
|
||||
assert tb.axi_ram.read(addr+length, 1) == b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axi_master.write_if.byte_lanes
|
||||
max_burst_size = tb.axi_master.write_if.max_burst_size
|
||||
|
||||
if size is None:
|
||||
size = max_burst_size
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in list(range(1, byte_lanes*2))+[1024]:
|
||||
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
|
||||
tb.log.info("length %d, offset %d, size %d", length, offset, size)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axi_ram.write(addr, test_data)
|
||||
|
||||
data = await tb.axi_master.read(addr, length, size=size)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(512, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
data_width = len(cocotb.top.s_axi.wdata)
|
||||
byte_lanes = data_width // 8
|
||||
max_burst_size = (byte_lanes-1).bit_length()
|
||||
|
||||
for test in [run_test_write, run_test_read]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("size", [None]+list(range(max_burst_size)))
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("reg_type", [None, 0, 1, 2])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axi_register(request, data_w, reg_type):
|
||||
dut = "taxi_axi_register"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 32
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['ID_W'] = 8
|
||||
parameters['AWUSER_EN'] = 0
|
||||
parameters['AWUSER_W'] = 1
|
||||
parameters['WUSER_EN'] = 0
|
||||
parameters['WUSER_W'] = 1
|
||||
parameters['BUSER_EN'] = 0
|
||||
parameters['BUSER_W'] = 1
|
||||
parameters['ARUSER_EN'] = 0
|
||||
parameters['ARUSER_W'] = 1
|
||||
parameters['RUSER_EN'] = 0
|
||||
parameters['RUSER_W'] = 1
|
||||
parameters['AW_REG_TYPE'] = 1 if reg_type is None else reg_type
|
||||
parameters['W_REG_TYPE'] = 2 if reg_type is None else reg_type
|
||||
parameters['B_REG_TYPE'] = 1 if reg_type is None else reg_type
|
||||
parameters['AR_REG_TYPE'] = 1 if reg_type is None else reg_type
|
||||
parameters['R_REG_TYPE'] = 2 if reg_type is None else reg_type
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
90
src/axi/tb/taxi_axi_register/test_taxi_axi_register.sv
Normal file
90
src/axi/tb/taxi_axi_register/test_taxi_axi_register.sv
Normal file
@@ -0,0 +1,90 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 register testbench
|
||||
*/
|
||||
module test_taxi_axi_register #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 32,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter ID_W = 8,
|
||||
parameter logic AWUSER_EN = 1'b0,
|
||||
parameter AWUSER_W = 1,
|
||||
parameter logic WUSER_EN = 1'b0,
|
||||
parameter WUSER_W = 1,
|
||||
parameter logic BUSER_EN = 1'b0,
|
||||
parameter BUSER_W = 1,
|
||||
parameter logic ARUSER_EN = 1'b0,
|
||||
parameter ARUSER_W = 1,
|
||||
parameter logic RUSER_EN = 1'b0,
|
||||
parameter RUSER_W = 1,
|
||||
parameter AW_REG_TYPE = 1,
|
||||
parameter W_REG_TYPE = 2,
|
||||
parameter B_REG_TYPE = 1,
|
||||
parameter AR_REG_TYPE = 1,
|
||||
parameter R_REG_TYPE = 2
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axi_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W),
|
||||
.STRB_W(STRB_W),
|
||||
.ID_W(ID_W),
|
||||
.AWUSER_EN(AWUSER_EN),
|
||||
.AWUSER_W(AWUSER_W),
|
||||
.WUSER_EN(WUSER_EN),
|
||||
.WUSER_W(WUSER_W),
|
||||
.BUSER_EN(BUSER_EN),
|
||||
.BUSER_W(BUSER_W),
|
||||
.ARUSER_EN(ARUSER_EN),
|
||||
.ARUSER_W(ARUSER_W),
|
||||
.RUSER_EN(RUSER_EN),
|
||||
.RUSER_W(RUSER_W)
|
||||
) s_axi(), m_axi();
|
||||
|
||||
taxi_axi_register #(
|
||||
.AW_REG_TYPE(AW_REG_TYPE),
|
||||
.W_REG_TYPE(W_REG_TYPE),
|
||||
.B_REG_TYPE(B_REG_TYPE),
|
||||
.AR_REG_TYPE(AR_REG_TYPE),
|
||||
.R_REG_TYPE(R_REG_TYPE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
.s_axi_wr(s_axi),
|
||||
.s_axi_rd(s_axi),
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
.m_axi_wr(m_axi),
|
||||
.m_axi_rd(m_axi)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
54
src/axi/tb/taxi_axil_dp_ram/Makefile
Normal file
54
src/axi/tb/taxi_axil_dp_ram/Makefile
Normal file
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axil_dp_ram
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 16
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_PIPELINE_OUTPUT := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
276
src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py
Normal file
276
src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py
Normal file
@@ -0,0 +1,276 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.a_clk, 8, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.b_clk, 10, units="ns").start())
|
||||
|
||||
self.axil_master = []
|
||||
|
||||
self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil_a), dut.a_clk, dut.a_rst))
|
||||
self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil_b), dut.b_clk, dut.b_rst))
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
for axil_master in self.axil_master:
|
||||
axil_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
axil_master.write_if.w_channel.set_pause_generator(generator())
|
||||
axil_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
for axil_master in self.axil_master:
|
||||
axil_master.write_if.b_channel.set_pause_generator(generator())
|
||||
axil_master.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.a_rst.setimmediatevalue(0)
|
||||
self.dut.b_rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
self.dut.a_rst.value = 1
|
||||
self.dut.b_rst.value = 1
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
self.dut.a_rst.value = 0
|
||||
await RisingEdge(self.dut.b_clk)
|
||||
self.dut.b_rst.value = 0
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, port=0, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
axil_master = tb.axil_master[port]
|
||||
byte_lanes = axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await axil_master.write(addr-4, b'\xaa'*(length+8))
|
||||
|
||||
await axil_master.write(addr, test_data)
|
||||
|
||||
data = await axil_master.read(addr-1, length+2)
|
||||
|
||||
assert data.data == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
await RisingEdge(dut.a_clk)
|
||||
await RisingEdge(dut.a_clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, port=0, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
axil_master = tb.axil_master[port]
|
||||
byte_lanes = axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await axil_master.write(addr, test_data)
|
||||
|
||||
data = await axil_master.read(addr, length)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.a_clk)
|
||||
await RisingEdge(dut.a_clk)
|
||||
|
||||
|
||||
async def run_test_arb(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset):
|
||||
wr_op = master.init_write(offset, b'\x11\x22\x33\x44')
|
||||
rd_op = master.init_read(offset, 4)
|
||||
|
||||
await wr_op.wait()
|
||||
await rd_op.wait()
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(10):
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master[0], k*256)))
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master[1], k*256)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0).join()
|
||||
|
||||
await RisingEdge(dut.a_clk)
|
||||
await RisingEdge(dut.a_clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(32, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master[k%len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0).join()
|
||||
|
||||
await RisingEdge(dut.a_clk)
|
||||
await RisingEdge(dut.a_clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
for test in [run_test_write, run_test_read]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("port", [0, 1])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_test_arb)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axil_dp_ram(request, data_w):
|
||||
dut = "taxi_axil_dp_ram"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axil_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 16
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['PIPELINE_OUTPUT'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
64
src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv
Normal file
64
src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv
Normal file
@@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite dual-port RAM testbench
|
||||
*/
|
||||
module test_taxi_axil_dp_ram #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 16,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter PIPELINE_OUTPUT = 0
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic a_clk;
|
||||
logic a_rst;
|
||||
logic b_clk;
|
||||
logic b_rst;
|
||||
|
||||
taxi_axil_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W+16),
|
||||
.STRB_W(STRB_W)
|
||||
) s_axil_a(), s_axil_b();
|
||||
|
||||
taxi_axil_dp_ram #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
|
||||
)
|
||||
uut (
|
||||
/*
|
||||
* Port A
|
||||
*/
|
||||
.a_clk(a_clk),
|
||||
.a_rst(a_rst),
|
||||
.s_axil_wr_a(s_axil_a),
|
||||
.s_axil_rd_a(s_axil_a),
|
||||
|
||||
/*
|
||||
* Port B
|
||||
*/
|
||||
.b_clk(b_clk),
|
||||
.b_rst(b_rst),
|
||||
.s_axil_wr_b(s_axil_b),
|
||||
.s_axil_rd_b(s_axil_b)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
54
src/axi/tb/taxi_axil_ram/Makefile
Normal file
54
src/axi/tb/taxi_axil_ram/Makefile
Normal file
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axil_ram
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 16
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_PIPELINE_OUTPUT := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
224
src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.py
Normal file
224
src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.py
Normal file
@@ -0,0 +1,224 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axil_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axil_master.write(addr-4, b'\xaa'*(length+8))
|
||||
|
||||
await tb.axil_master.write(addr, test_data)
|
||||
|
||||
data = await tb.axil_master.read(addr-1, length+2)
|
||||
|
||||
assert data.data == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axil_master.write(addr, test_data)
|
||||
|
||||
data = await tb.axil_master.read(addr, length)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(32, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0).join()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
for test in [run_test_write, run_test_read, run_stress_test]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axil_ram(request, data_w):
|
||||
dut = "taxi_axil_ram"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axil_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 16
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['PIPELINE_OUTPUT'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
55
src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.sv
Normal file
55
src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.sv
Normal file
@@ -0,0 +1,55 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite RAM testbench
|
||||
*/
|
||||
module test_taxi_axil_ram #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 16,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter PIPELINE_OUTPUT = 0
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axil_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W+16),
|
||||
.STRB_W(STRB_W)
|
||||
) s_axil();
|
||||
|
||||
taxi_axil_ram #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axil_wr(s_axil),
|
||||
.s_axil_rd(s_axil)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
69
src/axi/tb/taxi_axil_register/Makefile
Normal file
69
src/axi/tb/taxi_axil_register/Makefile
Normal file
@@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axil_register
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
REG_TYPE ?= 1
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 32
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_AWUSER_EN := 0
|
||||
export PARAM_AWUSER_W := 1
|
||||
export PARAM_WUSER_EN := 0
|
||||
export PARAM_WUSER_W := 1
|
||||
export PARAM_BUSER_EN := 0
|
||||
export PARAM_BUSER_W := 1
|
||||
export PARAM_ARUSER_EN := 0
|
||||
export PARAM_ARUSER_W := 1
|
||||
export PARAM_RUSER_EN := 0
|
||||
export PARAM_RUSER_W := 1
|
||||
export PARAM_AW_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_W_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_B_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_AR_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_R_REG_TYPE := $(REG_TYPE)
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
246
src/axi/tb/taxi_axil_register/test_taxi_axil_register.py
Normal file
246
src/axi/tb/taxi_axil_register/test_taxi_axil_register.py
Normal file
@@ -0,0 +1,246 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst)
|
||||
self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axil_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
self.axil_ram.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axil_ram.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.r_channel.set_pause_generator(generator())
|
||||
self.axil_ram.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axil_ram.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axil_ram.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axil_ram.write(addr-128, b'\xaa'*(length+256))
|
||||
|
||||
await tb.axil_master.write(addr, test_data)
|
||||
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
assert tb.axil_ram.read(addr, length) == test_data
|
||||
assert tb.axil_ram.read(addr-1, 1) == b'\xaa'
|
||||
assert tb.axil_ram.read(addr+length, 1) == b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axil_ram.write(addr, test_data)
|
||||
|
||||
data = await tb.axil_master.read(addr, length)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(32, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
for test in [run_test_write, run_test_read, run_stress_test]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("reg_type", [0, 1, 2])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axil_register(request, data_w, reg_type):
|
||||
dut = "taxi_axil_register"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 32
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['AWUSER_EN'] = 0
|
||||
parameters['AWUSER_W'] = 1
|
||||
parameters['WUSER_EN'] = 0
|
||||
parameters['WUSER_W'] = 1
|
||||
parameters['BUSER_EN'] = 0
|
||||
parameters['BUSER_W'] = 1
|
||||
parameters['ARUSER_EN'] = 0
|
||||
parameters['ARUSER_W'] = 1
|
||||
parameters['RUSER_EN'] = 0
|
||||
parameters['RUSER_W'] = 1
|
||||
parameters['AW_REG_TYPE'] = reg_type
|
||||
parameters['W_REG_TYPE'] = reg_type
|
||||
parameters['B_REG_TYPE'] = reg_type
|
||||
parameters['AR_REG_TYPE'] = reg_type
|
||||
parameters['R_REG_TYPE'] = reg_type
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
88
src/axi/tb/taxi_axil_register/test_taxi_axil_register.sv
Normal file
88
src/axi/tb/taxi_axil_register/test_taxi_axil_register.sv
Normal file
@@ -0,0 +1,88 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite register testbench
|
||||
*/
|
||||
module test_taxi_axil_register #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 32,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter logic AWUSER_EN = 1'b0,
|
||||
parameter AWUSER_W = 1,
|
||||
parameter logic WUSER_EN = 1'b0,
|
||||
parameter WUSER_W = 1,
|
||||
parameter logic BUSER_EN = 1'b0,
|
||||
parameter BUSER_W = 1,
|
||||
parameter logic ARUSER_EN = 1'b0,
|
||||
parameter ARUSER_W = 1,
|
||||
parameter logic RUSER_EN = 1'b0,
|
||||
parameter RUSER_W = 1,
|
||||
parameter AW_REG_TYPE = 1,
|
||||
parameter W_REG_TYPE = 1,
|
||||
parameter B_REG_TYPE = 1,
|
||||
parameter AR_REG_TYPE = 1,
|
||||
parameter R_REG_TYPE = 1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axil_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W),
|
||||
.STRB_W(STRB_W),
|
||||
.AWUSER_EN(AWUSER_EN),
|
||||
.AWUSER_W(AWUSER_W),
|
||||
.WUSER_EN(WUSER_EN),
|
||||
.WUSER_W(WUSER_W),
|
||||
.BUSER_EN(BUSER_EN),
|
||||
.BUSER_W(BUSER_W),
|
||||
.ARUSER_EN(ARUSER_EN),
|
||||
.ARUSER_W(ARUSER_W),
|
||||
.RUSER_EN(RUSER_EN),
|
||||
.RUSER_W(RUSER_W)
|
||||
) s_axil(), m_axil();
|
||||
|
||||
taxi_axil_register #(
|
||||
.AW_REG_TYPE(AW_REG_TYPE),
|
||||
.W_REG_TYPE(W_REG_TYPE),
|
||||
.B_REG_TYPE(B_REG_TYPE),
|
||||
.AR_REG_TYPE(AR_REG_TYPE),
|
||||
.R_REG_TYPE(R_REG_TYPE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axil_wr(s_axil),
|
||||
.s_axil_rd(s_axil),
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
.m_axil_wr(m_axil),
|
||||
.m_axil_rd(m_axil)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
1
src/axis/lib/taxi
Symbolic link
1
src/axis/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../
|
||||
290
src/axis/rtl/taxi_axis_adapter.sv
Normal file
290
src/axis/rtl/taxi_axis_adapter.sv
Normal file
@@ -0,0 +1,290 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream bus width adapter
|
||||
*/
|
||||
module taxi_axis_adapter
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam S_DATA_W = s_axis.DATA_W;
|
||||
localparam logic S_KEEP_EN = s_axis.KEEP_EN;
|
||||
localparam S_KEEP_W = s_axis.KEEP_W;
|
||||
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
|
||||
localparam logic LAST_EN = s_axis.LAST_EN;
|
||||
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
|
||||
localparam ID_W = s_axis.ID_W;
|
||||
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
|
||||
localparam DEST_W = s_axis.DEST_W;
|
||||
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
|
||||
localparam USER_W = s_axis.USER_W;
|
||||
|
||||
localparam M_DATA_W = m_axis.DATA_W;
|
||||
localparam logic M_KEEP_EN = m_axis.KEEP_EN;
|
||||
localparam M_KEEP_W = m_axis.KEEP_W;
|
||||
|
||||
// force keep width to 1 when disabled
|
||||
localparam S_BYTE_LANES = S_KEEP_EN ? S_KEEP_W : 1;
|
||||
localparam M_BYTE_LANES = M_KEEP_EN ? M_KEEP_W : 1;
|
||||
|
||||
// bus byte sizes (must be identical)
|
||||
localparam S_BYTE_SIZE = S_DATA_W / S_BYTE_LANES;
|
||||
localparam M_BYTE_SIZE = M_DATA_W / M_BYTE_LANES;
|
||||
|
||||
// check configuration
|
||||
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_W)
|
||||
$fatal(0, "Error: input data width not evenly divisible (instance %m)");
|
||||
|
||||
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_W)
|
||||
$fatal(0, "Error: output data width not evenly divisible (instance %m)");
|
||||
|
||||
if (S_BYTE_SIZE != M_BYTE_SIZE)
|
||||
$fatal(0, "Error: byte size mismatch (instance %m)");
|
||||
|
||||
wire [S_KEEP_W-1:0] s_axis_tkeep_int = S_KEEP_EN ? s_axis.tkeep : '1;
|
||||
|
||||
if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass
|
||||
// same width; bypass
|
||||
|
||||
assign s_axis.tready = m_axis.tready;
|
||||
|
||||
assign m_axis.tdata = s_axis.tdata;
|
||||
assign m_axis.tkeep = (M_KEEP_EN && S_KEEP_EN) ? s_axis.tkeep : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? s_axis.tstrb : m_axis.tkeep;
|
||||
assign m_axis.tvalid = s_axis.tvalid;
|
||||
assign m_axis.tlast = LAST_EN ? s_axis.tlast : 1'b1;
|
||||
assign m_axis.tid = ID_EN ? s_axis.tid : '0;
|
||||
assign m_axis.tdest = DEST_EN ? s_axis.tdest : '0;
|
||||
assign m_axis.tuser = USER_EN ? s_axis.tuser : '0;
|
||||
|
||||
end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
|
||||
// output is wider; upsize
|
||||
|
||||
// required number of segments in wider bus
|
||||
localparam SEG_COUNT = M_BYTE_LANES / S_BYTE_LANES;
|
||||
// data width and keep width per segment
|
||||
localparam SEG_DATA_W = M_DATA_W / SEG_COUNT;
|
||||
localparam SEG_KEEP_W = M_BYTE_LANES / SEG_COUNT;
|
||||
|
||||
localparam CL_SEG_COUNT = $clog2(SEG_COUNT);
|
||||
|
||||
logic [CL_SEG_COUNT-1:0] seg_reg = '0;
|
||||
|
||||
logic [S_DATA_W-1:0] s_axis_tdata_reg = '0;
|
||||
logic [S_KEEP_W-1:0] s_axis_tkeep_reg = '0;
|
||||
logic [S_KEEP_W-1:0] s_axis_tstrb_reg = '0;
|
||||
logic s_axis_tvalid_reg = 1'b0;
|
||||
logic s_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] s_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] s_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] s_axis_tuser_reg = '0;
|
||||
|
||||
logic [M_DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
logic [M_KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
logic [M_KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
logic m_axis_tvalid_reg = 1'b0;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
assign s_axis.tready = !s_axis_tvalid_reg;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_reg;
|
||||
assign m_axis.tkeep = M_KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
|
||||
assign m_axis.tvalid = m_axis_tvalid_reg;
|
||||
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
|
||||
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis.tready;
|
||||
|
||||
if (!m_axis_tvalid_reg || m_axis.tready) begin
|
||||
// output register empty
|
||||
|
||||
if (seg_reg == 0) begin
|
||||
m_axis_tdata_reg[seg_reg*SEG_DATA_W +: SEG_DATA_W] <= s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis.tdata;
|
||||
m_axis_tkeep_reg <= M_KEEP_W'(s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep_int);
|
||||
m_axis_tstrb_reg <= M_KEEP_W'(s_axis_tvalid_reg ? s_axis_tstrb_reg : s_axis.tstrb);
|
||||
end else begin
|
||||
m_axis_tdata_reg[seg_reg*SEG_DATA_W +: SEG_DATA_W] <= s_axis.tdata;
|
||||
m_axis_tkeep_reg[seg_reg*SEG_KEEP_W +: SEG_KEEP_W] <= s_axis_tkeep_int;
|
||||
m_axis_tstrb_reg[seg_reg*SEG_KEEP_W +: SEG_KEEP_W] <= s_axis.tstrb;
|
||||
end
|
||||
m_axis_tlast_reg <= s_axis_tvalid_reg ? s_axis_tlast_reg : s_axis.tlast;
|
||||
m_axis_tid_reg <= s_axis_tvalid_reg ? s_axis_tid_reg : s_axis.tid;
|
||||
m_axis_tdest_reg <= s_axis_tvalid_reg ? s_axis_tdest_reg : s_axis.tdest;
|
||||
m_axis_tuser_reg <= s_axis_tvalid_reg ? s_axis_tuser_reg : s_axis.tuser;
|
||||
|
||||
if (s_axis_tvalid_reg) begin
|
||||
// consume data from buffer
|
||||
s_axis_tvalid_reg <= 1'b0;
|
||||
|
||||
if ((LAST_EN && s_axis_tlast_reg) || seg_reg == CL_SEG_COUNT'(SEG_COUNT-1)) begin
|
||||
seg_reg <= '0;
|
||||
m_axis_tvalid_reg <= 1'b1;
|
||||
end else begin
|
||||
seg_reg <= seg_reg + 1;
|
||||
end
|
||||
end else if (s_axis.tvalid) begin
|
||||
// data direct from input
|
||||
if ((LAST_EN && s_axis.tlast) || seg_reg == CL_SEG_COUNT'(SEG_COUNT-1)) begin
|
||||
seg_reg <= '0;
|
||||
m_axis_tvalid_reg <= 1'b1;
|
||||
end else begin
|
||||
seg_reg <= seg_reg + 1;
|
||||
end
|
||||
end
|
||||
end else if (s_axis.tvalid && s_axis.tready) begin
|
||||
// store input data in skid buffer
|
||||
s_axis_tdata_reg <= s_axis.tdata;
|
||||
s_axis_tkeep_reg <= s_axis_tkeep_int;
|
||||
s_axis_tstrb_reg <= s_axis.tstrb;
|
||||
s_axis_tvalid_reg <= 1'b1;
|
||||
s_axis_tlast_reg <= s_axis.tlast;
|
||||
s_axis_tid_reg <= s_axis.tid;
|
||||
s_axis_tdest_reg <= s_axis.tdest;
|
||||
s_axis_tuser_reg <= s_axis.tuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
seg_reg <= '0;
|
||||
s_axis_tvalid_reg <= 1'b0;
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin : downsize
|
||||
// output is narrower; downsize
|
||||
|
||||
// required number of segments in wider bus
|
||||
localparam SEG_COUNT = S_BYTE_LANES / M_BYTE_LANES;
|
||||
// data width and keep width per segment
|
||||
localparam SEG_DATA_W = S_DATA_W / SEG_COUNT;
|
||||
localparam SEG_KEEP_W = S_BYTE_LANES / SEG_COUNT;
|
||||
|
||||
logic [S_DATA_W-1:0] s_axis_tdata_reg = '0;
|
||||
logic [S_KEEP_W-1:0] s_axis_tkeep_reg = '0;
|
||||
logic [S_KEEP_W-1:0] s_axis_tstrb_reg = '0;
|
||||
logic s_axis_tvalid_reg = 1'b0;
|
||||
logic s_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] s_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] s_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] s_axis_tuser_reg = '0;
|
||||
|
||||
logic [M_DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
logic [M_KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
logic [M_KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
logic m_axis_tvalid_reg = 1'b0;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
assign s_axis.tready = !s_axis_tvalid_reg;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_reg;
|
||||
assign m_axis.tkeep = M_KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
|
||||
assign m_axis.tvalid = m_axis_tvalid_reg;
|
||||
assign m_axis.tlast = m_axis_tlast_reg;
|
||||
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis.tready;
|
||||
|
||||
if (!m_axis_tvalid_reg || m_axis.tready) begin
|
||||
// output register empty
|
||||
|
||||
m_axis_tdata_reg <= M_DATA_W'(s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis.tdata);
|
||||
m_axis_tkeep_reg <= M_KEEP_W'(s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep_int);
|
||||
m_axis_tstrb_reg <= M_KEEP_W'(s_axis_tvalid_reg ? s_axis_tstrb_reg : s_axis.tstrb);
|
||||
m_axis_tlast_reg <= 1'b0;
|
||||
m_axis_tid_reg <= s_axis_tvalid_reg ? s_axis_tid_reg : s_axis.tid;
|
||||
m_axis_tdest_reg <= s_axis_tvalid_reg ? s_axis_tdest_reg : s_axis.tdest;
|
||||
m_axis_tuser_reg <= s_axis_tvalid_reg ? s_axis_tuser_reg : s_axis.tuser;
|
||||
|
||||
if (s_axis_tvalid_reg) begin
|
||||
// buffer has data; shift out from buffer
|
||||
s_axis_tdata_reg <= s_axis_tdata_reg >> SEG_DATA_W;
|
||||
s_axis_tkeep_reg <= s_axis_tkeep_reg >> SEG_KEEP_W;
|
||||
s_axis_tstrb_reg <= s_axis_tstrb_reg >> SEG_KEEP_W;
|
||||
|
||||
m_axis_tvalid_reg <= 1'b1;
|
||||
|
||||
if ((s_axis_tkeep_reg >> SEG_KEEP_W) == 0) begin
|
||||
s_axis_tvalid_reg <= 1'b0;
|
||||
m_axis_tlast_reg <= s_axis_tlast_reg;
|
||||
end
|
||||
end else if (s_axis.tvalid && s_axis.tready) begin
|
||||
// buffer is empty; store from input
|
||||
s_axis_tdata_reg <= s_axis.tdata >> SEG_DATA_W;
|
||||
s_axis_tkeep_reg <= s_axis_tkeep_int >> SEG_KEEP_W;
|
||||
s_axis_tstrb_reg <= s_axis.tstrb >> SEG_KEEP_W;
|
||||
s_axis_tlast_reg <= s_axis.tlast;
|
||||
s_axis_tid_reg <= s_axis.tid;
|
||||
s_axis_tdest_reg <= s_axis.tdest;
|
||||
s_axis_tuser_reg <= s_axis.tuser;
|
||||
|
||||
m_axis_tvalid_reg <= 1'b1;
|
||||
|
||||
if (S_KEEP_EN && (s_axis_tkeep_int >> SEG_KEEP_W) == 0) begin
|
||||
s_axis_tvalid_reg <= 1'b0;
|
||||
m_axis_tlast_reg <= s_axis.tlast;
|
||||
end else begin
|
||||
s_axis_tvalid_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
end else if (s_axis.tvalid && s_axis.tready) begin
|
||||
// store input data
|
||||
s_axis_tdata_reg <= s_axis.tdata;
|
||||
s_axis_tkeep_reg <= s_axis_tkeep_int;
|
||||
s_axis_tstrb_reg <= s_axis.tstrb;
|
||||
s_axis_tvalid_reg <= 1'b1;
|
||||
s_axis_tlast_reg <= s_axis.tlast;
|
||||
s_axis_tid_reg <= s_axis.tid;
|
||||
s_axis_tdest_reg <= s_axis.tdest;
|
||||
s_axis_tuser_reg <= s_axis.tuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axis_tvalid_reg <= 1'b0;
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
4
src/axis/rtl/taxi_axis_arb_mux.f
Normal file
4
src/axis/rtl/taxi_axis_arb_mux.f
Normal file
@@ -0,0 +1,4 @@
|
||||
taxi_axis_arb_mux.sv
|
||||
taxi_axis_if.sv
|
||||
../lib/taxi/src/prim/rtl/taxi_arbiter.sv
|
||||
../lib/taxi/src/prim/rtl/taxi_penc.sv
|
||||
306
src/axis/rtl/taxi_axis_arb_mux.sv
Normal file
306
src/axis/rtl/taxi_axis_arb_mux.sv
Normal file
@@ -0,0 +1,306 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream arbitrated multiplexer
|
||||
*/
|
||||
module taxi_axis_arb_mux #
|
||||
(
|
||||
// Number of AXI stream inputs
|
||||
parameter S_COUNT = 4,
|
||||
// Update tid with routing information
|
||||
parameter logic UPDATE_TID = 1'b0,
|
||||
// select round robin arbitration
|
||||
parameter logic ARB_ROUND_ROBIN = 1'b0,
|
||||
// LSB priority selection
|
||||
parameter logic ARB_LSB_HIGH_PRIO = 1'b1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Stream inputs (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis[S_COUNT],
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axis[0].DATA_W;
|
||||
localparam logic KEEP_EN = s_axis[0].KEEP_EN && m_axis.KEEP_EN;
|
||||
localparam KEEP_W = s_axis[0].KEEP_W;
|
||||
localparam logic STRB_EN = s_axis[0].STRB_EN && m_axis.STRB_EN;
|
||||
localparam logic LAST_EN = s_axis[0].LAST_EN && m_axis.LAST_EN;
|
||||
localparam logic ID_EN = s_axis[0].ID_EN && m_axis.ID_EN;
|
||||
localparam S_ID_W = s_axis[0].ID_W;
|
||||
localparam logic DEST_EN = s_axis[0].DEST_EN && m_axis.DEST_EN;
|
||||
localparam DEST_W = s_axis[0].DEST_W;
|
||||
localparam logic USER_EN = s_axis[0].USER_EN && m_axis.USER_EN;
|
||||
localparam USER_W = s_axis[0].USER_W;
|
||||
|
||||
localparam M_ID_W = m_axis.ID_W;
|
||||
|
||||
localparam CL_S_COUNT = $clog2(S_COUNT);
|
||||
|
||||
localparam S_ID_W_INT = S_ID_W > 0 ? S_ID_W : 1;
|
||||
|
||||
// check configuration
|
||||
if (UPDATE_TID) begin
|
||||
if (!ID_EN)
|
||||
$fatal(0, "Error: UPDATE_TID set requires ID_EN set (instance %m)");
|
||||
|
||||
if (M_ID_W < CL_S_COUNT)
|
||||
$fatal(0, "Error: M_ID_W too small for port count (instance %m)");
|
||||
end
|
||||
|
||||
// internal datapath
|
||||
logic [DATA_W-1:0] m_axis_tdata_int;
|
||||
logic [KEEP_W-1:0] m_axis_tkeep_int;
|
||||
logic [KEEP_W-1:0] m_axis_tstrb_int;
|
||||
logic m_axis_tvalid_int;
|
||||
logic m_axis_tready_int_reg = 1'b0;
|
||||
logic m_axis_tlast_int;
|
||||
logic [M_ID_W-1:0] m_axis_tid_int;
|
||||
logic [DEST_W-1:0] m_axis_tdest_int;
|
||||
logic [USER_W-1:0] m_axis_tuser_int;
|
||||
wire m_axis_tready_int_early;
|
||||
|
||||
if (S_COUNT == 1) begin
|
||||
// degenerate case
|
||||
|
||||
assign s_axis[0].tready = m_axis_tready_int_reg;
|
||||
|
||||
always_comb begin
|
||||
// pass through selected packet data
|
||||
m_axis_tdata_int = s_axis[0].tdata;
|
||||
m_axis_tkeep_int = s_axis[0].tkeep;
|
||||
m_axis_tstrb_int = s_axis[0].tstrb;
|
||||
m_axis_tvalid_int = s_axis[0].tvalid && m_axis_tready_int_reg;
|
||||
m_axis_tlast_int = s_axis[0].tlast;
|
||||
m_axis_tid_int = M_ID_W'(s_axis[0].tid);
|
||||
m_axis_tdest_int = s_axis[0].tdest;
|
||||
m_axis_tuser_int = s_axis[0].tuser;
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
wire [S_COUNT-1:0] req;
|
||||
wire [S_COUNT-1:0] ack;
|
||||
wire [S_COUNT-1:0] grant;
|
||||
wire grant_valid;
|
||||
wire [CL_S_COUNT-1:0] grant_index;
|
||||
|
||||
// input registers to pipeline arbitration delay
|
||||
logic [DATA_W-1:0] s_axis_tdata_reg[S_COUNT] = '{S_COUNT{'0}};
|
||||
logic [KEEP_W-1:0] s_axis_tkeep_reg[S_COUNT] = '{S_COUNT{'0}};
|
||||
logic [KEEP_W-1:0] s_axis_tstrb_reg[S_COUNT] = '{S_COUNT{'0}};
|
||||
logic [S_COUNT-1:0] s_axis_tvalid_reg = '0;
|
||||
logic [S_COUNT-1:0] s_axis_tlast_reg = '0;
|
||||
logic [S_ID_W-1:0] s_axis_tid_reg[S_COUNT] = '{S_COUNT{'0}};
|
||||
logic [DEST_W-1:0] s_axis_tdest_reg[S_COUNT] = '{S_COUNT{'0}};
|
||||
logic [USER_W-1:0] s_axis_tuser_reg[S_COUNT] = '{S_COUNT{'0}};
|
||||
|
||||
// unpack interface array
|
||||
wire [S_COUNT-1:0] s_axis_tvalid;
|
||||
wire [S_COUNT-1:0] s_axis_tready;
|
||||
|
||||
for (genvar n = 0; n < S_COUNT; n = n + 1) begin
|
||||
assign s_axis_tvalid[n] = s_axis[n].tvalid;
|
||||
assign s_axis[n].tready = s_axis_tready[n];
|
||||
end
|
||||
|
||||
assign s_axis_tready = ~s_axis_tvalid_reg | ({S_COUNT{m_axis_tready_int_reg}} & grant);
|
||||
|
||||
// mux for incoming packet
|
||||
wire [DATA_W-1:0] current_s_tdata = s_axis_tdata_reg[grant_index];
|
||||
wire [KEEP_W-1:0] current_s_tkeep = s_axis_tkeep_reg[grant_index];
|
||||
wire [KEEP_W-1:0] current_s_tstrb = s_axis_tstrb_reg[grant_index];
|
||||
wire current_s_tvalid = s_axis_tvalid_reg[grant_index];
|
||||
wire current_s_tready = s_axis_tready[grant_index];
|
||||
wire current_s_tlast = s_axis_tlast_reg[grant_index];
|
||||
wire [S_ID_W-1:0] current_s_tid = s_axis_tid_reg[grant_index];
|
||||
wire [DEST_W-1:0] current_s_tdest = s_axis_tdest_reg[grant_index];
|
||||
wire [USER_W-1:0] current_s_tuser = s_axis_tuser_reg[grant_index];
|
||||
|
||||
// arbiter instance
|
||||
taxi_arbiter #(
|
||||
.PORTS(S_COUNT),
|
||||
.ARB_ROUND_ROBIN(ARB_ROUND_ROBIN),
|
||||
.ARB_BLOCK(1'b1),
|
||||
.ARB_BLOCK_ACK(1'b1),
|
||||
.LSB_HIGH_PRIO(ARB_LSB_HIGH_PRIO)
|
||||
)
|
||||
arb_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.req(req),
|
||||
.ack(ack),
|
||||
.grant(grant),
|
||||
.grant_valid(grant_valid),
|
||||
.grant_index(grant_index)
|
||||
);
|
||||
|
||||
assign req = s_axis_tvalid | (s_axis_tvalid_reg & ~grant);
|
||||
assign ack = grant & s_axis_tvalid_reg & {S_COUNT{m_axis_tready_int_reg}} & (LAST_EN ? s_axis_tlast_reg : {S_COUNT{1'b1}});
|
||||
|
||||
always_comb begin
|
||||
// pass through selected packet data
|
||||
m_axis_tdata_int = current_s_tdata;
|
||||
m_axis_tkeep_int = current_s_tkeep;
|
||||
m_axis_tstrb_int = current_s_tstrb;
|
||||
m_axis_tvalid_int = current_s_tvalid && m_axis_tready_int_reg && grant_valid;
|
||||
m_axis_tlast_int = current_s_tlast;
|
||||
m_axis_tid_int = M_ID_W'(current_s_tid);
|
||||
if (UPDATE_TID && S_COUNT > 1) begin
|
||||
m_axis_tid_int[M_ID_W-1:M_ID_W-CL_S_COUNT] = grant_index;
|
||||
end
|
||||
m_axis_tdest_int = current_s_tdest;
|
||||
m_axis_tuser_int = current_s_tuser;
|
||||
end
|
||||
|
||||
for (genvar n = 0; n < S_COUNT; n = n + 1) begin
|
||||
always_ff @(posedge clk) begin
|
||||
// register inputs
|
||||
if (s_axis_tready[n]) begin
|
||||
s_axis_tdata_reg[n] <= s_axis[n].tdata;
|
||||
s_axis_tkeep_reg[n] <= s_axis[n].tkeep;
|
||||
s_axis_tstrb_reg[n] <= s_axis[n].tstrb;
|
||||
s_axis_tvalid_reg[n] <= s_axis[n].tvalid;
|
||||
s_axis_tlast_reg[n] <= s_axis[n].tlast;
|
||||
s_axis_tid_reg[n] <= s_axis[n].tid;
|
||||
s_axis_tdest_reg[n] <= s_axis[n].tdest;
|
||||
s_axis_tuser_reg[n] <= s_axis[n].tuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axis_tvalid_reg[n] <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic [M_ID_W-1:0] m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
|
||||
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
|
||||
logic temp_m_axis_tlast_reg = 1'b0;
|
||||
logic [M_ID_W-1:0] temp_m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
|
||||
|
||||
// datapath control
|
||||
logic store_axis_int_to_output;
|
||||
logic store_axis_int_to_temp;
|
||||
logic store_axis_temp_to_output;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_reg;
|
||||
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
|
||||
assign m_axis.tvalid = m_axis_tvalid_reg;
|
||||
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
|
||||
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axis_tvalid_next = m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
|
||||
store_axis_int_to_output = 1'b0;
|
||||
store_axis_int_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (m_axis.tready || !m_axis_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axis_tvalid_next = m_axis_tvalid_int;
|
||||
store_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axis_tvalid_next = m_axis_tvalid_int;
|
||||
store_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axis.tready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
||||
m_axis_tready_int_reg <= m_axis_tready_int_early;
|
||||
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axis_int_to_output) begin
|
||||
m_axis_tdata_reg <= m_axis_tdata_int;
|
||||
m_axis_tkeep_reg <= m_axis_tkeep_int;
|
||||
m_axis_tstrb_reg <= m_axis_tstrb_int;
|
||||
m_axis_tlast_reg <= m_axis_tlast_int;
|
||||
m_axis_tid_reg <= m_axis_tid_int;
|
||||
m_axis_tdest_reg <= m_axis_tdest_int;
|
||||
m_axis_tuser_reg <= m_axis_tuser_int;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
|
||||
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
|
||||
m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
|
||||
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
|
||||
m_axis_tid_reg <= temp_m_axis_tid_reg;
|
||||
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
|
||||
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_int_to_temp) begin
|
||||
temp_m_axis_tdata_reg <= m_axis_tdata_int;
|
||||
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
|
||||
temp_m_axis_tstrb_reg <= m_axis_tstrb_int;
|
||||
temp_m_axis_tlast_reg <= m_axis_tlast_int;
|
||||
temp_m_axis_tid_reg <= m_axis_tid_int;
|
||||
temp_m_axis_tdest_reg <= m_axis_tdest_int;
|
||||
temp_m_axis_tuser_reg <= m_axis_tuser_int;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
m_axis_tready_int_reg <= 1'b0;
|
||||
temp_m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
4
src/axis/rtl/taxi_axis_async_fifo.f
Normal file
4
src/axis/rtl/taxi_axis_async_fifo.f
Normal file
@@ -0,0 +1,4 @@
|
||||
taxi_axis_async_fifo.sv
|
||||
../lib/taxi/src/sync/rtl/taxi_sync_reset.sv
|
||||
../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
|
||||
taxi_axis_if.sv
|
||||
887
src/axis/rtl/taxi_axis_async_fifo.sv
Normal file
887
src/axis/rtl/taxi_axis_async_fifo.sv
Normal file
@@ -0,0 +1,887 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream asynchronous FIFO
|
||||
*/
|
||||
module taxi_axis_async_fifo #
|
||||
(
|
||||
// FIFO depth in words
|
||||
// KEEP_W words per cycle if KEEP_EN set
|
||||
// Rounded up to nearest power of 2 cycles
|
||||
parameter DEPTH = 4096,
|
||||
// FIFO ramstyle attribute
|
||||
parameter FIFO_RAMSTYLE = "auto",
|
||||
// number of RAM pipeline registers
|
||||
parameter RAM_PIPELINE = 1,
|
||||
// use output FIFO
|
||||
// When set, the RAM read enable and pipeline clock enables are removed
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
// output FIFO ramstyle attribute
|
||||
parameter OUTPUT_FIFO_RAMSTYLE = "distributed",
|
||||
// Frame FIFO mode - operate on frames instead of cycles
|
||||
// When set, m_axis_tvalid will not be deasserted within a frame
|
||||
// Requires LAST_EN set
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
// tuser value for bad frame marker
|
||||
parameter USER_BAD_FRAME_VALUE = 1'b1,
|
||||
// tuser mask for bad frame marker
|
||||
parameter USER_BAD_FRAME_MASK = 1'b1,
|
||||
// Drop frames larger than FIFO
|
||||
// Requires FRAME_FIFO set
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
// Drop frames marked bad
|
||||
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
// Drop incoming frames when full
|
||||
// When set, s_axis_tready is always asserted
|
||||
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
// Mark incoming frames as bad frames when full
|
||||
// When set, s_axis_tready is always asserted
|
||||
// Requires FRAME_FIFO to be clear
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
// Enable pause request input
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
// Pause between frames
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
)
|
||||
(
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
input wire logic s_clk,
|
||||
input wire logic s_rst,
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
input wire logic m_clk,
|
||||
input wire logic m_rst,
|
||||
taxi_axis_if.src m_axis,
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
input wire logic s_pause_req = 1'b0,
|
||||
output wire logic s_pause_ack,
|
||||
input wire logic m_pause_req = 1'b0,
|
||||
output wire logic m_pause_ack,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic [$clog2(DEPTH):0] s_status_depth,
|
||||
output wire logic [$clog2(DEPTH):0] s_status_depth_commit,
|
||||
output wire logic s_status_overflow,
|
||||
output wire logic s_status_bad_frame,
|
||||
output wire logic s_status_good_frame,
|
||||
output wire logic [$clog2(DEPTH):0] m_status_depth,
|
||||
output wire logic [$clog2(DEPTH):0] m_status_depth_commit,
|
||||
output wire logic m_status_overflow,
|
||||
output wire logic m_status_bad_frame,
|
||||
output wire logic m_status_good_frame
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axis.DATA_W;
|
||||
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
|
||||
localparam KEEP_W = s_axis.KEEP_W;
|
||||
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
|
||||
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
|
||||
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
|
||||
localparam ID_W = s_axis.ID_W;
|
||||
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
|
||||
localparam DEST_W = s_axis.DEST_W;
|
||||
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
|
||||
localparam USER_W = s_axis.USER_W;
|
||||
|
||||
localparam CL_DEPTH = $clog2(DEPTH);
|
||||
localparam CL_KEEP_W = $clog2(KEEP_W);
|
||||
localparam FIFO_AW = (KEEP_EN && KEEP_W > 1) ? $clog2(DEPTH/KEEP_W) : CL_DEPTH;
|
||||
|
||||
localparam OUTPUT_FIFO_AW = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
|
||||
|
||||
// check configuration
|
||||
if (FRAME_FIFO && !LAST_EN)
|
||||
$fatal(0, "Error: FRAME_FIFO set requires LAST_EN set (instance %m)");
|
||||
|
||||
if (DROP_OVERSIZE_FRAME && !FRAME_FIFO)
|
||||
$fatal(0, "Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
|
||||
|
||||
if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
|
||||
$fatal(0, "Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
|
||||
|
||||
if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
|
||||
$fatal(0, "Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
|
||||
|
||||
if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_W'(USER_BAD_FRAME_MASK) & {USER_W{1'b1}}) == 0)
|
||||
$fatal(0, "Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
|
||||
|
||||
if (MARK_WHEN_FULL && FRAME_FIFO)
|
||||
$fatal(0, "Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)");
|
||||
|
||||
if (MARK_WHEN_FULL && !LAST_EN)
|
||||
$fatal(0, "Error: MARK_WHEN_FULL set requires LAST_EN set (instance %m)");
|
||||
|
||||
if (m_axis.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
|
||||
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
|
||||
|
||||
localparam KEEP_OFFSET = DATA_W;
|
||||
localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0);
|
||||
localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0);
|
||||
localparam ID_OFFSET = LAST_OFFSET + (LAST_EN ? 1 : 0);
|
||||
localparam DEST_OFFSET = ID_OFFSET + (ID_EN ? ID_W : 0);
|
||||
localparam USER_OFFSET = DEST_OFFSET + (DEST_EN ? DEST_W : 0);
|
||||
localparam WIDTH = USER_OFFSET + (USER_EN ? USER_W : 0);
|
||||
|
||||
function [FIFO_AW:0] bin2gray(input [FIFO_AW:0] b);
|
||||
bin2gray = b ^ (b >> 1);
|
||||
endfunction
|
||||
|
||||
function [FIFO_AW:0] gray2bin(input [FIFO_AW:0] g);
|
||||
for (integer i = 0; i <= FIFO_AW; i = i + 1) begin
|
||||
gray2bin[i] = ^(g >> i);
|
||||
end
|
||||
endfunction
|
||||
|
||||
logic [FIFO_AW:0] wr_ptr_reg = '0;
|
||||
logic [FIFO_AW:0] wr_ptr_commit_reg = '0;
|
||||
logic [FIFO_AW:0] wr_ptr_gray_reg = '0;
|
||||
logic [FIFO_AW:0] wr_ptr_sync_commit_reg = '0;
|
||||
logic [FIFO_AW:0] rd_ptr_reg = '0;
|
||||
logic [FIFO_AW:0] rd_ptr_gray_reg = '0;
|
||||
logic [FIFO_AW:0] wr_ptr_conv_reg = '0;
|
||||
logic [FIFO_AW:0] rd_ptr_conv_reg = '0;
|
||||
|
||||
logic [FIFO_AW:0] wr_ptr_temp;
|
||||
logic [FIFO_AW:0] rd_ptr_temp;
|
||||
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic [FIFO_AW:0] wr_ptr_gray_sync1_reg = '0;
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic [FIFO_AW:0] wr_ptr_gray_sync2_reg = '0;
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic [FIFO_AW:0] wr_ptr_commit_sync_reg = '0;
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic [FIFO_AW:0] rd_ptr_gray_sync1_reg = '0;
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic [FIFO_AW:0] rd_ptr_gray_sync2_reg = '0;
|
||||
|
||||
logic wr_ptr_update_valid_reg = 1'b0;
|
||||
logic wr_ptr_update_reg = 1'b0;
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic wr_ptr_update_sync1_reg = 1'b0;
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic wr_ptr_update_sync2_reg = 1'b0;
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic wr_ptr_update_sync3_reg = 1'b0;
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic wr_ptr_update_ack_sync1_reg = 1'b0;
|
||||
(* SHREG_EXTRACT = "NO" *)
|
||||
logic wr_ptr_update_ack_sync2_reg = 1'b0;
|
||||
|
||||
wire s_rst_sync;
|
||||
wire m_rst_sync;
|
||||
|
||||
(* ramstyle = "no_rw_check" *)
|
||||
logic [WIDTH-1:0] mem[2**FIFO_AW];
|
||||
logic mem_read_data_valid_reg = 1'b0;
|
||||
|
||||
(* shreg_extract = "no" *)
|
||||
logic [WIDTH-1:0] mem_rd_data_pipe_reg[RAM_PIPELINE+1-1:0];
|
||||
logic [RAM_PIPELINE+1-1:0] mem_rd_valid_pipe_reg = 0;
|
||||
|
||||
// full when first TWO MSBs do NOT match, but rest matches
|
||||
// (gray code equivalent of first MSB different but rest same)
|
||||
wire full = wr_ptr_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {FIFO_AW-1{1'b0}}});
|
||||
// empty when pointers match exactly
|
||||
wire empty = FRAME_FIFO ? (rd_ptr_reg == wr_ptr_commit_sync_reg) : (rd_ptr_gray_reg == wr_ptr_gray_sync2_reg);
|
||||
// overflow within packet
|
||||
wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {FIFO_AW{1'b0}}});
|
||||
|
||||
// control signals
|
||||
logic write;
|
||||
logic read;
|
||||
logic store_output;
|
||||
|
||||
logic s_frame_reg = 1'b0;
|
||||
logic m_frame_reg = 1'b0;
|
||||
|
||||
logic drop_frame_reg = 1'b0;
|
||||
logic mark_frame_reg = 1'b0;
|
||||
logic send_frame_reg = 1'b0;
|
||||
logic overflow_reg = 1'b0;
|
||||
logic bad_frame_reg = 1'b0;
|
||||
logic good_frame_reg = 1'b0;
|
||||
|
||||
logic m_empty_pipe_reg = 1'b0;
|
||||
logic m_terminate_frame_reg = 1'b0;
|
||||
|
||||
logic [FIFO_AW:0] s_depth_reg = '0;
|
||||
logic [FIFO_AW:0] s_depth_commit_reg = '0;
|
||||
logic [FIFO_AW:0] m_depth_reg = '0;
|
||||
logic [FIFO_AW:0] m_depth_commit_reg = '0;
|
||||
|
||||
logic overflow_sync1_reg = 1'b0;
|
||||
logic overflow_sync2_reg = 1'b0;
|
||||
logic overflow_sync3_reg = 1'b0;
|
||||
logic overflow_sync4_reg = 1'b0;
|
||||
logic bad_frame_sync1_reg = 1'b0;
|
||||
logic bad_frame_sync2_reg = 1'b0;
|
||||
logic bad_frame_sync3_reg = 1'b0;
|
||||
logic bad_frame_sync4_reg = 1'b0;
|
||||
logic good_frame_sync1_reg = 1'b0;
|
||||
logic good_frame_sync2_reg = 1'b0;
|
||||
logic good_frame_sync3_reg = 1'b0;
|
||||
logic good_frame_sync4_reg = 1'b0;
|
||||
|
||||
assign s_axis.tready = (FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL)) && !s_rst_sync;
|
||||
|
||||
wire [WIDTH-1:0] mem_wr_data;
|
||||
|
||||
generate
|
||||
assign mem_wr_data[DATA_W-1:0] = s_axis.tdata;
|
||||
if (KEEP_EN) assign mem_wr_data[KEEP_OFFSET +: KEEP_W] = s_axis.tkeep;
|
||||
if (STRB_EN) assign mem_wr_data[STRB_OFFSET +: KEEP_W] = s_axis.tstrb;
|
||||
if (LAST_EN) assign mem_wr_data[LAST_OFFSET] = s_axis.tlast | mark_frame_reg;
|
||||
if (ID_EN) assign mem_wr_data[ID_OFFSET +: ID_W] = s_axis.tid;
|
||||
if (DEST_EN) assign mem_wr_data[DEST_OFFSET +: DEST_W] = s_axis.tdest;
|
||||
if (USER_EN) assign mem_wr_data[USER_OFFSET +: USER_W] = mark_frame_reg ? USER_W'(USER_BAD_FRAME_VALUE) : s_axis.tuser;
|
||||
endgenerate
|
||||
|
||||
wire [WIDTH-1:0] mem_rd_data = mem_rd_data_pipe_reg[RAM_PIPELINE+1-1];
|
||||
|
||||
wire m_axis_tready_pipe;
|
||||
wire m_axis_tvalid_pipe = mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1];
|
||||
|
||||
wire [DATA_W-1:0] m_axis_tdata_pipe = mem_rd_data[DATA_W-1:0];
|
||||
wire [KEEP_W-1:0] m_axis_tkeep_pipe;
|
||||
wire [KEEP_W-1:0] m_axis_tstrb_pipe;
|
||||
wire m_axis_tlast_pipe;
|
||||
wire [ID_W-1:0] m_axis_tid_pipe;
|
||||
wire [DEST_W-1:0] m_axis_tdest_pipe;
|
||||
wire [USER_W-1:0] m_axis_tuser_pipe;
|
||||
|
||||
if (KEEP_EN) begin
|
||||
assign m_axis_tkeep_pipe = mem_rd_data[KEEP_OFFSET +: KEEP_W];
|
||||
end else begin
|
||||
assign m_axis_tkeep_pipe = '1;
|
||||
end
|
||||
|
||||
if (STRB_EN) begin
|
||||
assign m_axis_tstrb_pipe = mem_rd_data[STRB_OFFSET +: KEEP_W];
|
||||
end else begin
|
||||
assign m_axis_tstrb_pipe = m_axis_tkeep_pipe;
|
||||
end
|
||||
|
||||
if (LAST_EN) begin
|
||||
assign m_axis_tlast_pipe = mem_rd_data[LAST_OFFSET] | m_terminate_frame_reg;
|
||||
end else begin
|
||||
assign m_axis_tlast_pipe = 1'b1;
|
||||
end
|
||||
|
||||
if (ID_EN) begin
|
||||
assign m_axis_tid_pipe = mem_rd_data[ID_OFFSET +: ID_W];
|
||||
end else begin
|
||||
assign m_axis_tid_pipe = '0;
|
||||
end
|
||||
|
||||
if (DEST_EN) begin
|
||||
assign m_axis_tdest_pipe = mem_rd_data[DEST_OFFSET +: DEST_W];
|
||||
end else begin
|
||||
assign m_axis_tdest_pipe = '0;
|
||||
end
|
||||
|
||||
if (USER_EN) begin
|
||||
assign m_axis_tuser_pipe = m_terminate_frame_reg ? USER_W'(USER_BAD_FRAME_VALUE) : mem_rd_data[USER_OFFSET +: USER_W];
|
||||
end else begin
|
||||
assign m_axis_tuser_pipe = '0;
|
||||
end
|
||||
|
||||
wire m_axis_tready_out;
|
||||
wire m_axis_tvalid_out;
|
||||
|
||||
wire [DATA_W-1:0] m_axis_tdata_out;
|
||||
wire [KEEP_W-1:0] m_axis_tkeep_out;
|
||||
wire [KEEP_W-1:0] m_axis_tstrb_out;
|
||||
wire m_axis_tlast_out;
|
||||
wire [ID_W-1:0] m_axis_tid_out;
|
||||
wire [DEST_W-1:0] m_axis_tdest_out;
|
||||
wire [USER_W-1:0] m_axis_tuser_out;
|
||||
|
||||
wire pipe_ready;
|
||||
|
||||
assign s_status_depth = (KEEP_EN && KEEP_W > 1) ? {s_depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(s_depth_reg);
|
||||
assign s_status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {s_depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(s_depth_commit_reg);
|
||||
assign s_status_overflow = overflow_reg;
|
||||
assign s_status_bad_frame = bad_frame_reg;
|
||||
assign s_status_good_frame = good_frame_reg;
|
||||
|
||||
assign m_status_depth = (KEEP_EN && KEEP_W > 1) ? {m_depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(m_depth_reg);
|
||||
assign m_status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {m_depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(m_depth_commit_reg);
|
||||
assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg;
|
||||
assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg;
|
||||
assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg;
|
||||
|
||||
// reset synchronization
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
s_reset_sync_inst (
|
||||
.clk(s_clk),
|
||||
.rst(m_rst),
|
||||
.out(s_rst_sync)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
m_reset_sync_inst (
|
||||
.clk(m_clk),
|
||||
.rst(s_rst),
|
||||
.out(m_rst_sync)
|
||||
);
|
||||
|
||||
// Write logic
|
||||
always_ff @(posedge s_clk) begin
|
||||
overflow_reg <= 1'b0;
|
||||
bad_frame_reg <= 1'b0;
|
||||
good_frame_reg <= 1'b0;
|
||||
|
||||
if (FRAME_FIFO && wr_ptr_update_valid_reg) begin
|
||||
// have updated pointer to sync
|
||||
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
|
||||
// no sync in progress; sync update
|
||||
wr_ptr_update_valid_reg <= 1'b0;
|
||||
wr_ptr_sync_commit_reg <= wr_ptr_commit_reg;
|
||||
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
|
||||
end
|
||||
end
|
||||
|
||||
if (s_axis.tready && s_axis.tvalid && LAST_EN) begin
|
||||
// track input frame status
|
||||
s_frame_reg <= !s_axis.tlast;
|
||||
end
|
||||
|
||||
if (s_rst_sync && LAST_EN) begin
|
||||
// if sink side is reset during transfer, drop partial frame
|
||||
if (s_frame_reg && !(s_axis.tready && s_axis.tvalid && s_axis.tlast)) begin
|
||||
drop_frame_reg <= 1'b1;
|
||||
end
|
||||
if (s_axis.tready && s_axis.tvalid && !s_axis.tlast) begin
|
||||
drop_frame_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (FRAME_FIFO) begin
|
||||
// frame FIFO mode
|
||||
if (s_axis.tready && s_axis.tvalid) begin
|
||||
// transfer in
|
||||
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
|
||||
// full, packet overflow, or currently dropping frame
|
||||
// drop frame
|
||||
drop_frame_reg <= 1'b1;
|
||||
if (s_axis.tlast) begin
|
||||
// end of frame, reset write pointer
|
||||
wr_ptr_temp = wr_ptr_commit_reg;
|
||||
wr_ptr_reg <= wr_ptr_temp;
|
||||
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
||||
drop_frame_reg <= 1'b0;
|
||||
overflow_reg <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
||||
wr_ptr_temp = wr_ptr_reg + 1;
|
||||
wr_ptr_reg <= wr_ptr_temp;
|
||||
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
||||
if (s_axis.tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
|
||||
// end of frame or send frame
|
||||
send_frame_reg <= !s_axis.tlast;
|
||||
if (s_axis.tlast && DROP_BAD_FRAME && (USER_W'(USER_BAD_FRAME_MASK) & ~(s_axis.tuser ^ USER_W'(USER_BAD_FRAME_VALUE))) != 0) begin
|
||||
// bad packet, reset write pointer
|
||||
wr_ptr_temp = wr_ptr_commit_reg;
|
||||
wr_ptr_reg <= wr_ptr_temp;
|
||||
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
||||
bad_frame_reg <= 1'b1;
|
||||
end else begin
|
||||
// good packet or packet overflow, update write pointer
|
||||
wr_ptr_temp = wr_ptr_reg + 1;
|
||||
wr_ptr_reg <= wr_ptr_temp;
|
||||
wr_ptr_commit_reg <= wr_ptr_temp;
|
||||
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
||||
|
||||
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
|
||||
// no sync in progress; sync update
|
||||
wr_ptr_update_valid_reg <= 1'b0;
|
||||
wr_ptr_sync_commit_reg <= wr_ptr_temp;
|
||||
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
|
||||
end else begin
|
||||
// sync in progress; flag it for later
|
||||
wr_ptr_update_valid_reg <= 1'b1;
|
||||
end
|
||||
|
||||
good_frame_reg <= s_axis.tlast;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else if (s_axis.tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
|
||||
// data valid with packet overflow
|
||||
// update write pointer
|
||||
send_frame_reg <= 1'b1;
|
||||
wr_ptr_temp = wr_ptr_reg;
|
||||
wr_ptr_reg <= wr_ptr_temp;
|
||||
wr_ptr_commit_reg <= wr_ptr_temp;
|
||||
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
||||
|
||||
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
|
||||
// no sync in progress; sync update
|
||||
wr_ptr_update_valid_reg <= 1'b0;
|
||||
wr_ptr_sync_commit_reg <= wr_ptr_temp;
|
||||
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
|
||||
end else begin
|
||||
// sync in progress; flag it for later
|
||||
wr_ptr_update_valid_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// normal FIFO mode
|
||||
if (s_axis.tready && s_axis.tvalid) begin
|
||||
if (drop_frame_reg && LAST_EN) begin
|
||||
// currently dropping frame
|
||||
if (s_axis.tlast) begin
|
||||
// end of frame
|
||||
if (!full && mark_frame_reg && MARK_WHEN_FULL) begin
|
||||
// terminate marked frame
|
||||
mark_frame_reg <= 1'b0;
|
||||
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
||||
wr_ptr_temp = wr_ptr_reg + 1;
|
||||
wr_ptr_reg <= wr_ptr_temp;
|
||||
wr_ptr_commit_reg <= wr_ptr_temp;
|
||||
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
||||
end
|
||||
// end of frame, clear drop flag
|
||||
drop_frame_reg <= 1'b0;
|
||||
overflow_reg <= 1'b1;
|
||||
end
|
||||
end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin
|
||||
// full or marking frame
|
||||
// drop frame; mark if this isn't the first cycle
|
||||
drop_frame_reg <= 1'b1;
|
||||
mark_frame_reg <= mark_frame_reg || s_frame_reg;
|
||||
if (s_axis.tlast) begin
|
||||
drop_frame_reg <= 1'b0;
|
||||
overflow_reg <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
// transfer in
|
||||
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
||||
wr_ptr_temp = wr_ptr_reg + 1;
|
||||
wr_ptr_reg <= wr_ptr_temp;
|
||||
wr_ptr_commit_reg <= wr_ptr_temp;
|
||||
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
||||
end
|
||||
end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin
|
||||
// terminate marked frame
|
||||
mark_frame_reg <= 1'b0;
|
||||
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
||||
wr_ptr_temp = wr_ptr_reg + 1;
|
||||
wr_ptr_reg <= wr_ptr_temp;
|
||||
wr_ptr_commit_reg <= wr_ptr_temp;
|
||||
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
|
||||
end
|
||||
end
|
||||
|
||||
if (s_rst_sync) begin
|
||||
wr_ptr_reg <= '0;
|
||||
wr_ptr_commit_reg <= '0;
|
||||
wr_ptr_gray_reg <= '0;
|
||||
wr_ptr_sync_commit_reg <= '0;
|
||||
|
||||
wr_ptr_update_valid_reg <= 1'b0;
|
||||
wr_ptr_update_reg <= 1'b0;
|
||||
end
|
||||
|
||||
if (s_rst) begin
|
||||
wr_ptr_reg <= '0;
|
||||
wr_ptr_commit_reg <= '0;
|
||||
wr_ptr_gray_reg <= '0;
|
||||
wr_ptr_sync_commit_reg <= '0;
|
||||
|
||||
wr_ptr_update_valid_reg <= 1'b0;
|
||||
wr_ptr_update_reg <= 1'b0;
|
||||
|
||||
s_frame_reg <= 1'b0;
|
||||
|
||||
drop_frame_reg <= 1'b0;
|
||||
mark_frame_reg <= 1'b0;
|
||||
send_frame_reg <= 1'b0;
|
||||
overflow_reg <= 1'b0;
|
||||
bad_frame_reg <= 1'b0;
|
||||
good_frame_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Write-side status
|
||||
always_ff @(posedge s_clk) begin
|
||||
rd_ptr_conv_reg <= gray2bin(rd_ptr_gray_sync2_reg);
|
||||
s_depth_reg <= wr_ptr_reg - rd_ptr_conv_reg;
|
||||
s_depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_conv_reg;
|
||||
end
|
||||
|
||||
// pointer synchronization
|
||||
always_ff @(posedge s_clk) begin
|
||||
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
|
||||
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
|
||||
wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
|
||||
wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
|
||||
|
||||
if (s_rst) begin
|
||||
rd_ptr_gray_sync1_reg <= '0;
|
||||
rd_ptr_gray_sync2_reg <= '0;
|
||||
wr_ptr_update_ack_sync1_reg <= 1'b0;
|
||||
wr_ptr_update_ack_sync2_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge m_clk) begin
|
||||
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
|
||||
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
|
||||
if (FRAME_FIFO && wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin
|
||||
wr_ptr_commit_sync_reg <= wr_ptr_sync_commit_reg;
|
||||
end
|
||||
wr_ptr_update_sync1_reg <= wr_ptr_update_reg;
|
||||
wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
|
||||
wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
|
||||
|
||||
if (FRAME_FIFO && m_rst_sync) begin
|
||||
wr_ptr_gray_sync1_reg <= '0;
|
||||
end
|
||||
|
||||
if (m_rst) begin
|
||||
wr_ptr_gray_sync1_reg <= '0;
|
||||
wr_ptr_gray_sync2_reg <= '0;
|
||||
wr_ptr_commit_sync_reg <= '0;
|
||||
wr_ptr_update_sync1_reg <= 1'b0;
|
||||
wr_ptr_update_sync2_reg <= 1'b0;
|
||||
wr_ptr_update_sync3_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// status synchronization
|
||||
always_ff @(posedge s_clk) begin
|
||||
overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg;
|
||||
bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg;
|
||||
good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg;
|
||||
|
||||
if (s_rst) begin
|
||||
overflow_sync1_reg <= 1'b0;
|
||||
bad_frame_sync1_reg <= 1'b0;
|
||||
good_frame_sync1_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge m_clk) begin
|
||||
overflow_sync2_reg <= overflow_sync1_reg;
|
||||
overflow_sync3_reg <= overflow_sync2_reg;
|
||||
overflow_sync4_reg <= overflow_sync3_reg;
|
||||
bad_frame_sync2_reg <= bad_frame_sync1_reg;
|
||||
bad_frame_sync3_reg <= bad_frame_sync2_reg;
|
||||
bad_frame_sync4_reg <= bad_frame_sync3_reg;
|
||||
good_frame_sync2_reg <= good_frame_sync1_reg;
|
||||
good_frame_sync3_reg <= good_frame_sync2_reg;
|
||||
good_frame_sync4_reg <= good_frame_sync3_reg;
|
||||
|
||||
if (m_rst) begin
|
||||
overflow_sync2_reg <= 1'b0;
|
||||
overflow_sync3_reg <= 1'b0;
|
||||
overflow_sync4_reg <= 1'b0;
|
||||
bad_frame_sync2_reg <= 1'b0;
|
||||
bad_frame_sync3_reg <= 1'b0;
|
||||
bad_frame_sync4_reg <= 1'b0;
|
||||
good_frame_sync2_reg <= 1'b0;
|
||||
good_frame_sync3_reg <= 1'b0;
|
||||
good_frame_sync4_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Read logic
|
||||
always_ff @(posedge m_clk) begin
|
||||
if (m_axis_tready_pipe) begin
|
||||
// output ready; invalidate stage
|
||||
mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
|
||||
m_terminate_frame_reg <= 1'b0;
|
||||
end
|
||||
|
||||
for (integer j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
|
||||
// if (m_axis_tready_pipe || ((~mem_rd_valid_pipe_reg) >> j)) begin
|
||||
if (m_axis_tready_pipe || ((RAM_PIPELINE+1)'(~mem_rd_valid_pipe_reg) >> j) != 0) begin
|
||||
// output ready or bubble in pipeline; transfer down pipeline
|
||||
mem_rd_valid_pipe_reg[j] <= mem_rd_valid_pipe_reg[j-1];
|
||||
mem_rd_data_pipe_reg[j] <= mem_rd_data_pipe_reg[j-1];
|
||||
mem_rd_valid_pipe_reg[j-1] <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (m_axis_tready_pipe || &mem_rd_valid_pipe_reg == 0) begin
|
||||
// output ready or bubble in pipeline; read new data from FIFO
|
||||
mem_rd_valid_pipe_reg[0] <= 1'b0;
|
||||
mem_rd_data_pipe_reg[0] <= mem[rd_ptr_reg[FIFO_AW-1:0]];
|
||||
if (!empty && !m_rst_sync && !m_empty_pipe_reg && pipe_ready) begin
|
||||
// not empty, increment pointer
|
||||
mem_rd_valid_pipe_reg[0] <= 1'b1;
|
||||
rd_ptr_temp = rd_ptr_reg + 1;
|
||||
rd_ptr_reg <= rd_ptr_temp;
|
||||
rd_ptr_gray_reg <= rd_ptr_temp ^ (rd_ptr_temp >> 1);
|
||||
end
|
||||
end
|
||||
|
||||
if (m_axis_tvalid_pipe && LAST_EN) begin
|
||||
// track output frame status
|
||||
if (m_axis_tlast_pipe && m_axis_tready_pipe) begin
|
||||
m_frame_reg <= 1'b0;
|
||||
end else begin
|
||||
m_frame_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (m_empty_pipe_reg && mem_rd_valid_pipe_reg == 0 && LAST_EN) begin
|
||||
// terminate frame
|
||||
// (only for frame transfers interrupted by source reset)
|
||||
if (m_frame_reg) begin
|
||||
mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b1;
|
||||
m_terminate_frame_reg <= 1'b1;
|
||||
end
|
||||
m_empty_pipe_reg <= 1'b0;
|
||||
end
|
||||
|
||||
if (m_rst_sync && LAST_EN) begin
|
||||
// if source side is reset during transfer, drop partial frame
|
||||
m_empty_pipe_reg <= 1'b1;
|
||||
end
|
||||
|
||||
if (m_rst_sync) begin
|
||||
rd_ptr_reg <= '0;
|
||||
rd_ptr_gray_reg <= '0;
|
||||
end
|
||||
|
||||
if (m_rst) begin
|
||||
rd_ptr_reg <= '0;
|
||||
rd_ptr_gray_reg <= '0;
|
||||
mem_rd_valid_pipe_reg <= '0;
|
||||
m_frame_reg <= 1'b0;
|
||||
m_empty_pipe_reg <= 1'b0;
|
||||
m_terminate_frame_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Read-side status
|
||||
always_ff @(posedge m_clk) begin
|
||||
wr_ptr_conv_reg <= gray2bin(wr_ptr_gray_sync2_reg);
|
||||
m_depth_reg <= wr_ptr_conv_reg - rd_ptr_reg;
|
||||
m_depth_commit_reg <= FRAME_FIFO ? wr_ptr_commit_sync_reg - rd_ptr_reg : wr_ptr_conv_reg - rd_ptr_reg;
|
||||
end
|
||||
|
||||
if (!OUTPUT_FIFO_EN) begin
|
||||
|
||||
assign pipe_ready = 1'b1;
|
||||
|
||||
assign m_axis_tready_pipe = m_axis_tready_out;
|
||||
assign m_axis_tvalid_out = m_axis_tvalid_pipe;
|
||||
|
||||
assign m_axis_tdata_out = m_axis_tdata_pipe;
|
||||
assign m_axis_tkeep_out = m_axis_tkeep_pipe;
|
||||
assign m_axis_tstrb_out = m_axis_tstrb_pipe;
|
||||
assign m_axis_tlast_out = m_axis_tlast_pipe;
|
||||
assign m_axis_tid_out = m_axis_tid_pipe;
|
||||
assign m_axis_tdest_out = m_axis_tdest_pipe;
|
||||
assign m_axis_tuser_out = m_axis_tuser_pipe;
|
||||
|
||||
end else begin : output_fifo
|
||||
|
||||
// output datapath logic
|
||||
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
logic m_axis_tvalid_reg = 1'b0;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = 0;
|
||||
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = 0;
|
||||
logic out_fifo_half_full_reg = 1'b0;
|
||||
|
||||
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}});
|
||||
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
||||
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic out_fifo_tlast[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [ID_W-1:0] out_fifo_tid[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW];
|
||||
|
||||
assign pipe_ready = !out_fifo_half_full_reg;
|
||||
|
||||
assign m_axis_tready_pipe = 1'b1;
|
||||
|
||||
assign m_axis_tdata_out = m_axis_tdata_reg;
|
||||
assign m_axis_tkeep_out = KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis_tstrb_out = STRB_EN ? m_axis_tkeep_reg : m_axis_tkeep_out;
|
||||
assign m_axis_tvalid_out = m_axis_tvalid_reg;
|
||||
assign m_axis_tlast_out = LAST_EN ? m_axis_tlast_reg : 1'b1;
|
||||
assign m_axis_tid_out = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis_tdest_out = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis_tuser_out = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
always_ff @(posedge m_clk) begin
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out;
|
||||
|
||||
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_AW-1);
|
||||
|
||||
if (!out_fifo_full && m_axis_tvalid_pipe) begin
|
||||
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdata_pipe;
|
||||
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tkeep_pipe;
|
||||
out_fifo_tstrb[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tstrb_pipe;
|
||||
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tlast_pipe;
|
||||
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tid_pipe;
|
||||
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdest_pipe;
|
||||
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tuser_pipe;
|
||||
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
||||
end
|
||||
|
||||
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin
|
||||
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tstrb_reg <= out_fifo_tstrb[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tvalid_reg <= 1'b1;
|
||||
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
||||
end
|
||||
|
||||
if (m_rst) begin
|
||||
out_fifo_wr_ptr_reg <= 0;
|
||||
out_fifo_rd_ptr_reg <= 0;
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
if (PAUSE_EN) begin : pause
|
||||
|
||||
// Pause logic
|
||||
logic pause_reg = 1'b0;
|
||||
logic pause_frame_reg = 1'b0;
|
||||
|
||||
wire s_pause_req_sync;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(1),
|
||||
.N(2)
|
||||
)
|
||||
pause_req_sync_inst (
|
||||
.clk(m_clk),
|
||||
.in(s_pause_req),
|
||||
.out(s_pause_req_sync)
|
||||
);
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(1),
|
||||
.N(2)
|
||||
)
|
||||
pause_ack_sync_inst (
|
||||
.clk(s_clk),
|
||||
.in(pause_reg),
|
||||
.out(s_pause_ack)
|
||||
);
|
||||
|
||||
assign m_axis_tready_out = m_axis.tready && !pause_reg;
|
||||
assign m_axis.tvalid = m_axis_tvalid_out && !pause_reg;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_out;
|
||||
assign m_axis.tkeep = m_axis_tkeep_out;
|
||||
assign m_axis.tstrb = m_axis_tstrb_out;
|
||||
assign m_axis.tlast = m_axis_tlast_out;
|
||||
assign m_axis.tid = m_axis_tid_out;
|
||||
assign m_axis.tdest = m_axis_tdest_out;
|
||||
assign m_axis.tuser = m_axis_tuser_out;
|
||||
|
||||
assign m_pause_ack = pause_reg;
|
||||
|
||||
always_ff @(posedge m_clk) begin
|
||||
if (FRAME_PAUSE) begin
|
||||
if (pause_reg) begin
|
||||
// paused; update pause status
|
||||
pause_reg <= m_pause_req || s_pause_req_sync;
|
||||
end else if (m_axis_tvalid_out) begin
|
||||
// frame transfer; set frame bit
|
||||
pause_frame_reg <= 1'b1;
|
||||
if (m_axis.tready && m_axis.tlast) begin
|
||||
// end of frame; clear frame bit and update pause status
|
||||
pause_frame_reg <= 1'b0;
|
||||
pause_reg <= m_pause_req || s_pause_req_sync;
|
||||
end
|
||||
end else if (!pause_frame_reg) begin
|
||||
// idle; update pause status
|
||||
pause_reg <= m_pause_req || s_pause_req_sync;
|
||||
end
|
||||
end else begin
|
||||
pause_reg <= m_pause_req || s_pause_req_sync;
|
||||
end
|
||||
|
||||
if (m_rst) begin
|
||||
pause_frame_reg <= 1'b0;
|
||||
pause_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
assign m_axis_tready_out = m_axis.tready;
|
||||
assign m_axis.tvalid = m_axis_tvalid_out;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_out;
|
||||
assign m_axis.tkeep = m_axis_tkeep_out;
|
||||
assign m_axis.tstrb = m_axis_tstrb_out;
|
||||
assign m_axis.tlast = m_axis_tlast_out;
|
||||
assign m_axis.tid = m_axis_tid_out;
|
||||
assign m_axis.tdest = m_axis_tdest_out;
|
||||
assign m_axis.tuser = m_axis_tuser_out;
|
||||
|
||||
assign s_pause_ack = 1'b0;
|
||||
assign m_pause_ack = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
3
src/axis/rtl/taxi_axis_async_fifo_adapter.f
Normal file
3
src/axis/rtl/taxi_axis_async_fifo_adapter.f
Normal file
@@ -0,0 +1,3 @@
|
||||
taxi_axis_async_fifo_adapter.sv
|
||||
taxi_axis_async_fifo.f
|
||||
taxi_axis_adapter.sv
|
||||
244
src/axis/rtl/taxi_axis_async_fifo_adapter.sv
Normal file
244
src/axis/rtl/taxi_axis_async_fifo_adapter.sv
Normal file
@@ -0,0 +1,244 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2019-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream asynchronous FIFO with width converter
|
||||
*/
|
||||
module taxi_axis_async_fifo_adapter #
|
||||
(
|
||||
// FIFO depth in words
|
||||
// KEEP_W words per cycle if KEEP_EN set
|
||||
// Rounded up to nearest power of 2 cycles
|
||||
parameter DEPTH = 4096,
|
||||
// number of RAM pipeline registers in FIFO
|
||||
parameter RAM_PIPELINE = 1,
|
||||
// use output FIFO
|
||||
// When set, the RAM read enable and pipeline clock enables are removed
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
// Frame FIFO mode - operate on frames instead of cycles
|
||||
// When set, m_axis_tvalid will not be deasserted within a frame
|
||||
// Requires LAST_EN set
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
// tuser value for bad frame marker
|
||||
parameter USER_BAD_FRAME_VALUE = 1'b1,
|
||||
// tuser mask for bad frame marker
|
||||
parameter USER_BAD_FRAME_MASK = 1'b1,
|
||||
// Drop frames larger than FIFO
|
||||
// Requires FRAME_FIFO set
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
// Drop frames marked bad
|
||||
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
// Drop incoming frames when full
|
||||
// When set, s_axis_tready is always asserted
|
||||
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
// Mark incoming frames as bad frames when full
|
||||
// When set, s_axis_tready is always asserted
|
||||
// Requires FRAME_FIFO to be clear
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
// Enable pause request input
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
// Pause between frames
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
)
|
||||
(
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
input wire logic s_clk,
|
||||
input wire logic s_rst,
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
input wire logic m_clk,
|
||||
input wire logic m_rst,
|
||||
taxi_axis_if.src m_axis,
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
input wire logic s_pause_req = 1'b0,
|
||||
output wire logic s_pause_ack,
|
||||
input wire logic m_pause_req = 1'b0,
|
||||
output wire logic m_pause_ack,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic [$clog2(DEPTH):0] s_status_depth,
|
||||
output wire logic [$clog2(DEPTH):0] s_status_depth_commit,
|
||||
output wire logic s_status_overflow,
|
||||
output wire logic s_status_bad_frame,
|
||||
output wire logic s_status_good_frame,
|
||||
output wire logic [$clog2(DEPTH):0] m_status_depth,
|
||||
output wire logic [$clog2(DEPTH):0] m_status_depth_commit,
|
||||
output wire logic m_status_overflow,
|
||||
output wire logic m_status_bad_frame,
|
||||
output wire logic m_status_good_frame
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam S_DATA_W = s_axis.DATA_W;
|
||||
localparam logic S_KEEP_EN = s_axis.KEEP_EN;
|
||||
localparam S_KEEP_W = s_axis.KEEP_W;
|
||||
localparam logic S_STRB_EN = s_axis.STRB_EN;
|
||||
|
||||
localparam M_DATA_W = m_axis.DATA_W;
|
||||
localparam logic M_KEEP_EN = m_axis.KEEP_EN;
|
||||
localparam M_KEEP_W = m_axis.KEEP_W;
|
||||
localparam logic M_STRB_EN = m_axis.STRB_EN;
|
||||
|
||||
// force keep width to 1 when disabled
|
||||
localparam S_BYTE_LANES = S_KEEP_EN ? S_KEEP_W : 1;
|
||||
localparam M_BYTE_LANES = M_KEEP_EN ? M_KEEP_W : 1;
|
||||
|
||||
// bus byte sizes (must be identical)
|
||||
localparam S_BYTE_SIZE = S_DATA_W / S_BYTE_LANES;
|
||||
localparam M_BYTE_SIZE = M_DATA_W / M_BYTE_LANES;
|
||||
// output bus is wider
|
||||
localparam EXPAND_BUS = M_BYTE_LANES > S_BYTE_LANES;
|
||||
// total data and keep widths
|
||||
localparam DATA_W = EXPAND_BUS ? M_DATA_W : S_DATA_W;
|
||||
localparam KEEP_W = EXPAND_BUS ? M_BYTE_LANES : S_BYTE_LANES;
|
||||
localparam KEEP_EN = EXPAND_BUS ? M_KEEP_EN : S_KEEP_EN;
|
||||
localparam STRB_EN = M_STRB_EN && S_STRB_EN;
|
||||
|
||||
// check configuration
|
||||
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_W)
|
||||
$fatal(0, "Error: input data width not evenly divisible (instance %m)");
|
||||
|
||||
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_W)
|
||||
$fatal(0, "Error: output data width not evenly divisible (instance %m)");
|
||||
|
||||
if (S_BYTE_SIZE != M_BYTE_SIZE)
|
||||
$fatal(0, "Error: byte size mismatch (instance %m)");
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(s_axis.STRB_EN),
|
||||
.LAST_EN(s_axis.LAST_EN),
|
||||
.ID_EN(s_axis.ID_EN),
|
||||
.ID_W(s_axis.ID_W),
|
||||
.DEST_EN(s_axis.DEST_EN),
|
||||
.DEST_W(s_axis.DEST_W),
|
||||
.USER_EN(s_axis.USER_EN),
|
||||
.USER_W(s_axis.USER_W)
|
||||
) axis_pre_fifo();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(m_axis.STRB_EN),
|
||||
.LAST_EN(m_axis.LAST_EN),
|
||||
.ID_EN(m_axis.ID_EN),
|
||||
.ID_W(m_axis.ID_W),
|
||||
.DEST_EN(m_axis.DEST_EN),
|
||||
.DEST_W(m_axis.DEST_W),
|
||||
.USER_EN(m_axis.USER_EN),
|
||||
.USER_W(m_axis.USER_W)
|
||||
) axis_post_fifo();
|
||||
|
||||
taxi_axis_adapter
|
||||
pre_fifo_adapter_inst (
|
||||
.clk(s_clk),
|
||||
.rst(s_rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(axis_pre_fifo)
|
||||
);
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
fifo_inst (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(s_clk),
|
||||
.s_rst(s_rst),
|
||||
.s_axis(axis_pre_fifo),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(m_clk),
|
||||
.m_rst(m_rst),
|
||||
.m_axis(axis_post_fifo),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(s_pause_req),
|
||||
.s_pause_ack(s_pause_ack),
|
||||
.m_pause_req(m_pause_req),
|
||||
.m_pause_ack(m_pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(s_status_depth),
|
||||
.s_status_depth_commit(s_status_depth_commit),
|
||||
.s_status_overflow(s_status_overflow),
|
||||
.s_status_bad_frame(s_status_bad_frame),
|
||||
.s_status_good_frame(s_status_good_frame),
|
||||
.m_status_depth(m_status_depth),
|
||||
.m_status_depth_commit(m_status_depth_commit),
|
||||
.m_status_overflow(m_status_overflow),
|
||||
.m_status_bad_frame(m_status_bad_frame),
|
||||
.m_status_good_frame(m_status_good_frame)
|
||||
);
|
||||
|
||||
taxi_axis_adapter
|
||||
post_fifo_adapter_inst (
|
||||
.clk(m_clk),
|
||||
.rst(m_rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(axis_post_fifo),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
179
src/axis/rtl/taxi_axis_broadcast.sv
Normal file
179
src/axis/rtl/taxi_axis_broadcast.sv
Normal file
@@ -0,0 +1,179 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2019-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream broadcaster
|
||||
*/
|
||||
module taxi_axis_broadcast #
|
||||
(
|
||||
// Number of AXI stream outputs
|
||||
parameter M_COUNT = 4
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream outputs (sources)
|
||||
*/
|
||||
taxi_axis_if.src m_axis[M_COUNT]
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axis.DATA_W;
|
||||
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis[0].KEEP_EN;
|
||||
localparam KEEP_W = s_axis.KEEP_W;
|
||||
localparam logic STRB_EN = s_axis.STRB_EN && m_axis[0].STRB_EN;
|
||||
localparam logic LAST_EN = s_axis.LAST_EN && m_axis[0].LAST_EN;
|
||||
localparam logic ID_EN = s_axis.ID_EN && m_axis[0].ID_EN;
|
||||
localparam ID_W = s_axis.ID_W;
|
||||
localparam logic DEST_EN = s_axis.DEST_EN && m_axis[0].DEST_EN;
|
||||
localparam DEST_W = s_axis.DEST_W;
|
||||
localparam logic USER_EN = s_axis.USER_EN && m_axis[0].USER_EN;
|
||||
localparam USER_W = s_axis.USER_W;
|
||||
|
||||
// check configuration
|
||||
if (m_axis[0].DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (KEEP_EN && m_axis[0].KEEP_W != KEEP_W)
|
||||
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
|
||||
|
||||
// datapath registers
|
||||
logic s_axis_tready_reg = 1'b0, s_axis_tready_next;
|
||||
|
||||
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
logic [M_COUNT-1:0] m_axis_tvalid_reg = '0, m_axis_tvalid_next;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
|
||||
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
|
||||
logic temp_m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
|
||||
|
||||
// // datapath control
|
||||
logic store_axis_input_to_output;
|
||||
logic store_axis_input_to_temp;
|
||||
logic store_axis_temp_to_output;
|
||||
|
||||
assign s_axis.tready = s_axis_tready_reg;
|
||||
|
||||
wire [M_COUNT-1:0] m_axis_tready;
|
||||
wire [M_COUNT-1:0] m_axis_tvalid;
|
||||
|
||||
for (genvar n = 0; n < M_COUNT; n = n + 1) begin
|
||||
|
||||
assign m_axis[n].tdata = m_axis_tdata_reg;
|
||||
assign m_axis[n].tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis[n].tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis[n].tkeep;
|
||||
assign m_axis[n].tvalid = m_axis_tvalid_reg[n];
|
||||
assign m_axis[n].tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
|
||||
assign m_axis[n].tid = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis[n].tdest = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis[n].tuser = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
assign m_axis_tready[n] = m_axis[n].tready;
|
||||
assign m_axis_tvalid[n] = m_axis[n].tvalid;
|
||||
|
||||
end
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (m_axis_tvalid == 0 || !s_axis.tvalid));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready;
|
||||
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
|
||||
store_axis_input_to_output = 1'b0;
|
||||
store_axis_input_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axis_tready_reg) begin
|
||||
// input is ready
|
||||
if (((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || m_axis_tvalid == 0) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axis_tvalid_next = {M_COUNT{s_axis.tvalid}};
|
||||
store_axis_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axis_tvalid_next = s_axis.tvalid;
|
||||
store_axis_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axis_tvalid_next = {M_COUNT{temp_m_axis_tvalid_reg}};
|
||||
temp_m_axis_tvalid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
s_axis_tready_reg <= s_axis_tready_early;
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
||||
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axis_input_to_output) begin
|
||||
m_axis_tdata_reg <= s_axis.tdata;
|
||||
m_axis_tkeep_reg <= s_axis.tkeep;
|
||||
m_axis_tstrb_reg <= s_axis.tstrb;
|
||||
m_axis_tlast_reg <= s_axis.tlast;
|
||||
m_axis_tid_reg <= s_axis.tid;
|
||||
m_axis_tdest_reg <= s_axis.tdest;
|
||||
m_axis_tuser_reg <= s_axis.tuser;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
|
||||
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
|
||||
m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
|
||||
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
|
||||
m_axis_tid_reg <= temp_m_axis_tid_reg;
|
||||
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
|
||||
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_input_to_temp) begin
|
||||
temp_m_axis_tdata_reg <= s_axis.tdata;
|
||||
temp_m_axis_tkeep_reg <= s_axis.tkeep;
|
||||
temp_m_axis_tstrb_reg <= s_axis.tstrb;
|
||||
temp_m_axis_tlast_reg <= s_axis.tlast;
|
||||
temp_m_axis_tid_reg <= s_axis.tid;
|
||||
temp_m_axis_tdest_reg <= s_axis.tdest;
|
||||
temp_m_axis_tuser_reg <= s_axis.tuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axis_tready_reg <= 1'b0;
|
||||
m_axis_tvalid_reg <= '0;
|
||||
temp_m_axis_tvalid_reg <= '0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
321
src/axis/rtl/taxi_axis_cobs_decode.sv
Normal file
321
src/axis/rtl/taxi_axis_cobs_decode.sv
Normal file
@@ -0,0 +1,321 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2016-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream consistent overhead byte stuffing (COBS) decoder
|
||||
*/
|
||||
module taxi_axis_cobs_decode
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis
|
||||
);
|
||||
|
||||
// check configuration
|
||||
if (m_axis.DATA_W != 8 || s_axis.DATA_W != 8)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
// state register
|
||||
localparam [1:0]
|
||||
STATE_IDLE = 2'd0,
|
||||
STATE_SEGMENT = 2'd1,
|
||||
STATE_NEXT_SEGMENT = 2'd2;
|
||||
|
||||
logic [1:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
logic [7:0] count_reg = 8'd0, count_next;
|
||||
logic suppress_zero_reg = 1'b0, suppress_zero_next;
|
||||
|
||||
logic [7:0] temp_tdata_reg = 8'd0, temp_tdata_next;
|
||||
logic temp_tvalid_reg = 1'b0, temp_tvalid_next;
|
||||
|
||||
// internal datapath
|
||||
logic [7:0] m_axis_tdata_int;
|
||||
logic m_axis_tvalid_int;
|
||||
logic m_axis_tready_int_reg = 1'b0;
|
||||
logic m_axis_tlast_int;
|
||||
logic m_axis_tuser_int;
|
||||
wire m_axis_tready_int_early;
|
||||
|
||||
logic s_axis_tready_reg = 1'b0, s_axis_tready_next;
|
||||
|
||||
assign s_axis.tready = s_axis_tready_reg;
|
||||
|
||||
always_comb begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
count_next = count_reg;
|
||||
suppress_zero_next = suppress_zero_reg;
|
||||
|
||||
temp_tdata_next = temp_tdata_reg;
|
||||
temp_tvalid_next = temp_tvalid_reg;
|
||||
|
||||
m_axis_tdata_int = 8'd0;
|
||||
m_axis_tvalid_int = 1'b0;
|
||||
m_axis_tlast_int = 1'b0;
|
||||
m_axis_tuser_int = 1'b0;
|
||||
|
||||
s_axis_tready_next = 1'b0;
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// idle state
|
||||
s_axis_tready_next = m_axis_tready_int_early || !temp_tvalid_reg;
|
||||
|
||||
// output final word
|
||||
m_axis_tdata_int = temp_tdata_reg;
|
||||
m_axis_tvalid_int = temp_tvalid_reg;
|
||||
m_axis_tlast_int = temp_tvalid_reg;
|
||||
temp_tvalid_next = temp_tvalid_reg && !m_axis_tready_int_reg;
|
||||
|
||||
if (s_axis.tready && s_axis.tvalid) begin
|
||||
// valid input data
|
||||
// skip any leading zeros
|
||||
if (s_axis.tdata != 8'd0) begin
|
||||
// store count value and zero suppress
|
||||
count_next = s_axis.tdata-1;
|
||||
suppress_zero_next = (s_axis.tdata == 8'd255);
|
||||
s_axis_tready_next = m_axis_tready_int_early;
|
||||
if (s_axis.tdata == 8'd1) begin
|
||||
// next byte will be count value
|
||||
state_next = STATE_NEXT_SEGMENT;
|
||||
end else begin
|
||||
// next byte will be data
|
||||
state_next = STATE_SEGMENT;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_SEGMENT: begin
|
||||
// receive segment
|
||||
s_axis_tready_next = m_axis_tready_int_early;
|
||||
|
||||
if (s_axis.tready && s_axis.tvalid) begin
|
||||
// valid input data
|
||||
// store in temp register
|
||||
temp_tdata_next = s_axis.tdata;
|
||||
temp_tvalid_next = 1'b1;
|
||||
// move temp to output
|
||||
m_axis_tdata_int = temp_tdata_reg;
|
||||
m_axis_tvalid_int = temp_tvalid_reg;
|
||||
// decrement count
|
||||
count_next = count_reg - 1;
|
||||
if (s_axis.tdata == 8'd0) begin
|
||||
// got a zero byte in a frame - mark it as an error and re-sync
|
||||
temp_tvalid_next = 1'b0;
|
||||
m_axis_tvalid_int = 1'b1;
|
||||
m_axis_tuser_int = 1'b1;
|
||||
m_axis_tlast_int = 1'b1;
|
||||
s_axis_tready_next = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end else if (s_axis.LAST_EN && s_axis.tlast) begin
|
||||
// end of frame
|
||||
if (count_reg == 8'd1 && (!s_axis.USER_EN || !s_axis.tuser)) begin
|
||||
// end of frame indication at correct time, go to idle to output final byte
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
|
||||
temp_tvalid_next = 1'b0;
|
||||
m_axis_tvalid_int = 1'b1;
|
||||
m_axis_tuser_int = 1'b1;
|
||||
m_axis_tlast_int = 1'b1;
|
||||
s_axis_tready_next = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else if (count_reg == 8'd1) begin
|
||||
// next byte will be count value
|
||||
state_next = STATE_NEXT_SEGMENT;
|
||||
end else begin
|
||||
// next byte will be data
|
||||
state_next = STATE_SEGMENT;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_SEGMENT;
|
||||
end
|
||||
end
|
||||
STATE_NEXT_SEGMENT: begin
|
||||
// next segment
|
||||
s_axis_tready_next = m_axis_tready_int_early;
|
||||
|
||||
if (s_axis.tready && s_axis.tvalid) begin
|
||||
// valid input data
|
||||
// store zero in temp if not suppressed
|
||||
temp_tdata_next = 8'd0;
|
||||
temp_tvalid_next = !suppress_zero_reg;
|
||||
// move temp to output
|
||||
m_axis_tdata_int = temp_tdata_reg;
|
||||
m_axis_tvalid_int = temp_tvalid_reg;
|
||||
if (s_axis.tdata == 8'd0) begin
|
||||
// got a zero byte delineating the end of the frame, so mark as such and re-sync
|
||||
temp_tvalid_next = 1'b0;
|
||||
m_axis_tuser_int = s_axis.tuser;
|
||||
m_axis_tlast_int = 1'b1;
|
||||
s_axis_tready_next = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end else if (s_axis.LAST_EN && s_axis.tlast) begin
|
||||
if (s_axis.tdata == 8'd1 && (!s_axis.USER_EN || !s_axis.tuser)) begin
|
||||
// end of frame indication at correct time, go to idle to output final byte
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
|
||||
temp_tvalid_next = 1'b0;
|
||||
m_axis_tvalid_int = 1'b1;
|
||||
m_axis_tuser_int = 1'b1;
|
||||
m_axis_tlast_int = 1'b1;
|
||||
s_axis_tready_next = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
// otherwise, store count value and zero suppress
|
||||
count_next = s_axis.tdata-1;
|
||||
suppress_zero_next = (s_axis.tdata == 8'd255);
|
||||
s_axis_tready_next = m_axis_tready_int_early;
|
||||
if (s_axis.tdata == 8'd1) begin
|
||||
// next byte will be count value
|
||||
state_next = STATE_NEXT_SEGMENT;
|
||||
end else begin
|
||||
// next byte will be data
|
||||
state_next = STATE_SEGMENT;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_NEXT_SEGMENT;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
// invalid state
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
count_reg <= count_next;
|
||||
suppress_zero_reg <= suppress_zero_next;
|
||||
|
||||
temp_tdata_reg <= temp_tdata_next;
|
||||
temp_tvalid_reg <= temp_tvalid_next;
|
||||
|
||||
s_axis_tready_reg <= s_axis_tready_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
temp_tvalid_reg <= 1'b0;
|
||||
s_axis_tready_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
logic [7:0] m_axis_tdata_reg = 8'd0;
|
||||
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic m_axis_tuser_reg = 1'b0;
|
||||
|
||||
logic [7:0] temp_m_axis_tdata_reg = 8'd0;
|
||||
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
|
||||
logic temp_m_axis_tlast_reg = 1'b0;
|
||||
logic temp_m_axis_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
logic store_axis_int_to_output;
|
||||
logic store_axis_int_to_temp;
|
||||
logic store_axis_temp_to_output;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_reg;
|
||||
assign m_axis.tkeep = 1'b1;
|
||||
assign m_axis.tstrb = m_axis.tkeep;
|
||||
assign m_axis.tvalid = m_axis_tvalid_reg;
|
||||
assign m_axis.tlast = m_axis_tlast_reg;
|
||||
assign m_axis.tid = '0;
|
||||
assign m_axis.tdest = '0;
|
||||
assign m_axis.tuser = m_axis_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axis_tvalid_next = m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
|
||||
store_axis_int_to_output = 1'b0;
|
||||
store_axis_int_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (m_axis.tready || !m_axis_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axis_tvalid_next = m_axis_tvalid_int;
|
||||
store_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axis_tvalid_next = m_axis_tvalid_int;
|
||||
store_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axis.tready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
||||
m_axis_tready_int_reg <= m_axis_tready_int_early;
|
||||
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axis_int_to_output) begin
|
||||
m_axis_tdata_reg <= m_axis_tdata_int;
|
||||
m_axis_tlast_reg <= m_axis_tlast_int;
|
||||
m_axis_tuser_reg <= m_axis_tuser_int;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
|
||||
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
|
||||
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_int_to_temp) begin
|
||||
temp_m_axis_tdata_reg <= m_axis_tdata_int;
|
||||
temp_m_axis_tlast_reg <= m_axis_tlast_int;
|
||||
temp_m_axis_tuser_reg <= m_axis_tuser_int;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
m_axis_tready_int_reg <= 1'b0;
|
||||
temp_m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
3
src/axis/rtl/taxi_axis_cobs_encode.f
Normal file
3
src/axis/rtl/taxi_axis_cobs_encode.f
Normal file
@@ -0,0 +1,3 @@
|
||||
taxi_axis_cobs_encode.sv
|
||||
taxi_axis_fifo.sv
|
||||
taxi_axis_if.sv
|
||||
469
src/axis/rtl/taxi_axis_cobs_encode.sv
Normal file
469
src/axis/rtl/taxi_axis_cobs_encode.sv
Normal file
@@ -0,0 +1,469 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2016-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream consistent overhead byte stuffing (COBS) encoder
|
||||
*/
|
||||
module taxi_axis_cobs_encode #
|
||||
(
|
||||
// append zero for in band framing
|
||||
parameter logic APPEND_ZERO = 1'b1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis
|
||||
);
|
||||
|
||||
// check configuration
|
||||
if (m_axis.DATA_W != 8 || s_axis.DATA_W != 8)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
// state register
|
||||
localparam [1:0]
|
||||
INPUT_STATE_IDLE = 2'd0,
|
||||
INPUT_STATE_SEGMENT = 2'd1,
|
||||
INPUT_STATE_FINAL_ZERO = 2'd2,
|
||||
INPUT_STATE_APPEND_ZERO = 2'd3;
|
||||
|
||||
logic [1:0] input_state_reg = INPUT_STATE_IDLE, input_state_next;
|
||||
|
||||
localparam [0:0]
|
||||
OUTPUT_STATE_IDLE = 1'd0,
|
||||
OUTPUT_STATE_SEGMENT = 1'd1;
|
||||
|
||||
logic [0:0] output_state_reg = OUTPUT_STATE_IDLE, output_state_next;
|
||||
|
||||
logic [7:0] input_count_reg = 8'd0, input_count_next;
|
||||
logic [7:0] output_count_reg = 8'd0, output_count_next;
|
||||
logic fail_frame_reg = 1'b0, fail_frame_next;
|
||||
|
||||
// internal datapath
|
||||
logic [7:0] m_axis_tdata_int;
|
||||
logic m_axis_tvalid_int;
|
||||
logic m_axis_tready_int_reg = 1'b0;
|
||||
logic m_axis_tlast_int;
|
||||
logic m_axis_tuser_int;
|
||||
wire m_axis_tready_int_early;
|
||||
|
||||
logic s_axis_tready_mask;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) code_fifo_in(), code_fifo_out();
|
||||
taxi_axis_if #(.DATA_W(8)) data_fifo_in(), data_fifo_out();
|
||||
|
||||
assign s_axis.tready = code_fifo_in.tready && data_fifo_in.tready && s_axis_tready_mask;
|
||||
|
||||
taxi_axis_fifo #(
|
||||
.DEPTH(256),
|
||||
.FRAME_FIFO(0)
|
||||
)
|
||||
code_fifo_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(code_fifo_in),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(code_fifo_out),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.pause_req(),
|
||||
.pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_depth(),
|
||||
.status_depth_commit(),
|
||||
.status_overflow(),
|
||||
.status_bad_frame(),
|
||||
.status_good_frame()
|
||||
);
|
||||
|
||||
taxi_axis_fifo #(
|
||||
.DEPTH(256),
|
||||
.FRAME_FIFO(0)
|
||||
)
|
||||
data_fifo_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(data_fifo_in),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(data_fifo_out),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.pause_req(),
|
||||
.pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_depth(),
|
||||
.status_depth_commit(),
|
||||
.status_overflow(),
|
||||
.status_bad_frame(),
|
||||
.status_good_frame()
|
||||
);
|
||||
|
||||
always @* begin
|
||||
input_state_next = INPUT_STATE_IDLE;
|
||||
|
||||
input_count_next = input_count_reg;
|
||||
|
||||
fail_frame_next = fail_frame_reg;
|
||||
|
||||
s_axis_tready_mask = 1'b0;
|
||||
|
||||
code_fifo_in.tdata = 8'd0;
|
||||
code_fifo_in.tvalid = 1'b0;
|
||||
code_fifo_in.tlast = 1'b0;
|
||||
code_fifo_in.tuser = 1'b0;
|
||||
|
||||
data_fifo_in.tdata = s_axis.tdata;
|
||||
data_fifo_in.tvalid = 1'b0;
|
||||
data_fifo_in.tlast = 1'b0;
|
||||
data_fifo_in.tuser = 1'b0;
|
||||
|
||||
case (input_state_reg)
|
||||
INPUT_STATE_IDLE: begin
|
||||
// idle state
|
||||
s_axis_tready_mask = 1'b1;
|
||||
fail_frame_next = 1'b0;
|
||||
|
||||
if (s_axis.tready && s_axis.tvalid) begin
|
||||
// valid input data
|
||||
|
||||
if (s_axis.tdata == 8'd0 || (s_axis.tlast && s_axis.tuser)) begin
|
||||
// got a zero or propagated error, so store a zero code
|
||||
code_fifo_in.tdata = 8'd1;
|
||||
code_fifo_in.tvalid = 1'b1;
|
||||
if (s_axis.tlast) begin
|
||||
// last byte, so close out the frame
|
||||
fail_frame_next = s_axis.tuser;
|
||||
input_state_next = INPUT_STATE_FINAL_ZERO;
|
||||
end else begin
|
||||
// return to idle to await next segment
|
||||
input_state_next = INPUT_STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
// got something other than a zero, so store it and init the segment counter
|
||||
input_count_next = 8'd2;
|
||||
data_fifo_in.tdata = s_axis.tdata;
|
||||
data_fifo_in.tvalid = 1'b1;
|
||||
if (s_axis.tlast) begin
|
||||
// last byte, so store the code and close out the frame
|
||||
code_fifo_in.tdata = 8'd2;
|
||||
code_fifo_in.tvalid = 1'b1;
|
||||
if (APPEND_ZERO) begin
|
||||
// zero frame mode, need to add a zero code to end the frame
|
||||
input_state_next = INPUT_STATE_APPEND_ZERO;
|
||||
end else begin
|
||||
// normal frame mode, close out the frame
|
||||
data_fifo_in.tlast = 1'b1;
|
||||
input_state_next = INPUT_STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
// await more segment data
|
||||
input_state_next = INPUT_STATE_SEGMENT;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
input_state_next = INPUT_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
INPUT_STATE_SEGMENT: begin
|
||||
// encode segment
|
||||
s_axis_tready_mask = 1'b1;
|
||||
fail_frame_next = 1'b0;
|
||||
|
||||
if (s_axis.tready && s_axis.tvalid) begin
|
||||
// valid input data
|
||||
|
||||
if (s_axis.tdata == 8'd0 || (s_axis.tlast && s_axis.tuser)) begin
|
||||
// got a zero or propagated error, so store the code
|
||||
code_fifo_in.tdata = input_count_reg;
|
||||
code_fifo_in.tvalid = 1'b1;
|
||||
if (s_axis.tlast) begin
|
||||
// last byte, so close out the frame
|
||||
fail_frame_next = s_axis.tuser;
|
||||
input_state_next = INPUT_STATE_FINAL_ZERO;
|
||||
end else begin
|
||||
// return to idle to await next segment
|
||||
input_state_next = INPUT_STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
// got something other than a zero, so store it and increment the segment counter
|
||||
input_count_next = input_count_reg+1;
|
||||
data_fifo_in.tdata = s_axis.tdata;
|
||||
data_fifo_in.tvalid = 1'b1;
|
||||
if (input_count_reg == 8'd254) begin
|
||||
// 254 bytes in frame, so dump and reset counter
|
||||
code_fifo_in.tdata = input_count_reg+1;
|
||||
code_fifo_in.tvalid = 1'b1;
|
||||
input_count_next = 8'd1;
|
||||
end
|
||||
if (s_axis.tlast) begin
|
||||
// last byte, so store the code and close out the frame
|
||||
code_fifo_in.tdata = input_count_reg+1;
|
||||
code_fifo_in.tvalid = 1'b1;
|
||||
if (APPEND_ZERO) begin
|
||||
// zero frame mode, need to add a zero code to end the frame
|
||||
input_state_next = INPUT_STATE_APPEND_ZERO;
|
||||
end else begin
|
||||
// normal frame mode, close out the frame
|
||||
data_fifo_in.tlast = 1'b1;
|
||||
input_state_next = INPUT_STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
// await more segment data
|
||||
input_state_next = INPUT_STATE_SEGMENT;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
input_state_next = INPUT_STATE_SEGMENT;
|
||||
end
|
||||
end
|
||||
INPUT_STATE_FINAL_ZERO: begin
|
||||
// final zero code required
|
||||
s_axis_tready_mask = 1'b0;
|
||||
|
||||
if (code_fifo_in.tready) begin
|
||||
// push a zero code and close out frame
|
||||
if (fail_frame_reg) begin
|
||||
code_fifo_in.tdata = 8'd2;
|
||||
code_fifo_in.tuser = 1'b1;
|
||||
end else begin
|
||||
code_fifo_in.tdata = 8'd1;
|
||||
end
|
||||
code_fifo_in.tvalid = 1'b1;
|
||||
if (APPEND_ZERO) begin
|
||||
// zero frame mode, need to add a zero code to end the frame
|
||||
input_state_next = INPUT_STATE_APPEND_ZERO;
|
||||
end else begin
|
||||
// normal frame mode, close out the frame
|
||||
code_fifo_in.tlast = 1'b1;
|
||||
fail_frame_next = 1'b0;
|
||||
input_state_next = INPUT_STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
input_state_next = INPUT_STATE_FINAL_ZERO;
|
||||
end
|
||||
end
|
||||
INPUT_STATE_APPEND_ZERO: begin
|
||||
// append zero for zero framing
|
||||
s_axis_tready_mask = 1'b0;
|
||||
|
||||
if (code_fifo_in.tready) begin
|
||||
// push frame termination code and close out frame
|
||||
code_fifo_in.tdata = 8'd0;
|
||||
code_fifo_in.tlast = 1'b1;
|
||||
code_fifo_in.tuser = fail_frame_reg;
|
||||
code_fifo_in.tvalid = 1'b1;
|
||||
fail_frame_next = 1'b0;
|
||||
input_state_next = INPUT_STATE_IDLE;
|
||||
end else begin
|
||||
input_state_next = INPUT_STATE_APPEND_ZERO;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
output_state_next = OUTPUT_STATE_IDLE;
|
||||
|
||||
output_count_next = output_count_reg;
|
||||
|
||||
m_axis_tdata_int = 8'd0;
|
||||
m_axis_tvalid_int = 1'b0;
|
||||
m_axis_tlast_int = 1'b0;
|
||||
m_axis_tuser_int = 1'b0;
|
||||
|
||||
code_fifo_out.tready = 1'b0;
|
||||
|
||||
data_fifo_out.tready = 1'b0;
|
||||
|
||||
case (output_state_reg)
|
||||
OUTPUT_STATE_IDLE: begin
|
||||
// idle state
|
||||
|
||||
if (m_axis_tready_int_reg && code_fifo_out.tvalid) begin
|
||||
// transfer out code byte and load counter
|
||||
m_axis_tdata_int = code_fifo_out.tdata;
|
||||
m_axis_tlast_int = code_fifo_out.tlast;
|
||||
m_axis_tuser_int = code_fifo_out.tuser && code_fifo_out.tlast;
|
||||
output_count_next = code_fifo_out.tdata-1;
|
||||
m_axis_tvalid_int = 1'b1;
|
||||
code_fifo_out.tready = 1'b1;
|
||||
if (code_fifo_out.tdata == 8'd0 || code_fifo_out.tdata == 8'd1 || code_fifo_out.tuser) begin
|
||||
// frame termination and zero codes will be followed by codes
|
||||
output_state_next = OUTPUT_STATE_IDLE;
|
||||
end else begin
|
||||
// transfer out data
|
||||
output_state_next = OUTPUT_STATE_SEGMENT;
|
||||
end
|
||||
end else begin
|
||||
output_state_next = OUTPUT_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
OUTPUT_STATE_SEGMENT: begin
|
||||
// segment output
|
||||
|
||||
if (m_axis_tready_int_reg && data_fifo_out.tvalid) begin
|
||||
// transfer out data byte and decrement counter
|
||||
m_axis_tdata_int = data_fifo_out.tdata;
|
||||
m_axis_tlast_int = data_fifo_out.tlast;
|
||||
output_count_next = output_count_reg - 1;
|
||||
m_axis_tvalid_int = 1'b1;
|
||||
data_fifo_out.tready = 1'b1;
|
||||
if (output_count_reg == 1) begin
|
||||
// done with segment, get a code byte next
|
||||
output_state_next = OUTPUT_STATE_IDLE;
|
||||
end else begin
|
||||
// more data to transfer
|
||||
output_state_next = OUTPUT_STATE_SEGMENT;
|
||||
end
|
||||
end else begin
|
||||
output_state_next = OUTPUT_STATE_SEGMENT;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
input_state_reg <= input_state_next;
|
||||
output_state_reg <= output_state_next;
|
||||
|
||||
input_count_reg <= input_count_next;
|
||||
output_count_reg <= output_count_next;
|
||||
fail_frame_reg <= fail_frame_next;
|
||||
|
||||
if (rst) begin
|
||||
input_state_reg <= INPUT_STATE_IDLE;
|
||||
output_state_reg <= OUTPUT_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [7:0] m_axis_tdata_reg = 8'd0;
|
||||
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
|
||||
reg m_axis_tlast_reg = 1'b0;
|
||||
reg m_axis_tuser_reg = 1'b0;
|
||||
|
||||
reg [7:0] temp_m_axis_tdata_reg = 8'd0;
|
||||
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
|
||||
reg temp_m_axis_tlast_reg = 1'b0;
|
||||
reg temp_m_axis_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_axis_int_to_output;
|
||||
reg store_axis_int_to_temp;
|
||||
reg store_axis_temp_to_output;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_reg;
|
||||
assign m_axis.tkeep = 1'b1;
|
||||
assign m_axis.tstrb = m_axis.tkeep;
|
||||
assign m_axis.tvalid = m_axis_tvalid_reg;
|
||||
assign m_axis.tlast = m_axis_tlast_reg;
|
||||
assign m_axis.tid = '0;
|
||||
assign m_axis.tdest = '0;
|
||||
assign m_axis.tuser = m_axis_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
m_axis_tvalid_next = m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
|
||||
store_axis_int_to_output = 1'b0;
|
||||
store_axis_int_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (m_axis.tready || !m_axis_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axis_tvalid_next = m_axis_tvalid_int;
|
||||
store_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axis_tvalid_next = m_axis_tvalid_int;
|
||||
store_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axis.tready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
||||
m_axis_tready_int_reg <= m_axis_tready_int_early;
|
||||
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axis_int_to_output) begin
|
||||
m_axis_tdata_reg <= m_axis_tdata_int;
|
||||
m_axis_tlast_reg <= m_axis_tlast_int;
|
||||
m_axis_tuser_reg <= m_axis_tuser_int;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
|
||||
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
|
||||
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_int_to_temp) begin
|
||||
temp_m_axis_tdata_reg <= m_axis_tdata_int;
|
||||
temp_m_axis_tlast_reg <= m_axis_tlast_int;
|
||||
temp_m_axis_tuser_reg <= m_axis_tuser_int;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
m_axis_tready_int_reg <= 1'b0;
|
||||
temp_m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
560
src/axis/rtl/taxi_axis_fifo.sv
Normal file
560
src/axis/rtl/taxi_axis_fifo.sv
Normal file
@@ -0,0 +1,560 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2013-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream FIFO
|
||||
*/
|
||||
module taxi_axis_fifo #
|
||||
(
|
||||
// FIFO depth in words
|
||||
// KEEP_W words per cycle if KEEP_EN set
|
||||
// Rounded up to nearest power of 2 cycles
|
||||
parameter DEPTH = 4096,
|
||||
// number of RAM pipeline registers
|
||||
parameter RAM_PIPELINE = 1,
|
||||
// use output FIFO
|
||||
// When set, the RAM read enable and pipeline clock enables are removed
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
// Frame FIFO mode - operate on frames instead of cycles
|
||||
// When set, m_axis_tvalid will not be deasserted within a frame
|
||||
// Requires LAST_EN set
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
// tuser value for bad frame marker
|
||||
parameter USER_BAD_FRAME_VALUE = 1'b1,
|
||||
// tuser mask for bad frame marker
|
||||
parameter USER_BAD_FRAME_MASK = 1'b1,
|
||||
// Drop frames larger than FIFO
|
||||
// Requires FRAME_FIFO set
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
// Drop frames marked bad
|
||||
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
// Drop incoming frames when full
|
||||
// When set, s_axis.tready is always asserted
|
||||
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
// Mark incoming frames as bad frames when full
|
||||
// When set, s_axis.tready is always asserted
|
||||
// Requires FRAME_FIFO to be clear
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
// Enable pause request input
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
// Pause between frames
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis,
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
input wire logic pause_req = 1'b0,
|
||||
output wire logic pause_ack,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic [$clog2(DEPTH):0] status_depth,
|
||||
output wire logic [$clog2(DEPTH):0] status_depth_commit,
|
||||
output wire logic status_overflow,
|
||||
output wire logic status_bad_frame,
|
||||
output wire logic status_good_frame
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axis.DATA_W;
|
||||
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
|
||||
localparam KEEP_W = s_axis.KEEP_W;
|
||||
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
|
||||
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
|
||||
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
|
||||
localparam ID_W = s_axis.ID_W;
|
||||
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
|
||||
localparam DEST_W = s_axis.DEST_W;
|
||||
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
|
||||
localparam USER_W = s_axis.USER_W;
|
||||
|
||||
localparam CL_DEPTH = $clog2(DEPTH);
|
||||
localparam CL_KEEP_W = $clog2(KEEP_W);
|
||||
localparam FIFO_AW = (KEEP_EN && KEEP_W > 1) ? $clog2(DEPTH/KEEP_W) : CL_DEPTH;
|
||||
|
||||
localparam OUTPUT_FIFO_AW = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
|
||||
|
||||
// check configuration
|
||||
if (FRAME_FIFO && !LAST_EN)
|
||||
$fatal(0, "Error: FRAME_FIFO set requires LAST_EN set (instance %m)");
|
||||
|
||||
if (DROP_OVERSIZE_FRAME && !FRAME_FIFO)
|
||||
$fatal(0, "Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
|
||||
|
||||
if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
|
||||
$fatal(0, "Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
|
||||
|
||||
if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
|
||||
$fatal(0, "Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
|
||||
|
||||
if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_W'(USER_BAD_FRAME_MASK) & {USER_W{1'b1}}) == 0)
|
||||
$fatal(0, "Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
|
||||
|
||||
if (MARK_WHEN_FULL && FRAME_FIFO)
|
||||
$fatal(0, "Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)");
|
||||
|
||||
if (MARK_WHEN_FULL && !LAST_EN)
|
||||
$fatal(0, "Error: MARK_WHEN_FULL set requires LAST_EN set (instance %m)");
|
||||
|
||||
if (m_axis.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
|
||||
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
|
||||
|
||||
localparam KEEP_OFFSET = DATA_W;
|
||||
localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0);
|
||||
localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0);
|
||||
localparam ID_OFFSET = LAST_OFFSET + (LAST_EN ? 1 : 0);
|
||||
localparam DEST_OFFSET = ID_OFFSET + (ID_EN ? ID_W : 0);
|
||||
localparam USER_OFFSET = DEST_OFFSET + (DEST_EN ? DEST_W : 0);
|
||||
localparam WIDTH = USER_OFFSET + (USER_EN ? USER_W : 0);
|
||||
|
||||
logic [FIFO_AW:0] wr_ptr_reg = '0;
|
||||
logic [FIFO_AW:0] wr_ptr_commit_reg = '0;
|
||||
logic [FIFO_AW:0] rd_ptr_reg = '0;
|
||||
|
||||
(* ramstyle = "no_rw_check" *)
|
||||
logic [WIDTH-1:0] mem[2**FIFO_AW];
|
||||
|
||||
(* shreg_extract = "no" *)
|
||||
logic [WIDTH-1:0] mem_rd_data_pipe_reg[RAM_PIPELINE+1-1:0];
|
||||
logic [RAM_PIPELINE+1-1:0] mem_rd_valid_pipe_reg = '0;
|
||||
|
||||
// full when first MSB differs but the rest match
|
||||
wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {FIFO_AW{1'b0}}});
|
||||
// empty when pointers match exactly
|
||||
wire empty = wr_ptr_commit_reg == rd_ptr_reg;
|
||||
// overflow within packet, same as full but based on write commit
|
||||
wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {FIFO_AW{1'b0}}});
|
||||
|
||||
logic s_frame_reg = 1'b0;
|
||||
|
||||
logic drop_frame_reg = 1'b0;
|
||||
logic mark_frame_reg = 1'b0;
|
||||
logic send_frame_reg = 1'b0;
|
||||
logic [FIFO_AW:0] depth_reg = '0;
|
||||
logic [FIFO_AW:0] depth_commit_reg = '0;
|
||||
logic overflow_reg = 1'b0;
|
||||
logic bad_frame_reg = 1'b0;
|
||||
logic good_frame_reg = 1'b0;
|
||||
|
||||
assign s_axis.tready = FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL);
|
||||
|
||||
wire [WIDTH-1:0] mem_wr_data;
|
||||
|
||||
assign mem_wr_data[DATA_W-1:0] = s_axis.tdata;
|
||||
if (KEEP_EN) assign mem_wr_data[KEEP_OFFSET +: KEEP_W] = s_axis.tkeep;
|
||||
if (STRB_EN) assign mem_wr_data[STRB_OFFSET +: KEEP_W] = s_axis.tkeep;
|
||||
if (LAST_EN) assign mem_wr_data[LAST_OFFSET] = s_axis.tlast | mark_frame_reg;
|
||||
if (ID_EN) assign mem_wr_data[ID_OFFSET +: ID_W] = s_axis.tid;
|
||||
if (DEST_EN) assign mem_wr_data[DEST_OFFSET +: DEST_W] = s_axis.tdest;
|
||||
if (USER_EN) assign mem_wr_data[USER_OFFSET +: USER_W] = mark_frame_reg ? USER_W'(USER_BAD_FRAME_VALUE) : s_axis.tuser;
|
||||
|
||||
wire [WIDTH-1:0] mem_rd_data = mem_rd_data_pipe_reg[RAM_PIPELINE+1-1];
|
||||
|
||||
wire m_axis_tready_pipe;
|
||||
wire m_axis_tvalid_pipe = mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1];
|
||||
|
||||
wire [DATA_W-1:0] m_axis_tdata_pipe = mem_rd_data[DATA_W-1:0];
|
||||
wire [KEEP_W-1:0] m_axis_tkeep_pipe;
|
||||
wire [KEEP_W-1:0] m_axis_tstrb_pipe;
|
||||
wire m_axis_tlast_pipe;
|
||||
wire [ID_W-1:0] m_axis_tid_pipe;
|
||||
wire [DEST_W-1:0] m_axis_tdest_pipe;
|
||||
wire [USER_W-1:0] m_axis_tuser_pipe;
|
||||
|
||||
if (KEEP_EN) begin
|
||||
assign m_axis_tkeep_pipe = mem_rd_data[KEEP_OFFSET +: KEEP_W];
|
||||
end else begin
|
||||
assign m_axis_tkeep_pipe = '1;
|
||||
end
|
||||
|
||||
if (STRB_EN) begin
|
||||
assign m_axis_tstrb_pipe = mem_rd_data[STRB_OFFSET +: KEEP_W];
|
||||
end else begin
|
||||
assign m_axis_tstrb_pipe = m_axis_tkeep_pipe;
|
||||
end
|
||||
|
||||
if (LAST_EN) begin
|
||||
assign m_axis_tlast_pipe = mem_rd_data[LAST_OFFSET];
|
||||
end else begin
|
||||
assign m_axis_tlast_pipe = 1'b1;
|
||||
end
|
||||
|
||||
if (ID_EN) begin
|
||||
assign m_axis_tid_pipe = mem_rd_data[ID_OFFSET +: ID_W];
|
||||
end else begin
|
||||
assign m_axis_tid_pipe = '0;
|
||||
end
|
||||
|
||||
if (DEST_EN) begin
|
||||
assign m_axis_tdest_pipe = mem_rd_data[DEST_OFFSET +: DEST_W];
|
||||
end else begin
|
||||
assign m_axis_tdest_pipe = '0;
|
||||
end
|
||||
|
||||
if (USER_EN) begin
|
||||
assign m_axis_tuser_pipe = mem_rd_data[USER_OFFSET +: USER_W];
|
||||
end else begin
|
||||
assign m_axis_tuser_pipe = '0;
|
||||
end
|
||||
|
||||
wire m_axis_tready_out;
|
||||
wire m_axis_tvalid_out;
|
||||
|
||||
wire [DATA_W-1:0] m_axis_tdata_out;
|
||||
wire [KEEP_W-1:0] m_axis_tkeep_out;
|
||||
wire [KEEP_W-1:0] m_axis_tstrb_out;
|
||||
wire m_axis_tlast_out;
|
||||
wire [ID_W-1:0] m_axis_tid_out;
|
||||
wire [DEST_W-1:0] m_axis_tdest_out;
|
||||
wire [USER_W-1:0] m_axis_tuser_out;
|
||||
|
||||
wire pipe_ready;
|
||||
|
||||
assign status_depth = (KEEP_EN && KEEP_W > 1) ? {depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(depth_reg);
|
||||
assign status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(depth_commit_reg);
|
||||
assign status_overflow = overflow_reg;
|
||||
assign status_bad_frame = bad_frame_reg;
|
||||
assign status_good_frame = good_frame_reg;
|
||||
|
||||
// Write logic
|
||||
always_ff @(posedge clk) begin
|
||||
overflow_reg <= 1'b0;
|
||||
bad_frame_reg <= 1'b0;
|
||||
good_frame_reg <= 1'b0;
|
||||
|
||||
if (s_axis.tready && s_axis.tvalid && LAST_EN) begin
|
||||
// track input frame status
|
||||
s_frame_reg <= !s_axis.tlast;
|
||||
end
|
||||
|
||||
if (FRAME_FIFO) begin
|
||||
// frame FIFO mode
|
||||
if (s_axis.tready && s_axis.tvalid) begin
|
||||
// transfer in
|
||||
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
|
||||
// full, packet overflow, or currently dropping frame
|
||||
// drop frame
|
||||
drop_frame_reg <= 1'b1;
|
||||
if (s_axis.tlast) begin
|
||||
// end of frame, reset write pointer
|
||||
wr_ptr_reg <= wr_ptr_commit_reg;
|
||||
drop_frame_reg <= 1'b0;
|
||||
overflow_reg <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
// store it
|
||||
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
||||
wr_ptr_reg <= wr_ptr_reg + 1;
|
||||
if (s_axis.tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
|
||||
// end of frame or send frame
|
||||
send_frame_reg <= !s_axis.tlast;
|
||||
if (s_axis.tlast && DROP_BAD_FRAME && (USER_W'(USER_BAD_FRAME_MASK) & ~(s_axis.tuser ^ USER_W'(USER_BAD_FRAME_VALUE))) != 0) begin
|
||||
// bad packet, reset write pointer
|
||||
wr_ptr_reg <= wr_ptr_commit_reg;
|
||||
bad_frame_reg <= 1'b1;
|
||||
end else begin
|
||||
// good packet or packet overflow, update write pointer
|
||||
wr_ptr_commit_reg <= wr_ptr_reg + 1;
|
||||
good_frame_reg <= s_axis.tlast;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else if (s_axis.tvalid && full_wr && !DROP_OVERSIZE_FRAME) begin
|
||||
// data valid with packet overflow
|
||||
// update write pointer
|
||||
send_frame_reg <= 1'b1;
|
||||
wr_ptr_commit_reg <= wr_ptr_reg;
|
||||
end
|
||||
end else begin
|
||||
// normal FIFO mode
|
||||
if (s_axis.tready && s_axis.tvalid) begin
|
||||
if (drop_frame_reg && MARK_WHEN_FULL) begin
|
||||
// currently dropping frame
|
||||
if (s_axis.tlast) begin
|
||||
// end of frame
|
||||
if (!full && mark_frame_reg) begin
|
||||
// terminate marked frame
|
||||
mark_frame_reg <= 1'b0;
|
||||
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
||||
wr_ptr_reg <= wr_ptr_reg + 1;
|
||||
wr_ptr_commit_reg <= wr_ptr_reg + 1;
|
||||
end
|
||||
// end of frame, clear drop flag
|
||||
drop_frame_reg <= 1'b0;
|
||||
overflow_reg <= 1'b1;
|
||||
end
|
||||
end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin
|
||||
// full or marking frame
|
||||
// drop frame; mark if this isn't the first cycle
|
||||
drop_frame_reg <= 1'b1;
|
||||
mark_frame_reg <= mark_frame_reg || s_frame_reg;
|
||||
if (s_axis.tlast) begin
|
||||
drop_frame_reg <= 1'b0;
|
||||
overflow_reg <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
// transfer in
|
||||
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
||||
wr_ptr_reg <= wr_ptr_reg + 1;
|
||||
wr_ptr_commit_reg <= wr_ptr_reg + 1;
|
||||
end
|
||||
end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin
|
||||
// terminate marked frame
|
||||
mark_frame_reg <= 1'b0;
|
||||
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
|
||||
wr_ptr_reg <= wr_ptr_reg + 1;
|
||||
wr_ptr_commit_reg <= wr_ptr_reg + 1;
|
||||
end
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
wr_ptr_reg <= '0;
|
||||
wr_ptr_commit_reg <= '0;
|
||||
|
||||
s_frame_reg <= 1'b0;
|
||||
|
||||
drop_frame_reg <= 1'b0;
|
||||
mark_frame_reg <= 1'b0;
|
||||
send_frame_reg <= 1'b0;
|
||||
overflow_reg <= 1'b0;
|
||||
bad_frame_reg <= 1'b0;
|
||||
good_frame_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Status
|
||||
always_ff @(posedge clk) begin
|
||||
depth_reg <= wr_ptr_reg - rd_ptr_reg;
|
||||
depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_reg;
|
||||
end
|
||||
|
||||
// Read logic
|
||||
always_ff @(posedge clk) begin
|
||||
if (m_axis_tready_pipe) begin
|
||||
// output ready; invalidate stage
|
||||
mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
|
||||
end
|
||||
|
||||
for (integer j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
|
||||
if (m_axis_tready_pipe || ((RAM_PIPELINE+1)'(~mem_rd_valid_pipe_reg) >> j) != 0) begin
|
||||
// if (m_axis_tready_pipe || &mem_rd_valid_pipe_reg[1:1] == 0) begin
|
||||
// output ready or bubble in pipeline; transfer down pipeline
|
||||
mem_rd_valid_pipe_reg[j] <= mem_rd_valid_pipe_reg[j-1];
|
||||
mem_rd_data_pipe_reg[j] <= mem_rd_data_pipe_reg[j-1];
|
||||
mem_rd_valid_pipe_reg[j-1] <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (m_axis_tready_pipe || &mem_rd_valid_pipe_reg == 0) begin
|
||||
// output ready or bubble in pipeline; read new data from FIFO
|
||||
mem_rd_valid_pipe_reg[0] <= 1'b0;
|
||||
mem_rd_data_pipe_reg[0] <= mem[rd_ptr_reg[FIFO_AW-1:0]];
|
||||
if (!empty && pipe_ready) begin
|
||||
// not empty, increment pointer
|
||||
mem_rd_valid_pipe_reg[0] <= 1'b1;
|
||||
rd_ptr_reg <= rd_ptr_reg + 1;
|
||||
end
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
rd_ptr_reg <= '0;
|
||||
mem_rd_valid_pipe_reg <= '0;
|
||||
end
|
||||
end
|
||||
|
||||
if (!OUTPUT_FIFO_EN) begin
|
||||
|
||||
assign pipe_ready = 1'b1;
|
||||
|
||||
assign m_axis_tready_pipe = m_axis_tready_out;
|
||||
assign m_axis_tvalid_out = m_axis_tvalid_pipe;
|
||||
|
||||
assign m_axis_tdata_out = m_axis_tdata_pipe;
|
||||
assign m_axis_tkeep_out = m_axis_tkeep_pipe;
|
||||
assign m_axis_tstrb_out = m_axis_tstrb_pipe;
|
||||
assign m_axis_tlast_out = m_axis_tlast_pipe;
|
||||
assign m_axis_tid_out = m_axis_tid_pipe;
|
||||
assign m_axis_tdest_out = m_axis_tdest_pipe;
|
||||
assign m_axis_tuser_out = m_axis_tuser_pipe;
|
||||
|
||||
end else begin : output_fifo
|
||||
|
||||
// output datapath logic
|
||||
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
logic m_axis_tvalid_reg = 1'b0;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = '0;
|
||||
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = '0;
|
||||
logic out_fifo_half_full_reg = 1'b0;
|
||||
|
||||
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}});
|
||||
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
||||
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic out_fifo_tlast[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [ID_W-1:0] out_fifo_tid[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW];
|
||||
|
||||
assign pipe_ready = !out_fifo_half_full_reg;
|
||||
|
||||
assign m_axis_tready_pipe = 1'b1;
|
||||
|
||||
assign m_axis_tdata_out = m_axis_tdata_reg;
|
||||
assign m_axis_tkeep_out = KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis_tstrb_out = STRB_EN ? m_axis_tstrb_reg : m_axis_tkeep_out;
|
||||
assign m_axis_tvalid_out = m_axis_tvalid_reg;
|
||||
assign m_axis_tlast_out = LAST_EN ? m_axis_tlast_reg : 1'b1;
|
||||
assign m_axis_tid_out = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis_tdest_out = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis_tuser_out = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out;
|
||||
|
||||
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_AW-1);
|
||||
|
||||
if (!out_fifo_full && m_axis_tvalid_pipe) begin
|
||||
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdata_pipe;
|
||||
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tkeep_pipe;
|
||||
out_fifo_tstrb[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tstrb_pipe;
|
||||
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tlast_pipe;
|
||||
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tid_pipe;
|
||||
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdest_pipe;
|
||||
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tuser_pipe;
|
||||
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
||||
end
|
||||
|
||||
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin
|
||||
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tstrb_reg <= out_fifo_tstrb[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tvalid_reg <= 1'b1;
|
||||
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
|
||||
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
out_fifo_wr_ptr_reg <= '0;
|
||||
out_fifo_rd_ptr_reg <= '0;
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
if (PAUSE_EN) begin : pause
|
||||
|
||||
// Pause logic
|
||||
logic pause_reg = 1'b0;
|
||||
logic pause_frame_reg = 1'b0;
|
||||
|
||||
assign m_axis_tready_out = m_axis.tready && !pause_reg;
|
||||
assign m_axis.tvalid = m_axis_tvalid_out && !pause_reg;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_out;
|
||||
assign m_axis.tkeep = m_axis_tkeep_out;
|
||||
assign m_axis.tstrb = m_axis_tstrb_out;
|
||||
assign m_axis.tlast = m_axis_tlast_out;
|
||||
assign m_axis.tid = m_axis_tid_out;
|
||||
assign m_axis.tdest = m_axis_tdest_out;
|
||||
assign m_axis.tuser = m_axis_tuser_out;
|
||||
|
||||
assign pause_ack = pause_reg;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (FRAME_PAUSE) begin
|
||||
if (pause_reg) begin
|
||||
// paused; update pause status
|
||||
pause_reg <= pause_req;
|
||||
end else if (m_axis_tvalid_out) begin
|
||||
// frame transfer; set frame bit
|
||||
pause_frame_reg <= 1'b1;
|
||||
if (m_axis.tready && m_axis.tlast) begin
|
||||
// end of frame; clear frame bit and update pause status
|
||||
pause_frame_reg <= 1'b0;
|
||||
pause_reg <= pause_req;
|
||||
end
|
||||
end else if (!pause_frame_reg) begin
|
||||
// idle; update pause status
|
||||
pause_reg <= pause_req;
|
||||
end
|
||||
end else begin
|
||||
pause_reg <= pause_req;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
pause_frame_reg <= 1'b0;
|
||||
pause_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
assign m_axis_tready_out = m_axis.tready;
|
||||
assign m_axis.tvalid = m_axis_tvalid_out;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_out;
|
||||
assign m_axis.tkeep = m_axis_tkeep_out;
|
||||
assign m_axis.tstrb = m_axis_tstrb_out;
|
||||
assign m_axis.tlast = m_axis_tlast_out;
|
||||
assign m_axis.tid = m_axis_tid_out;
|
||||
assign m_axis.tdest = m_axis_tdest_out;
|
||||
assign m_axis.tuser = m_axis_tuser_out;
|
||||
|
||||
assign pause_ack = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
4
src/axis/rtl/taxi_axis_fifo_adapter.f
Normal file
4
src/axis/rtl/taxi_axis_fifo_adapter.f
Normal file
@@ -0,0 +1,4 @@
|
||||
taxi_axis_fifo_adapter.sv
|
||||
taxi_axis_fifo.sv
|
||||
taxi_axis_adapter.sv
|
||||
taxi_axis_if.sv
|
||||
228
src/axis/rtl/taxi_axis_fifo_adapter.sv
Normal file
228
src/axis/rtl/taxi_axis_fifo_adapter.sv
Normal file
@@ -0,0 +1,228 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2019-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream FIFO with width converter
|
||||
*/
|
||||
module taxi_axis_fifo_adapter #
|
||||
(
|
||||
// FIFO depth in words
|
||||
// KEEP_W words per cycle if KEEP_EN set
|
||||
// Rounded up to nearest power of 2 cycles
|
||||
parameter DEPTH = 4096,
|
||||
// number of RAM pipeline registers in FIFO
|
||||
parameter RAM_PIPELINE = 1,
|
||||
// use output FIFO
|
||||
// When set, the RAM read enable and pipeline clock enables are removed
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
// Frame FIFO mode - operate on frames instead of cycles
|
||||
// When set, m_axis_tvalid will not be deasserted within a frame
|
||||
// Requires logic LAST_EN set
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
// tuser value for bad frame marker
|
||||
parameter USER_BAD_FRAME_VALUE = 1'b1,
|
||||
// tuser mask for bad frame marker
|
||||
parameter USER_BAD_FRAME_MASK = 1'b1,
|
||||
// Drop frames larger than FIFO
|
||||
// Requires FRAME_FIFO set
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
// Drop frames marked bad
|
||||
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
// Drop incoming frames when full
|
||||
// When set, s_axis_tready is always asserted
|
||||
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
// Mark incoming frames as bad frames when full
|
||||
// When set, s_axis_tready is always asserted
|
||||
// Requires FRAME_FIFO to be clear
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
// Enable pause request input
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
// Pause between frames
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis,
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
input wire logic pause_req = 1'b0,
|
||||
output wire logic pause_ack,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic [$clog2(DEPTH):0] status_depth,
|
||||
output wire logic [$clog2(DEPTH):0] status_depth_commit,
|
||||
output wire logic status_overflow,
|
||||
output wire logic status_bad_frame,
|
||||
output wire logic status_good_frame
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam S_DATA_W = s_axis.DATA_W;
|
||||
localparam logic S_KEEP_EN = s_axis.KEEP_EN;
|
||||
localparam S_KEEP_W = s_axis.KEEP_W;
|
||||
localparam logic S_STRB_EN = s_axis.STRB_EN;
|
||||
|
||||
localparam M_DATA_W = m_axis.DATA_W;
|
||||
localparam logic M_KEEP_EN = m_axis.KEEP_EN;
|
||||
localparam M_KEEP_W = m_axis.KEEP_W;
|
||||
localparam logic M_STRB_EN = m_axis.STRB_EN;
|
||||
|
||||
// force keep width to 1 when disabled
|
||||
localparam S_BYTE_LANES = S_KEEP_EN ? S_KEEP_W : 1;
|
||||
localparam M_BYTE_LANES = M_KEEP_EN ? M_KEEP_W : 1;
|
||||
|
||||
// bus byte sizes (must be identical)
|
||||
localparam S_BYTE_SIZE = S_DATA_W / S_BYTE_LANES;
|
||||
localparam M_BYTE_SIZE = M_DATA_W / M_BYTE_LANES;
|
||||
// output bus is wider
|
||||
localparam EXPAND_BUS = M_BYTE_LANES > S_BYTE_LANES;
|
||||
// total data and keep widths
|
||||
localparam DATA_W = EXPAND_BUS ? M_DATA_W : S_DATA_W;
|
||||
localparam KEEP_W = EXPAND_BUS ? M_BYTE_LANES : S_BYTE_LANES;
|
||||
localparam KEEP_EN = EXPAND_BUS ? M_KEEP_EN : S_KEEP_EN;
|
||||
localparam STRB_EN = EXPAND_BUS ? M_STRB_EN : S_STRB_EN;
|
||||
|
||||
// check configuration
|
||||
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_W)
|
||||
$fatal(0, "Error: input data width not evenly divisible (instance %m)");
|
||||
|
||||
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_W)
|
||||
$fatal(0, "Error: output data width not evenly divisible (instance %m)");
|
||||
|
||||
if (S_BYTE_SIZE != M_BYTE_SIZE)
|
||||
$fatal(0, "Error: byte size mismatch (instance %m)");
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(s_axis.STRB_EN),
|
||||
.LAST_EN(s_axis.LAST_EN),
|
||||
.ID_EN(s_axis.ID_EN),
|
||||
.ID_W(s_axis.ID_W),
|
||||
.DEST_EN(s_axis.DEST_EN),
|
||||
.DEST_W(s_axis.DEST_W),
|
||||
.USER_EN(s_axis.USER_EN),
|
||||
.USER_W(s_axis.USER_W)
|
||||
) axis_pre_fifo();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(m_axis.STRB_EN),
|
||||
.LAST_EN(m_axis.LAST_EN),
|
||||
.ID_EN(m_axis.ID_EN),
|
||||
.ID_W(m_axis.ID_W),
|
||||
.DEST_EN(m_axis.DEST_EN),
|
||||
.DEST_W(m_axis.DEST_W),
|
||||
.USER_EN(m_axis.USER_EN),
|
||||
.USER_W(m_axis.USER_W)
|
||||
) axis_post_fifo();
|
||||
|
||||
taxi_axis_adapter
|
||||
pre_fifo_adapter_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(axis_pre_fifo)
|
||||
);
|
||||
|
||||
taxi_axis_fifo #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
fifo_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(axis_pre_fifo),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(axis_post_fifo),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.pause_req(pause_req),
|
||||
.pause_ack(pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_depth(status_depth),
|
||||
.status_depth_commit(status_depth_commit),
|
||||
.status_overflow(status_overflow),
|
||||
.status_bad_frame(status_bad_frame),
|
||||
.status_good_frame(status_good_frame)
|
||||
);
|
||||
|
||||
taxi_axis_adapter
|
||||
post_fifo_adapter_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(axis_post_fifo),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
82
src/axis/rtl/taxi_axis_if.sv
Normal file
82
src/axis/rtl/taxi_axis_if.sv
Normal file
@@ -0,0 +1,82 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
interface taxi_axis_if #(
|
||||
// Width of AXI stream interfaces in bits
|
||||
parameter DATA_W = 8,
|
||||
// tkeep signal width (bytes per cycle)
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
// Use tkeep signal
|
||||
parameter logic KEEP_EN = KEEP_W > 1,
|
||||
// Use tstrb signal
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
// Use tlast signal
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
// Use tid signal
|
||||
parameter logic ID_EN = 0,
|
||||
// tid signal width
|
||||
parameter ID_W = 8,
|
||||
// Use tdest signal
|
||||
parameter logic DEST_EN = 0,
|
||||
// tdest signal width
|
||||
parameter DEST_W = 8,
|
||||
// Use tuser signal
|
||||
parameter logic USER_EN = 0,
|
||||
// tuser signal width
|
||||
parameter USER_W = 1
|
||||
)
|
||||
();
|
||||
logic [DATA_W-1:0] tdata;
|
||||
logic [KEEP_W-1:0] tkeep;
|
||||
logic [KEEP_W-1:0] tstrb;
|
||||
logic [ID_W-1:0] tid;
|
||||
logic [DEST_W-1:0] tdest;
|
||||
logic [USER_W-1:0] tuser;
|
||||
logic tlast;
|
||||
logic tvalid;
|
||||
logic tready;
|
||||
|
||||
modport src (
|
||||
output tdata,
|
||||
output tkeep,
|
||||
output tstrb,
|
||||
output tid,
|
||||
output tdest,
|
||||
output tuser,
|
||||
output tlast,
|
||||
output tvalid,
|
||||
input tready
|
||||
);
|
||||
|
||||
modport snk (
|
||||
input tdata,
|
||||
input tkeep,
|
||||
input tstrb,
|
||||
input tid,
|
||||
input tdest,
|
||||
input tuser,
|
||||
input tlast,
|
||||
input tvalid,
|
||||
output tready
|
||||
);
|
||||
|
||||
modport mon (
|
||||
input tdata,
|
||||
input tkeep,
|
||||
input tstrb,
|
||||
input tid,
|
||||
input tdest,
|
||||
input tuser,
|
||||
input tlast,
|
||||
input tvalid,
|
||||
input tready
|
||||
);
|
||||
|
||||
endinterface
|
||||
272
src/axis/rtl/taxi_axis_mux.sv
Normal file
272
src/axis/rtl/taxi_axis_mux.sv
Normal file
@@ -0,0 +1,272 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream multiplexer
|
||||
*/
|
||||
module taxi_axis_mux #
|
||||
(
|
||||
// Number of AXI stream inputs
|
||||
parameter S_COUNT = 4
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
|
||||
/*
|
||||
* AXI4-Stream inputs (sinks)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis[S_COUNT],
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis,
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
input wire logic enable,
|
||||
input wire logic [$clog2(S_COUNT)-1:0] select
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axis[0].DATA_W;
|
||||
localparam logic KEEP_EN = s_axis[0].KEEP_EN && m_axis.KEEP_EN;
|
||||
localparam KEEP_W = s_axis[0].KEEP_W;
|
||||
localparam logic STRB_EN = s_axis[0].STRB_EN && m_axis.STRB_EN;
|
||||
localparam logic LAST_EN = s_axis[0].LAST_EN && m_axis.LAST_EN;
|
||||
localparam logic ID_EN = s_axis[0].ID_EN && m_axis.ID_EN;
|
||||
localparam ID_W = s_axis[0].ID_W;
|
||||
localparam logic DEST_EN = s_axis[0].DEST_EN && m_axis.DEST_EN;
|
||||
localparam DEST_W = s_axis[0].DEST_W;
|
||||
localparam logic USER_EN = s_axis[0].USER_EN && m_axis.USER_EN;
|
||||
localparam USER_W = s_axis[0].USER_W;
|
||||
|
||||
// check configuration
|
||||
if (m_axis.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
|
||||
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
|
||||
|
||||
parameter CL_S_COUNT = $clog2(S_COUNT);
|
||||
|
||||
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
|
||||
reg frame_reg = 1'b0, frame_next;
|
||||
|
||||
reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
|
||||
|
||||
// internal datapath
|
||||
reg [DATA_W-1:0] m_axis_tdata_int;
|
||||
reg [KEEP_W-1:0] m_axis_tkeep_int;
|
||||
reg [KEEP_W-1:0] m_axis_tstrb_int;
|
||||
reg m_axis_tvalid_int;
|
||||
reg m_axis_tready_int_reg = 1'b0;
|
||||
reg m_axis_tlast_int;
|
||||
reg [ID_W-1:0] m_axis_tid_int;
|
||||
reg [DEST_W-1:0] m_axis_tdest_int;
|
||||
reg [USER_W-1:0] m_axis_tuser_int;
|
||||
wire m_axis_tready_int_early;
|
||||
|
||||
// unpack interface array
|
||||
wire [DATA_W-1:0] s_axis_tdata[S_COUNT];
|
||||
wire [KEEP_W-1:0] s_axis_tkeep[S_COUNT];
|
||||
wire [KEEP_W-1:0] s_axis_tstrb[S_COUNT];
|
||||
wire [S_COUNT-1:0] s_axis_tvalid;
|
||||
wire [S_COUNT-1:0] s_axis_tready;
|
||||
wire [S_COUNT-1:0] s_axis_tlast;
|
||||
wire [ID_W-1:0] s_axis_tid[S_COUNT];
|
||||
wire [DEST_W-1:0] s_axis_tdest[S_COUNT];
|
||||
wire [USER_W-1:0] s_axis_tuser[S_COUNT];
|
||||
|
||||
for (genvar n = 0; n < S_COUNT; n = n + 1) begin
|
||||
assign s_axis_tdata[n] = s_axis[n].tdata;
|
||||
assign s_axis_tkeep[n] = s_axis[n].tkeep;
|
||||
assign s_axis_tstrb[n] = s_axis[n].tstrb;
|
||||
assign s_axis_tvalid[n] = s_axis[n].tvalid;
|
||||
assign s_axis[n].tready = s_axis_tready[n];
|
||||
assign s_axis_tlast[n] = s_axis[n].tlast;
|
||||
assign s_axis_tid[n] = s_axis[n].tid;
|
||||
assign s_axis_tdest[n] = s_axis[n].tdest;
|
||||
assign s_axis_tuser[n] = s_axis[n].tuser;
|
||||
end
|
||||
|
||||
assign s_axis_tready = s_axis_tready_reg;
|
||||
|
||||
// mux for incoming packet
|
||||
wire [DATA_W-1:0] current_s_tdata = s_axis_tdata[select_reg];
|
||||
wire [KEEP_W-1:0] current_s_tkeep = s_axis_tkeep[select_reg];
|
||||
wire [KEEP_W-1:0] current_s_tstrb = s_axis_tstrb[select_reg];
|
||||
wire current_s_tvalid = s_axis_tvalid[select_reg];
|
||||
wire current_s_tready = s_axis_tready[select_reg];
|
||||
wire current_s_tlast = s_axis_tlast[select_reg];
|
||||
wire [ID_W-1:0] current_s_tid = s_axis_tid[select_reg];
|
||||
wire [DEST_W-1:0] current_s_tdest = s_axis_tdest[select_reg];
|
||||
wire [USER_W-1:0] current_s_tuser = s_axis_tuser[select_reg];
|
||||
|
||||
always_comb begin
|
||||
select_next = select_reg;
|
||||
frame_next = frame_reg;
|
||||
|
||||
s_axis_tready_next = 0;
|
||||
|
||||
if (current_s_tvalid & current_s_tready) begin
|
||||
// end of frame detection
|
||||
if (current_s_tlast) begin
|
||||
frame_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (!frame_reg && enable && s_axis_tvalid[select]) begin
|
||||
// start of frame, grab select value
|
||||
frame_next = 1'b1;
|
||||
select_next = select;
|
||||
end
|
||||
|
||||
// generate ready signal on selected port
|
||||
s_axis_tready_next[select_next] = m_axis_tready_int_early && frame_next;
|
||||
|
||||
// pass through selected packet data
|
||||
m_axis_tdata_int = current_s_tdata;
|
||||
m_axis_tkeep_int = current_s_tkeep;
|
||||
m_axis_tstrb_int = current_s_tstrb;
|
||||
m_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
|
||||
m_axis_tlast_int = current_s_tlast;
|
||||
m_axis_tid_int = current_s_tid;
|
||||
m_axis_tdest_int = current_s_tdest;
|
||||
m_axis_tuser_int = current_s_tuser;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
select_reg <= select_next;
|
||||
frame_reg <= frame_next;
|
||||
s_axis_tready_reg <= s_axis_tready_next;
|
||||
|
||||
if (rst) begin
|
||||
select_reg <= 0;
|
||||
frame_reg <= 1'b0;
|
||||
s_axis_tready_reg <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
reg [KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
reg [KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
|
||||
reg m_axis_tlast_reg = 1'b0;
|
||||
reg [ID_W-1:0] m_axis_tid_reg = '0;
|
||||
reg [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
reg [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
reg [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
|
||||
reg [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
|
||||
reg [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
|
||||
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
|
||||
reg temp_m_axis_tlast_reg = 1'b0;
|
||||
reg [ID_W-1:0] temp_m_axis_tid_reg = '0;
|
||||
reg [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
|
||||
reg [USER_W-1:0] temp_m_axis_tuser_reg = '0;
|
||||
|
||||
// datapath control
|
||||
reg store_axis_int_to_output;
|
||||
reg store_axis_int_to_temp;
|
||||
reg store_axis_temp_to_output;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_reg;
|
||||
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
|
||||
assign m_axis.tvalid = m_axis_tvalid_reg;
|
||||
assign m_axis.tlast = m_axis_tlast_reg;
|
||||
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axis_tvalid_next = m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
|
||||
store_axis_int_to_output = 1'b0;
|
||||
store_axis_int_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (m_axis.tready || !m_axis_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axis_tvalid_next = m_axis_tvalid_int;
|
||||
store_axis_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axis_tvalid_next = m_axis_tvalid_int;
|
||||
store_axis_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axis.tready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
||||
m_axis_tready_int_reg <= m_axis_tready_int_early;
|
||||
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axis_int_to_output) begin
|
||||
m_axis_tdata_reg <= m_axis_tdata_int;
|
||||
m_axis_tkeep_reg <= m_axis_tkeep_int;
|
||||
m_axis_tstrb_reg <= m_axis_tstrb_int;
|
||||
m_axis_tlast_reg <= m_axis_tlast_int;
|
||||
m_axis_tid_reg <= m_axis_tid_int;
|
||||
m_axis_tdest_reg <= m_axis_tdest_int;
|
||||
m_axis_tuser_reg <= m_axis_tuser_int;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
|
||||
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
|
||||
m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
|
||||
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
|
||||
m_axis_tid_reg <= temp_m_axis_tid_reg;
|
||||
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
|
||||
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_int_to_temp) begin
|
||||
temp_m_axis_tdata_reg <= m_axis_tdata_int;
|
||||
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
|
||||
temp_m_axis_tstrb_reg <= m_axis_tstrb_int;
|
||||
temp_m_axis_tlast_reg <= m_axis_tlast_int;
|
||||
temp_m_axis_tid_reg <= m_axis_tid_int;
|
||||
temp_m_axis_tdest_reg <= m_axis_tdest_int;
|
||||
temp_m_axis_tuser_reg <= m_axis_tuser_int;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
m_axis_tready_int_reg <= 1'b0;
|
||||
temp_m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
235
src/axis/rtl/taxi_axis_pipeline_fifo.sv
Normal file
235
src/axis/rtl/taxi_axis_pipeline_fifo.sv
Normal file
@@ -0,0 +1,235 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream pipeline FIFO
|
||||
*/
|
||||
module taxi_axis_pipeline_fifo #
|
||||
(
|
||||
// Number of registers in pipeline
|
||||
parameter LENGTH = 2
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axis.DATA_W;
|
||||
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
|
||||
localparam KEEP_W = s_axis.KEEP_W;
|
||||
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
|
||||
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
|
||||
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
|
||||
localparam ID_W = s_axis.ID_W;
|
||||
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
|
||||
localparam DEST_W = s_axis.DEST_W;
|
||||
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
|
||||
localparam USER_W = s_axis.USER_W;
|
||||
|
||||
// check configuration
|
||||
if (m_axis.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
|
||||
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
|
||||
|
||||
localparam FIFO_AW = LENGTH < 2 ? 3 : $clog2(LENGTH*4+1);
|
||||
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .ID_W(ID_W), .DEST_W(DEST_W), .USER_W(USER_W)) axis_pipe[LENGTH+1]();
|
||||
|
||||
for (genvar n = 0; n < LENGTH; n = n + 1) begin : stage
|
||||
|
||||
(* shreg_extract = "no" *)
|
||||
logic [DATA_W-1:0] axis_tdata_reg = 0;
|
||||
(* shreg_extract = "no" *)
|
||||
logic [KEEP_W-1:0] axis_tkeep_reg = 0;
|
||||
(* shreg_extract = "no" *)
|
||||
logic [KEEP_W-1:0] axis_tstrb_reg = 0;
|
||||
(* shreg_extract = "no" *)
|
||||
logic axis_tvalid_reg = 0;
|
||||
(* shreg_extract = "no" *)
|
||||
logic axis_tready_reg = 0;
|
||||
(* shreg_extract = "no" *)
|
||||
logic axis_tlast_reg = 0;
|
||||
(* shreg_extract = "no" *)
|
||||
logic [ID_W-1:0] axis_tid_reg = 0;
|
||||
(* shreg_extract = "no" *)
|
||||
logic [DEST_W-1:0] axis_tdest_reg = 0;
|
||||
(* shreg_extract = "no" *)
|
||||
logic [USER_W-1:0] axis_tuser_reg = 0;
|
||||
|
||||
assign axis_pipe[n+1].tdata = axis_tdata_reg;
|
||||
assign axis_pipe[n+1].tkeep = axis_tkeep_reg;
|
||||
assign axis_pipe[n+1].tstrb = axis_tstrb_reg;
|
||||
assign axis_pipe[n+1].tvalid = axis_tvalid_reg;
|
||||
assign axis_pipe[n+1].tlast = axis_tlast_reg;
|
||||
assign axis_pipe[n+1].tid = axis_tid_reg;
|
||||
assign axis_pipe[n+1].tdest = axis_tdest_reg;
|
||||
assign axis_pipe[n+1].tuser = axis_tuser_reg;
|
||||
|
||||
assign axis_pipe[n].tready = axis_tready_reg;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
axis_tdata_reg <= axis_pipe[n].tdata;
|
||||
axis_tkeep_reg <= axis_pipe[n].tkeep;
|
||||
axis_tstrb_reg <= axis_pipe[n].tstrb;
|
||||
axis_tvalid_reg <= axis_pipe[n].tvalid;
|
||||
axis_tlast_reg <= axis_pipe[n].tlast;
|
||||
axis_tid_reg <= axis_pipe[n].tid;
|
||||
axis_tdest_reg <= axis_pipe[n].tdest;
|
||||
axis_tuser_reg <= axis_pipe[n].tuser;
|
||||
|
||||
axis_tready_reg <= axis_pipe[n+1].tready;
|
||||
|
||||
if (rst) begin
|
||||
axis_tvalid_reg <= 1'b0;
|
||||
axis_tready_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
if (LENGTH > 0) begin : fifo
|
||||
|
||||
assign axis_pipe[0].tdata = s_axis.tdata;
|
||||
assign axis_pipe[0].tkeep = s_axis.tkeep;
|
||||
assign axis_pipe[0].tstrb = s_axis.tstrb;
|
||||
assign axis_pipe[0].tvalid = s_axis.tvalid & s_axis.tready;
|
||||
assign axis_pipe[0].tlast = s_axis.tlast;
|
||||
assign axis_pipe[0].tid = s_axis.tid;
|
||||
assign axis_pipe[0].tdest = s_axis.tdest;
|
||||
assign axis_pipe[0].tuser = s_axis.tuser;
|
||||
assign s_axis.tready = axis_pipe[0].tready;
|
||||
|
||||
wire [DATA_W-1:0] m_axis_tdata_int = axis_pipe[LENGTH].tdata;
|
||||
wire [KEEP_W-1:0] m_axis_tkeep_int = axis_pipe[LENGTH].tkeep;
|
||||
wire [KEEP_W-1:0] m_axis_tstrb_int = axis_pipe[LENGTH].tstrb;
|
||||
wire m_axis_tvalid_int = axis_pipe[LENGTH].tvalid;
|
||||
wire m_axis_tready_int;
|
||||
wire m_axis_tlast_int = axis_pipe[LENGTH].tlast;
|
||||
wire [ID_W-1:0] m_axis_tid_int = axis_pipe[LENGTH].tid;
|
||||
wire [DEST_W-1:0] m_axis_tdest_int = axis_pipe[LENGTH].tdest;
|
||||
wire [USER_W-1:0] m_axis_tuser_int = axis_pipe[LENGTH].tuser;
|
||||
|
||||
assign axis_pipe[LENGTH].tready = m_axis_tready_int;
|
||||
|
||||
// output datapath logic
|
||||
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
logic m_axis_tvalid_reg = 1'b0;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
logic [FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = 0;
|
||||
logic [FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = 0;
|
||||
logic out_fifo_half_full_reg = 1'b0;
|
||||
|
||||
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {FIFO_AW{1'b0}}});
|
||||
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
||||
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [DATA_W-1:0] out_fifo_tdata[2**FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [KEEP_W-1:0] out_fifo_tkeep[2**FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [KEEP_W-1:0] out_fifo_tstrb[2**FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic out_fifo_tlast[2**FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [ID_W-1:0] out_fifo_tid[2**FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [DEST_W-1:0] out_fifo_tdest[2**FIFO_AW];
|
||||
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
||||
logic [USER_W-1:0] out_fifo_tuser[2**FIFO_AW];
|
||||
|
||||
assign m_axis_tready_int = !out_fifo_half_full_reg;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_reg;
|
||||
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
|
||||
assign m_axis.tvalid = m_axis_tvalid_reg;
|
||||
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
|
||||
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis.tready;
|
||||
|
||||
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
|
||||
|
||||
if (!out_fifo_full && m_axis_tvalid_int) begin
|
||||
out_fifo_tdata[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tdata_int;
|
||||
out_fifo_tkeep[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tkeep_int;
|
||||
out_fifo_tstrb[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tstrb_int;
|
||||
out_fifo_tlast[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tlast_int;
|
||||
out_fifo_tid[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tid_int;
|
||||
out_fifo_tdest[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tdest_int;
|
||||
out_fifo_tuser[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tuser_int;
|
||||
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
||||
end
|
||||
|
||||
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis.tready)) begin
|
||||
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
|
||||
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
|
||||
m_axis_tstrb_reg <= out_fifo_tstrb[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
|
||||
m_axis_tvalid_reg <= 1'b1;
|
||||
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
|
||||
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
|
||||
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
|
||||
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
|
||||
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
out_fifo_wr_ptr_reg <= 0;
|
||||
out_fifo_rd_ptr_reg <= 0;
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
// bypass
|
||||
|
||||
assign m_axis.tdata = s_axis.tdata;
|
||||
assign m_axis.tkeep = KEEP_EN ? s_axis.tkeep : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? s_axis.tstrb : m_axis.tkeep;
|
||||
assign m_axis.tvalid = s_axis.tvalid;
|
||||
assign m_axis.tlast = LAST_EN ? s_axis.tlast : 1'b1;
|
||||
assign m_axis.tid = ID_EN ? s_axis.tid : '0;
|
||||
assign m_axis.tdest = DEST_EN ? s_axis.tdest : '0;
|
||||
assign m_axis.tuser = USER_EN ? s_axis.tuser : '0;
|
||||
|
||||
assign s_axis.tready = m_axis.tready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
3
src/axis/rtl/taxi_axis_pipeline_register.f
Normal file
3
src/axis/rtl/taxi_axis_pipeline_register.f
Normal file
@@ -0,0 +1,3 @@
|
||||
taxi_axis_pipeline_register.sv
|
||||
taxi_axis_register.sv
|
||||
taxi_axis_if.sv
|
||||
119
src/axis/rtl/taxi_axis_pipeline_register.sv
Normal file
119
src/axis/rtl/taxi_axis_pipeline_register.sv
Normal file
@@ -0,0 +1,119 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream pipeline register
|
||||
*/
|
||||
module taxi_axis_pipeline_register #
|
||||
(
|
||||
// Register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter REG_TYPE = 2,
|
||||
// Number of registers in pipeline
|
||||
parameter LENGTH = 2
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axis.DATA_W;
|
||||
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
|
||||
localparam KEEP_W = s_axis.KEEP_W;
|
||||
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
|
||||
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
|
||||
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
|
||||
localparam ID_W = s_axis.ID_W;
|
||||
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
|
||||
localparam DEST_W = s_axis.DEST_W;
|
||||
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
|
||||
localparam USER_W = s_axis.USER_W;
|
||||
|
||||
// check configuration
|
||||
if (m_axis.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
|
||||
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) axis_pipe[LENGTH+1]();
|
||||
|
||||
assign axis_pipe[0].tdata = s_axis.tdata;
|
||||
assign axis_pipe[0].tkeep = s_axis.tkeep;
|
||||
assign axis_pipe[0].tstrb = s_axis.tstrb;
|
||||
assign axis_pipe[0].tvalid = s_axis.tvalid;
|
||||
assign s_axis.tready = axis_pipe[0].tready;
|
||||
assign axis_pipe[0].tlast = s_axis.tlast;
|
||||
assign axis_pipe[0].tid = s_axis.tid;
|
||||
assign axis_pipe[0].tdest = s_axis.tdest;
|
||||
assign axis_pipe[0].tuser = s_axis.tuser;
|
||||
|
||||
assign m_axis.tdata = axis_pipe[LENGTH].tdata;
|
||||
assign m_axis.tkeep = axis_pipe[LENGTH].tkeep;
|
||||
assign m_axis.tstrb = axis_pipe[LENGTH].tstrb;
|
||||
assign m_axis.tvalid = axis_pipe[LENGTH].tvalid;
|
||||
assign axis_pipe[LENGTH].tready = m_axis.tready;
|
||||
assign m_axis.tlast = axis_pipe[LENGTH].tlast;
|
||||
assign m_axis.tid = axis_pipe[LENGTH].tid;
|
||||
assign m_axis.tdest = axis_pipe[LENGTH].tdest;
|
||||
assign m_axis.tuser = axis_pipe[LENGTH].tuser;
|
||||
|
||||
for (genvar i = 0; i < LENGTH; i = i + 1) begin : pipe_reg
|
||||
|
||||
taxi_axis_register #(
|
||||
.REG_TYPE(REG_TYPE)
|
||||
)
|
||||
reg_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(axis_pipe[i]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(axis_pipe[i+1])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
256
src/axis/rtl/taxi_axis_register.sv
Normal file
256
src/axis/rtl/taxi_axis_register.sv
Normal file
@@ -0,0 +1,256 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream register
|
||||
*/
|
||||
module taxi_axis_register #
|
||||
(
|
||||
// Register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter REG_TYPE = 2
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis,
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
taxi_axis_if.src m_axis
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axis.DATA_W;
|
||||
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
|
||||
localparam KEEP_W = s_axis.KEEP_W;
|
||||
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
|
||||
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
|
||||
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
|
||||
localparam ID_W = s_axis.ID_W;
|
||||
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
|
||||
localparam DEST_W = s_axis.DEST_W;
|
||||
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
|
||||
localparam USER_W = s_axis.USER_W;
|
||||
|
||||
// check configuration
|
||||
if (m_axis.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
|
||||
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
|
||||
|
||||
if (REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axis_tready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
|
||||
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
|
||||
logic temp_m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
|
||||
|
||||
// datapath control
|
||||
logic store_axis_input_to_output;
|
||||
logic store_axis_input_to_temp;
|
||||
logic store_axis_temp_to_output;
|
||||
|
||||
assign s_axis.tready = s_axis_tready_reg;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_reg;
|
||||
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : s_axis.tkeep;
|
||||
assign m_axis.tvalid = m_axis_tvalid_reg;
|
||||
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
|
||||
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axis_tready_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis.tvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axis_tvalid_next = m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
|
||||
store_axis_input_to_output = 1'b0;
|
||||
store_axis_input_to_temp = 1'b0;
|
||||
store_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axis_tready_reg) begin
|
||||
// input is ready
|
||||
if (m_axis.tready || !m_axis_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axis_tvalid_next = s_axis.tvalid;
|
||||
store_axis_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axis_tvalid_next = s_axis.tvalid;
|
||||
store_axis_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axis.tready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
|
||||
temp_m_axis_tvalid_next = 1'b0;
|
||||
store_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axis_tready_reg <= s_axis_tready_early;
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
||||
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axis_input_to_output) begin
|
||||
m_axis_tdata_reg <= s_axis.tdata;
|
||||
m_axis_tkeep_reg <= s_axis.tkeep;
|
||||
m_axis_tstrb_reg <= s_axis.tstrb;
|
||||
m_axis_tlast_reg <= s_axis.tlast;
|
||||
m_axis_tid_reg <= s_axis.tid;
|
||||
m_axis_tdest_reg <= s_axis.tdest;
|
||||
m_axis_tuser_reg <= s_axis.tuser;
|
||||
end else if (store_axis_temp_to_output) begin
|
||||
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
|
||||
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
|
||||
m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
|
||||
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
|
||||
m_axis_tid_reg <= temp_m_axis_tid_reg;
|
||||
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
|
||||
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_axis_input_to_temp) begin
|
||||
temp_m_axis_tdata_reg <= s_axis.tdata;
|
||||
temp_m_axis_tkeep_reg <= s_axis.tkeep;
|
||||
temp_m_axis_tstrb_reg <= s_axis.tstrb;
|
||||
temp_m_axis_tlast_reg <= s_axis.tlast;
|
||||
temp_m_axis_tid_reg <= s_axis.tid;
|
||||
temp_m_axis_tdest_reg <= s_axis.tdest;
|
||||
temp_m_axis_tuser_reg <= s_axis.tuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axis_tready_reg <= 1'b0;
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
temp_m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axis_tready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
|
||||
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
|
||||
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
|
||||
logic m_axis_tlast_reg = 1'b0;
|
||||
logic [ID_W-1:0] m_axis_tid_reg = '0;
|
||||
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
|
||||
logic [USER_W-1:0] m_axis_tuser_reg = '0;
|
||||
|
||||
// datapath control
|
||||
logic store_axis_input_to_output;
|
||||
|
||||
assign s_axis.tready = s_axis_tready_reg;
|
||||
|
||||
assign m_axis.tdata = m_axis_tdata_reg;
|
||||
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? s_axis.tstrb : s_axis.tkeep;
|
||||
assign m_axis.tvalid = m_axis_tvalid_reg;
|
||||
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
|
||||
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
|
||||
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
|
||||
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axis_tready_early = !m_axis_tvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axis_tvalid_next = m_axis_tvalid_reg;
|
||||
|
||||
store_axis_input_to_output = 1'b0;
|
||||
|
||||
if (s_axis_tready_reg) begin
|
||||
m_axis_tvalid_next = s_axis.tvalid;
|
||||
store_axis_input_to_output = 1'b1;
|
||||
end else if (m_axis.tready) begin
|
||||
m_axis_tvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axis_tready_reg <= s_axis_tready_early;
|
||||
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axis_input_to_output) begin
|
||||
m_axis_tdata_reg <= s_axis.tdata;
|
||||
m_axis_tkeep_reg <= s_axis.tkeep;
|
||||
m_axis_tstrb_reg <= s_axis.tstrb;
|
||||
m_axis_tlast_reg <= s_axis.tlast;
|
||||
m_axis_tid_reg <= s_axis.tid;
|
||||
m_axis_tdest_reg <= s_axis.tdest;
|
||||
m_axis_tuser_reg <= s_axis.tuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axis_tready_reg <= 1'b0;
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
// bypass
|
||||
|
||||
assign m_axis.tdata = s_axis.tdata;
|
||||
assign m_axis.tkeep = KEEP_EN ? s_axis.tkeep : '1;
|
||||
assign m_axis.tstrb = STRB_EN ? s_axis.tstrb : s_axis.tkeep;
|
||||
assign m_axis.tvalid = s_axis.tvalid;
|
||||
assign m_axis.tlast = LAST_EN ? s_axis.tlast : 1'b1;
|
||||
assign m_axis.tid = ID_EN ? s_axis.tid : '0;
|
||||
assign m_axis.tdest = DEST_EN ? s_axis.tdest : '0;
|
||||
assign m_axis.tuser = USER_EN ? s_axis.tuser : '0;
|
||||
|
||||
assign s_axis.tready = m_axis.tready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
80
src/axis/syn/vivado/taxi_axis_async_fifo.tcl
Normal file
80
src/axis/syn/vivado/taxi_axis_async_fifo.tcl
Normal file
@@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2019-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# AXI stream asynchronous FIFO timing constraints
|
||||
|
||||
foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_axis_async_fifo || REF_NAME == taxi_axis_async_fifo)}] {
|
||||
puts "Inserting timing constraints for taxi_axis_async_fifo instance $fifo_inst"
|
||||
|
||||
# get clock periods
|
||||
set write_clk [get_clocks -of_objects [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/rd_ptr_gray_sync1_reg_reg[*]"]]
|
||||
set read_clk [get_clocks -of_objects [get_cells -quiet "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"]]
|
||||
|
||||
set write_clk_period [if {[llength $write_clk]} {get_property -min PERIOD $write_clk} {expr 1.0}]
|
||||
set read_clk_period [if {[llength $read_clk]} {get_property -min PERIOD $read_clk} {expr 1.0}]
|
||||
|
||||
set min_clk_period [expr min($write_clk_period, $read_clk_period)]
|
||||
|
||||
# pointer synchronization
|
||||
set sync_ffs [get_cells -quiet -hier -regexp ".*/rd_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"]
|
||||
|
||||
if {[llength $sync_ffs]} {
|
||||
set_property ASYNC_REG TRUE $sync_ffs
|
||||
|
||||
set_max_delay -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/rd_ptr_gray_sync1_reg_reg[*]"] -datapath_only $read_clk_period
|
||||
set_bus_skew -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/rd_ptr_gray_sync1_reg_reg[*]"] $write_clk_period
|
||||
}
|
||||
|
||||
set sync_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"]
|
||||
|
||||
if {[llength $sync_ffs]} {
|
||||
set_property ASYNC_REG TRUE $sync_ffs
|
||||
|
||||
set_max_delay -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] -datapath_only $write_clk_period
|
||||
set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] $read_clk_period
|
||||
}
|
||||
|
||||
set sync_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_commit_sync_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"]
|
||||
|
||||
if {[llength $sync_ffs]} {
|
||||
set_property ASYNC_REG TRUE $sync_ffs
|
||||
|
||||
set_max_delay -from [get_cells -quiet "$fifo_inst/wr_ptr_sync_commit_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_commit_sync_reg_reg[*]"] -datapath_only $write_clk_period
|
||||
set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_sync_commit_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_commit_sync_reg_reg[*]"] $read_clk_period
|
||||
}
|
||||
|
||||
# output register (needed for distributed RAM sync write/async read)
|
||||
set output_reg_ffs [get_cells -quiet "$fifo_inst/mem_rd_data_pipe_reg_reg[0][*]"]
|
||||
|
||||
if {[llength $output_reg_ffs]} {
|
||||
if {[llength $write_clk]} {
|
||||
set_false_path -from $write_clk -to $output_reg_ffs
|
||||
}
|
||||
}
|
||||
|
||||
# frame FIFO pointer update synchronization
|
||||
set update_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_update(_ack)?_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
|
||||
|
||||
if {[llength $update_ffs]} {
|
||||
set_property ASYNC_REG TRUE $update_ffs
|
||||
|
||||
set_max_delay -from [get_cells "$fifo_inst/wr_ptr_update_reg_reg"] -to [get_cells "$fifo_inst/wr_ptr_update_sync1_reg_reg"] -datapath_only $write_clk_period
|
||||
set_max_delay -from [get_cells "$fifo_inst/wr_ptr_update_sync3_reg_reg"] -to [get_cells "$fifo_inst/wr_ptr_update_ack_sync1_reg_reg"] -datapath_only $read_clk_period
|
||||
}
|
||||
|
||||
# status synchronization
|
||||
foreach i {overflow bad_frame good_frame} {
|
||||
set status_sync_regs [get_cells -quiet -hier -regexp ".*/${i}_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
|
||||
|
||||
if {[llength $status_sync_regs]} {
|
||||
set_property ASYNC_REG TRUE $status_sync_regs
|
||||
|
||||
set_max_delay -from [get_cells "$fifo_inst/${i}_sync1_reg_reg"] -to [get_cells "$fifo_inst/${i}_sync2_reg_reg"] -datapath_only $read_clk_period
|
||||
}
|
||||
}
|
||||
}
|
||||
64
src/axis/tb/taxi_axis_adapter/Makefile
Normal file
64
src/axis/tb/taxi_axis_adapter/Makefile
Normal file
@@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_adapter
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_DATA_W := 8
|
||||
export PARAM_S_KEEP_EN := $(shell expr $(PARAM_S_DATA_W) \> 8 )
|
||||
export PARAM_S_KEEP_W := $(shell expr \( $(PARAM_S_DATA_W) + 7 \) / 8 )
|
||||
export PARAM_S_STRB_EN := 0
|
||||
export PARAM_M_DATA_W := 8
|
||||
export PARAM_M_KEEP_EN := $(shell expr $(PARAM_M_DATA_W) \> 8 )
|
||||
export PARAM_M_KEEP_W := $(shell expr \( $(PARAM_M_DATA_W) + 7 \) / 8 )
|
||||
export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
266
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.py
Normal file
266
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.py
Normal file
@@ -0,0 +1,266 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
# set tkeep to all zeros when disabled to verify correct handling
|
||||
if not int(dut.S_KEEP_EN.value):
|
||||
test_frame.tkeep = [0]*len(test_data)
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = max(len(cocotb.top.s_axis.tdata), len(cocotb.top.m_axis.tdata))
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("m_data_width", [8, 16, 32])
|
||||
@pytest.mark.parametrize("s_data_width", [8, 16, 32])
|
||||
def test_taxi_axis_register(request, s_data_width, m_data_width):
|
||||
dut = "taxi_axis_adapter"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_DATA_W'] = s_data_width
|
||||
parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
|
||||
parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
|
||||
parameters['S_STRB_EN'] = 0
|
||||
parameters['M_DATA_W'] = m_data_width
|
||||
parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
|
||||
parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
|
||||
parameters['M_STRB_EN'] = parameters['S_STRB_EN']
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
88
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv
Normal file
88
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv
Normal file
@@ -0,0 +1,88 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream FIFO testbench
|
||||
*/
|
||||
module test_taxi_axis_adapter #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter S_DATA_W = 8,
|
||||
parameter logic S_KEEP_EN = (S_DATA_W>8),
|
||||
parameter S_KEEP_W = ((S_DATA_W+7)/8),
|
||||
parameter logic S_STRB_EN = 0,
|
||||
parameter M_DATA_W = 8,
|
||||
parameter logic M_KEEP_EN = (M_DATA_W>8),
|
||||
parameter M_KEEP_W = ((M_DATA_W+7)/8),
|
||||
parameter logic M_STRB_EN = 0,
|
||||
parameter logic ID_EN = 0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1,
|
||||
parameter USER_W = 1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(S_DATA_W),
|
||||
.KEEP_EN(S_KEEP_EN),
|
||||
.KEEP_W(S_KEEP_W),
|
||||
.STRB_EN(S_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(M_DATA_W),
|
||||
.KEEP_EN(M_KEEP_EN),
|
||||
.KEEP_W(M_KEEP_W),
|
||||
.STRB_EN(M_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) m_axis();
|
||||
|
||||
taxi_axis_adapter
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
65
src/axis/tb/taxi_axis_arb_mux/Makefile
Normal file
65
src/axis/tb/taxi_axis_arb_mux/Makefile
Normal file
@@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_arb_mux
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_COUNT := 4
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
|
||||
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_S_ID_W := 8
|
||||
export PARAM_M_ID_W := $(shell python -c "print($(PARAM_S_ID_W) + ($(PARAM_S_COUNT)-1).bit_length())")
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_UPDATE_TID := 1
|
||||
export PARAM_ARB_ROUND_ROBIN := 0
|
||||
export PARAM_ARB_LSB_HIGH_PRIO := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
365
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py
Normal file
365
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py
Normal file
@@ -0,0 +1,365 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Event
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.s_axis]
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
for source in self.source:
|
||||
source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, port=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_width = len(tb.source[0].bus.tid)
|
||||
id_count = 2**id_width
|
||||
id_mask = id_count-1
|
||||
|
||||
src_width = (len(tb.source)-1).bit_length()
|
||||
src_mask = 2**src_width-1 if src_width else 0
|
||||
src_shift = id_width-src_width
|
||||
max_count = 2**src_shift
|
||||
count_mask = max_count-1
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id | (port << src_shift)
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[port].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % max_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert (rx_frame.tid & id_mask) == test_frame.tid
|
||||
assert ((rx_frame.tid >> src_shift) & src_mask) == port
|
||||
assert (rx_frame.tid >> id_width) == port
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut, port=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source[port].send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_arb_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source[0].byte_lanes
|
||||
id_width = len(tb.source[0].bus.tid)
|
||||
id_count = 2**id_width
|
||||
id_mask = id_count-1
|
||||
|
||||
src_width = (len(tb.source)-1).bit_length()
|
||||
src_mask = 2**src_width-1 if src_width else 0
|
||||
src_shift = id_width-src_width
|
||||
max_count = 2**src_shift
|
||||
count_mask = max_count-1
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_frames = []
|
||||
|
||||
length = byte_lanes*16
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
for k in range(5):
|
||||
test_frame = AxiStreamFrame(test_data, tx_complete=Event())
|
||||
|
||||
src_ind = 0
|
||||
|
||||
if k == 0:
|
||||
src_ind = 0
|
||||
elif k == 4:
|
||||
await test_frames[1].tx_complete.wait()
|
||||
for j in range(8):
|
||||
await RisingEdge(dut.clk)
|
||||
src_ind = 0
|
||||
else:
|
||||
src_ind = 1
|
||||
|
||||
test_frame.tid = cur_id | (src_ind << src_shift)
|
||||
test_frame.tdest = 0
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[src_ind].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % max_count
|
||||
|
||||
for k in [0, 1, 2, 4, 3]:
|
||||
test_frame = test_frames[k]
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert (rx_frame.tid & id_mask) == test_frame.tid
|
||||
assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width)
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source[0].byte_lanes
|
||||
id_width = len(tb.source[0].bus.tid)
|
||||
id_count = 2**id_width
|
||||
id_mask = id_count-1
|
||||
|
||||
src_width = (len(tb.source)-1).bit_length()
|
||||
src_mask = 2**src_width-1 if src_width else 0
|
||||
src_shift = id_width-src_width
|
||||
max_count = 2**src_shift
|
||||
count_mask = max_count-1
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = [list() for x in tb.source]
|
||||
|
||||
for p in range(len(tb.source)):
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id | (p << src_shift)
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames[p].append(test_frame)
|
||||
await tb.source[p].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % max_count
|
||||
|
||||
while any(test_frames):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
test_frame = None
|
||||
|
||||
for lst in test_frames:
|
||||
if lst and lst[0].tid == (rx_frame.tid & id_mask):
|
||||
test_frame = lst.pop(0)
|
||||
break
|
||||
|
||||
assert test_frame is not None
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert (rx_frame.tid & id_mask) == test_frame.tid
|
||||
assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width)
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
ports = len(cocotb.top.s_axis)
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("port", list(range(ports)))
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("port", list(range(ports)))
|
||||
factory.generate_tests()
|
||||
|
||||
if ports > 1:
|
||||
factory = TestFactory(run_arb_test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("round_robin", [0, 1])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("s_count", [1, 4])
|
||||
def test_taxi_axis_arb_mux(request, s_count, data_w, round_robin):
|
||||
dut = "taxi_axis_arb_mux"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_COUNT'] = s_count
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['S_ID_W'] = 8
|
||||
parameters['M_ID_W'] = parameters['S_ID_W'] + (s_count-1).bit_length()
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['UPDATE_TID'] = 1
|
||||
parameters['ARB_ROUND_ROBIN'] = round_robin
|
||||
parameters['ARB_LSB_HIGH_PRIO'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
95
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv
Normal file
95
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv
Normal file
@@ -0,0 +1,95 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream arbitrated multiplexer testbench
|
||||
*/
|
||||
module test_taxi_axis_arb_mux #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter S_COUNT = 4,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter S_ID_W = 8,
|
||||
parameter M_ID_W = S_ID_W+$clog2(S_COUNT),
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter logic UPDATE_TID = 1'b0,
|
||||
parameter logic ARB_ROUND_ROBIN = 1'b0,
|
||||
parameter logic ARB_LSB_HIGH_PRIO = 1'b1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(S_ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis[S_COUNT]();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(M_ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) m_axis();
|
||||
|
||||
taxi_axis_arb_mux #(
|
||||
.S_COUNT(S_COUNT),
|
||||
.UPDATE_TID(UPDATE_TID),
|
||||
.ARB_ROUND_ROBIN(ARB_ROUND_ROBIN),
|
||||
.ARB_LSB_HIGH_PRIO(ARB_LSB_HIGH_PRIO)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
72
src/axis/tb/taxi_axis_async_fifo/Makefile
Normal file
72
src/axis/tb/taxi_axis_async_fifo/Makefile
Normal file
@@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_async_fifo
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_W) )))
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_RAM_PIPELINE := 1
|
||||
export PARAM_OUTPUT_FIFO_EN := 0
|
||||
export PARAM_FRAME_FIFO := 1
|
||||
export PARAM_USER_BAD_FRAME_VALUE := 1
|
||||
export PARAM_USER_BAD_FRAME_MASK := 1
|
||||
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
|
||||
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_DROP_WHEN_FULL := 0
|
||||
export PARAM_MARK_WHEN_FULL := 0
|
||||
export PARAM_PAUSE_EN := 1
|
||||
export PARAM_FRAME_PAUSE := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
735
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py
Normal file
735
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py
Normal file
@@ -0,0 +1,735 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
s_clk = int(os.getenv("S_CLK_PERIOD", "10"))
|
||||
m_clk = int(os.getenv("M_CLK_PERIOD", "11"))
|
||||
|
||||
cocotb.start_soon(Clock(dut.s_clk, s_clk, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.m_clk, m_clk, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.s_clk, dut.s_rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.m_clk, dut.m_rst)
|
||||
|
||||
dut.s_pause_req.setimmediatevalue(0)
|
||||
dut.m_pause_req.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.m_rst.setimmediatevalue(0)
|
||||
self.dut.s_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.m_rst.value = 1
|
||||
self.dut.s_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.m_rst.value = 0
|
||||
self.dut.s_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
|
||||
async def reset_source(self):
|
||||
self.dut.s_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.s_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.s_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
|
||||
async def reset_sink(self):
|
||||
self.dut.m_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
self.dut.m_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
self.dut.m_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
if int(dut.DROP_BAD_FRAME.value):
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 512))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(1024):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_in_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
if int(dut.FRAME_FIFO.value):
|
||||
assert tb.sink.empty()
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_in_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_out_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
await RisingEdge(dut.m_axis.tvalid)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_out_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
await RisingEdge(dut.m_axis.tvalid)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
|
||||
for k in range(16):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
dut.m_pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.m_pause_req.value = 0
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
dut.s_pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.s_pause_req.value = 0
|
||||
|
||||
for k in range(16):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
size = (16*byte_lanes)
|
||||
count = depth*2 // size
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
for k in range(count):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
assert tb.source.idle()
|
||||
else:
|
||||
assert not tb.source.idle()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_count = 0
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
rx_count += 1
|
||||
|
||||
assert rx_count < count
|
||||
|
||||
else:
|
||||
for k in range(count):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_oversize(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_OVERSIZE_FRAME.value):
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value):
|
||||
assert rx_frame.tuser
|
||||
else:
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(512):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
cycles = 0
|
||||
while cycles < 100:
|
||||
cycles += 1
|
||||
if not tb.source.idle() or int(dut.s_axis.tvalid.value) or int(dut.m_axis.tvalid.value) or int(dut.m_status_depth.value):
|
||||
cycles = 0
|
||||
await RisingEdge(dut.m_clk)
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert not rx_frame.tuser
|
||||
|
||||
while True:
|
||||
test_frame = test_frames.pop(0)
|
||||
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
|
||||
break
|
||||
|
||||
assert len(test_frames) < 512
|
||||
|
||||
else:
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_init_sink_pause_source_reset,
|
||||
run_test_init_sink_pause_sink_reset,
|
||||
run_test_shift_in_source_reset,
|
||||
run_test_shift_in_sink_reset,
|
||||
run_test_shift_out_source_reset,
|
||||
run_test_shift_out_sink_reset,
|
||||
run_test_pause,
|
||||
run_test_overflow,
|
||||
run_test_oversize
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("s_clk", "m_clk"), [(10, 10), (10, 11), (11, 10)])
|
||||
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
|
||||
"drop_when_full", "mark_when_full"),
|
||||
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
|
||||
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
|
||||
@pytest.mark.parametrize(("ram_pipeline", "output_fifo"),
|
||||
[(0, 0), (1, 0), (4, 0), (0, 1), (1, 1), (4, 1)])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32, 64])
|
||||
def test_taxi_axis_async_fifo(request, data_w, ram_pipeline, output_fifo,
|
||||
frame_fifo, drop_oversize_frame, drop_bad_frame,
|
||||
drop_when_full, mark_when_full, s_clk, m_clk):
|
||||
|
||||
dut = "taxi_axis_async_fifo"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['DEPTH'] = 1024 * parameters['KEEP_W']
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['RAM_PIPELINE'] = ram_pipeline
|
||||
parameters['OUTPUT_FIFO_EN'] = output_fifo
|
||||
parameters['FRAME_FIFO'] = frame_fifo
|
||||
parameters['USER_BAD_FRAME_VALUE'] = 1
|
||||
parameters['USER_BAD_FRAME_MASK'] = 1
|
||||
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
|
||||
parameters['DROP_BAD_FRAME'] = drop_bad_frame
|
||||
parameters['DROP_WHEN_FULL'] = drop_when_full
|
||||
parameters['MARK_WHEN_FULL'] = mark_when_full
|
||||
parameters['PAUSE_EN'] = 1
|
||||
parameters['FRAME_PAUSE'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
extra_env['S_CLK_PERIOD'] = str(s_clk)
|
||||
extra_env['M_CLK_PERIOD'] = str(m_clk)
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
138
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv
Normal file
138
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv
Normal file
@@ -0,0 +1,138 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream asynchronous FIFO testbench
|
||||
*/
|
||||
module test_taxi_axis_async_fifo #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DEPTH = 4096,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter RAM_PIPELINE = 1,
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic s_clk;
|
||||
logic s_rst;
|
||||
|
||||
logic m_clk;
|
||||
logic m_rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
logic s_pause_req;
|
||||
logic s_pause_ack;
|
||||
logic m_pause_req;
|
||||
logic m_pause_ack;
|
||||
|
||||
logic [$clog2(DEPTH):0] s_status_depth;
|
||||
logic [$clog2(DEPTH):0] s_status_depth_commit;
|
||||
logic s_status_overflow;
|
||||
logic s_status_bad_frame;
|
||||
logic s_status_good_frame;
|
||||
logic [$clog2(DEPTH):0] m_status_depth;
|
||||
logic [$clog2(DEPTH):0] m_status_depth_commit;
|
||||
logic m_status_overflow;
|
||||
logic m_status_bad_frame;
|
||||
logic m_status_good_frame;
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
uut (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(s_clk),
|
||||
.s_rst(s_rst),
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(m_clk),
|
||||
.m_rst(m_rst),
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(s_pause_req),
|
||||
.s_pause_ack(s_pause_ack),
|
||||
.m_pause_req(m_pause_req),
|
||||
.m_pause_ack(m_pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(s_status_depth),
|
||||
.s_status_depth_commit(s_status_depth_commit),
|
||||
.s_status_overflow(s_status_overflow),
|
||||
.s_status_bad_frame(s_status_bad_frame),
|
||||
.s_status_good_frame(s_status_good_frame),
|
||||
.m_status_depth(m_status_depth),
|
||||
.m_status_depth_commit(m_status_depth_commit),
|
||||
.m_status_overflow(m_status_overflow),
|
||||
.m_status_bad_frame(m_status_bad_frame),
|
||||
.m_status_good_frame(m_status_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
75
src/axis/tb/taxi_axis_async_fifo_adapter/Makefile
Normal file
75
src/axis/tb/taxi_axis_async_fifo_adapter/Makefile
Normal file
@@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_async_fifo_adapter
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_DATA_W := 8
|
||||
export PARAM_S_KEEP_EN := $(shell echo $$(( $(PARAM_S_DATA_W) > 8 )))
|
||||
export PARAM_S_KEEP_W := $(shell echo $$(( ( $(PARAM_S_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_S_STRB_EN := 0
|
||||
export PARAM_M_DATA_W := 8
|
||||
export PARAM_M_KEEP_EN := $(shell echo $$(( $(PARAM_M_DATA_W) > 8 )))
|
||||
export PARAM_M_KEEP_W := $(shell echo $$(( ( $(PARAM_M_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
|
||||
export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_W) > $(PARAM_M_KEEP_W) ? $(PARAM_S_KEEP_W) : $(PARAM_M_KEEP_W)) )))
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_RAM_PIPELINE := 1
|
||||
export PARAM_OUTPUT_FIFO_EN := 0
|
||||
export PARAM_FRAME_FIFO := 1
|
||||
export PARAM_USER_BAD_FRAME_VALUE := 1
|
||||
export PARAM_USER_BAD_FRAME_MASK := 1
|
||||
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
|
||||
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_DROP_WHEN_FULL := 0
|
||||
export PARAM_MARK_WHEN_FULL := 0
|
||||
export PARAM_PAUSE_EN := 1
|
||||
export PARAM_FRAME_PAUSE := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,731 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
s_clk = int(os.getenv("S_CLK_PERIOD", "10"))
|
||||
m_clk = int(os.getenv("M_CLK_PERIOD", "11"))
|
||||
|
||||
cocotb.start_soon(Clock(dut.s_clk, s_clk, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.m_clk, m_clk, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.s_clk, dut.s_rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.m_clk, dut.m_rst)
|
||||
|
||||
dut.s_pause_req.setimmediatevalue(0)
|
||||
dut.m_pause_req.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.m_rst.setimmediatevalue(0)
|
||||
self.dut.s_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.m_rst.value = 1
|
||||
self.dut.s_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.m_rst.value = 0
|
||||
self.dut.s_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
|
||||
async def reset_source(self):
|
||||
self.dut.s_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.s_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.s_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
|
||||
async def reset_sink(self):
|
||||
self.dut.m_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
self.dut.m_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
self.dut.m_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
if int(dut.DROP_BAD_FRAME.value):
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_in_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
if int(dut.FRAME_FIFO.value):
|
||||
assert tb.sink.empty()
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_in_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_out_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
await RisingEdge(dut.m_axis.tvalid)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_out_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
await RisingEdge(dut.m_axis.tvalid)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
|
||||
for k in range(16):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
dut.m_pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.m_pause_req.value = 0
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
dut.s_pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.s_pause_req.value = 0
|
||||
|
||||
for k in range(16):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
size = (16*byte_lanes)
|
||||
count = depth*2 // size
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
for k in range(count):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
assert tb.source.idle()
|
||||
else:
|
||||
assert not tb.source.idle()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_count = 0
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
rx_count += 1
|
||||
|
||||
assert rx_count < count
|
||||
|
||||
else:
|
||||
for k in range(count):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_oversize(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_OVERSIZE_FRAME.value):
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value):
|
||||
assert rx_frame.tuser
|
||||
else:
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(512):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
|
||||
cycles = 0
|
||||
while cycles < 100:
|
||||
cycles += 1
|
||||
if not tb.source.idle() or dut.s_axis.tvalid.value.integer or dut.m_axis.tvalid.value.integer or dut.m_status_depth.value.integer:
|
||||
cycles = 0
|
||||
await RisingEdge(dut.m_clk)
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert not rx_frame.tuser
|
||||
|
||||
while True:
|
||||
test_frame = test_frames.pop(0)
|
||||
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
|
||||
break
|
||||
|
||||
assert len(test_frames) < 512
|
||||
|
||||
else:
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = max(len(cocotb.top.m_axis.tdata), len(cocotb.top.s_axis.tdata))
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_init_sink_pause_source_reset,
|
||||
run_test_init_sink_pause_sink_reset,
|
||||
run_test_shift_in_source_reset,
|
||||
run_test_shift_in_sink_reset,
|
||||
run_test_shift_out_source_reset,
|
||||
run_test_shift_out_sink_reset,
|
||||
run_test_pause,
|
||||
run_test_overflow,
|
||||
run_test_oversize
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
|
||||
"drop_when_full", "mark_when_full"),
|
||||
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
|
||||
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
|
||||
@pytest.mark.parametrize("m_data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("s_data_w", [8, 16, 32])
|
||||
def test_taxi_axis_async_fifo_adapter(request, s_data_w, m_data_w,
|
||||
frame_fifo, drop_oversize_frame, drop_bad_frame,
|
||||
drop_when_full, mark_when_full):
|
||||
|
||||
dut = "taxi_axis_async_fifo_adapter"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_DATA_W'] = s_data_w
|
||||
parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
|
||||
parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
|
||||
parameters['M_DATA_W'] = m_data_w
|
||||
parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
|
||||
parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
|
||||
parameters['DEPTH'] = 1024 * max(parameters['S_KEEP_W'], parameters['M_KEEP_W'])
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['RAM_PIPELINE'] = 1
|
||||
parameters['OUTPUT_FIFO_EN'] = 0
|
||||
parameters['FRAME_FIFO'] = frame_fifo
|
||||
parameters['USER_BAD_FRAME_VALUE'] = 1
|
||||
parameters['USER_BAD_FRAME_MASK'] = 1
|
||||
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
|
||||
parameters['DROP_BAD_FRAME'] = drop_bad_frame
|
||||
parameters['DROP_WHEN_FULL'] = drop_when_full
|
||||
parameters['MARK_WHEN_FULL'] = mark_when_full
|
||||
parameters['PAUSE_EN'] = 1
|
||||
parameters['FRAME_PAUSE'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,153 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream asynchronous FIFO with width converter testbench
|
||||
*/
|
||||
module test_taxi_axis_async_fifo_adapter #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DEPTH = 4096,
|
||||
parameter S_DATA_W = 8,
|
||||
parameter logic S_KEEP_EN = (S_DATA_W>8),
|
||||
parameter S_KEEP_W = ((S_DATA_W+7)/8),
|
||||
parameter logic S_STRB_EN = 0,
|
||||
parameter M_DATA_W = 8,
|
||||
parameter logic M_KEEP_EN = (M_DATA_W>8),
|
||||
parameter M_KEEP_W = ((M_DATA_W+7)/8),
|
||||
parameter logic M_STRB_EN = 0,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter RAM_PIPELINE = 1,
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic s_clk;
|
||||
logic s_rst;
|
||||
taxi_axis_if #(
|
||||
.DATA_W(S_DATA_W),
|
||||
.KEEP_EN(S_KEEP_EN),
|
||||
.KEEP_W(S_KEEP_W),
|
||||
.STRB_EN(S_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis();
|
||||
|
||||
logic m_clk;
|
||||
logic m_rst;
|
||||
taxi_axis_if #(
|
||||
.DATA_W(M_DATA_W),
|
||||
.KEEP_EN(M_KEEP_EN),
|
||||
.KEEP_W(M_KEEP_W),
|
||||
.STRB_EN(M_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) m_axis();
|
||||
|
||||
logic s_pause_req;
|
||||
logic s_pause_ack;
|
||||
logic m_pause_req;
|
||||
logic m_pause_ack;
|
||||
|
||||
logic [$clog2(DEPTH):0] s_status_depth;
|
||||
logic [$clog2(DEPTH):0] s_status_depth_commit;
|
||||
logic s_status_overflow;
|
||||
logic s_status_bad_frame;
|
||||
logic s_status_good_frame;
|
||||
logic [$clog2(DEPTH):0] m_status_depth;
|
||||
logic [$clog2(DEPTH):0] m_status_depth_commit;
|
||||
logic m_status_overflow;
|
||||
logic m_status_bad_frame;
|
||||
logic m_status_good_frame;
|
||||
|
||||
taxi_axis_async_fifo_adapter #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
uut (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(s_clk),
|
||||
.s_rst(s_rst),
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(m_clk),
|
||||
.m_rst(m_rst),
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(s_pause_req),
|
||||
.s_pause_ack(s_pause_ack),
|
||||
.m_pause_req(m_pause_req),
|
||||
.m_pause_ack(m_pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(s_status_depth),
|
||||
.s_status_depth_commit(s_status_depth_commit),
|
||||
.s_status_overflow(s_status_overflow),
|
||||
.s_status_bad_frame(s_status_bad_frame),
|
||||
.s_status_good_frame(s_status_good_frame),
|
||||
.m_status_depth(m_status_depth),
|
||||
.m_status_depth_commit(m_status_depth_commit),
|
||||
.m_status_overflow(m_status_overflow),
|
||||
.m_status_bad_frame(m_status_bad_frame),
|
||||
.m_status_good_frame(m_status_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_broadcast/Makefile
Normal file
62
src/axis/tb/taxi_axis_broadcast/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_broadcast
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_M_COUNT := 4
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
|
||||
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
190
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.py
Normal file
190
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.py
Normal file
@@ -0,0 +1,190 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = [AxiStreamSink(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.m_axis]
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
for sink in self.sink:
|
||||
sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
for sink in tb.sink:
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
for sink in tb.sink:
|
||||
assert sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.s_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("m_count", range(1, 4))
|
||||
def test_taxi_axis_broadcast(request, m_count, data_w):
|
||||
dut = "taxi_axis_broadcast"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['M_COUNT'] = m_count
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
74
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv
Normal file
74
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv
Normal file
@@ -0,0 +1,74 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream broadcaster testbench
|
||||
*/
|
||||
module test_taxi_axis_broadcast #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter M_COUNT = 4,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis[M_COUNT]();
|
||||
|
||||
taxi_axis_broadcast #(
|
||||
.M_COUNT(M_COUNT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
51
src/axis/tb/taxi_axis_cobs_decode/Makefile
Normal file
51
src/axis/tb/taxi_axis_cobs_decode/Makefile
Normal file
@@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_cobs_decode
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
#export PARAM_APPEND_ZERO := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
243
src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py
Normal file
243
src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py
Normal file
@@ -0,0 +1,243 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
def cobs_encode(block):
|
||||
block = bytearray(block)
|
||||
enc = bytearray()
|
||||
|
||||
seg = bytearray()
|
||||
code = 1
|
||||
|
||||
new_data = True
|
||||
|
||||
for b in block:
|
||||
if b == 0:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
code = 1
|
||||
seg = bytearray()
|
||||
new_data = True
|
||||
else:
|
||||
code += 1
|
||||
seg.append(b)
|
||||
new_data = True
|
||||
if code == 255:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
code = 1
|
||||
seg = bytearray()
|
||||
new_data = False
|
||||
|
||||
if new_data:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
|
||||
return bytes(enc)
|
||||
|
||||
|
||||
def cobs_decode(block):
|
||||
block = bytearray(block)
|
||||
dec = bytearray()
|
||||
|
||||
code = 0
|
||||
|
||||
i = 0
|
||||
|
||||
if 0 in block:
|
||||
return None
|
||||
|
||||
while i < len(block):
|
||||
code = block[i]
|
||||
i += 1
|
||||
if i+code-1 > len(block):
|
||||
return None
|
||||
dec.extend(block[i:i+code-1])
|
||||
i += code-1
|
||||
if code < 255 and i < len(block):
|
||||
dec.append(0)
|
||||
|
||||
return bytes(dec)
|
||||
|
||||
|
||||
def prbs31(state=0x7fffffff):
|
||||
while True:
|
||||
for i in range(8):
|
||||
if bool(state & 0x08000000) ^ bool(state & 0x40000000):
|
||||
state = ((state & 0x3fffffff) << 1) | 1
|
||||
else:
|
||||
state = (state & 0x3fffffff) << 1
|
||||
yield state & 0xff
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
enc = cobs_encode(test_data)
|
||||
test_frame = AxiStreamFrame(enc)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(1, 33))+list(range(253, 259))+[512]+[1]*64
|
||||
|
||||
|
||||
def zero_payload(length):
|
||||
return bytearray(length)
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
def nonzero_incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(1, 256)), length))
|
||||
|
||||
|
||||
def nonzero_incrementing_payload_zero_framed(length):
|
||||
return bytearray([0]+list(itertools.islice(itertools.cycle(range(1, 256)), length))+[0])
|
||||
|
||||
|
||||
def prbs_payload(length):
|
||||
gen = prbs31()
|
||||
return bytearray([next(gen) for x in range(length)])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [zero_payload, nonzero_incrementing_payload, nonzero_incrementing_payload_zero_framed, prbs_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_taxi_axis_cobs_decode(request):
|
||||
dut = "taxi_axis_cobs_decode"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,48 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream COBS decoder testbench
|
||||
*/
|
||||
module test_taxi_axis_cobs_decode();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(8),
|
||||
.LAST_EN(1),
|
||||
.USER_EN(1),
|
||||
.USER_W(1)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_cobs_decode
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
50
src/axis/tb/taxi_axis_cobs_encode/Makefile
Normal file
50
src/axis/tb/taxi_axis_cobs_encode/Makefile
Normal file
@@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_cobs_encode
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_APPEND_ZERO := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
252
src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py
Normal file
252
src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py
Normal file
@@ -0,0 +1,252 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
def cobs_encode(block):
|
||||
block = bytearray(block)
|
||||
enc = bytearray()
|
||||
|
||||
seg = bytearray()
|
||||
code = 1
|
||||
|
||||
new_data = True
|
||||
|
||||
for b in block:
|
||||
if b == 0:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
code = 1
|
||||
seg = bytearray()
|
||||
new_data = True
|
||||
else:
|
||||
code += 1
|
||||
seg.append(b)
|
||||
new_data = True
|
||||
if code == 255:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
code = 1
|
||||
seg = bytearray()
|
||||
new_data = False
|
||||
|
||||
if new_data:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
|
||||
return bytes(enc)
|
||||
|
||||
|
||||
def cobs_decode(block):
|
||||
block = bytearray(block)
|
||||
dec = bytearray()
|
||||
|
||||
code = 0
|
||||
|
||||
i = 0
|
||||
|
||||
if 0 in block:
|
||||
return None
|
||||
|
||||
while i < len(block):
|
||||
code = block[i]
|
||||
i += 1
|
||||
if i+code-1 > len(block):
|
||||
return None
|
||||
dec.extend(block[i:i+code-1])
|
||||
i += code-1
|
||||
if code < 255 and i < len(block):
|
||||
dec.append(0)
|
||||
|
||||
return bytes(dec)
|
||||
|
||||
|
||||
def prbs31(state=0x7fffffff):
|
||||
while True:
|
||||
for i in range(8):
|
||||
if bool(state & 0x08000000) ^ bool(state & 0x40000000):
|
||||
state = ((state & 0x3fffffff) << 1) | 1
|
||||
else:
|
||||
state = (state & 0x3fffffff) << 1
|
||||
yield state & 0xff
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
append_zero = int(os.getenv("PARAM_APPEND_ZERO"))
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if append_zero:
|
||||
assert rx_frame.tdata == cobs_encode(test_data)+b'\x00'
|
||||
assert cobs_decode(rx_frame.tdata[:-1]) == test_data
|
||||
else:
|
||||
assert rx_frame.tdata == cobs_encode(test_data)
|
||||
assert cobs_decode(rx_frame.tdata) == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(1, 33))+list(range(253, 259))+[512]+[1]*64
|
||||
|
||||
|
||||
def zero_payload(length):
|
||||
return bytearray(length)
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
def nonzero_incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(1, 256)), length))
|
||||
|
||||
|
||||
def nonzero_incrementing_payload_zero_framed(length):
|
||||
return bytearray([0]+list(itertools.islice(itertools.cycle(range(1, 256)), length))+[0])
|
||||
|
||||
|
||||
def prbs_payload(length):
|
||||
gen = prbs31()
|
||||
return bytearray([next(gen) for x in range(length)])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [zero_payload, nonzero_incrementing_payload, nonzero_incrementing_payload_zero_framed, prbs_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("append_zero", [0, 1])
|
||||
def test_taxi_axis_cobs_encode(request, append_zero):
|
||||
dut = "taxi_axis_cobs_encode"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['APPEND_ZERO'] = append_zero
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,56 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream COBS encoder testbench
|
||||
*/
|
||||
module test_taxi_axis_cobs_encode #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter logic APPEND_ZERO = 1'b1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(8),
|
||||
.LAST_EN(1),
|
||||
.USER_EN(1),
|
||||
.USER_W(1)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_cobs_encode #(
|
||||
.APPEND_ZERO(APPEND_ZERO)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
73
src/axis/tb/taxi_axis_fifo/Makefile
Normal file
73
src/axis/tb/taxi_axis_fifo/Makefile
Normal file
@@ -0,0 +1,73 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_fifo
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_W) )))
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_RAM_PIPELINE := 1
|
||||
export PARAM_OUTPUT_FIFO_EN := 0
|
||||
export PARAM_FRAME_FIFO := 1
|
||||
export PARAM_USER_BAD_FRAME_VALUE := 1
|
||||
export PARAM_USER_BAD_FRAME_MASK := 1
|
||||
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
|
||||
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_DROP_WHEN_FULL := 0
|
||||
export PARAM_MARK_WHEN_FULL := 0
|
||||
export PARAM_PAUSE_EN := 1
|
||||
export PARAM_FRAME_PAUSE := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
514
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.py
Normal file
514
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.py
Normal file
@@ -0,0 +1,514 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
dut.pause_req.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
if dut.DROP_BAD_FRAME.value:
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
|
||||
for k in range(16):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.pause_req.value = 0
|
||||
|
||||
for k in range(16):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
size = (16*byte_lanes)
|
||||
count = depth*2 // size
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
for k in range(count):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
|
||||
assert tb.source.idle()
|
||||
else:
|
||||
assert not tb.source.idle()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
rx_count = 0
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
rx_count += 1
|
||||
|
||||
assert rx_count < count
|
||||
|
||||
else:
|
||||
for k in range(count):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_oversize(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if dut.DROP_OVERSIZE_FRAME.value:
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value:
|
||||
assert rx_frame.tuser
|
||||
else:
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(512):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
|
||||
cycles = 0
|
||||
while cycles < 100:
|
||||
cycles += 1
|
||||
if not tb.source.idle() or dut.s_axis.tvalid.value.integer or dut.m_axis.tvalid.value.integer or dut.status_depth.value.integer:
|
||||
cycles = 0
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert len(test_frames) > 0
|
||||
|
||||
while True:
|
||||
test_frame = test_frames.pop(0)
|
||||
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
|
||||
break
|
||||
|
||||
assert len(test_frames) < 512
|
||||
|
||||
else:
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_pause,
|
||||
run_test_overflow,
|
||||
run_test_oversize
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
|
||||
"drop_when_full", "mark_when_full"),
|
||||
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
|
||||
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
|
||||
@pytest.mark.parametrize(("ram_pipeline", "output_fifo"),
|
||||
[(0, 0), (1, 0), (4, 0), (0, 1), (1, 1), (4, 1)])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32, 64])
|
||||
def test_taxi_axis_fifo(request, data_w, ram_pipeline, output_fifo,
|
||||
frame_fifo, drop_oversize_frame, drop_bad_frame,
|
||||
drop_when_full, mark_when_full):
|
||||
|
||||
dut = "taxi_axis_fifo"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['DEPTH'] = 1024 * parameters['KEEP_W']
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['RAM_PIPELINE'] = ram_pipeline
|
||||
parameters['OUTPUT_FIFO_EN'] = output_fifo
|
||||
parameters['FRAME_FIFO'] = frame_fifo
|
||||
parameters['USER_BAD_FRAME_VALUE'] = 1
|
||||
parameters['USER_BAD_FRAME_MASK'] = 1
|
||||
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
|
||||
parameters['DROP_BAD_FRAME'] = drop_bad_frame
|
||||
parameters['DROP_WHEN_FULL'] = drop_when_full
|
||||
parameters['MARK_WHEN_FULL'] = mark_when_full
|
||||
parameters['PAUSE_EN'] = 1
|
||||
parameters['FRAME_PAUSE'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
120
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.sv
Normal file
120
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.sv
Normal file
@@ -0,0 +1,120 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream FIFO testbench
|
||||
*/
|
||||
module test_taxi_axis_fifo #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DEPTH = 4096,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter RAM_PIPELINE = 1,
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
logic pause_req;
|
||||
logic pause_ack;
|
||||
|
||||
logic [$clog2(DEPTH):0] status_depth;
|
||||
logic [$clog2(DEPTH):0] status_depth_commit;
|
||||
logic status_overflow;
|
||||
logic status_bad_frame;
|
||||
logic status_good_frame;
|
||||
|
||||
taxi_axis_fifo #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.pause_req(pause_req),
|
||||
.pause_ack(pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_depth(status_depth),
|
||||
.status_depth_commit(status_depth_commit),
|
||||
.status_overflow(status_overflow),
|
||||
.status_bad_frame(status_bad_frame),
|
||||
.status_good_frame(status_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
75
src/axis/tb/taxi_axis_fifo_adapter/Makefile
Normal file
75
src/axis/tb/taxi_axis_fifo_adapter/Makefile
Normal file
@@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_fifo_adapter
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_DATA_W := 8
|
||||
export PARAM_S_KEEP_EN := $(shell echo $$(( $(PARAM_S_DATA_W) > 8 )))
|
||||
export PARAM_S_KEEP_W := $(shell echo $$(( ( $(PARAM_S_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_S_STRB_EN := 0
|
||||
export PARAM_M_DATA_W := 8
|
||||
export PARAM_M_KEEP_EN := $(shell echo $$(( $(PARAM_M_DATA_W) > 8 )))
|
||||
export PARAM_M_KEEP_W := $(shell echo $$(( ( $(PARAM_M_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
|
||||
export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_W) > $(PARAM_M_KEEP_W) ? $(PARAM_S_KEEP_W) : $(PARAM_M_KEEP_W)) )))
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_RAM_PIPELINE := 1
|
||||
export PARAM_OUTPUT_FIFO_EN := 0
|
||||
export PARAM_FRAME_FIFO := 1
|
||||
export PARAM_USER_BAD_FRAME_VALUE := 1
|
||||
export PARAM_USER_BAD_FRAME_MASK := 1
|
||||
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
|
||||
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_DROP_WHEN_FULL := 0
|
||||
export PARAM_MARK_WHEN_FULL := 0
|
||||
export PARAM_PAUSE_EN := 1
|
||||
export PARAM_FRAME_PAUSE := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,513 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
dut.pause_req.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
if int(dut.DROP_BAD_FRAME.value):
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
|
||||
for k in range(16):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.pause_req.value = 0
|
||||
|
||||
for k in range(16):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
size = (16*byte_lanes)
|
||||
count = depth*2 // size
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
for k in range(count):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
assert tb.source.idle()
|
||||
else:
|
||||
assert not tb.source.idle()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
rx_count = 0
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
rx_count += 1
|
||||
|
||||
assert rx_count < count
|
||||
|
||||
else:
|
||||
for k in range(count):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_oversize(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if dut.DROP_OVERSIZE_FRAME.value:
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value:
|
||||
assert rx_frame.tuser
|
||||
else:
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(512):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
cycles = 0
|
||||
while cycles < 100:
|
||||
cycles += 1
|
||||
if not tb.source.idle() or int(dut.s_axis.tvalid.value) or int(dut.m_axis.tvalid.value) or int(dut.status_depth.value):
|
||||
cycles = 0
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert not rx_frame.tuser
|
||||
|
||||
while True:
|
||||
test_frame = test_frames.pop(0)
|
||||
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
|
||||
break
|
||||
|
||||
assert len(test_frames) < 512
|
||||
|
||||
else:
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = max(len(cocotb.top.m_axis.tdata), len(cocotb.top.s_axis.tdata))
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_pause,
|
||||
run_test_overflow,
|
||||
run_test_oversize
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
|
||||
"drop_when_full", "mark_when_full"),
|
||||
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
|
||||
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
|
||||
@pytest.mark.parametrize("m_data_width", [8, 16, 32])
|
||||
@pytest.mark.parametrize("s_data_width", [8, 16, 32])
|
||||
def test_taxi_axis_fifo_adapter(request, s_data_width, m_data_width,
|
||||
frame_fifo, drop_oversize_frame, drop_bad_frame,
|
||||
drop_when_full, mark_when_full):
|
||||
|
||||
dut = "taxi_axis_fifo_adapter"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_DATA_W'] = s_data_width
|
||||
parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
|
||||
parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
|
||||
parameters['S_STRB_EN'] = 0
|
||||
parameters['M_DATA_W'] = m_data_width
|
||||
parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
|
||||
parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
|
||||
parameters['M_STRB_EN'] = parameters['S_STRB_EN']
|
||||
parameters['DEPTH'] = 1024 * max(parameters['S_KEEP_W'], parameters['M_KEEP_W'])
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['RAM_PIPELINE'] = 1
|
||||
parameters['OUTPUT_FIFO_EN'] = 0
|
||||
parameters['FRAME_FIFO'] = frame_fifo
|
||||
parameters['USER_BAD_FRAME_VALUE'] = 1
|
||||
parameters['USER_BAD_FRAME_MASK'] = 1
|
||||
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
|
||||
parameters['DROP_BAD_FRAME'] = drop_bad_frame
|
||||
parameters['DROP_WHEN_FULL'] = drop_when_full
|
||||
parameters['MARK_WHEN_FULL'] = mark_when_full
|
||||
parameters['PAUSE_EN'] = 1
|
||||
parameters['FRAME_PAUSE'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,137 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream FIFO with width converter testbench
|
||||
*/
|
||||
module test_taxi_axis_fifo_adapter #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DEPTH = 4096,
|
||||
parameter S_DATA_W = 8,
|
||||
parameter logic S_KEEP_EN = (S_DATA_W>8),
|
||||
parameter S_KEEP_W = ((S_DATA_W+7)/8),
|
||||
parameter logic S_STRB_EN = 0,
|
||||
parameter M_DATA_W = 8,
|
||||
parameter logic M_KEEP_EN = (M_DATA_W>8),
|
||||
parameter M_KEEP_W = ((M_DATA_W+7)/8),
|
||||
parameter logic M_STRB_EN = 0,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter RAM_PIPELINE = 1,
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(S_DATA_W),
|
||||
.KEEP_EN(S_KEEP_EN),
|
||||
.KEEP_W(S_KEEP_W),
|
||||
.STRB_EN(S_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(M_DATA_W),
|
||||
.KEEP_EN(M_KEEP_EN),
|
||||
.KEEP_W(M_KEEP_W),
|
||||
.STRB_EN(M_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) m_axis();
|
||||
|
||||
logic pause_req;
|
||||
logic pause_ack;
|
||||
|
||||
logic [$clog2(DEPTH):0] status_depth;
|
||||
logic [$clog2(DEPTH):0] status_depth_commit;
|
||||
logic status_overflow;
|
||||
logic status_bad_frame;
|
||||
logic status_good_frame;
|
||||
|
||||
taxi_axis_fifo_adapter #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.pause_req(pause_req),
|
||||
.pause_ack(pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_depth(status_depth),
|
||||
.status_depth_commit(status_depth_commit),
|
||||
.status_overflow(status_overflow),
|
||||
.status_bad_frame(status_bad_frame),
|
||||
.status_good_frame(status_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_mux/Makefile
Normal file
62
src/axis/tb/taxi_axis_mux/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_mux
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_COUNT := 4
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
|
||||
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
226
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.py
Normal file
226
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.py
Normal file
@@ -0,0 +1,226 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.s_axis]
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
dut.enable.setimmediatevalue(0)
|
||||
dut.select.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
for source in self.source:
|
||||
source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, port=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source[port].bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
dut.enable.setimmediatevalue(1)
|
||||
dut.select.setimmediatevalue(port)
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[port].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut, port=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
dut.enable.setimmediatevalue(1)
|
||||
dut.select.setimmediatevalue(port)
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source[port].send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
ports = len(cocotb.top.s_axis)
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("port", list(range(ports)))
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("port", list(range(ports)))
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("s_count", [4])
|
||||
def test_taxi_axis_mux(request, s_count, data_w):
|
||||
dut = "taxi_axis_mux"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_COUNT'] = s_count
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
83
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv
Normal file
83
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv
Normal file
@@ -0,0 +1,83 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream multiplexer testbench
|
||||
*/
|
||||
module test_taxi_axis_mux #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter S_COUNT = 4,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis[S_COUNT](), m_axis();
|
||||
|
||||
logic enable;
|
||||
logic [$clog2(S_COUNT)-1:0] select;
|
||||
|
||||
taxi_axis_mux #(
|
||||
.S_COUNT(S_COUNT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.enable(enable),
|
||||
.select(select)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_pipeline_fifo/Makefile
Normal file
62
src/axis/tb/taxi_axis_pipeline_fifo/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_pipeline_fifo
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_LENGTH := 2
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,350 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 2048))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(2048):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_overflow
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16])
|
||||
@pytest.mark.parametrize("length", list(range(17)))
|
||||
def test_taxi_axis_pipeline_fifo(request, length, data_w):
|
||||
dut = "taxi_axis_pipeline_fifo"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['LENGTH'] = length
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,74 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream pipeline FIFO testbench
|
||||
*/
|
||||
module test_taxi_axis_pipeline_fifo #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter LENGTH = 2
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_pipeline_fifo #(
|
||||
.LENGTH(LENGTH)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_pipeline_register/Makefile
Normal file
62
src/axis/tb/taxi_axis_pipeline_register/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_pipeline_register
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_REG_TYPE := 2
|
||||
export PARAM_LENGTH := 2
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,261 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("reg_type", [0, 1, 2])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("length", [0, 1, 2])
|
||||
def test_taxi_axis_pipeline_register(request, length, data_w, reg_type):
|
||||
dut = "taxi_axis_pipeline_register"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['REG_TYPE'] = reg_type
|
||||
parameters['LENGTH'] = length
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,76 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream pipeline register testbench
|
||||
*/
|
||||
module test_taxi_axis_pipeline_register #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter REG_TYPE = 2,
|
||||
parameter LENGTH = 2
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_pipeline_register #(
|
||||
.REG_TYPE(REG_TYPE),
|
||||
.LENGTH(LENGTH)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_register/Makefile
Normal file
62
src/axis/tb/taxi_axis_register/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_register
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_REG_TYPE := 2
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
260
src/axis/tb/taxi_axis_register/test_taxi_axis_register.py
Normal file
260
src/axis/tb/taxi_axis_register/test_taxi_axis_register.py
Normal file
@@ -0,0 +1,260 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("reg_type", [0, 1, 2])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axis_register(request, data_w, reg_type):
|
||||
dut = "taxi_axis_register"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['REG_TYPE'] = reg_type
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
74
src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv
Normal file
74
src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv
Normal file
@@ -0,0 +1,74 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream register testbench
|
||||
*/
|
||||
module test_taxi_axis_register #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter REG_TYPE = 2
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_register #(
|
||||
.REG_TYPE(REG_TYPE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
32
src/eth/example/ADM_PCIE_9V3/fpga/README.md
Normal file
32
src/eth/example/ADM_PCIE_9V3/fpga/README.md
Normal file
@@ -0,0 +1,32 @@
|
||||
# Taxi Example Design for ADM-PCIE-9V3
|
||||
|
||||
## Introduction
|
||||
|
||||
This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board.
|
||||
|
||||
The design places looped-back MACs on the QSFP28 ports.
|
||||
|
||||
* QSFP28
|
||||
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
|
||||
|
||||
## Board details
|
||||
|
||||
* FPGA: xcvu3p-ffvc1517-2-i
|
||||
* 25GBASE-R PHY: Soft PCS with GTY transceivers
|
||||
|
||||
## Licensing
|
||||
|
||||
* Toolchain
|
||||
* Vivado Enterprise (requires license)
|
||||
* IP
|
||||
* No licensed vendor IP or 3rd party IP
|
||||
|
||||
## How to build
|
||||
|
||||
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
|
||||
|
||||
## How to test
|
||||
|
||||
Run `make program` to program the board with Vivado.
|
||||
|
||||
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
|
||||
153
src/eth/example/ADM_PCIE_9V3/fpga/common/vivado.mk
Normal file
153
src/eth/example/ADM_PCIE_9V3/fpga/common/vivado.mk
Normal file
@@ -0,0 +1,153 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016-2025 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - list of source files
|
||||
# INC_FILES - list of include files
|
||||
# XDC_FILES - list of timing constraint files
|
||||
# XCI_FILES - list of IP XCI files
|
||||
# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
|
||||
# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
|
||||
#
|
||||
# Note: both SYN_FILES and INC_FILES support file list files. File list
|
||||
# files are files with a .f extension that contain a list of additional
|
||||
# files to include, one path relative to the .f file location per line.
|
||||
# The .f files are processed recursively, and then the complete file list
|
||||
# is de-duplicated, with later files in the list taking precedence.
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: fpga vivado tmpclean clean distclean
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include $(CONFIG)
|
||||
|
||||
FPGA_TOP ?= fpga
|
||||
PROJECT ?= $(FPGA_TOP)
|
||||
XDC_FILES ?= $(PROJECT).xdc
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
|
||||
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything (fpga)
|
||||
# fpga: build FPGA config
|
||||
# vivado: open project in Vivado
|
||||
# tmpclean: remove intermediate files
|
||||
# clean: remove output files and project files
|
||||
# distclean: remove archived output files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(PROJECT).bit
|
||||
|
||||
vivado: $(PROJECT).xpr
|
||||
vivado $(PROJECT).xpr
|
||||
|
||||
tmpclean::
|
||||
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean:: tmpclean
|
||||
-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
|
||||
|
||||
distclean:: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
|
||||
# create fresh project if Makefile or IP files have changed
|
||||
create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
|
||||
echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
|
||||
echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
|
||||
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
|
||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
# source config TCL scripts if any source file has changed
|
||||
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
||||
echo "open_project -quiet $(PROJECT).xpr" > $@
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
$(PROJECT).xpr: create_project.tcl update_config.tcl
|
||||
vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
|
||||
|
||||
# synthesis run
|
||||
$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
|
||||
echo "open_project $(PROJECT).xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
|
||||
echo "open_project $(PROJECT).xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "open_run impl_1" >> run_impl.tcl
|
||||
echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
|
||||
echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# output files (including potentially bit, bin, ltx, and xsa)
|
||||
$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
|
||||
echo "open_project $(PROJECT).xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
|
||||
echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
|
||||
echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
|
||||
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
|
||||
490
src/eth/example/ADM_PCIE_9V3/fpga/fpga.xdc
Normal file
490
src/eth/example/ADM_PCIE_9V3/fpga/fpga.xdc
Normal file
@@ -0,0 +1,490 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the ADM-PCIE-9V3
|
||||
# part: xcvu3p-ffvc1517-2-i
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
# 300 MHz system clock
|
||||
set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
|
||||
set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
|
||||
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}]
|
||||
set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}]
|
||||
set_property -dict {LOC AU23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_r}]
|
||||
set_property -dict {LOC AH24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[0]}]
|
||||
set_property -dict {LOC AJ23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[1]}]
|
||||
|
||||
set_false_path -to [get_ports {user_led_g[*] user_led_r front_led[*]}]
|
||||
set_output_delay 0 [get_ports {user_led_g[*] user_led_r front_led[*]}]
|
||||
|
||||
# Switches
|
||||
set_property -dict {LOC AV27 IOSTANDARD LVCMOS18} [get_ports {user_sw[0]}]
|
||||
set_property -dict {LOC AW27 IOSTANDARD LVCMOS18} [get_ports {user_sw[1]}]
|
||||
|
||||
set_false_path -from [get_ports {user_sw[*]}]
|
||||
set_input_delay 0 [get_ports {user_sw[*]}]
|
||||
|
||||
# GPIO
|
||||
#set_property -dict {LOC G30 IOSTANDARD LVCMOS18} [get_ports gpio_p[0]]
|
||||
#set_property -dict {LOC F30 IOSTANDARD LVCMOS18} [get_ports gpio_n[0]]
|
||||
#set_property -dict {LOC J31 IOSTANDARD LVCMOS18} [get_ports gpio_p[1]]
|
||||
#set_property -dict {LOC H31 IOSTANDARD LVCMOS18} [get_ports gpio_n[1]]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC G38 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC G39 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F35 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F36 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E38 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E39 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D35 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D36 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C38 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C39 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C33 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C34 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B36 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B37 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A33 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A34 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC N33 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ?
|
||||
set_property -dict {LOC N34 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ?
|
||||
set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l]
|
||||
set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_0_sel_l]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
|
||||
|
||||
set_property -dict {LOC R38 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC R39 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P35 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P36 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N38 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N39 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M36 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L38 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L39 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K36 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J38 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J39 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H35 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H36 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC U33 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ?
|
||||
#set_property -dict {LOC U34 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ?
|
||||
set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l]
|
||||
set_property -dict {LOC D30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_1_sel_l]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
#create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p]
|
||||
|
||||
set_property -dict {LOC B29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_reset_l]
|
||||
set_property -dict {LOC C29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_int_l]
|
||||
#set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_scl]
|
||||
#set_property -dict {LOC A29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_sda]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_0_sel_l qsfp_1_sel_l qsfp_reset_l}]
|
||||
set_output_delay 0 [get_ports {qsfp_0_sel_l qsfp_1_sel_l qsfp_reset_l}]
|
||||
set_false_path -from [get_ports {qsfp_0_modprs_l qsfp_1_modprs_l qsfp_int_l}]
|
||||
set_input_delay 0 [get_ports {qsfp_0_modprs_l qsfp_1_modprs_l qsfp_int_l}]
|
||||
|
||||
#set_false_path -to [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
|
||||
#set_output_delay 0 [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
|
||||
#set_false_path -from [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
|
||||
|
||||
# I2C interface
|
||||
#set_property -dict {LOC AT25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
|
||||
#set_property -dict {LOC AT26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
|
||||
#set_property -dict {LOC AP23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_wp]
|
||||
|
||||
#set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl eeprom_wp}]
|
||||
#set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl eeprom_wp}]
|
||||
#set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC J2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC J1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC H5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC H4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC L2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC L1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC K5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC K4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC N2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC N1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC M5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC M4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC R2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC R1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC P5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC P4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC U2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC U1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC T5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC T4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC W2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC W1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC V5 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC V4 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AA2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AA1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AB5 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AB4 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AC2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AC1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AD5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AD4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AE2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AE1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AF5 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AF4 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AH5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AH4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AK5 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AK4 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AM5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AP5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AW7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AW6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AA7 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_226
|
||||
#set_property -dict {LOC AA6 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_226
|
||||
#set_property -dict {LOC AJ7 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_224
|
||||
#set_property -dict {LOC AJ6 } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_224
|
||||
#set_property -dict {LOC AJ31 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_0]
|
||||
#set_property -dict {LOC AH29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_1]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
|
||||
|
||||
#set_false_path -from [get_ports {perst_0}]
|
||||
#set_input_delay 0 [get_ports {perst_0}]
|
||||
|
||||
# DDR4 C0
|
||||
# 5x K4A8G085WB-RC
|
||||
#set_property -dict {LOC F9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
#set_property -dict {LOC G9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
#set_property -dict {LOC G11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
#set_property -dict {LOC D11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
#set_property -dict {LOC E12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
#set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
#set_property -dict {LOC F10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
#set_property -dict {LOC J9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
#set_property -dict {LOC J8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
#set_property -dict {LOC F12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
#set_property -dict {LOC D9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
#set_property -dict {LOC H11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
#set_property -dict {LOC E8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
#set_property -dict {LOC J11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
#set_property -dict {LOC C9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
#set_property -dict {LOC B11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
#set_property -dict {LOC K12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
#set_property -dict {LOC H9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}]
|
||||
#set_property -dict {LOC F8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
#set_property -dict {LOC H8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
#set_property -dict {LOC D10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
#set_property -dict {LOC E11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
#set_property -dict {LOC B10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}]
|
||||
#set_property -dict {LOC C11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}]
|
||||
#set_property -dict {LOC A9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}]
|
||||
#set_property -dict {LOC H12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}]
|
||||
#set_property -dict {LOC G12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}]
|
||||
#set_property -dict {LOC B9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}]
|
||||
#set_property -dict {LOC E10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}]
|
||||
#set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
#set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}]
|
||||
#set_property -dict {LOC G7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
#set_property -dict {LOC F7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
#set_property -dict {LOC H7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}]
|
||||
#set_property -dict {LOC J10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}]
|
||||
|
||||
#set_property -dict {LOC L10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
#set_property -dict {LOC L9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
#set_property -dict {LOC N9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
#set_property -dict {LOC M9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
#set_property -dict {LOC M10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
#set_property -dict {LOC K11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
#set_property -dict {LOC M11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
#set_property -dict {LOC K10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
#set_property -dict {LOC L17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
#set_property -dict {LOC M15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
#set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
#set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
#set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
#set_property -dict {LOC F17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
#set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
#set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
#set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
#set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
#set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
#set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
#set_property -dict {LOC D21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
#set_property -dict {LOC G19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
#set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
#set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
#set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
#set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
#set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
#set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
#set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
#set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
#set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
#set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
#set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
#set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
#set_property -dict {LOC K13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
#set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
#set_property -dict {LOC M12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
#set_property -dict {LOC L12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
#set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
#set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
#set_property -dict {LOC F13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
#set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
#set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
#set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
#set_property -dict {LOC F22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
#set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
#set_property -dict {LOC C21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
#set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
#set_property -dict {LOC K21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
#set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
#set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
#set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
#set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
#set_property -dict {LOC K16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
#set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC D14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 C1
|
||||
# 5x K4A8G085WB-RC
|
||||
#set_property -dict {LOC AN9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
#set_property -dict {LOC AM9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
#set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
#set_property -dict {LOC AU9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
#set_property -dict {LOC AT10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
#set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
#set_property -dict {LOC AM12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
#set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
#set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
#set_property -dict {LOC AP7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
#set_property -dict {LOC AR8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
#set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
#set_property -dict {LOC AP8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
#set_property -dict {LOC AK11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
#set_property -dict {LOC AP9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
#set_property -dict {LOC AV10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
#set_property -dict {LOC AT11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
#set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}]
|
||||
#set_property -dict {LOC AN11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
#set_property -dict {LOC AR9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
#set_property -dict {LOC AP12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
#set_property -dict {LOC AN10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
#set_property -dict {LOC AW13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}]
|
||||
#set_property -dict {LOC AU10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}]
|
||||
#set_property -dict {LOC AW11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}]
|
||||
#set_property -dict {LOC AM7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
|
||||
#set_property -dict {LOC AN7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
|
||||
#set_property -dict {LOC AU12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
#set_property -dict {LOC AT12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
#set_property -dict {LOC AV9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
#set_property -dict {LOC AR11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
#set_property -dict {LOC AM8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
#set_property -dict {LOC AN12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
#set_property -dict {LOC AR10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}]
|
||||
#set_property -dict {LOC AV11 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}]
|
||||
|
||||
#set_property -dict {LOC AK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
#set_property -dict {LOC AK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
#set_property -dict {LOC AH10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
#set_property -dict {LOC AJ11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
#set_property -dict {LOC AJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
#set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
#set_property -dict {LOC AG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
#set_property -dict {LOC AJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
#set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
#set_property -dict {LOC AL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
#set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
#set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
#set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
#set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
#set_property -dict {LOC AP17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
#set_property -dict {LOC AN15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
#set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
#set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
#set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
#set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
#set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
#set_property -dict {LOC AW17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
#set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
#set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
#set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
#set_property -dict {LOC AN21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
#set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
#set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
#set_property -dict {LOC AR20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
#set_property -dict {LOC AU22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
#set_property -dict {LOC AV19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
#set_property -dict {LOC AW22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
#set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
#set_property -dict {LOC AT22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
#set_property -dict {LOC AW21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
#set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
#set_property -dict {LOC AH19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
#set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
#set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
#set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
#set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
#set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
#set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
#set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
#set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
#set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
#set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
#set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
#set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
#set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
#set_property -dict {LOC AJ14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
#set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
#set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
#set_property -dict {LOC AG17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
#set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
#set_property -dict {LOC AG9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
#set_property -dict {LOC AH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
#set_property -dict {LOC AK16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
#set_property -dict {LOC AL16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
#set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
#set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
#set_property -dict {LOC AU17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
#set_property -dict {LOC AV17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
#set_property -dict {LOC AN22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
#set_property -dict {LOC AP22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
#set_property -dict {LOC AV22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
#set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
#set_property -dict {LOC AG20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
#set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
#set_property -dict {LOC AK21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
#set_property -dict {LOC AL21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
#set_property -dict {LOC AH16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
#set_property -dict {LOC AH15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
#set_property -dict {LOC AG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC AK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC AU20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}]
|
||||
|
||||
# QSPI flash
|
||||
#set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}]
|
||||
#set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}]
|
||||
#set_property -dict {LOC AF28 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}]
|
||||
#set_property -dict {LOC AG28 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}]
|
||||
#set_property -dict {LOC AV30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}]
|
||||
|
||||
#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_false_path -from [get_ports {qspi_1_dq}]
|
||||
#set_input_delay 0 [get_ports {qspi_1_dq}]
|
||||
89
src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile
Normal file
89
src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile
Normal file
@@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu3p-ffvc1517-2-i
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
|
||||
|
||||
# Configuration
|
||||
# CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT)_primary.mcs\" \"$(PROJECT)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)_primary.prm\" \"$(PROJECT)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
89
src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile
Normal file
89
src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile
Normal file
@@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu3p-ffvc1517-2-i
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
|
||||
|
||||
# Configuration
|
||||
# CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT)_primary.mcs\" \"$(PROJECT)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)_primary.prm\" \"$(PROJECT)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
1
src/eth/example/ADM_PCIE_9V3/fpga/lib/taxi
Symbolic link
1
src/eth/example/ADM_PCIE_9V3/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../../../
|
||||
243
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv
Normal file
243
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,243 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 300MHz LVDS
|
||||
*/
|
||||
input wire logic clk_300mhz_p,
|
||||
input wire logic clk_300mhz_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [1:0] user_led_g,
|
||||
output wire logic user_led_r,
|
||||
output wire logic [1:0] front_led,
|
||||
input wire logic [1:0] user_sw,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp_0_tx_p,
|
||||
output wire logic [3:0] qsfp_0_tx_n,
|
||||
input wire logic [3:0] qsfp_0_rx_p,
|
||||
input wire logic [3:0] qsfp_0_rx_n,
|
||||
input wire logic qsfp_0_mgt_refclk_p,
|
||||
input wire logic qsfp_0_mgt_refclk_n,
|
||||
input wire logic qsfp_0_modprs_l,
|
||||
output wire logic qsfp_0_sel_l,
|
||||
|
||||
output wire logic [3:0] qsfp_1_tx_p,
|
||||
output wire logic [3:0] qsfp_1_tx_n,
|
||||
input wire logic [3:0] qsfp_1_rx_p,
|
||||
input wire logic [3:0] qsfp_1_rx_n,
|
||||
// input wire logic qsfp_1_mgt_refclk_p,
|
||||
// input wire logic qsfp_1_mgt_refclk_n,
|
||||
input wire logic qsfp_1_modprs_l,
|
||||
output wire logic qsfp_1_sel_l,
|
||||
|
||||
output wire logic qsfp_reset_l,
|
||||
input wire logic qsfp_int_l
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_300mhz_ibufg;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFGDS #(
|
||||
.DIFF_TERM("FALSE"),
|
||||
.IBUF_LOW_PWR("FALSE")
|
||||
)
|
||||
clk_300mhz_ibufg_inst (
|
||||
.O (clk_300mhz_ibufg),
|
||||
.I (clk_300mhz_p),
|
||||
.IB (clk_300mhz_n)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 300 MHz input
|
||||
.CLKIN1_PERIOD(3.333),
|
||||
.REF_JITTER1(0.010),
|
||||
// 300 MHz input / 3 = 100 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(3),
|
||||
// 100 MHz PFD * 12.5 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(12.5),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(10),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(90),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(20),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(4),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 300 MHz input
|
||||
.CLKIN1(clk_300mhz_ibufg),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire [1:0] user_sw_int;
|
||||
|
||||
taxi_debounce_switch #(
|
||||
.WIDTH(2),
|
||||
.N(4),
|
||||
.RATE(125000)
|
||||
)
|
||||
debounce_switch_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
.in({user_sw}),
|
||||
.out({user_sw_int})
|
||||
);
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.user_led_g(user_led_g),
|
||||
.user_led_r(user_led_r),
|
||||
.front_led(front_led),
|
||||
.user_sw(user_sw_int),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.qsfp_0_tx_p(qsfp_0_tx_p),
|
||||
.qsfp_0_tx_n(qsfp_0_tx_n),
|
||||
.qsfp_0_rx_p(qsfp_0_rx_p),
|
||||
.qsfp_0_rx_n(qsfp_0_rx_n),
|
||||
.qsfp_0_mgt_refclk_p(qsfp_0_mgt_refclk_p),
|
||||
.qsfp_0_mgt_refclk_n(qsfp_0_mgt_refclk_n),
|
||||
.qsfp_0_modprs_l(qsfp_0_modprs_l),
|
||||
.qsfp_0_sel_l(qsfp_0_sel_l),
|
||||
|
||||
.qsfp_1_tx_p(qsfp_1_tx_p),
|
||||
.qsfp_1_tx_n(qsfp_1_tx_n),
|
||||
.qsfp_1_rx_p(qsfp_1_rx_p),
|
||||
.qsfp_1_rx_n(qsfp_1_rx_n),
|
||||
// .qsfp_1_mgt_refclk_p(qsfp_1_mgt_refclk_p),
|
||||
// .qsfp_1_mgt_refclk_n(qsfp_1_mgt_refclk_n),
|
||||
.qsfp_1_modprs_l(qsfp_1_modprs_l),
|
||||
.qsfp_1_sel_l(qsfp_1_sel_l),
|
||||
|
||||
.qsfp_reset_l(qsfp_reset_l),
|
||||
.qsfp_int_l(qsfp_int_l)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
401
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
Normal file
401
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,401 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk_125mhz,
|
||||
input wire logic rst_125mhz,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [1:0] user_led_g,
|
||||
output wire logic user_led_r,
|
||||
output wire logic [1:0] front_led,
|
||||
input wire logic [1:0] user_sw,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp_0_tx_p,
|
||||
output wire logic [3:0] qsfp_0_tx_n,
|
||||
input wire logic [3:0] qsfp_0_rx_p,
|
||||
input wire logic [3:0] qsfp_0_rx_n,
|
||||
input wire logic qsfp_0_mgt_refclk_p,
|
||||
input wire logic qsfp_0_mgt_refclk_n,
|
||||
input wire logic qsfp_0_modprs_l,
|
||||
output wire logic qsfp_0_sel_l,
|
||||
|
||||
output wire logic [3:0] qsfp_1_tx_p,
|
||||
output wire logic [3:0] qsfp_1_tx_n,
|
||||
input wire logic [3:0] qsfp_1_rx_p,
|
||||
input wire logic [3:0] qsfp_1_rx_n,
|
||||
// input wire logic qsfp_1_mgt_refclk_p,
|
||||
// input wire logic qsfp_1_mgt_refclk_n,
|
||||
input wire logic qsfp_1_modprs_l,
|
||||
output wire logic qsfp_1_sel_l,
|
||||
|
||||
output wire logic qsfp_reset_l,
|
||||
input wire logic qsfp_int_l
|
||||
);
|
||||
|
||||
// QSFP28
|
||||
assign qsfp_0_sel_l = 1'b1;
|
||||
assign qsfp_1_sel_l = 1'b1;
|
||||
assign qsfp_reset_l = 1'b1;
|
||||
|
||||
wire [7:0] qsfp_tx_clk;
|
||||
wire [7:0] qsfp_tx_rst;
|
||||
wire [7:0] qsfp_rx_clk;
|
||||
wire [7:0] qsfp_rx_rst;
|
||||
|
||||
wire [7:0] qsfp_rx_status;
|
||||
|
||||
wire [1:0] qsfp_gtpowergood;
|
||||
|
||||
wire qsfp_0_mgt_refclk;
|
||||
wire qsfp_0_mgt_refclk_int;
|
||||
wire qsfp_0_mgt_refclk_bufg;
|
||||
|
||||
wire qsfp_rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[8]();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[8]();
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[8]();
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_qsfp_stat[2]();
|
||||
|
||||
if (SIM) begin
|
||||
|
||||
assign qsfp_0_mgt_refclk = qsfp_0_mgt_refclk_p;
|
||||
assign qsfp_0_mgt_refclk_int = qsfp_0_mgt_refclk_p;
|
||||
assign qsfp_0_mgt_refclk_bufg = qsfp_0_mgt_refclk_int;
|
||||
|
||||
end else begin
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
|
||||
.I (qsfp_0_mgt_refclk_p),
|
||||
.IB (qsfp_0_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (qsfp_0_mgt_refclk),
|
||||
.ODIV2 (qsfp_0_mgt_refclk_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_qsfp_0_mgt_refclk_inst (
|
||||
.CE (&qsfp_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (qsfp_0_mgt_refclk_int),
|
||||
.O (qsfp_0_mgt_refclk_bufg)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_sync_reset_inst (
|
||||
.clk(qsfp_0_mgt_refclk_bufg),
|
||||
.rst(rst_125mhz),
|
||||
.out(qsfp_rst)
|
||||
);
|
||||
|
||||
wire [7:0] qsfp_tx_p;
|
||||
wire [7:0] qsfp_tx_n;
|
||||
wire [7:0] qsfp_rx_p = {qsfp_1_rx_p, qsfp_0_rx_p};
|
||||
wire [7:0] qsfp_rx_n = {qsfp_1_rx_n, qsfp_0_rx_n};
|
||||
|
||||
assign qsfp_0_tx_p = qsfp_tx_p[3:0];
|
||||
assign qsfp_0_tx_n = qsfp_tx_n[3:0];
|
||||
assign qsfp_1_tx_p = qsfp_tx_p[7:4];
|
||||
assign qsfp_1_tx_n = qsfp_tx_n[7:4];
|
||||
|
||||
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
|
||||
|
||||
localparam CNT = 4;
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(CNT),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4),
|
||||
.STAT_EN(1'b0)
|
||||
)
|
||||
mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(qsfp_rst),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(qsfp_gtpowergood[n]),
|
||||
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp_tx_p[n*CNT +: CNT]),
|
||||
.xcvr_txn(qsfp_tx_n[n*CNT +: CNT]),
|
||||
.xcvr_rxp(qsfp_rx_p[n*CNT +: CNT]),
|
||||
.xcvr_rxn(qsfp_rx_n[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(qsfp_rx_clk[n*CNT +: CNT]),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]),
|
||||
.tx_clk(qsfp_tx_clk[n*CNT +: CNT]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_qsfp_tx[n*CNT +: CNT]),
|
||||
.m_axis_tx_cpl(axis_qsfp_tx_cpl[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('{CNT{'0}}),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('{CNT{'0}}),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('{CNT{'0}}),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('{CNT{'0}}),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('{CNT{'0}}),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk_125mhz),
|
||||
.stat_rst(rst_125mhz),
|
||||
.m_axis_stat(axis_qsfp_stat[n]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(qsfp_rx_status[n*CNT +: CNT]),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(),
|
||||
.stat_rx_err_bad_block(),
|
||||
.stat_rx_err_framing(),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop('0),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
|
||||
.cfg_tx_ifg('{CNT{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
for (genvar n = 0; n < 8; n = n + 1) begin : qsfp_ch
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(16384),
|
||||
.RAM_PIPELINE(2),
|
||||
.FRAME_FIFO(1),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(1),
|
||||
.DROP_BAD_FRAME(1),
|
||||
.DROP_WHEN_FULL(1)
|
||||
)
|
||||
ch_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(qsfp_rx_clk[n]),
|
||||
.s_rst(qsfp_rx_rst[n]),
|
||||
.s_axis(axis_qsfp_rx[n]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(qsfp_tx_clk[n]),
|
||||
.m_rst(qsfp_tx_rst[n]),
|
||||
.m_axis(axis_qsfp_tx[n]),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
56
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile
Normal file
56
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"virtexuplus\""
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py
Symbolic link
1
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/src/eth/tb/baser.py
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user