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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
1
src/axi/lib/taxi
Symbolic link
1
src/axi/lib/taxi
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../../../
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257
src/axi/rtl/taxi_axi_if.sv
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257
src/axi/rtl/taxi_axi_if.sv
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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interface taxi_axi_if #(
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// Width of data bus in bits
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parameter DATA_W = 32,
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// Width of address bus in bits
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parameter ADDR_W = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_W = (DATA_W/8),
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// Width of ID signal
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parameter ID_W = 8,
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// Use awuser signal
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parameter logic AWUSER_EN = 1'b0,
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// Width of awuser signal
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parameter AWUSER_W = 1,
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// Use wuser signal
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parameter logic WUSER_EN = 1'b0,
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// Width of wuser signal
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parameter WUSER_W = 1,
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// Use buser signal
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parameter logic BUSER_EN = 1'b0,
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// Width of buser signal
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parameter BUSER_W = 1,
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// Use aruser signal
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parameter logic ARUSER_EN = 1'b0,
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// Width of aruser signal
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parameter ARUSER_W = 1,
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// Use ruser signal
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parameter logic RUSER_EN = 1'b0,
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// Width of ruser signal
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parameter RUSER_W = 1
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)
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();
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// AW
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logic [ID_W-1:0] awid;
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logic [ADDR_W-1:0] awaddr;
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logic [7:0] awlen;
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logic [2:0] awsize;
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logic [1:0] awburst;
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logic awlock;
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logic [3:0] awcache;
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logic [2:0] awprot;
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logic [3:0] awqos;
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logic [3:0] awregion;
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logic [AWUSER_W-1:0] awuser;
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logic awvalid;
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logic awready;
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// W
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logic [DATA_W-1:0] wdata;
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logic [STRB_W-1:0] wstrb;
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logic wlast;
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logic [WUSER_W-1:0] wuser;
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logic wvalid;
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logic wready;
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// B
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logic [ID_W-1:0] bid;
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logic [1:0] bresp;
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logic [BUSER_W-1:0] buser;
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logic bvalid;
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logic bready;
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// AR
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logic [ID_W-1:0] arid;
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logic [ADDR_W-1:0] araddr;
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logic [7:0] arlen;
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logic [2:0] arsize;
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logic [1:0] arburst;
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logic arlock;
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logic [3:0] arcache;
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logic [2:0] arprot;
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logic [3:0] arqos;
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logic [3:0] arregion;
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logic [ARUSER_W-1:0] aruser;
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logic arvalid;
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logic arready;
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// R
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logic [ID_W-1:0] rid;
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logic [DATA_W-1:0] rdata;
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logic [1:0] rresp;
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logic rlast;
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logic [RUSER_W-1:0] ruser;
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logic rvalid;
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logic rready;
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modport wr_mst (
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// AW
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output awid,
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output awaddr,
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output awlen,
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output awsize,
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output awburst,
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output awlock,
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output awcache,
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output awprot,
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output awqos,
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output awregion,
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output awuser,
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output awvalid,
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input awready,
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// W
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output wdata,
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output wstrb,
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output wlast,
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output wuser,
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output wvalid,
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input wready,
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// B
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input bid,
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input bresp,
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input buser,
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input bvalid,
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output bready
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);
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modport rd_mst (
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// AR
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output arid,
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output araddr,
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output arlen,
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output arsize,
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output arburst,
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output arlock,
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output arcache,
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output arprot,
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output arqos,
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output arregion,
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output aruser,
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output arvalid,
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input arready,
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// R
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input rid,
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input rdata,
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input rresp,
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input rlast,
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input ruser,
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input rvalid,
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output rready
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);
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modport wr_slv (
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// AW
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input awid,
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input awaddr,
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input awlen,
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input awsize,
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input awburst,
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input awlock,
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input awcache,
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input awprot,
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input awqos,
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input awregion,
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input awuser,
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input awvalid,
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output awready,
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// W
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input wdata,
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input wstrb,
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input wlast,
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input wuser,
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input wvalid,
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output wready,
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// B
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output bid,
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output bresp,
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output buser,
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output bvalid,
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input bready
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);
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modport rd_slv (
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// AR
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input arid,
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input araddr,
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input arlen,
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input arsize,
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input arburst,
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input arlock,
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input arcache,
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input arprot,
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input arqos,
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input arregion,
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input aruser,
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input arvalid,
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output arready,
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// R
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output rid,
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output rdata,
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output rresp,
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output rlast,
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output ruser,
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output rvalid,
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input rready
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);
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modport wr_mon (
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// AW
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input awid,
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input awaddr,
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input awlen,
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input awsize,
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input awburst,
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input awlock,
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input awcache,
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input awprot,
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input awqos,
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input awregion,
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input awuser,
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input awvalid,
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input awready,
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// W
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input wdata,
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input wstrb,
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input wlast,
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input wuser,
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input wvalid,
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input wready,
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// B
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input bid,
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input bresp,
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input buser,
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input bvalid,
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input bready
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);
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modport rd_mon (
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// AR
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input arid,
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input araddr,
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input arlen,
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input arsize,
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input arburst,
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input arlock,
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input arcache,
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input arprot,
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input arqos,
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input arregion,
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input aruser,
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input arvalid,
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input arready,
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// R
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input rid,
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input rdata,
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input rresp,
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input rlast,
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input ruser,
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input rvalid,
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input rready
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);
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endinterface
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327
src/axi/rtl/taxi_axi_ram.sv
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327
src/axi/rtl/taxi_axi_ram.sv
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@@ -0,0 +1,327 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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||||
- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 RAM
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*/
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module taxi_axi_ram #
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(
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// Width of address bus in bits
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parameter ADDR_W = 16,
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// Extra pipeline register on output
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parameter logic PIPELINE_OUTPUT = 1'b0
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4 slave interface
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*/
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taxi_axi_if.wr_slv s_axi_wr,
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taxi_axi_if.rd_slv s_axi_rd
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);
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// extract parameters
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localparam DATA_W = s_axi_wr.DATA_W;
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localparam STRB_W = s_axi_wr.STRB_W;
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localparam WR_ID_W = s_axi_wr.ID_W;
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localparam RD_ID_W = s_axi_rd.ID_W;
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localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
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localparam BYTE_LANES = STRB_W;
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localparam BYTE_W = DATA_W/BYTE_LANES;
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// check configuration
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if (BYTE_W * STRB_W != DATA_W)
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$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
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if (2**$clog2(BYTE_LANES) != BYTE_LANES)
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$fatal(0, "Error: AXI byte lane count must be even power of two (instance %m)");
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if (s_axi_wr.DATA_W != s_axi_rd.DATA_W)
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$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
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if (s_axi_wr.ADDR_W < ADDR_W || s_axi_rd.ADDR_W < ADDR_W)
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$fatal(0, "Error: AXI address width is insufficient (instance %m)");
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localparam [0:0]
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READ_STATE_IDLE = 1'd0,
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READ_STATE_BURST = 1'd1;
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logic [0:0] read_state_reg = READ_STATE_IDLE, read_state_next;
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localparam [1:0]
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WRITE_STATE_IDLE = 2'd0,
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WRITE_STATE_BURST = 2'd1,
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WRITE_STATE_RESP = 2'd2;
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logic [1:0] write_state_reg = WRITE_STATE_IDLE, write_state_next;
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logic mem_wr_en;
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logic mem_rd_en;
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logic [WR_ID_W-1:0] write_id_reg = '0, write_id_next;
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logic [ADDR_W-1:0] write_addr_reg = '0, write_addr_next;
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logic [7:0] write_count_reg = 8'd0, write_count_next;
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logic [2:0] write_size_reg = 3'd0, write_size_next;
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logic [1:0] write_burst_reg = 2'd0, write_burst_next;
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logic [RD_ID_W-1:0] read_id_reg = '0, read_id_next;
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logic [ADDR_W-1:0] read_addr_reg = '0, read_addr_next;
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logic [7:0] read_count_reg = 8'd0, read_count_next;
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logic [2:0] read_size_reg = 3'd0, read_size_next;
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logic [1:0] read_burst_reg = 2'd0, read_burst_next;
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logic s_axi_awready_reg = 1'b0, s_axi_awready_next;
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logic s_axi_wready_reg = 1'b0, s_axi_wready_next;
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logic [WR_ID_W-1:0] s_axi_bid_reg = '0, s_axi_bid_next;
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logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
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logic s_axi_arready_reg = 1'b0, s_axi_arready_next;
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logic [RD_ID_W-1:0] s_axi_rid_reg = '0, s_axi_rid_next;
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logic [DATA_W-1:0] s_axi_rdata_reg = '0, s_axi_rdata_next;
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logic s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
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logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
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logic [RD_ID_W-1:0] s_axi_rid_pipe_reg = '0;
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logic [DATA_W-1:0] s_axi_rdata_pipe_reg = '0;
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logic s_axi_rlast_pipe_reg = 1'b0;
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logic s_axi_rvalid_pipe_reg = 1'b0;
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// (* RAM_STYLE="BLOCK" *)
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logic [DATA_W-1:0] mem[2**VALID_ADDR_W];
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wire [VALID_ADDR_W-1:0] read_addr_valid = VALID_ADDR_W'(read_addr_reg >> (ADDR_W - VALID_ADDR_W));
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wire [VALID_ADDR_W-1:0] write_addr_valid = VALID_ADDR_W'(write_addr_reg >> (ADDR_W - VALID_ADDR_W));
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assign s_axi_wr.awready = s_axi_awready_reg;
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assign s_axi_wr.wready = s_axi_wready_reg;
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assign s_axi_wr.bid = s_axi_bid_reg;
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assign s_axi_wr.bresp = 2'b00;
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assign s_axi_wr.bvalid = s_axi_bvalid_reg;
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assign s_axi_rd.arready = s_axi_arready_reg;
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assign s_axi_rd.rid = PIPELINE_OUTPUT ? s_axi_rid_pipe_reg : s_axi_rid_reg;
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assign s_axi_rd.rdata = PIPELINE_OUTPUT ? s_axi_rdata_pipe_reg : s_axi_rdata_reg;
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assign s_axi_rd.rresp = 2'b00;
|
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assign s_axi_rd.rlast = PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : s_axi_rlast_reg;
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assign s_axi_rd.rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg;
|
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|
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initial begin
|
||||
// two nested loops for smaller number of iterations per loop
|
||||
// workaround for synthesizer complaints about large loop counts
|
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for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin
|
||||
for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin
|
||||
mem[j] = '0;
|
||||
end
|
||||
end
|
||||
end
|
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|
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always_comb begin
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write_state_next = WRITE_STATE_IDLE;
|
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|
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mem_wr_en = 1'b0;
|
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|
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write_id_next = write_id_reg;
|
||||
write_addr_next = write_addr_reg;
|
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write_count_next = write_count_reg;
|
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write_size_next = write_size_reg;
|
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write_burst_next = write_burst_reg;
|
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|
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s_axi_awready_next = 1'b0;
|
||||
s_axi_wready_next = 1'b0;
|
||||
s_axi_bid_next = s_axi_bid_reg;
|
||||
s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_wr.bready;
|
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|
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case (write_state_reg)
|
||||
WRITE_STATE_IDLE: begin
|
||||
s_axi_awready_next = 1'b1;
|
||||
|
||||
if (s_axi_wr.awready && s_axi_wr.awvalid) begin
|
||||
write_id_next = s_axi_wr.awid;
|
||||
write_addr_next = ADDR_W'(s_axi_wr.awaddr);
|
||||
write_count_next = s_axi_wr.awlen;
|
||||
write_size_next = s_axi_wr.awsize <= 3'($clog2(STRB_W)) ? s_axi_wr.awsize : 3'($clog2(STRB_W));
|
||||
write_burst_next = s_axi_wr.awburst;
|
||||
|
||||
s_axi_awready_next = 1'b0;
|
||||
s_axi_wready_next = 1'b1;
|
||||
write_state_next = WRITE_STATE_BURST;
|
||||
end else begin
|
||||
write_state_next = WRITE_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
WRITE_STATE_BURST: begin
|
||||
s_axi_wready_next = 1'b1;
|
||||
|
||||
if (s_axi_wr.wready && s_axi_wr.wvalid) begin
|
||||
mem_wr_en = 1'b1;
|
||||
if (write_burst_reg != 2'b00) begin
|
||||
write_addr_next = write_addr_reg + (1 << write_size_reg);
|
||||
end
|
||||
write_count_next = write_count_reg - 1;
|
||||
if (write_count_reg > 0) begin
|
||||
write_state_next = WRITE_STATE_BURST;
|
||||
end else begin
|
||||
s_axi_wready_next = 1'b0;
|
||||
if (s_axi_wr.bready || !s_axi_wr.bvalid) begin
|
||||
s_axi_bid_next = write_id_reg;
|
||||
s_axi_bvalid_next = 1'b1;
|
||||
s_axi_awready_next = 1'b1;
|
||||
write_state_next = WRITE_STATE_IDLE;
|
||||
end else begin
|
||||
write_state_next = WRITE_STATE_RESP;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
write_state_next = WRITE_STATE_BURST;
|
||||
end
|
||||
end
|
||||
WRITE_STATE_RESP: begin
|
||||
if (s_axi_wr.bready || !s_axi_wr.bvalid) begin
|
||||
s_axi_bid_next = write_id_reg;
|
||||
s_axi_bvalid_next = 1'b1;
|
||||
s_axi_awready_next = 1'b1;
|
||||
write_state_next = WRITE_STATE_IDLE;
|
||||
end else begin
|
||||
write_state_next = WRITE_STATE_RESP;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
write_state_next = WRITE_STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
write_state_reg <= write_state_next;
|
||||
|
||||
write_id_reg <= write_id_next;
|
||||
write_addr_reg <= write_addr_next;
|
||||
write_count_reg <= write_count_next;
|
||||
write_size_reg <= write_size_next;
|
||||
write_burst_reg <= write_burst_next;
|
||||
|
||||
s_axi_awready_reg <= s_axi_awready_next;
|
||||
s_axi_wready_reg <= s_axi_wready_next;
|
||||
s_axi_bid_reg <= s_axi_bid_next;
|
||||
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
||||
|
||||
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
|
||||
if (mem_wr_en & s_axi_wr.wstrb[i]) begin
|
||||
mem[write_addr_valid][BYTE_W*i +: BYTE_W] <= s_axi_wr.wdata[BYTE_W*i +: BYTE_W];
|
||||
end
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
write_state_reg <= WRITE_STATE_IDLE;
|
||||
|
||||
s_axi_awready_reg <= 1'b0;
|
||||
s_axi_wready_reg <= 1'b0;
|
||||
s_axi_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
read_state_next = READ_STATE_IDLE;
|
||||
|
||||
mem_rd_en = 1'b0;
|
||||
|
||||
s_axi_rid_next = s_axi_rid_reg;
|
||||
s_axi_rlast_next = s_axi_rlast_reg;
|
||||
s_axi_rvalid_next = s_axi_rvalid_reg && !(s_axi_rd.rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg));
|
||||
|
||||
read_id_next = read_id_reg;
|
||||
read_addr_next = read_addr_reg;
|
||||
read_count_next = read_count_reg;
|
||||
read_size_next = read_size_reg;
|
||||
read_burst_next = read_burst_reg;
|
||||
|
||||
s_axi_arready_next = 1'b0;
|
||||
|
||||
case (read_state_reg)
|
||||
READ_STATE_IDLE: begin
|
||||
s_axi_arready_next = 1'b1;
|
||||
|
||||
if (s_axi_rd.arready && s_axi_rd.arvalid) begin
|
||||
read_id_next = s_axi_rd.arid;
|
||||
read_addr_next = ADDR_W'(s_axi_rd.araddr);
|
||||
read_count_next = s_axi_rd.arlen;
|
||||
read_size_next = s_axi_rd.arsize <= 3'($clog2(STRB_W)) ? s_axi_rd.arsize : 3'($clog2(STRB_W));
|
||||
read_burst_next = s_axi_rd.arburst;
|
||||
|
||||
s_axi_arready_next = 1'b0;
|
||||
read_state_next = READ_STATE_BURST;
|
||||
end else begin
|
||||
read_state_next = READ_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
READ_STATE_BURST: begin
|
||||
if (s_axi_rd.rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg) || !s_axi_rvalid_reg) begin
|
||||
mem_rd_en = 1'b1;
|
||||
s_axi_rvalid_next = 1'b1;
|
||||
s_axi_rid_next = read_id_reg;
|
||||
s_axi_rlast_next = read_count_reg == 0;
|
||||
if (read_burst_reg != 2'b00) begin
|
||||
read_addr_next = read_addr_reg + (1 << read_size_reg);
|
||||
end
|
||||
read_count_next = read_count_reg - 1;
|
||||
if (read_count_reg > 0) begin
|
||||
read_state_next = READ_STATE_BURST;
|
||||
end else begin
|
||||
s_axi_arready_next = 1'b1;
|
||||
read_state_next = READ_STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
read_state_next = READ_STATE_BURST;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
read_state_reg <= read_state_next;
|
||||
|
||||
read_id_reg <= read_id_next;
|
||||
read_addr_reg <= read_addr_next;
|
||||
read_count_reg <= read_count_next;
|
||||
read_size_reg <= read_size_next;
|
||||
read_burst_reg <= read_burst_next;
|
||||
|
||||
s_axi_arready_reg <= s_axi_arready_next;
|
||||
s_axi_rid_reg <= s_axi_rid_next;
|
||||
s_axi_rlast_reg <= s_axi_rlast_next;
|
||||
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
||||
|
||||
if (mem_rd_en) begin
|
||||
s_axi_rdata_reg <= mem[read_addr_valid];
|
||||
end
|
||||
|
||||
if (!s_axi_rvalid_pipe_reg || s_axi_rd.rready) begin
|
||||
s_axi_rid_pipe_reg <= s_axi_rid_reg;
|
||||
s_axi_rdata_pipe_reg <= s_axi_rdata_reg;
|
||||
s_axi_rlast_pipe_reg <= s_axi_rlast_reg;
|
||||
s_axi_rvalid_pipe_reg <= s_axi_rvalid_reg;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
read_state_reg <= READ_STATE_IDLE;
|
||||
|
||||
s_axi_arready_reg <= 1'b0;
|
||||
s_axi_rvalid_reg <= 1'b0;
|
||||
s_axi_rvalid_pipe_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
4
src/axi/rtl/taxi_axi_register.f
Normal file
4
src/axi/rtl/taxi_axi_register.f
Normal file
@@ -0,0 +1,4 @@
|
||||
taxi_axi_register.sv
|
||||
taxi_axi_register_wr.sv
|
||||
taxi_axi_register_rd.sv
|
||||
taxi_axi_if.sv
|
||||
94
src/axi/rtl/taxi_axi_register.sv
Normal file
94
src/axi/rtl/taxi_axi_register.sv
Normal file
@@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 register
|
||||
*/
|
||||
module taxi_axi_register #
|
||||
(
|
||||
// AW channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter AW_REG_TYPE = 1,
|
||||
// W channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter W_REG_TYPE = 2,
|
||||
// B channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter B_REG_TYPE = 1,
|
||||
// AR channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter AR_REG_TYPE = 1,
|
||||
// R channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter R_REG_TYPE = 2
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
taxi_axi_if.wr_slv s_axi_wr,
|
||||
taxi_axi_if.rd_slv s_axi_rd,
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
taxi_axi_if.wr_mst m_axi_wr,
|
||||
taxi_axi_if.rd_mst m_axi_rd
|
||||
);
|
||||
|
||||
taxi_axi_register_wr #(
|
||||
.AW_REG_TYPE(AW_REG_TYPE),
|
||||
.W_REG_TYPE(W_REG_TYPE),
|
||||
.B_REG_TYPE(B_REG_TYPE)
|
||||
)
|
||||
axi_register_wr_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
.s_axi_wr(s_axi_wr),
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
.m_axi_wr(m_axi_wr)
|
||||
);
|
||||
|
||||
taxi_axi_register_rd #(
|
||||
.AR_REG_TYPE(AR_REG_TYPE),
|
||||
.R_REG_TYPE(R_REG_TYPE)
|
||||
)
|
||||
axi_register_rd_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
.s_axi_rd(s_axi_rd),
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
.m_axi_rd(m_axi_rd)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
472
src/axi/rtl/taxi_axi_register_rd.sv
Normal file
472
src/axi/rtl/taxi_axi_register_rd.sv
Normal file
@@ -0,0 +1,472 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 register (read)
|
||||
*/
|
||||
module taxi_axi_register_rd #
|
||||
(
|
||||
// AR channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter AR_REG_TYPE = 1,
|
||||
// R channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter R_REG_TYPE = 2
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
taxi_axi_if.rd_slv s_axi_rd,
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
taxi_axi_if.rd_mst m_axi_rd
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axi_rd.DATA_W;
|
||||
localparam ADDR_W = s_axi_rd.ADDR_W;
|
||||
localparam STRB_W = s_axi_rd.STRB_W;
|
||||
localparam ID_W = s_axi_rd.ID_W;
|
||||
localparam logic ARUSER_EN = s_axi_rd.ARUSER_EN && m_axi_rd.ARUSER_EN;
|
||||
localparam ARUSER_W = s_axi_rd.ARUSER_W;
|
||||
localparam logic RUSER_EN = s_axi_rd.RUSER_EN && m_axi_rd.RUSER_EN;
|
||||
localparam RUSER_W = s_axi_rd.RUSER_W;
|
||||
|
||||
if (m_axi_rd.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (m_axi_rd.STRB_W != STRB_W)
|
||||
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
|
||||
|
||||
// AR channel
|
||||
|
||||
if (AR_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_arready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] m_axi_arid_reg = '0;
|
||||
logic [ADDR_W-1:0] m_axi_araddr_reg = '0;
|
||||
logic [7:0] m_axi_arlen_reg = '0;
|
||||
logic [2:0] m_axi_arsize_reg = '0;
|
||||
logic [1:0] m_axi_arburst_reg = '0;
|
||||
logic m_axi_arlock_reg = '0;
|
||||
logic [3:0] m_axi_arcache_reg = '0;
|
||||
logic [2:0] m_axi_arprot_reg = '0;
|
||||
logic [3:0] m_axi_arqos_reg = '0;
|
||||
logic [3:0] m_axi_arregion_reg = '0;
|
||||
logic [ARUSER_W-1:0] m_axi_aruser_reg = '0;
|
||||
logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
|
||||
|
||||
logic [ID_W-1:0] temp_m_axi_arid_reg = '0;
|
||||
logic [ADDR_W-1:0] temp_m_axi_araddr_reg = '0;
|
||||
logic [7:0] temp_m_axi_arlen_reg = '0;
|
||||
logic [2:0] temp_m_axi_arsize_reg = '0;
|
||||
logic [1:0] temp_m_axi_arburst_reg = '0;
|
||||
logic temp_m_axi_arlock_reg = '0;
|
||||
logic [3:0] temp_m_axi_arcache_reg = '0;
|
||||
logic [2:0] temp_m_axi_arprot_reg = '0;
|
||||
logic [3:0] temp_m_axi_arqos_reg = '0;
|
||||
logic [3:0] temp_m_axi_arregion_reg = '0;
|
||||
logic [ARUSER_W-1:0] temp_m_axi_aruser_reg = '0;
|
||||
logic temp_m_axi_arvalid_reg = 1'b0, temp_m_axi_arvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_ar_input_to_output;
|
||||
logic store_axi_ar_input_to_temp;
|
||||
logic store_axi_ar_temp_to_output;
|
||||
|
||||
assign s_axi_rd.arready = s_axi_arready_reg;
|
||||
|
||||
assign m_axi_rd.arid = m_axi_arid_reg;
|
||||
assign m_axi_rd.araddr = m_axi_araddr_reg;
|
||||
assign m_axi_rd.arlen = m_axi_arlen_reg;
|
||||
assign m_axi_rd.arsize = m_axi_arsize_reg;
|
||||
assign m_axi_rd.arburst = m_axi_arburst_reg;
|
||||
assign m_axi_rd.arlock = m_axi_arlock_reg;
|
||||
assign m_axi_rd.arcache = m_axi_arcache_reg;
|
||||
assign m_axi_rd.arprot = m_axi_arprot_reg;
|
||||
assign m_axi_rd.arqos = m_axi_arqos_reg;
|
||||
assign m_axi_rd.arregion = m_axi_arregion_reg;
|
||||
assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0;
|
||||
assign m_axi_rd.arvalid = m_axi_arvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axi_arready_early = m_axi_rd.arready || (!temp_m_axi_arvalid_reg && (!m_axi_arvalid_reg || !s_axi_rd.arvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_arvalid_next = m_axi_arvalid_reg;
|
||||
temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg;
|
||||
|
||||
store_axi_ar_input_to_output = 1'b0;
|
||||
store_axi_ar_input_to_temp = 1'b0;
|
||||
store_axi_ar_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axi_arready_reg) begin
|
||||
// input is ready
|
||||
if (m_axi_rd.arready || !m_axi_arvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axi_arvalid_next = s_axi_rd.arvalid;
|
||||
store_axi_ar_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axi_arvalid_next = s_axi_rd.arvalid;
|
||||
store_axi_ar_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axi_rd.arready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axi_arvalid_next = temp_m_axi_arvalid_reg;
|
||||
temp_m_axi_arvalid_next = 1'b0;
|
||||
store_axi_ar_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_arready_reg <= s_axi_arready_early;
|
||||
m_axi_arvalid_reg <= m_axi_arvalid_next;
|
||||
temp_m_axi_arvalid_reg <= temp_m_axi_arvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_ar_input_to_output) begin
|
||||
m_axi_arid_reg <= s_axi_rd.arid;
|
||||
m_axi_araddr_reg <= s_axi_rd.araddr;
|
||||
m_axi_arlen_reg <= s_axi_rd.arlen;
|
||||
m_axi_arsize_reg <= s_axi_rd.arsize;
|
||||
m_axi_arburst_reg <= s_axi_rd.arburst;
|
||||
m_axi_arlock_reg <= s_axi_rd.arlock;
|
||||
m_axi_arcache_reg <= s_axi_rd.arcache;
|
||||
m_axi_arprot_reg <= s_axi_rd.arprot;
|
||||
m_axi_arqos_reg <= s_axi_rd.arqos;
|
||||
m_axi_arregion_reg <= s_axi_rd.arregion;
|
||||
m_axi_aruser_reg <= s_axi_rd.aruser;
|
||||
end else if (store_axi_ar_temp_to_output) begin
|
||||
m_axi_arid_reg <= temp_m_axi_arid_reg;
|
||||
m_axi_araddr_reg <= temp_m_axi_araddr_reg;
|
||||
m_axi_arlen_reg <= temp_m_axi_arlen_reg;
|
||||
m_axi_arsize_reg <= temp_m_axi_arsize_reg;
|
||||
m_axi_arburst_reg <= temp_m_axi_arburst_reg;
|
||||
m_axi_arlock_reg <= temp_m_axi_arlock_reg;
|
||||
m_axi_arcache_reg <= temp_m_axi_arcache_reg;
|
||||
m_axi_arprot_reg <= temp_m_axi_arprot_reg;
|
||||
m_axi_arqos_reg <= temp_m_axi_arqos_reg;
|
||||
m_axi_arregion_reg <= temp_m_axi_arregion_reg;
|
||||
m_axi_aruser_reg <= temp_m_axi_aruser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_ar_input_to_temp) begin
|
||||
temp_m_axi_arid_reg <= s_axi_rd.arid;
|
||||
temp_m_axi_araddr_reg <= s_axi_rd.araddr;
|
||||
temp_m_axi_arlen_reg <= s_axi_rd.arlen;
|
||||
temp_m_axi_arsize_reg <= s_axi_rd.arsize;
|
||||
temp_m_axi_arburst_reg <= s_axi_rd.arburst;
|
||||
temp_m_axi_arlock_reg <= s_axi_rd.arlock;
|
||||
temp_m_axi_arcache_reg <= s_axi_rd.arcache;
|
||||
temp_m_axi_arprot_reg <= s_axi_rd.arprot;
|
||||
temp_m_axi_arqos_reg <= s_axi_rd.arqos;
|
||||
temp_m_axi_arregion_reg <= s_axi_rd.arregion;
|
||||
temp_m_axi_aruser_reg <= s_axi_rd.aruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_arready_reg <= 1'b0;
|
||||
m_axi_arvalid_reg <= 1'b0;
|
||||
temp_m_axi_arvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (AR_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_arready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] m_axi_arid_reg = '0;
|
||||
logic [ADDR_W-1:0] m_axi_araddr_reg = '0;
|
||||
logic [7:0] m_axi_arlen_reg = '0;
|
||||
logic [2:0] m_axi_arsize_reg = '0;
|
||||
logic [1:0] m_axi_arburst_reg = '0;
|
||||
logic m_axi_arlock_reg = '0;
|
||||
logic [3:0] m_axi_arcache_reg = '0;
|
||||
logic [2:0] m_axi_arprot_reg = '0;
|
||||
logic [3:0] m_axi_arqos_reg = '0;
|
||||
logic [3:0] m_axi_arregion_reg = '0;
|
||||
logic [ARUSER_W-1:0] m_axi_aruser_reg = '0;
|
||||
logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_ar_input_to_output;
|
||||
|
||||
assign s_axi_rd.arready = s_axi_arready_reg;
|
||||
|
||||
assign m_axi_rd.arid = m_axi_arid_reg;
|
||||
assign m_axi_rd.araddr = m_axi_araddr_reg;
|
||||
assign m_axi_rd.arlen = m_axi_arlen_reg;
|
||||
assign m_axi_rd.arsize = m_axi_arsize_reg;
|
||||
assign m_axi_rd.arburst = m_axi_arburst_reg;
|
||||
assign m_axi_rd.arlock = m_axi_arlock_reg;
|
||||
assign m_axi_rd.arcache = m_axi_arcache_reg;
|
||||
assign m_axi_rd.arprot = m_axi_arprot_reg;
|
||||
assign m_axi_rd.arqos = m_axi_arqos_reg;
|
||||
assign m_axi_rd.arregion = m_axi_arregion_reg;
|
||||
assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0;
|
||||
assign m_axi_rd.arvalid = m_axi_arvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axi_arready_early = !m_axi_arvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_arvalid_next = m_axi_arvalid_reg;
|
||||
|
||||
store_axi_ar_input_to_output = 1'b0;
|
||||
|
||||
if (s_axi_arready_reg) begin
|
||||
m_axi_arvalid_next = s_axi_rd.arvalid;
|
||||
store_axi_ar_input_to_output = 1'b1;
|
||||
end else if (m_axi_rd.arready) begin
|
||||
m_axi_arvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_arready_reg <= s_axi_arready_early;
|
||||
m_axi_arvalid_reg <= m_axi_arvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_ar_input_to_output) begin
|
||||
m_axi_arid_reg <= s_axi_rd.arid;
|
||||
m_axi_araddr_reg <= s_axi_rd.araddr;
|
||||
m_axi_arlen_reg <= s_axi_rd.arlen;
|
||||
m_axi_arsize_reg <= s_axi_rd.arsize;
|
||||
m_axi_arburst_reg <= s_axi_rd.arburst;
|
||||
m_axi_arlock_reg <= s_axi_rd.arlock;
|
||||
m_axi_arcache_reg <= s_axi_rd.arcache;
|
||||
m_axi_arprot_reg <= s_axi_rd.arprot;
|
||||
m_axi_arqos_reg <= s_axi_rd.arqos;
|
||||
m_axi_arregion_reg <= s_axi_rd.arregion;
|
||||
m_axi_aruser_reg <= s_axi_rd.aruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_arready_reg <= 1'b0;
|
||||
m_axi_arvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass AR channel
|
||||
assign m_axi_rd.arid = s_axi_rd.arid;
|
||||
assign m_axi_rd.araddr = s_axi_rd.araddr;
|
||||
assign m_axi_rd.arlen = s_axi_rd.arlen;
|
||||
assign m_axi_rd.arsize = s_axi_rd.arsize;
|
||||
assign m_axi_rd.arburst = s_axi_rd.arburst;
|
||||
assign m_axi_rd.arlock = s_axi_rd.arlock;
|
||||
assign m_axi_rd.arcache = s_axi_rd.arcache;
|
||||
assign m_axi_rd.arprot = s_axi_rd.arprot;
|
||||
assign m_axi_rd.arqos = s_axi_rd.arqos;
|
||||
assign m_axi_rd.arregion = s_axi_rd.arregion;
|
||||
assign m_axi_rd.aruser = ARUSER_EN ? s_axi_rd.aruser : '0;
|
||||
assign m_axi_rd.arvalid = s_axi_rd.arvalid;
|
||||
assign s_axi_rd.arready = m_axi_rd.arready;
|
||||
|
||||
end
|
||||
|
||||
// R channel
|
||||
|
||||
if (R_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axi_rready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] s_axi_rid_reg = '0;
|
||||
logic [DATA_W-1:0] s_axi_rdata_reg = '0;
|
||||
logic [1:0] s_axi_rresp_reg = 2'b0;
|
||||
logic s_axi_rlast_reg = 1'b0;
|
||||
logic [RUSER_W-1:0] s_axi_ruser_reg = '0;
|
||||
logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
|
||||
|
||||
logic [ID_W-1:0] temp_s_axi_rid_reg = '0;
|
||||
logic [DATA_W-1:0] temp_s_axi_rdata_reg = '0;
|
||||
logic [1:0] temp_s_axi_rresp_reg = 2'b0;
|
||||
logic temp_s_axi_rlast_reg = 1'b0;
|
||||
logic [RUSER_W-1:0] temp_s_axi_ruser_reg = '0;
|
||||
logic temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_r_input_to_output;
|
||||
logic store_axi_r_input_to_temp;
|
||||
logic store_axi_r_temp_to_output;
|
||||
|
||||
assign m_axi_rd.rready = m_axi_rready_reg;
|
||||
|
||||
assign s_axi_rd.rid = s_axi_rid_reg;
|
||||
assign s_axi_rd.rdata = s_axi_rdata_reg;
|
||||
assign s_axi_rd.rresp = s_axi_rresp_reg;
|
||||
assign s_axi_rd.rlast = s_axi_rlast_reg;
|
||||
assign s_axi_rd.ruser = RUSER_EN ? s_axi_ruser_reg : '0;
|
||||
assign s_axi_rd.rvalid = s_axi_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire m_axi_rready_early = s_axi_rd.rready || (!temp_s_axi_rvalid_reg && (!s_axi_rvalid_reg || !m_axi_rd.rvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axi_rvalid_next = s_axi_rvalid_reg;
|
||||
temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;
|
||||
|
||||
store_axi_r_input_to_output = 1'b0;
|
||||
store_axi_r_input_to_temp = 1'b0;
|
||||
store_axi_r_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axi_rready_reg) begin
|
||||
// input is ready
|
||||
if (s_axi_rd.rready || !s_axi_rvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axi_rvalid_next = m_axi_rd.rvalid;
|
||||
store_axi_r_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axi_rvalid_next = m_axi_rd.rvalid;
|
||||
store_axi_r_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (s_axi_rd.rready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axi_rvalid_next = temp_s_axi_rvalid_reg;
|
||||
temp_s_axi_rvalid_next = 1'b0;
|
||||
store_axi_r_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axi_rready_reg <= m_axi_rready_early;
|
||||
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
||||
temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_r_input_to_output) begin
|
||||
s_axi_rid_reg <= m_axi_rd.rid;
|
||||
s_axi_rdata_reg <= m_axi_rd.rdata;
|
||||
s_axi_rresp_reg <= m_axi_rd.rresp;
|
||||
s_axi_rlast_reg <= m_axi_rd.rlast;
|
||||
s_axi_ruser_reg <= m_axi_rd.ruser;
|
||||
end else if (store_axi_r_temp_to_output) begin
|
||||
s_axi_rid_reg <= temp_s_axi_rid_reg;
|
||||
s_axi_rdata_reg <= temp_s_axi_rdata_reg;
|
||||
s_axi_rresp_reg <= temp_s_axi_rresp_reg;
|
||||
s_axi_rlast_reg <= temp_s_axi_rlast_reg;
|
||||
s_axi_ruser_reg <= temp_s_axi_ruser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_r_input_to_temp) begin
|
||||
temp_s_axi_rid_reg <= m_axi_rd.rid;
|
||||
temp_s_axi_rdata_reg <= m_axi_rd.rdata;
|
||||
temp_s_axi_rresp_reg <= m_axi_rd.rresp;
|
||||
temp_s_axi_rlast_reg <= m_axi_rd.rlast;
|
||||
temp_s_axi_ruser_reg <= m_axi_rd.ruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axi_rready_reg <= 1'b0;
|
||||
s_axi_rvalid_reg <= 1'b0;
|
||||
temp_s_axi_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (R_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axi_rready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] s_axi_rid_reg = '0;
|
||||
logic [DATA_W-1:0] s_axi_rdata_reg = '0;
|
||||
logic [1:0] s_axi_rresp_reg = 2'b0;
|
||||
logic s_axi_rlast_reg = 1'b0;
|
||||
logic [RUSER_W-1:0] s_axi_ruser_reg = '0;
|
||||
logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_r_input_to_output;
|
||||
|
||||
assign m_axi_rd.rready = m_axi_rready_reg;
|
||||
|
||||
assign s_axi_rd.rid = s_axi_rid_reg;
|
||||
assign s_axi_rd.rdata = s_axi_rdata_reg;
|
||||
assign s_axi_rd.rresp = s_axi_rresp_reg;
|
||||
assign s_axi_rd.rlast = s_axi_rlast_reg;
|
||||
assign s_axi_rd.ruser = RUSER_EN ? s_axi_ruser_reg : '0;
|
||||
assign s_axi_rd.rvalid = s_axi_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axi_rready_early = !s_axi_rvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axi_rvalid_next = s_axi_rvalid_reg;
|
||||
|
||||
store_axi_r_input_to_output = 1'b0;
|
||||
|
||||
if (m_axi_rready_reg) begin
|
||||
s_axi_rvalid_next = m_axi_rd.rvalid;
|
||||
store_axi_r_input_to_output = 1'b1;
|
||||
end else if (s_axi_rd.rready) begin
|
||||
s_axi_rvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axi_rready_reg <= m_axi_rready_early;
|
||||
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_r_input_to_output) begin
|
||||
s_axi_rid_reg <= m_axi_rd.rid;
|
||||
s_axi_rdata_reg <= m_axi_rd.rdata;
|
||||
s_axi_rresp_reg <= m_axi_rd.rresp;
|
||||
s_axi_rlast_reg <= m_axi_rd.rlast;
|
||||
s_axi_ruser_reg <= m_axi_rd.ruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axi_rready_reg <= 1'b0;
|
||||
s_axi_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass R channel
|
||||
assign s_axi_rd.rid = m_axi_rd.rid;
|
||||
assign s_axi_rd.rdata = m_axi_rd.rdata;
|
||||
assign s_axi_rd.rresp = m_axi_rd.rresp;
|
||||
assign s_axi_rd.rlast = m_axi_rd.rlast;
|
||||
assign s_axi_rd.ruser = RUSER_EN ? m_axi_rd.ruser : '0;
|
||||
assign s_axi_rd.rvalid = m_axi_rd.rvalid;
|
||||
assign m_axi_rd.rready = s_axi_rd.rready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
623
src/axi/rtl/taxi_axi_register_wr.sv
Normal file
623
src/axi/rtl/taxi_axi_register_wr.sv
Normal file
@@ -0,0 +1,623 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 register (write)
|
||||
*/
|
||||
module taxi_axi_register_wr #
|
||||
(
|
||||
// AW channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter AW_REG_TYPE = 1,
|
||||
// W channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter W_REG_TYPE = 2,
|
||||
// B channel register type
|
||||
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
|
||||
parameter B_REG_TYPE = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
taxi_axi_if.wr_slv s_axi_wr,
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
taxi_axi_if.wr_mst m_axi_wr
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axi_wr.DATA_W;
|
||||
localparam ADDR_W = s_axi_wr.ADDR_W;
|
||||
localparam STRB_W = s_axi_wr.STRB_W;
|
||||
localparam ID_W = s_axi_wr.ID_W;
|
||||
localparam logic AWUSER_EN = s_axi_wr.AWUSER_EN && m_axi_wr.AWUSER_EN;
|
||||
localparam AWUSER_W = s_axi_wr.AWUSER_W;
|
||||
localparam logic WUSER_EN = s_axi_wr.WUSER_EN && m_axi_wr.WUSER_EN;
|
||||
localparam WUSER_W = s_axi_wr.WUSER_W;
|
||||
localparam logic BUSER_EN = s_axi_wr.BUSER_EN && m_axi_wr.BUSER_EN;
|
||||
localparam BUSER_W = s_axi_wr.BUSER_W;
|
||||
|
||||
if (m_axi_wr.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (m_axi_wr.STRB_W != STRB_W)
|
||||
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
|
||||
|
||||
// AW channel
|
||||
|
||||
if (AW_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_awready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] m_axi_awid_reg = '0;
|
||||
logic [ADDR_W-1:0] m_axi_awaddr_reg = '0;
|
||||
logic [7:0] m_axi_awlen_reg = '0;
|
||||
logic [2:0] m_axi_awsize_reg = '0;
|
||||
logic [1:0] m_axi_awburst_reg = '0;
|
||||
logic m_axi_awlock_reg = '0;
|
||||
logic [3:0] m_axi_awcache_reg = '0;
|
||||
logic [2:0] m_axi_awprot_reg = '0;
|
||||
logic [3:0] m_axi_awqos_reg = '0;
|
||||
logic [3:0] m_axi_awregion_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axi_awuser_reg = '0;
|
||||
logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
|
||||
|
||||
logic [ID_W-1:0] temp_m_axi_awid_reg = '0;
|
||||
logic [ADDR_W-1:0] temp_m_axi_awaddr_reg = '0;
|
||||
logic [7:0] temp_m_axi_awlen_reg = '0;
|
||||
logic [2:0] temp_m_axi_awsize_reg = '0;
|
||||
logic [1:0] temp_m_axi_awburst_reg = '0;
|
||||
logic temp_m_axi_awlock_reg = '0;
|
||||
logic [3:0] temp_m_axi_awcache_reg = '0;
|
||||
logic [2:0] temp_m_axi_awprot_reg = '0;
|
||||
logic [3:0] temp_m_axi_awqos_reg = '0;
|
||||
logic [3:0] temp_m_axi_awregion_reg = '0;
|
||||
logic [AWUSER_W-1:0] temp_m_axi_awuser_reg = '0;
|
||||
logic temp_m_axi_awvalid_reg = 1'b0, temp_m_axi_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_aw_input_to_output;
|
||||
logic store_axi_aw_input_to_temp;
|
||||
logic store_axi_aw_temp_to_output;
|
||||
|
||||
assign s_axi_wr.awready = s_axi_awready_reg;
|
||||
|
||||
assign m_axi_wr.awid = m_axi_awid_reg;
|
||||
assign m_axi_wr.awaddr = m_axi_awaddr_reg;
|
||||
assign m_axi_wr.awlen = m_axi_awlen_reg;
|
||||
assign m_axi_wr.awsize = m_axi_awsize_reg;
|
||||
assign m_axi_wr.awburst = m_axi_awburst_reg;
|
||||
assign m_axi_wr.awlock = m_axi_awlock_reg;
|
||||
assign m_axi_wr.awcache = m_axi_awcache_reg;
|
||||
assign m_axi_wr.awprot = m_axi_awprot_reg;
|
||||
assign m_axi_wr.awqos = m_axi_awqos_reg;
|
||||
assign m_axi_wr.awregion = m_axi_awregion_reg;
|
||||
assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0;
|
||||
assign m_axi_wr.awvalid = m_axi_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axi_awready_early = m_axi_wr.awready || (!temp_m_axi_awvalid_reg && (!m_axi_awvalid_reg || !s_axi_wr.awvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_awvalid_next = m_axi_awvalid_reg;
|
||||
temp_m_axi_awvalid_next = temp_m_axi_awvalid_reg;
|
||||
|
||||
store_axi_aw_input_to_output = 1'b0;
|
||||
store_axi_aw_input_to_temp = 1'b0;
|
||||
store_axi_aw_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axi_awready_reg) begin
|
||||
// input is ready
|
||||
if (m_axi_wr.awready || !m_axi_awvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axi_awvalid_next = s_axi_wr.awvalid;
|
||||
store_axi_aw_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axi_awvalid_next = s_axi_wr.awvalid;
|
||||
store_axi_aw_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axi_wr.awready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axi_awvalid_next = temp_m_axi_awvalid_reg;
|
||||
temp_m_axi_awvalid_next = 1'b0;
|
||||
store_axi_aw_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_awready_reg <= s_axi_awready_early;
|
||||
m_axi_awvalid_reg <= m_axi_awvalid_next;
|
||||
temp_m_axi_awvalid_reg <= temp_m_axi_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_aw_input_to_output) begin
|
||||
m_axi_awid_reg <= s_axi_wr.awid;
|
||||
m_axi_awaddr_reg <= s_axi_wr.awaddr;
|
||||
m_axi_awlen_reg <= s_axi_wr.awlen;
|
||||
m_axi_awsize_reg <= s_axi_wr.awsize;
|
||||
m_axi_awburst_reg <= s_axi_wr.awburst;
|
||||
m_axi_awlock_reg <= s_axi_wr.awlock;
|
||||
m_axi_awcache_reg <= s_axi_wr.awcache;
|
||||
m_axi_awprot_reg <= s_axi_wr.awprot;
|
||||
m_axi_awqos_reg <= s_axi_wr.awqos;
|
||||
m_axi_awregion_reg <= s_axi_wr.awregion;
|
||||
m_axi_awuser_reg <= s_axi_wr.awuser;
|
||||
end else if (store_axi_aw_temp_to_output) begin
|
||||
m_axi_awid_reg <= temp_m_axi_awid_reg;
|
||||
m_axi_awaddr_reg <= temp_m_axi_awaddr_reg;
|
||||
m_axi_awlen_reg <= temp_m_axi_awlen_reg;
|
||||
m_axi_awsize_reg <= temp_m_axi_awsize_reg;
|
||||
m_axi_awburst_reg <= temp_m_axi_awburst_reg;
|
||||
m_axi_awlock_reg <= temp_m_axi_awlock_reg;
|
||||
m_axi_awcache_reg <= temp_m_axi_awcache_reg;
|
||||
m_axi_awprot_reg <= temp_m_axi_awprot_reg;
|
||||
m_axi_awqos_reg <= temp_m_axi_awqos_reg;
|
||||
m_axi_awregion_reg <= temp_m_axi_awregion_reg;
|
||||
m_axi_awuser_reg <= temp_m_axi_awuser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_aw_input_to_temp) begin
|
||||
temp_m_axi_awid_reg <= s_axi_wr.awid;
|
||||
temp_m_axi_awaddr_reg <= s_axi_wr.awaddr;
|
||||
temp_m_axi_awlen_reg <= s_axi_wr.awlen;
|
||||
temp_m_axi_awsize_reg <= s_axi_wr.awsize;
|
||||
temp_m_axi_awburst_reg <= s_axi_wr.awburst;
|
||||
temp_m_axi_awlock_reg <= s_axi_wr.awlock;
|
||||
temp_m_axi_awcache_reg <= s_axi_wr.awcache;
|
||||
temp_m_axi_awprot_reg <= s_axi_wr.awprot;
|
||||
temp_m_axi_awqos_reg <= s_axi_wr.awqos;
|
||||
temp_m_axi_awregion_reg <= s_axi_wr.awregion;
|
||||
temp_m_axi_awuser_reg <= s_axi_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_awready_reg <= 1'b0;
|
||||
m_axi_awvalid_reg <= 1'b0;
|
||||
temp_m_axi_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (AW_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_awready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] m_axi_awid_reg = '0;
|
||||
logic [ADDR_W-1:0] m_axi_awaddr_reg = '0;
|
||||
logic [7:0] m_axi_awlen_reg = '0;
|
||||
logic [2:0] m_axi_awsize_reg = '0;
|
||||
logic [1:0] m_axi_awburst_reg = '0;
|
||||
logic m_axi_awlock_reg = '0;
|
||||
logic [3:0] m_axi_awcache_reg = '0;
|
||||
logic [2:0] m_axi_awprot_reg = '0;
|
||||
logic [3:0] m_axi_awqos_reg = '0;
|
||||
logic [3:0] m_axi_awregion_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axi_awuser_reg = '0;
|
||||
logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_aw_input_to_output;
|
||||
|
||||
assign s_axi_wr.awready = s_axi_awready_reg;
|
||||
|
||||
assign m_axi_wr.awid = m_axi_awid_reg;
|
||||
assign m_axi_wr.awaddr = m_axi_awaddr_reg;
|
||||
assign m_axi_wr.awlen = m_axi_awlen_reg;
|
||||
assign m_axi_wr.awsize = m_axi_awsize_reg;
|
||||
assign m_axi_wr.awburst = m_axi_awburst_reg;
|
||||
assign m_axi_wr.awlock = m_axi_awlock_reg;
|
||||
assign m_axi_wr.awcache = m_axi_awcache_reg;
|
||||
assign m_axi_wr.awprot = m_axi_awprot_reg;
|
||||
assign m_axi_wr.awqos = m_axi_awqos_reg;
|
||||
assign m_axi_wr.awregion = m_axi_awregion_reg;
|
||||
assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0;
|
||||
assign m_axi_wr.awvalid = m_axi_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axi_awready_eawly = !m_axi_awvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_awvalid_next = m_axi_awvalid_reg;
|
||||
|
||||
store_axi_aw_input_to_output = 1'b0;
|
||||
|
||||
if (s_axi_awready_reg) begin
|
||||
m_axi_awvalid_next = s_axi_wr.awvalid;
|
||||
store_axi_aw_input_to_output = 1'b1;
|
||||
end else if (m_axi_wr.awready) begin
|
||||
m_axi_awvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_awready_reg <= s_axi_awready_eawly;
|
||||
m_axi_awvalid_reg <= m_axi_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_aw_input_to_output) begin
|
||||
m_axi_awid_reg <= s_axi_wr.awid;
|
||||
m_axi_awaddr_reg <= s_axi_wr.awaddr;
|
||||
m_axi_awlen_reg <= s_axi_wr.awlen;
|
||||
m_axi_awsize_reg <= s_axi_wr.awsize;
|
||||
m_axi_awburst_reg <= s_axi_wr.awburst;
|
||||
m_axi_awlock_reg <= s_axi_wr.awlock;
|
||||
m_axi_awcache_reg <= s_axi_wr.awcache;
|
||||
m_axi_awprot_reg <= s_axi_wr.awprot;
|
||||
m_axi_awqos_reg <= s_axi_wr.awqos;
|
||||
m_axi_awregion_reg <= s_axi_wr.awregion;
|
||||
m_axi_awuser_reg <= s_axi_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_awready_reg <= 1'b0;
|
||||
m_axi_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass AW channel
|
||||
assign m_axi_wr.awid = s_axi_wr.awid;
|
||||
assign m_axi_wr.awaddr = s_axi_wr.awaddr;
|
||||
assign m_axi_wr.awlen = s_axi_wr.awlen;
|
||||
assign m_axi_wr.awsize = s_axi_wr.awsize;
|
||||
assign m_axi_wr.awburst = s_axi_wr.awburst;
|
||||
assign m_axi_wr.awlock = s_axi_wr.awlock;
|
||||
assign m_axi_wr.awcache = s_axi_wr.awcache;
|
||||
assign m_axi_wr.awprot = s_axi_wr.awprot;
|
||||
assign m_axi_wr.awqos = s_axi_wr.awqos;
|
||||
assign m_axi_wr.awregion = s_axi_wr.awregion;
|
||||
assign m_axi_wr.awuser = AWUSER_EN ? s_axi_wr.awuser : '0;
|
||||
assign m_axi_wr.awvalid = s_axi_wr.awvalid;
|
||||
assign s_axi_wr.awready = m_axi_wr.awready;
|
||||
|
||||
end
|
||||
|
||||
// W channel
|
||||
|
||||
if (W_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axi_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axi_wstrb_reg = '0;
|
||||
logic m_axi_wlast_reg = 1'b0;
|
||||
logic [WUSER_W-1:0] m_axi_wuser_reg = '0;
|
||||
logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
|
||||
|
||||
logic [DATA_W-1:0] temp_m_axi_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] temp_m_axi_wstrb_reg = '0;
|
||||
logic temp_m_axi_wlast_reg = 1'b0;
|
||||
logic [WUSER_W-1:0] temp_m_axi_wuser_reg = '0;
|
||||
logic temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_w_input_to_output;
|
||||
logic store_axi_w_input_to_temp;
|
||||
logic store_axi_w_temp_to_output;
|
||||
|
||||
assign s_axi_wr.wready = s_axi_wready_reg;
|
||||
|
||||
assign m_axi_wr.wdata = m_axi_wdata_reg;
|
||||
assign m_axi_wr.wstrb = m_axi_wstrb_reg;
|
||||
assign m_axi_wr.wlast = m_axi_wlast_reg;
|
||||
assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0;
|
||||
assign m_axi_wr.wvalid = m_axi_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axi_wready_early = m_axi_wr.wready || (!temp_m_axi_wvalid_reg && (!m_axi_wvalid_reg || !s_axi_wr.wvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_wvalid_next = m_axi_wvalid_reg;
|
||||
temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
|
||||
|
||||
store_axi_w_input_to_output = 1'b0;
|
||||
store_axi_w_input_to_temp = 1'b0;
|
||||
store_axi_w_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axi_wready_reg) begin
|
||||
// input is ready
|
||||
if (m_axi_wr.wready || !m_axi_wvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axi_wvalid_next = s_axi_wr.wvalid;
|
||||
store_axi_w_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axi_wvalid_next = s_axi_wr.wvalid;
|
||||
store_axi_w_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axi_wr.wready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axi_wvalid_next = temp_m_axi_wvalid_reg;
|
||||
temp_m_axi_wvalid_next = 1'b0;
|
||||
store_axi_w_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_wready_reg <= s_axi_wready_early;
|
||||
m_axi_wvalid_reg <= m_axi_wvalid_next;
|
||||
temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_w_input_to_output) begin
|
||||
m_axi_wdata_reg <= s_axi_wr.wdata;
|
||||
m_axi_wstrb_reg <= s_axi_wr.wstrb;
|
||||
m_axi_wlast_reg <= s_axi_wr.wlast;
|
||||
m_axi_wuser_reg <= s_axi_wr.wuser;
|
||||
end else if (store_axi_w_temp_to_output) begin
|
||||
m_axi_wdata_reg <= temp_m_axi_wdata_reg;
|
||||
m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
|
||||
m_axi_wlast_reg <= temp_m_axi_wlast_reg;
|
||||
m_axi_wuser_reg <= temp_m_axi_wuser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_w_input_to_temp) begin
|
||||
temp_m_axi_wdata_reg <= s_axi_wr.wdata;
|
||||
temp_m_axi_wstrb_reg <= s_axi_wr.wstrb;
|
||||
temp_m_axi_wlast_reg <= s_axi_wr.wlast;
|
||||
temp_m_axi_wuser_reg <= s_axi_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_wready_reg <= 1'b0;
|
||||
m_axi_wvalid_reg <= 1'b0;
|
||||
temp_m_axi_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (W_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axi_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axi_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axi_wstrb_reg = '0;
|
||||
logic m_axi_wlast_reg = 1'b0;
|
||||
logic [WUSER_W-1:0] m_axi_wuser_reg = '0;
|
||||
logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_w_input_to_output;
|
||||
|
||||
assign s_axi_wr.wready = s_axi_wready_reg;
|
||||
|
||||
assign m_axi_wr.wdata = m_axi_wdata_reg;
|
||||
assign m_axi_wr.wstrb = m_axi_wstrb_reg;
|
||||
assign m_axi_wr.wlast = m_axi_wlast_reg;
|
||||
assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0;
|
||||
assign m_axi_wr.wvalid = m_axi_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axi_wready_ewly = !m_axi_wvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axi_wvalid_next = m_axi_wvalid_reg;
|
||||
|
||||
store_axi_w_input_to_output = 1'b0;
|
||||
|
||||
if (s_axi_wready_reg) begin
|
||||
m_axi_wvalid_next = s_axi_wr.wvalid;
|
||||
store_axi_w_input_to_output = 1'b1;
|
||||
end else if (m_axi_wr.wready) begin
|
||||
m_axi_wvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axi_wready_reg <= s_axi_wready_ewly;
|
||||
m_axi_wvalid_reg <= m_axi_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_w_input_to_output) begin
|
||||
m_axi_wdata_reg <= s_axi_wr.wdata;
|
||||
m_axi_wstrb_reg <= s_axi_wr.wstrb;
|
||||
m_axi_wlast_reg <= s_axi_wr.wlast;
|
||||
m_axi_wuser_reg <= s_axi_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axi_wready_reg <= 1'b0;
|
||||
m_axi_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass W channel
|
||||
assign m_axi_wr.wdata = s_axi_wr.wdata;
|
||||
assign m_axi_wr.wstrb = s_axi_wr.wstrb;
|
||||
assign m_axi_wr.wlast = s_axi_wr.wlast;
|
||||
assign m_axi_wr.wuser = WUSER_EN ? s_axi_wr.wuser : '0;
|
||||
assign m_axi_wr.wvalid = s_axi_wr.wvalid;
|
||||
assign s_axi_wr.wready = m_axi_wr.wready;
|
||||
|
||||
end
|
||||
|
||||
// B channel
|
||||
|
||||
if (B_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axi_bready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] s_axi_bid_reg = '0;
|
||||
logic [1:0] s_axi_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axi_buser_reg = '0;
|
||||
logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
|
||||
|
||||
logic [ID_W-1:0] temp_s_axi_bid_reg = '0;
|
||||
logic [1:0] temp_s_axi_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] temp_s_axi_buser_reg = '0;
|
||||
logic temp_s_axi_bvalid_reg = 1'b0, temp_s_axi_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_b_input_to_output;
|
||||
logic store_axi_b_input_to_temp;
|
||||
logic store_axi_b_temp_to_output;
|
||||
|
||||
assign m_axi_wr.bready = m_axi_bready_reg;
|
||||
|
||||
assign s_axi_wr.bid = s_axi_bid_reg;
|
||||
assign s_axi_wr.bresp = s_axi_bresp_reg;
|
||||
assign s_axi_wr.buser = BUSER_EN ? s_axi_buser_reg : '0;
|
||||
assign s_axi_wr.bvalid = s_axi_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire m_axi_bready_early = s_axi_wr.bready || (!temp_s_axi_bvalid_reg && (!s_axi_bvalid_reg || !m_axi_wr.bvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axi_bvalid_next = s_axi_bvalid_reg;
|
||||
temp_s_axi_bvalid_next = temp_s_axi_bvalid_reg;
|
||||
|
||||
store_axi_b_input_to_output = 1'b0;
|
||||
store_axi_b_input_to_temp = 1'b0;
|
||||
store_axi_b_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axi_bready_reg) begin
|
||||
// input is ready
|
||||
if (s_axi_wr.bready || !s_axi_bvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axi_bvalid_next = m_axi_wr.bvalid;
|
||||
store_axi_b_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axi_bvalid_next = m_axi_wr.bvalid;
|
||||
store_axi_b_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (s_axi_wr.bready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axi_bvalid_next = temp_s_axi_bvalid_reg;
|
||||
temp_s_axi_bvalid_next = 1'b0;
|
||||
store_axi_b_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axi_bready_reg <= m_axi_bready_early;
|
||||
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
||||
temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_b_input_to_output) begin
|
||||
s_axi_bid_reg <= m_axi_wr.bid;
|
||||
s_axi_bresp_reg <= m_axi_wr.bresp;
|
||||
s_axi_buser_reg <= m_axi_wr.buser;
|
||||
end else if (store_axi_b_temp_to_output) begin
|
||||
s_axi_bid_reg <= temp_s_axi_bid_reg;
|
||||
s_axi_bresp_reg <= temp_s_axi_bresp_reg;
|
||||
s_axi_buser_reg <= temp_s_axi_buser_reg;
|
||||
end
|
||||
|
||||
if (store_axi_b_input_to_temp) begin
|
||||
temp_s_axi_bid_reg <= m_axi_wr.bid;
|
||||
temp_s_axi_bresp_reg <= m_axi_wr.bresp;
|
||||
temp_s_axi_buser_reg <= m_axi_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axi_bready_reg <= 1'b0;
|
||||
s_axi_bvalid_reg <= 1'b0;
|
||||
temp_s_axi_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (B_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axi_bready_reg = 1'b0;
|
||||
|
||||
logic [ID_W-1:0] s_axi_bid_reg = '0;
|
||||
logic [1:0] s_axi_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axi_buser_reg = '0;
|
||||
logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axi_b_input_to_output;
|
||||
|
||||
assign m_axi_wr.bready = m_axi_bready_reg;
|
||||
|
||||
assign s_axi_wr.bid = s_axi_bid_reg;
|
||||
assign s_axi_wr.bresp = s_axi_bresp_reg;
|
||||
assign s_axi_wr.buser = BUSER_EN ? s_axi_buser_reg : '0;
|
||||
assign s_axi_wr.bvalid = s_axi_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axi_bready_early = !s_axi_bvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axi_bvalid_next = s_axi_bvalid_reg;
|
||||
|
||||
store_axi_b_input_to_output = 1'b0;
|
||||
|
||||
if (m_axi_bready_reg) begin
|
||||
s_axi_bvalid_next = m_axi_wr.bvalid;
|
||||
store_axi_b_input_to_output = 1'b1;
|
||||
end else if (s_axi_wr.bready) begin
|
||||
s_axi_bvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axi_bready_reg <= m_axi_bready_early;
|
||||
s_axi_bvalid_reg <= s_axi_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axi_b_input_to_output) begin
|
||||
s_axi_bid_reg <= m_axi_wr.bid;
|
||||
s_axi_bresp_reg <= m_axi_wr.bresp;
|
||||
s_axi_buser_reg <= m_axi_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axi_bready_reg <= 1'b0;
|
||||
s_axi_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass B channel
|
||||
assign s_axi_wr.bid = m_axi_wr.bid;
|
||||
assign s_axi_wr.bresp = m_axi_wr.bresp;
|
||||
assign s_axi_wr.buser = BUSER_EN ? m_axi_wr.buser : '0;
|
||||
assign s_axi_wr.bvalid = m_axi_wr.bvalid;
|
||||
assign m_axi_wr.bready = s_axi_wr.bready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
284
src/axi/rtl/taxi_axil_dp_ram.sv
Normal file
284
src/axi/rtl/taxi_axil_dp_ram.sv
Normal file
@@ -0,0 +1,284 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Lite dual-port RAM
|
||||
*/
|
||||
module taxi_axil_dp_ram #
|
||||
(
|
||||
// Width of address bus in bits
|
||||
parameter ADDR_W = 16,
|
||||
// Extra pipeline register on output
|
||||
parameter logic PIPELINE_OUTPUT = 1'b0
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Port A
|
||||
*/
|
||||
input wire logic a_clk,
|
||||
input wire logic a_rst,
|
||||
taxi_axil_if.wr_slv s_axil_wr_a,
|
||||
taxi_axil_if.rd_slv s_axil_rd_a,
|
||||
|
||||
/*
|
||||
* Port B
|
||||
*/
|
||||
input wire logic b_clk,
|
||||
input wire logic b_rst,
|
||||
taxi_axil_if.wr_slv s_axil_wr_b,
|
||||
taxi_axil_if.rd_slv s_axil_rd_b
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axil_wr_a.DATA_W;
|
||||
localparam STRB_W = s_axil_wr_a.STRB_W;
|
||||
|
||||
localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
|
||||
localparam BYTE_LANES = STRB_W;
|
||||
localparam BYTE_W = DATA_W/BYTE_LANES;
|
||||
|
||||
// check configuration
|
||||
if (BYTE_W * STRB_W != DATA_W)
|
||||
$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
|
||||
|
||||
if (2**$clog2(BYTE_LANES) != BYTE_LANES)
|
||||
$fatal(0, "Error: AXI word width must be even power of two (instance %m)");
|
||||
|
||||
if (s_axil_wr_a.DATA_W != s_axil_rd_a.DATA_W || s_axil_wr_b.DATA_W != s_axil_rd_b.DATA_W || s_axil_wr_a.DATA_W != s_axil_wr_b.DATA_W)
|
||||
$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
|
||||
|
||||
if (s_axil_wr_a.ADDR_W < ADDR_W || s_axil_wr_a.ADDR_W < ADDR_W || s_axil_rd_b.ADDR_W < ADDR_W || s_axil_rd_b.ADDR_W < ADDR_W)
|
||||
$fatal(0, "Error: AXI address width is insufficient (instance %m)");
|
||||
|
||||
logic read_eligible_a;
|
||||
logic write_eligible_a;
|
||||
|
||||
logic read_eligible_b;
|
||||
logic write_eligible_b;
|
||||
|
||||
logic mem_wr_en_a;
|
||||
logic mem_rd_en_a;
|
||||
|
||||
logic mem_wr_en_b;
|
||||
logic mem_rd_en_b;
|
||||
|
||||
logic last_read_a_reg = 1'b0, last_read_a_next;
|
||||
logic last_read_b_reg = 1'b0, last_read_b_next;
|
||||
|
||||
logic s_axil_a_awready_reg = 1'b0, s_axil_a_awready_next;
|
||||
logic s_axil_a_wready_reg = 1'b0, s_axil_a_wready_next;
|
||||
logic s_axil_a_bvalid_reg = 1'b0, s_axil_a_bvalid_next;
|
||||
logic s_axil_a_arready_reg = 1'b0, s_axil_a_arready_next;
|
||||
logic [DATA_W-1:0] s_axil_a_rdata_reg = '0, s_axil_a_rdata_next;
|
||||
logic s_axil_a_rvalid_reg = 1'b0, s_axil_a_rvalid_next;
|
||||
logic [DATA_W-1:0] s_axil_a_rdata_pipe_reg = '0;
|
||||
logic s_axil_a_rvalid_pipe_reg = 1'b0;
|
||||
|
||||
logic s_axil_b_awready_reg = 1'b0, s_axil_b_awready_next;
|
||||
logic s_axil_b_wready_reg = 1'b0, s_axil_b_wready_next;
|
||||
logic s_axil_b_bvalid_reg = 1'b0, s_axil_b_bvalid_next;
|
||||
logic s_axil_b_arready_reg = 1'b0, s_axil_b_arready_next;
|
||||
logic [DATA_W-1:0] s_axil_b_rdata_reg = '0, s_axil_b_rdata_next;
|
||||
logic s_axil_b_rvalid_reg = 1'b0, s_axil_b_rvalid_next;
|
||||
logic [DATA_W-1:0] s_axil_b_rdata_pipe_reg = '0;
|
||||
logic s_axil_b_rvalid_pipe_reg = 1'b0;
|
||||
|
||||
// verilator lint_off MULTIDRIVEN
|
||||
// (* RAM_STYLE="BLOCK" *)
|
||||
logic [DATA_W-1:0] mem[2**VALID_ADDR_W];
|
||||
// verilator lint_on MULTIDRIVEN
|
||||
|
||||
wire [VALID_ADDR_W-1:0] s_axil_a_awaddr_valid = VALID_ADDR_W'(s_axil_wr_a.awaddr >> (ADDR_W - VALID_ADDR_W));
|
||||
wire [VALID_ADDR_W-1:0] s_axil_a_araddr_valid = VALID_ADDR_W'(s_axil_rd_a.araddr >> (ADDR_W - VALID_ADDR_W));
|
||||
|
||||
wire [VALID_ADDR_W-1:0] s_axil_b_awaddr_valid = VALID_ADDR_W'(s_axil_wr_b.awaddr >> (ADDR_W - VALID_ADDR_W));
|
||||
wire [VALID_ADDR_W-1:0] s_axil_b_araddr_valid = VALID_ADDR_W'(s_axil_rd_b.araddr >> (ADDR_W - VALID_ADDR_W));
|
||||
|
||||
assign s_axil_wr_a.awready = s_axil_a_awready_reg;
|
||||
assign s_axil_wr_a.wready = s_axil_a_wready_reg;
|
||||
assign s_axil_wr_a.bresp = 2'b00;
|
||||
assign s_axil_wr_a.bvalid = s_axil_a_bvalid_reg;
|
||||
|
||||
assign s_axil_rd_a.arready = s_axil_a_arready_reg;
|
||||
assign s_axil_rd_a.rdata = PIPELINE_OUTPUT ? s_axil_a_rdata_pipe_reg : s_axil_a_rdata_reg;
|
||||
assign s_axil_rd_a.rresp = 2'b00;
|
||||
assign s_axil_rd_a.rvalid = PIPELINE_OUTPUT ? s_axil_a_rvalid_pipe_reg : s_axil_a_rvalid_reg;
|
||||
|
||||
assign s_axil_wr_b.awready = s_axil_b_awready_reg;
|
||||
assign s_axil_wr_b.wready = s_axil_b_wready_reg;
|
||||
assign s_axil_wr_b.bresp = 2'b00;
|
||||
assign s_axil_wr_b.bvalid = s_axil_b_bvalid_reg;
|
||||
|
||||
assign s_axil_rd_b.arready = s_axil_b_arready_reg;
|
||||
assign s_axil_rd_b.rdata = PIPELINE_OUTPUT ? s_axil_b_rdata_pipe_reg : s_axil_b_rdata_reg;
|
||||
assign s_axil_rd_b.rresp = 2'b00;
|
||||
assign s_axil_rd_b.rvalid = PIPELINE_OUTPUT ? s_axil_b_rvalid_pipe_reg : s_axil_b_rvalid_reg;
|
||||
|
||||
initial begin
|
||||
// two nested loops for smaller number of iterations per loop
|
||||
// workaround for synthesizer complaints about large loop counts
|
||||
for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin
|
||||
for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin
|
||||
mem[j] = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
mem_wr_en_a = 1'b0;
|
||||
mem_rd_en_a = 1'b0;
|
||||
|
||||
last_read_a_next = last_read_a_reg;
|
||||
|
||||
s_axil_a_awready_next = 1'b0;
|
||||
s_axil_a_wready_next = 1'b0;
|
||||
s_axil_a_bvalid_next = s_axil_a_bvalid_reg && !s_axil_wr_a.bready;
|
||||
|
||||
s_axil_a_arready_next = 1'b0;
|
||||
s_axil_a_rvalid_next = s_axil_a_rvalid_reg && !(s_axil_rd_a.rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg));
|
||||
|
||||
write_eligible_a = s_axil_wr_a.awvalid && s_axil_wr_a.wvalid && (!s_axil_wr_a.bvalid || s_axil_wr_a.bready) && (!s_axil_wr_a.awready && !s_axil_wr_a.wready);
|
||||
read_eligible_a = s_axil_rd_a.arvalid && (!s_axil_rd_a.rvalid || s_axil_rd_a.rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg)) && (!s_axil_rd_a.arready);
|
||||
|
||||
if (write_eligible_a && (!read_eligible_a || last_read_a_reg)) begin
|
||||
last_read_a_next = 1'b0;
|
||||
|
||||
s_axil_a_awready_next = 1'b1;
|
||||
s_axil_a_wready_next = 1'b1;
|
||||
s_axil_a_bvalid_next = 1'b1;
|
||||
|
||||
mem_wr_en_a = 1'b1;
|
||||
end else if (read_eligible_a) begin
|
||||
last_read_a_next = 1'b1;
|
||||
|
||||
s_axil_a_arready_next = 1'b1;
|
||||
s_axil_a_rvalid_next = 1'b1;
|
||||
|
||||
mem_rd_en_a = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge a_clk) begin
|
||||
last_read_a_reg <= last_read_a_next;
|
||||
|
||||
s_axil_a_awready_reg <= s_axil_a_awready_next;
|
||||
s_axil_a_wready_reg <= s_axil_a_wready_next;
|
||||
s_axil_a_bvalid_reg <= s_axil_a_bvalid_next;
|
||||
|
||||
s_axil_a_arready_reg <= s_axil_a_arready_next;
|
||||
s_axil_a_rvalid_reg <= s_axil_a_rvalid_next;
|
||||
|
||||
if (mem_rd_en_a) begin
|
||||
s_axil_a_rdata_reg <= mem[s_axil_a_araddr_valid];
|
||||
end else begin
|
||||
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
|
||||
if (mem_wr_en_a && s_axil_wr_a.wstrb[i]) begin
|
||||
mem[s_axil_a_awaddr_valid][BYTE_W*i +: BYTE_W] <= s_axil_wr_a.wdata[BYTE_W*i +: BYTE_W];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if (!s_axil_a_rvalid_pipe_reg || s_axil_rd_a.rready) begin
|
||||
s_axil_a_rdata_pipe_reg <= s_axil_a_rdata_reg;
|
||||
s_axil_a_rvalid_pipe_reg <= s_axil_a_rvalid_reg;
|
||||
end
|
||||
|
||||
if (a_rst) begin
|
||||
last_read_a_reg <= 1'b0;
|
||||
|
||||
s_axil_a_awready_reg <= 1'b0;
|
||||
s_axil_a_wready_reg <= 1'b0;
|
||||
s_axil_a_bvalid_reg <= 1'b0;
|
||||
|
||||
s_axil_a_arready_reg <= 1'b0;
|
||||
s_axil_a_rvalid_reg <= 1'b0;
|
||||
s_axil_a_rvalid_pipe_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
mem_wr_en_b = 1'b0;
|
||||
mem_rd_en_b = 1'b0;
|
||||
|
||||
last_read_b_next = last_read_b_reg;
|
||||
|
||||
s_axil_b_awready_next = 1'b0;
|
||||
s_axil_b_wready_next = 1'b0;
|
||||
s_axil_b_bvalid_next = s_axil_b_bvalid_reg && !s_axil_wr_b.bready;
|
||||
|
||||
s_axil_b_arready_next = 1'b0;
|
||||
s_axil_b_rvalid_next = s_axil_b_rvalid_reg && !(s_axil_rd_b.rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg));
|
||||
|
||||
write_eligible_b = s_axil_wr_b.awvalid && s_axil_wr_b.wvalid && (!s_axil_wr_b.bvalid || s_axil_wr_b.bready) && (!s_axil_wr_b.awready && !s_axil_wr_b.wready);
|
||||
read_eligible_b = s_axil_rd_b.arvalid && (!s_axil_rd_b.rvalid || s_axil_rd_b.rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg)) && (!s_axil_rd_b.arready);
|
||||
|
||||
if (write_eligible_b && (!read_eligible_b || last_read_b_reg)) begin
|
||||
last_read_b_next = 1'b0;
|
||||
|
||||
s_axil_b_awready_next = 1'b1;
|
||||
s_axil_b_wready_next = 1'b1;
|
||||
s_axil_b_bvalid_next = 1'b1;
|
||||
|
||||
mem_wr_en_b = 1'b1;
|
||||
end else if (read_eligible_b) begin
|
||||
last_read_b_next = 1'b1;
|
||||
|
||||
s_axil_b_arready_next = 1'b1;
|
||||
s_axil_b_rvalid_next = 1'b1;
|
||||
|
||||
mem_rd_en_b = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge b_clk) begin
|
||||
last_read_b_reg <= last_read_b_next;
|
||||
|
||||
s_axil_b_awready_reg <= s_axil_b_awready_next;
|
||||
s_axil_b_wready_reg <= s_axil_b_wready_next;
|
||||
s_axil_b_bvalid_reg <= s_axil_b_bvalid_next;
|
||||
|
||||
s_axil_b_arready_reg <= s_axil_b_arready_next;
|
||||
s_axil_b_rvalid_reg <= s_axil_b_rvalid_next;
|
||||
|
||||
if (mem_rd_en_b) begin
|
||||
s_axil_b_rdata_reg <= mem[s_axil_b_araddr_valid];
|
||||
end else begin
|
||||
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
|
||||
if (mem_wr_en_b && s_axil_wr_b.wstrb[i]) begin
|
||||
mem[s_axil_b_awaddr_valid][BYTE_W*i +: BYTE_W] <= s_axil_wr_b.wdata[BYTE_W*i +: BYTE_W];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if (!s_axil_b_rvalid_pipe_reg || s_axil_rd_b.rready) begin
|
||||
s_axil_b_rdata_pipe_reg <= s_axil_b_rdata_reg;
|
||||
s_axil_b_rvalid_pipe_reg <= s_axil_b_rvalid_reg;
|
||||
end
|
||||
|
||||
if (b_rst) begin
|
||||
last_read_b_reg <= 1'b0;
|
||||
|
||||
s_axil_b_awready_reg <= 1'b0;
|
||||
s_axil_b_wready_reg <= 1'b0;
|
||||
s_axil_b_bvalid_reg <= 1'b0;
|
||||
|
||||
s_axil_b_arready_reg <= 1'b0;
|
||||
s_axil_b_rvalid_reg <= 1'b0;
|
||||
s_axil_b_rvalid_pipe_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
175
src/axi/rtl/taxi_axil_if.sv
Normal file
175
src/axi/rtl/taxi_axil_if.sv
Normal file
@@ -0,0 +1,175 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
interface taxi_axil_if #(
|
||||
// Width of data bus in bits
|
||||
parameter DATA_W = 32,
|
||||
// Width of address bus in bits
|
||||
parameter ADDR_W = 32,
|
||||
// Width of wstrb (width of data bus in words)
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
// Use awuser signal
|
||||
parameter logic AWUSER_EN = 1'b0,
|
||||
// Width of awuser signal
|
||||
parameter AWUSER_W = 1,
|
||||
// Use wuser signal
|
||||
parameter logic WUSER_EN = 1'b0,
|
||||
// Width of wuser signal
|
||||
parameter WUSER_W = 1,
|
||||
// Use buser signal
|
||||
parameter logic BUSER_EN = 1'b0,
|
||||
// Width of buser signal
|
||||
parameter BUSER_W = 1,
|
||||
// Use aruser signal
|
||||
parameter logic ARUSER_EN = 1'b0,
|
||||
// Width of aruser signal
|
||||
parameter ARUSER_W = 1,
|
||||
// Use ruser signal
|
||||
parameter logic RUSER_EN = 1'b0,
|
||||
// Width of ruser signal
|
||||
parameter RUSER_W = 1
|
||||
)
|
||||
();
|
||||
// AW
|
||||
logic [ADDR_W-1:0] awaddr;
|
||||
logic [2:0] awprot;
|
||||
logic [AWUSER_W-1:0] awuser;
|
||||
logic awvalid;
|
||||
logic awready;
|
||||
// W
|
||||
logic [DATA_W-1:0] wdata;
|
||||
logic [STRB_W-1:0] wstrb;
|
||||
logic [WUSER_W-1:0] wuser;
|
||||
logic wvalid;
|
||||
logic wready;
|
||||
// B
|
||||
logic [1:0] bresp;
|
||||
logic [BUSER_W-1:0] buser;
|
||||
logic bvalid;
|
||||
logic bready;
|
||||
// AR
|
||||
logic [ADDR_W-1:0] araddr;
|
||||
logic [2:0] arprot;
|
||||
logic [ARUSER_W-1:0] aruser;
|
||||
logic arvalid;
|
||||
logic arready;
|
||||
// R
|
||||
logic [DATA_W-1:0] rdata;
|
||||
logic [1:0] rresp;
|
||||
logic [RUSER_W-1:0] ruser;
|
||||
logic rvalid;
|
||||
logic rready;
|
||||
|
||||
modport wr_mst (
|
||||
// AW
|
||||
output awaddr,
|
||||
output awprot,
|
||||
output awuser,
|
||||
output awvalid,
|
||||
input awready,
|
||||
// W
|
||||
output wdata,
|
||||
output wstrb,
|
||||
output wuser,
|
||||
output wvalid,
|
||||
input wready,
|
||||
// B
|
||||
input bresp,
|
||||
input buser,
|
||||
input bvalid,
|
||||
output bready
|
||||
);
|
||||
|
||||
modport rd_mst (
|
||||
// AR
|
||||
output araddr,
|
||||
output arprot,
|
||||
output aruser,
|
||||
output arvalid,
|
||||
input arready,
|
||||
// R
|
||||
input rdata,
|
||||
input rresp,
|
||||
input ruser,
|
||||
input rvalid,
|
||||
output rready
|
||||
);
|
||||
|
||||
modport wr_slv (
|
||||
// AW
|
||||
input awaddr,
|
||||
input awprot,
|
||||
input awuser,
|
||||
input awvalid,
|
||||
output awready,
|
||||
// W
|
||||
input wdata,
|
||||
input wstrb,
|
||||
input wuser,
|
||||
input wvalid,
|
||||
output wready,
|
||||
// B
|
||||
output bresp,
|
||||
output buser,
|
||||
output bvalid,
|
||||
input bready
|
||||
);
|
||||
|
||||
modport rd_slv (
|
||||
// AR
|
||||
input araddr,
|
||||
input arprot,
|
||||
input aruser,
|
||||
input arvalid,
|
||||
output arready,
|
||||
// R
|
||||
output rdata,
|
||||
output rresp,
|
||||
output ruser,
|
||||
output rvalid,
|
||||
input rready
|
||||
);
|
||||
|
||||
modport wr_mon (
|
||||
// AW
|
||||
input awaddr,
|
||||
input awprot,
|
||||
input awuser,
|
||||
input awvalid,
|
||||
input awready,
|
||||
// W
|
||||
input wdata,
|
||||
input wstrb,
|
||||
input wuser,
|
||||
input wvalid,
|
||||
input wready,
|
||||
// B
|
||||
input bresp,
|
||||
input buser,
|
||||
input bvalid,
|
||||
input bready
|
||||
);
|
||||
|
||||
modport rd_mon (
|
||||
// AR
|
||||
input araddr,
|
||||
input arprot,
|
||||
input aruser,
|
||||
input arvalid,
|
||||
input arready,
|
||||
// R
|
||||
input rdata,
|
||||
input rresp,
|
||||
input ruser,
|
||||
input rvalid,
|
||||
input rready
|
||||
);
|
||||
|
||||
endinterface
|
||||
165
src/axi/rtl/taxi_axil_ram.sv
Normal file
165
src/axi/rtl/taxi_axil_ram.sv
Normal file
@@ -0,0 +1,165 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Lite RAM
|
||||
*/
|
||||
module taxi_axil_ram #
|
||||
(
|
||||
// Width of address bus in bits
|
||||
parameter ADDR_W = 16,
|
||||
// Extra pipeline register on output
|
||||
parameter logic PIPELINE_OUTPUT = 1'b0
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
taxi_axil_if.wr_slv s_axil_wr,
|
||||
taxi_axil_if.rd_slv s_axil_rd
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axil_wr.DATA_W;
|
||||
localparam STRB_W = s_axil_wr.STRB_W;
|
||||
|
||||
localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
|
||||
localparam BYTE_LANES = STRB_W;
|
||||
localparam BYTE_W = DATA_W/BYTE_LANES;
|
||||
|
||||
// check configuration
|
||||
if (BYTE_W * STRB_W != DATA_W)
|
||||
$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
|
||||
|
||||
if (2**$clog2(BYTE_LANES) != BYTE_LANES)
|
||||
$fatal(0, "Error: AXI byte lane count must be even power of two (instance %m)");
|
||||
|
||||
if (s_axil_wr.DATA_W != s_axil_rd.DATA_W)
|
||||
$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
|
||||
|
||||
if (s_axil_wr.ADDR_W < ADDR_W || s_axil_rd.ADDR_W < ADDR_W)
|
||||
$fatal(0, "Error: AXI address width is insufficient (instance %m)");
|
||||
|
||||
logic mem_wr_en;
|
||||
logic mem_rd_en;
|
||||
|
||||
logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
|
||||
logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
|
||||
logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
logic s_axil_arready_reg = 1'b0, s_axil_arready_next;
|
||||
logic [DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next;
|
||||
logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
|
||||
logic [DATA_W-1:0] s_axil_rdata_pipe_reg = '0;
|
||||
logic s_axil_rvalid_pipe_reg = 1'b0;
|
||||
|
||||
// (* RAM_STYLE="BLOCK" *)
|
||||
logic [DATA_W-1:0] mem[2**VALID_ADDR_W];
|
||||
|
||||
wire [VALID_ADDR_W-1:0] s_axil_awaddr_valid = VALID_ADDR_W'(s_axil_wr.awaddr >> (ADDR_W - VALID_ADDR_W));
|
||||
wire [VALID_ADDR_W-1:0] s_axil_araddr_valid = VALID_ADDR_W'(s_axil_rd.araddr >> (ADDR_W - VALID_ADDR_W));
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
assign s_axil_wr.bresp = 2'b00;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
assign s_axil_rd.arready = s_axil_arready_reg;
|
||||
assign s_axil_rd.rdata = PIPELINE_OUTPUT ? s_axil_rdata_pipe_reg : s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = 2'b00;
|
||||
assign s_axil_rd.rvalid = PIPELINE_OUTPUT ? s_axil_rvalid_pipe_reg : s_axil_rvalid_reg;
|
||||
|
||||
initial begin
|
||||
// two nested loops for smaller number of iterations per loop
|
||||
// workaround for synthesizer complaints about large loop counts
|
||||
for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin
|
||||
for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin
|
||||
mem[j] = '0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
mem_wr_en = 1'b0;
|
||||
|
||||
s_axil_awready_next = 1'b0;
|
||||
s_axil_wready_next = 1'b0;
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
|
||||
|
||||
if (s_axil_wr.awvalid && s_axil_wr.wvalid && (!s_axil_wr.bvalid || s_axil_wr.bready) && (!s_axil_wr.awready && !s_axil_wr.wready)) begin
|
||||
s_axil_awready_next = 1'b1;
|
||||
s_axil_wready_next = 1'b1;
|
||||
s_axil_bvalid_next = 1'b1;
|
||||
|
||||
mem_wr_en = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_awready_reg <= s_axil_awready_next;
|
||||
s_axil_wready_reg <= s_axil_wready_next;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
|
||||
if (mem_wr_en && s_axil_wr.wstrb[i]) begin
|
||||
mem[s_axil_awaddr_valid][BYTE_W*i +: BYTE_W] <= s_axil_wr.wdata[BYTE_W*i +: BYTE_W];
|
||||
end
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
mem_rd_en = 1'b0;
|
||||
|
||||
s_axil_arready_next = 1'b0;
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg && !(s_axil_rd.rready || (PIPELINE_OUTPUT && !s_axil_rvalid_pipe_reg));
|
||||
|
||||
if (s_axil_rd.arvalid && (!s_axil_rd.rvalid || s_axil_rd.rready || (PIPELINE_OUTPUT && !s_axil_rvalid_pipe_reg)) && (!s_axil_rd.arready)) begin
|
||||
s_axil_arready_next = 1'b1;
|
||||
s_axil_rvalid_next = 1'b1;
|
||||
|
||||
mem_rd_en = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_arready_reg <= s_axil_arready_next;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
if (mem_rd_en) begin
|
||||
s_axil_rdata_reg <= mem[s_axil_araddr_valid];
|
||||
end
|
||||
|
||||
if (!s_axil_rvalid_pipe_reg || s_axil_rd.rready) begin
|
||||
s_axil_rdata_pipe_reg <= s_axil_rdata_reg;
|
||||
s_axil_rvalid_pipe_reg <= s_axil_rvalid_reg;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
s_axil_rvalid_pipe_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
4
src/axi/rtl/taxi_axil_register.f
Normal file
4
src/axi/rtl/taxi_axil_register.f
Normal file
@@ -0,0 +1,4 @@
|
||||
taxi_axil_register.sv
|
||||
taxi_axil_register_wr.sv
|
||||
taxi_axil_register_rd.sv
|
||||
taxi_axil_if.sv
|
||||
94
src/axi/rtl/taxi_axil_register.sv
Normal file
94
src/axi/rtl/taxi_axil_register.sv
Normal file
@@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite register
|
||||
*/
|
||||
module taxi_axil_register #
|
||||
(
|
||||
// AW channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter AW_REG_TYPE = 1,
|
||||
// W channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter W_REG_TYPE = 1,
|
||||
// B channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter B_REG_TYPE = 1,
|
||||
// AR channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter AR_REG_TYPE = 1,
|
||||
// R channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter R_REG_TYPE = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
taxi_axil_if.wr_slv s_axil_wr,
|
||||
taxi_axil_if.rd_slv s_axil_rd,
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
taxi_axil_if.wr_mst m_axil_wr,
|
||||
taxi_axil_if.rd_mst m_axil_rd
|
||||
);
|
||||
|
||||
taxi_axil_register_wr #(
|
||||
.AW_REG_TYPE(AW_REG_TYPE),
|
||||
.W_REG_TYPE(W_REG_TYPE),
|
||||
.B_REG_TYPE(B_REG_TYPE)
|
||||
)
|
||||
axil_register_wr_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axil_wr(s_axil_wr),
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
.m_axil_wr(m_axil_wr)
|
||||
);
|
||||
|
||||
taxi_axil_register_rd #(
|
||||
.AR_REG_TYPE(AR_REG_TYPE),
|
||||
.R_REG_TYPE(R_REG_TYPE)
|
||||
)
|
||||
axil_register_rd_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axil_rd(s_axil_rd),
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
.m_axil_rd(m_axil_rd)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
371
src/axi/rtl/taxi_axil_register_rd.sv
Normal file
371
src/axi/rtl/taxi_axil_register_rd.sv
Normal file
@@ -0,0 +1,371 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite register (read)
|
||||
*/
|
||||
module taxi_axil_register_rd #
|
||||
(
|
||||
// AR channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter AR_REG_TYPE = 1,
|
||||
// R channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter R_REG_TYPE = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
taxi_axil_if.rd_slv s_axil_rd,
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
taxi_axil_if.rd_mst m_axil_rd
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axil_rd.DATA_W;
|
||||
localparam ADDR_W = s_axil_rd.ADDR_W;
|
||||
localparam STRB_W = s_axil_rd.STRB_W;
|
||||
localparam logic ARUSER_EN = s_axil_rd.ARUSER_EN && m_axil_rd.ARUSER_EN;
|
||||
localparam ARUSER_W = s_axil_rd.ARUSER_W;
|
||||
localparam logic RUSER_EN = s_axil_rd.RUSER_EN && m_axil_rd.RUSER_EN;
|
||||
localparam RUSER_W = s_axil_rd.RUSER_W;
|
||||
|
||||
if (m_axil_rd.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (m_axil_rd.STRB_W != STRB_W)
|
||||
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
|
||||
|
||||
// AR channel
|
||||
|
||||
if (AR_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_arready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_araddr_reg = '0;
|
||||
logic [2:0] m_axil_arprot_reg = '0;
|
||||
logic [ARUSER_W-1:0] m_axil_aruser_reg = '0;
|
||||
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
|
||||
|
||||
logic [ADDR_W-1:0] temp_m_axil_araddr_reg = '0;
|
||||
logic [2:0] temp_m_axil_arprot_reg = '0;
|
||||
logic [ARUSER_W-1:0] temp_m_axil_aruser_reg = '0;
|
||||
logic temp_m_axil_arvalid_reg = 1'b0, temp_m_axil_arvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_ar_input_to_output;
|
||||
logic store_axil_ar_input_to_temp;
|
||||
logic store_axil_ar_temp_to_output;
|
||||
|
||||
assign s_axil_rd.arready = s_axil_arready_reg;
|
||||
|
||||
assign m_axil_rd.araddr = m_axil_araddr_reg;
|
||||
assign m_axil_rd.arprot = m_axil_arprot_reg;
|
||||
assign m_axil_rd.aruser = ARUSER_EN ? m_axil_aruser_reg : '0;
|
||||
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axil_arready_early = m_axil_rd.arready || (!temp_m_axil_arvalid_reg && (!m_axil_arvalid_reg || !s_axil_rd.arvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_arvalid_next = m_axil_arvalid_reg;
|
||||
temp_m_axil_arvalid_next = temp_m_axil_arvalid_reg;
|
||||
|
||||
store_axil_ar_input_to_output = 1'b0;
|
||||
store_axil_ar_input_to_temp = 1'b0;
|
||||
store_axil_ar_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axil_arready_reg) begin
|
||||
// input is ready
|
||||
if (m_axil_rd.arready || !m_axil_arvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axil_arvalid_next = s_axil_rd.arvalid;
|
||||
store_axil_ar_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axil_arvalid_next = s_axil_rd.arvalid;
|
||||
store_axil_ar_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axil_rd.arready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axil_arvalid_next = temp_m_axil_arvalid_reg;
|
||||
temp_m_axil_arvalid_next = 1'b0;
|
||||
store_axil_ar_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_arready_reg <= s_axil_arready_early;
|
||||
m_axil_arvalid_reg <= m_axil_arvalid_next;
|
||||
temp_m_axil_arvalid_reg <= temp_m_axil_arvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_ar_input_to_output) begin
|
||||
m_axil_araddr_reg <= s_axil_rd.araddr;
|
||||
m_axil_arprot_reg <= s_axil_rd.arprot;
|
||||
m_axil_aruser_reg <= s_axil_rd.aruser;
|
||||
end else if (store_axil_ar_temp_to_output) begin
|
||||
m_axil_araddr_reg <= temp_m_axil_araddr_reg;
|
||||
m_axil_arprot_reg <= temp_m_axil_arprot_reg;
|
||||
m_axil_aruser_reg <= temp_m_axil_aruser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_ar_input_to_temp) begin
|
||||
temp_m_axil_araddr_reg <= s_axil_rd.araddr;
|
||||
temp_m_axil_arprot_reg <= s_axil_rd.arprot;
|
||||
temp_m_axil_aruser_reg <= s_axil_rd.aruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
m_axil_arvalid_reg <= 1'b0;
|
||||
temp_m_axil_arvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (AR_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_arready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_araddr_reg = '0;
|
||||
logic [2:0] m_axil_arprot_reg = '0;
|
||||
logic [ARUSER_W-1:0] m_axil_aruser_reg = '0;
|
||||
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_ar_input_to_output;
|
||||
|
||||
assign s_axil_rd.arready = s_axil_arready_reg;
|
||||
|
||||
assign m_axil_rd.araddr = m_axil_araddr_reg;
|
||||
assign m_axil_rd.arprot = m_axil_arprot_reg;
|
||||
assign m_axil_rd.aruser = ARUSER_EN ? m_axil_aruser_reg : '0;
|
||||
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axil_arready_early = !m_axil_arvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_arvalid_next = m_axil_arvalid_reg;
|
||||
|
||||
store_axil_ar_input_to_output = 1'b0;
|
||||
|
||||
if (s_axil_arready_reg) begin
|
||||
m_axil_arvalid_next = s_axil_rd.arvalid;
|
||||
store_axil_ar_input_to_output = 1'b1;
|
||||
end else if (m_axil_rd.arready) begin
|
||||
m_axil_arvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_arready_reg <= s_axil_arready_early;
|
||||
m_axil_arvalid_reg <= m_axil_arvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_ar_input_to_output) begin
|
||||
m_axil_araddr_reg <= s_axil_rd.araddr;
|
||||
m_axil_arprot_reg <= s_axil_rd.arprot;
|
||||
m_axil_aruser_reg <= s_axil_rd.aruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
m_axil_arvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass AR channel
|
||||
assign m_axil_rd.araddr = s_axil_rd.araddr;
|
||||
assign m_axil_rd.arprot = s_axil_rd.arprot;
|
||||
assign m_axil_rd.aruser = ARUSER_EN ? s_axil_rd.aruser : '0;
|
||||
assign m_axil_rd.arvalid = s_axil_rd.arvalid;
|
||||
assign s_axil_rd.arready = m_axil_rd.arready;
|
||||
|
||||
end
|
||||
|
||||
// R channel
|
||||
|
||||
if (R_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_rready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] s_axil_rdata_reg = '0;
|
||||
logic [1:0] s_axil_rresp_reg = 2'b0;
|
||||
logic [RUSER_W-1:0] s_axil_ruser_reg = '0;
|
||||
logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
|
||||
|
||||
logic [DATA_W-1:0] temp_s_axil_rdata_reg = '0;
|
||||
logic [1:0] temp_s_axil_rresp_reg = 2'b0;
|
||||
logic [RUSER_W-1:0] temp_s_axil_ruser_reg = '0;
|
||||
logic temp_s_axil_rvalid_reg = 1'b0, temp_s_axil_rvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_r_input_to_output;
|
||||
logic store_axil_r_input_to_temp;
|
||||
logic store_axil_r_temp_to_output;
|
||||
|
||||
assign m_axil_rd.rready = m_axil_rready_reg;
|
||||
|
||||
assign s_axil_rd.rdata = s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = s_axil_rresp_reg;
|
||||
assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
|
||||
assign s_axil_rd.rvalid = s_axil_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire m_axil_rready_early = s_axil_rd.rready || (!temp_s_axil_rvalid_reg && (!s_axil_rvalid_reg || !m_axil_rd.rvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg;
|
||||
temp_s_axil_rvalid_next = temp_s_axil_rvalid_reg;
|
||||
|
||||
store_axil_r_input_to_output = 1'b0;
|
||||
store_axil_r_input_to_temp = 1'b0;
|
||||
store_axil_r_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axil_rready_reg) begin
|
||||
// input is ready
|
||||
if (s_axil_rd.rready || !s_axil_rvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axil_rvalid_next = m_axil_rd.rvalid;
|
||||
store_axil_r_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axil_rvalid_next = m_axil_rd.rvalid;
|
||||
store_axil_r_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (s_axil_rd.rready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axil_rvalid_next = temp_s_axil_rvalid_reg;
|
||||
temp_s_axil_rvalid_next = 1'b0;
|
||||
store_axil_r_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_rready_reg <= m_axil_rready_early;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
temp_s_axil_rvalid_reg <= temp_s_axil_rvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_r_input_to_output) begin
|
||||
s_axil_rdata_reg <= m_axil_rd.rdata;
|
||||
s_axil_rresp_reg <= m_axil_rd.rresp;
|
||||
s_axil_ruser_reg <= m_axil_rd.ruser;
|
||||
end else if (store_axil_r_temp_to_output) begin
|
||||
s_axil_rdata_reg <= temp_s_axil_rdata_reg;
|
||||
s_axil_rresp_reg <= temp_s_axil_rresp_reg;
|
||||
s_axil_ruser_reg <= temp_s_axil_ruser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_r_input_to_temp) begin
|
||||
temp_s_axil_rdata_reg <= m_axil_rd.rdata;
|
||||
temp_s_axil_rresp_reg <= m_axil_rd.rresp;
|
||||
temp_s_axil_ruser_reg <= m_axil_rd.ruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_rready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
temp_s_axil_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (R_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_rready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] s_axil_rdata_reg = '0;
|
||||
logic [1:0] s_axil_rresp_reg = 2'b0;
|
||||
logic [RUSER_W-1:0] s_axil_ruser_reg = '0;
|
||||
logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_r_input_to_output;
|
||||
|
||||
assign m_axil_rd.rready = m_axil_rready_reg;
|
||||
|
||||
assign s_axil_rd.rdata = s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = s_axil_rresp_reg;
|
||||
assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
|
||||
assign s_axil_rd.rvalid = s_axil_rvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axil_rready_early = !s_axil_rvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg;
|
||||
|
||||
store_axil_r_input_to_output = 1'b0;
|
||||
|
||||
if (m_axil_rready_reg) begin
|
||||
s_axil_rvalid_next = m_axil_rd.rvalid;
|
||||
store_axil_r_input_to_output = 1'b1;
|
||||
end else if (s_axil_rd.rready) begin
|
||||
s_axil_rvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_rready_reg <= m_axil_rready_early;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_r_input_to_output) begin
|
||||
s_axil_rdata_reg <= m_axil_rd.rdata;
|
||||
s_axil_rresp_reg <= m_axil_rd.rresp;
|
||||
s_axil_ruser_reg <= m_axil_rd.ruser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_rready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass R channel
|
||||
assign s_axil_rd.rdata = m_axil_rd.rdata;
|
||||
assign s_axil_rd.rresp = m_axil_rd.rresp;
|
||||
assign s_axil_rd.ruser = RUSER_EN ? m_axil_rd.ruser : '0;
|
||||
assign s_axil_rd.rvalid = m_axil_rd.rvalid;
|
||||
assign m_axil_rd.rready = s_axil_rd.rready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
522
src/axi/rtl/taxi_axil_register_wr.sv
Normal file
522
src/axi/rtl/taxi_axil_register_wr.sv
Normal file
@@ -0,0 +1,522 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2018-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite register (write)
|
||||
*/
|
||||
module taxi_axil_register_wr #
|
||||
(
|
||||
// AW channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter AW_REG_TYPE = 1,
|
||||
// W channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter W_REG_TYPE = 1,
|
||||
// B channel register type
|
||||
// 0 to bypass, 1 for simple buffer
|
||||
parameter B_REG_TYPE = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
taxi_axil_if.wr_slv s_axil_wr,
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
taxi_axil_if.wr_mst m_axil_wr
|
||||
);
|
||||
|
||||
// extract parameters
|
||||
localparam DATA_W = s_axil_wr.DATA_W;
|
||||
localparam ADDR_W = s_axil_wr.ADDR_W;
|
||||
localparam STRB_W = s_axil_wr.STRB_W;
|
||||
localparam logic AWUSER_EN = s_axil_wr.AWUSER_EN && m_axil_wr.AWUSER_EN;
|
||||
localparam AWUSER_W = s_axil_wr.AWUSER_W;
|
||||
localparam logic WUSER_EN = s_axil_wr.WUSER_EN && m_axil_wr.WUSER_EN;
|
||||
localparam WUSER_W = s_axil_wr.WUSER_W;
|
||||
localparam logic BUSER_EN = s_axil_wr.BUSER_EN && m_axil_wr.BUSER_EN;
|
||||
localparam BUSER_W = s_axil_wr.BUSER_W;
|
||||
|
||||
if (m_axil_wr.DATA_W != DATA_W)
|
||||
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
|
||||
|
||||
if (m_axil_wr.STRB_W != STRB_W)
|
||||
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
|
||||
|
||||
// AW channel
|
||||
|
||||
if (AW_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_awready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_awaddr_reg = '0;
|
||||
logic [2:0] m_axil_awprot_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axil_awuser_reg = '0;
|
||||
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
|
||||
|
||||
logic [ADDR_W-1:0] temp_m_axil_awaddr_reg = '0;
|
||||
logic [2:0] temp_m_axil_awprot_reg = '0;
|
||||
logic [AWUSER_W-1:0] temp_m_axil_awuser_reg = '0;
|
||||
logic temp_m_axil_awvalid_reg = 1'b0, temp_m_axil_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_aw_input_to_output;
|
||||
logic store_axil_aw_input_to_temp;
|
||||
logic store_axil_aw_temp_to_output;
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
|
||||
assign m_axil_wr.awaddr = m_axil_awaddr_reg;
|
||||
assign m_axil_wr.awprot = m_axil_awprot_reg;
|
||||
assign m_axil_wr.awuser = AWUSER_EN ? m_axil_awuser_reg : '0;
|
||||
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axil_awready_early = m_axil_wr.awready || (!temp_m_axil_awvalid_reg && (!m_axil_awvalid_reg || !s_axil_wr.awvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_awvalid_next = m_axil_awvalid_reg;
|
||||
temp_m_axil_awvalid_next = temp_m_axil_awvalid_reg;
|
||||
|
||||
store_axil_aw_input_to_output = 1'b0;
|
||||
store_axil_aw_input_to_temp = 1'b0;
|
||||
store_axil_aw_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axil_awready_reg) begin
|
||||
// input is ready
|
||||
if (m_axil_wr.awready || !m_axil_awvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axil_awvalid_next = s_axil_wr.awvalid;
|
||||
store_axil_aw_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axil_awvalid_next = s_axil_wr.awvalid;
|
||||
store_axil_aw_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axil_wr.awready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axil_awvalid_next = temp_m_axil_awvalid_reg;
|
||||
temp_m_axil_awvalid_next = 1'b0;
|
||||
store_axil_aw_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_awready_reg <= s_axil_awready_early;
|
||||
m_axil_awvalid_reg <= m_axil_awvalid_next;
|
||||
temp_m_axil_awvalid_reg <= temp_m_axil_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_aw_input_to_output) begin
|
||||
m_axil_awaddr_reg <= s_axil_wr.awaddr;
|
||||
m_axil_awprot_reg <= s_axil_wr.awprot;
|
||||
m_axil_awuser_reg <= s_axil_wr.awuser;
|
||||
end else if (store_axil_aw_temp_to_output) begin
|
||||
m_axil_awaddr_reg <= temp_m_axil_awaddr_reg;
|
||||
m_axil_awprot_reg <= temp_m_axil_awprot_reg;
|
||||
m_axil_awuser_reg <= temp_m_axil_awuser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_aw_input_to_temp) begin
|
||||
temp_m_axil_awaddr_reg <= s_axil_wr.awaddr;
|
||||
temp_m_axil_awprot_reg <= s_axil_wr.awprot;
|
||||
temp_m_axil_awuser_reg <= s_axil_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
m_axil_awvalid_reg <= 1'b0;
|
||||
temp_m_axil_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (AW_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_awready_reg = 1'b0;
|
||||
|
||||
logic [ADDR_W-1:0] m_axil_awaddr_reg = '0;
|
||||
logic [2:0] m_axil_awprot_reg = '0;
|
||||
logic [AWUSER_W-1:0] m_axil_awuser_reg = '0;
|
||||
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_aw_input_to_output;
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
|
||||
assign m_axil_wr.awaddr = m_axil_awaddr_reg;
|
||||
assign m_axil_wr.awprot = m_axil_awprot_reg;
|
||||
assign m_axil_wr.awuser = AWUSER_EN ? m_axil_awuser_reg : '0;
|
||||
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axil_awready_early = !m_axil_awvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_awvalid_next = m_axil_awvalid_reg;
|
||||
|
||||
store_axil_aw_input_to_output = 1'b0;
|
||||
|
||||
if (s_axil_awready_reg) begin
|
||||
m_axil_awvalid_next = s_axil_wr.awvalid;
|
||||
store_axil_aw_input_to_output = 1'b1;
|
||||
end else if (m_axil_wr.awready) begin
|
||||
m_axil_awvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_awready_reg <= s_axil_awready_early;
|
||||
m_axil_awvalid_reg <= m_axil_awvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_aw_input_to_output) begin
|
||||
m_axil_awaddr_reg <= s_axil_wr.awaddr;
|
||||
m_axil_awprot_reg <= s_axil_wr.awprot;
|
||||
m_axil_awuser_reg <= s_axil_wr.awuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
m_axil_awvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass AW channel
|
||||
assign m_axil_wr.awaddr = s_axil_wr.awaddr;
|
||||
assign m_axil_wr.awprot = s_axil_wr.awprot;
|
||||
assign m_axil_wr.awuser = AWUSER_EN ? s_axil_wr.awuser : '0;
|
||||
assign m_axil_wr.awvalid = s_axil_wr.awvalid;
|
||||
assign s_axil_wr.awready = m_axil_wr.awready;
|
||||
|
||||
end
|
||||
|
||||
// W channel
|
||||
|
||||
if (W_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axil_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axil_wstrb_reg = '0;
|
||||
logic [WUSER_W-1:0] m_axil_wuser_reg = '0;
|
||||
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
|
||||
|
||||
logic [DATA_W-1:0] temp_m_axil_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] temp_m_axil_wstrb_reg = '0;
|
||||
logic [WUSER_W-1:0] temp_m_axil_wuser_reg = '0;
|
||||
logic temp_m_axil_wvalid_reg = 1'b0, temp_m_axil_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_w_input_to_output;
|
||||
logic store_axil_w_input_to_temp;
|
||||
logic store_axil_w_temp_to_output;
|
||||
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
|
||||
assign m_axil_wr.wdata = m_axil_wdata_reg;
|
||||
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
|
||||
assign m_axil_wr.wuser = WUSER_EN ? m_axil_wuser_reg : '0;
|
||||
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire s_axil_wready_early = m_axil_wr.wready || (!temp_m_axil_wvalid_reg && (!m_axil_wvalid_reg || !s_axil_wr.wvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_wvalid_next = m_axil_wvalid_reg;
|
||||
temp_m_axil_wvalid_next = temp_m_axil_wvalid_reg;
|
||||
|
||||
store_axil_w_input_to_output = 1'b0;
|
||||
store_axil_w_input_to_temp = 1'b0;
|
||||
store_axil_w_temp_to_output = 1'b0;
|
||||
|
||||
if (s_axil_wready_reg) begin
|
||||
// input is ready
|
||||
if (m_axil_wr.wready || !m_axil_wvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_axil_wvalid_next = s_axil_wr.wvalid;
|
||||
store_axil_w_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_axil_wvalid_next = s_axil_wr.wvalid;
|
||||
store_axil_w_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_axil_wr.wready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_axil_wvalid_next = temp_m_axil_wvalid_reg;
|
||||
temp_m_axil_wvalid_next = 1'b0;
|
||||
store_axil_w_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_wready_reg <= s_axil_wready_early;
|
||||
m_axil_wvalid_reg <= m_axil_wvalid_next;
|
||||
temp_m_axil_wvalid_reg <= temp_m_axil_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_w_input_to_output) begin
|
||||
m_axil_wdata_reg <= s_axil_wr.wdata;
|
||||
m_axil_wstrb_reg <= s_axil_wr.wstrb;
|
||||
m_axil_wuser_reg <= s_axil_wr.wuser;
|
||||
end else if (store_axil_w_temp_to_output) begin
|
||||
m_axil_wdata_reg <= temp_m_axil_wdata_reg;
|
||||
m_axil_wstrb_reg <= temp_m_axil_wstrb_reg;
|
||||
m_axil_wuser_reg <= temp_m_axil_wuser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_w_input_to_temp) begin
|
||||
temp_m_axil_wdata_reg <= s_axil_wr.wdata;
|
||||
temp_m_axil_wstrb_reg <= s_axil_wr.wstrb;
|
||||
temp_m_axil_wuser_reg <= s_axil_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
m_axil_wvalid_reg <= 1'b0;
|
||||
temp_m_axil_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (W_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic s_axil_wready_reg = 1'b0;
|
||||
|
||||
logic [DATA_W-1:0] m_axil_wdata_reg = '0;
|
||||
logic [STRB_W-1:0] m_axil_wstrb_reg = '0;
|
||||
logic [WUSER_W-1:0] m_axil_wuser_reg = '0;
|
||||
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_w_input_to_output;
|
||||
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
|
||||
assign m_axil_wr.wdata = m_axil_wdata_reg;
|
||||
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
|
||||
assign m_axil_wr.wuser = WUSER_EN ? m_axil_wuser_reg : '0;
|
||||
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire s_axil_wready_early = !m_axil_wvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
m_axil_wvalid_next = m_axil_wvalid_reg;
|
||||
|
||||
store_axil_w_input_to_output = 1'b0;
|
||||
|
||||
if (s_axil_wready_reg) begin
|
||||
m_axil_wvalid_next = s_axil_wr.wvalid;
|
||||
store_axil_w_input_to_output = 1'b1;
|
||||
end else if (m_axil_wr.wready) begin
|
||||
m_axil_wvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
s_axil_wready_reg <= s_axil_wready_early;
|
||||
m_axil_wvalid_reg <= m_axil_wvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_w_input_to_output) begin
|
||||
m_axil_wdata_reg <= s_axil_wr.wdata;
|
||||
m_axil_wstrb_reg <= s_axil_wr.wstrb;
|
||||
m_axil_wuser_reg <= s_axil_wr.wuser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
m_axil_wvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass W channel
|
||||
assign m_axil_wr.wdata = s_axil_wr.wdata;
|
||||
assign m_axil_wr.wstrb = s_axil_wr.wstrb;
|
||||
assign m_axil_wr.wuser = WUSER_EN ? s_axil_wr.wuser : '0;
|
||||
assign m_axil_wr.wvalid = s_axil_wr.wvalid;
|
||||
assign s_axil_wr.wready = m_axil_wr.wready;
|
||||
|
||||
end
|
||||
|
||||
// B channel
|
||||
|
||||
if (B_REG_TYPE > 1) begin
|
||||
// skid buffer, no bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_bready_reg = 1'b0;
|
||||
|
||||
logic [1:0] s_axil_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axil_buser_reg = '0;
|
||||
logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
|
||||
logic [1:0] temp_s_axil_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] temp_s_axil_buser_reg = '0;
|
||||
logic temp_s_axil_bvalid_reg = 1'b0, temp_s_axil_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_b_input_to_output;
|
||||
logic store_axil_b_input_to_temp;
|
||||
logic store_axil_b_temp_to_output;
|
||||
|
||||
assign m_axil_wr.bready = m_axil_bready_reg;
|
||||
|
||||
assign s_axil_wr.bresp = s_axil_bresp_reg;
|
||||
assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
wire m_axil_bready_early = s_axil_wr.bready || (!temp_s_axil_bvalid_reg && (!s_axil_bvalid_reg || !m_axil_wr.bvalid));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg;
|
||||
temp_s_axil_bvalid_next = temp_s_axil_bvalid_reg;
|
||||
|
||||
store_axil_b_input_to_output = 1'b0;
|
||||
store_axil_b_input_to_temp = 1'b0;
|
||||
store_axil_b_temp_to_output = 1'b0;
|
||||
|
||||
if (m_axil_bready_reg) begin
|
||||
// input is ready
|
||||
if (s_axil_wr.bready || !s_axil_bvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
s_axil_bvalid_next = m_axil_wr.bvalid;
|
||||
store_axil_b_input_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_s_axil_bvalid_next = m_axil_wr.bvalid;
|
||||
store_axil_b_input_to_temp = 1'b1;
|
||||
end
|
||||
end else if (s_axil_wr.bready) begin
|
||||
// input is not ready, but output is ready
|
||||
s_axil_bvalid_next = temp_s_axil_bvalid_reg;
|
||||
temp_s_axil_bvalid_next = 1'b0;
|
||||
store_axil_b_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_bready_reg <= m_axil_bready_early;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
temp_s_axil_bvalid_reg <= temp_s_axil_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_b_input_to_output) begin
|
||||
s_axil_bresp_reg <= m_axil_wr.bresp;
|
||||
s_axil_buser_reg <= m_axil_wr.buser;
|
||||
end else if (store_axil_b_temp_to_output) begin
|
||||
s_axil_bresp_reg <= temp_s_axil_bresp_reg;
|
||||
s_axil_buser_reg <= temp_s_axil_buser_reg;
|
||||
end
|
||||
|
||||
if (store_axil_b_input_to_temp) begin
|
||||
temp_s_axil_bresp_reg <= m_axil_wr.bresp;
|
||||
temp_s_axil_buser_reg <= m_axil_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_bready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
temp_s_axil_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else if (B_REG_TYPE == 1) begin
|
||||
// simple register, inserts bubble cycles
|
||||
|
||||
// datapath registers
|
||||
logic m_axil_bready_reg = 1'b0;
|
||||
|
||||
logic [1:0] s_axil_bresp_reg = 2'b0;
|
||||
logic [BUSER_W-1:0] s_axil_buser_reg = '0;
|
||||
logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
|
||||
// datapath control
|
||||
logic store_axil_b_input_to_output;
|
||||
|
||||
assign m_axil_wr.bready = m_axil_bready_reg;
|
||||
|
||||
assign s_axil_wr.bresp = s_axil_bresp_reg;
|
||||
assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
// enable ready input next cycle if output buffer will be empty
|
||||
wire m_axil_bready_early = !s_axil_bvalid_next;
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg;
|
||||
|
||||
store_axil_b_input_to_output = 1'b0;
|
||||
|
||||
if (m_axil_bready_reg) begin
|
||||
s_axil_bvalid_next = m_axil_wr.bvalid;
|
||||
store_axil_b_input_to_output = 1'b1;
|
||||
end else if (s_axil_wr.bready) begin
|
||||
s_axil_bvalid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
m_axil_bready_reg <= m_axil_bready_early;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_axil_b_input_to_output) begin
|
||||
s_axil_bresp_reg <= m_axil_wr.bresp;
|
||||
s_axil_buser_reg <= m_axil_wr.buser;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axil_bready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
// bypass B channel
|
||||
assign s_axil_wr.bresp = m_axil_wr.bresp;
|
||||
assign s_axil_wr.buser = BUSER_EN ? m_axil_wr.buser : '0;
|
||||
assign s_axil_wr.bvalid = m_axil_wr.bvalid;
|
||||
assign m_axil_wr.bready = s_axil_wr.bready;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
54
src/axi/tb/taxi_axi_ram/Makefile
Normal file
54
src/axi/tb/taxi_axi_ram/Makefile
Normal file
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axi_ram
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axi_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 16
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_PIPELINE_OUTPUT := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
243
src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.py
Normal file
243
src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.py
Normal file
@@ -0,0 +1,243 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiBus, AxiMaster
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.axi_master = AxiMaster(AxiBus.from_entity(dut.s_axi), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axi_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axi_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axi_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axi_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axi_master.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axi_master.write_if.byte_lanes
|
||||
max_burst_size = tb.axi_master.write_if.max_burst_size
|
||||
|
||||
if size is None:
|
||||
size = max_burst_size
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in list(range(1, byte_lanes*2))+[1024]:
|
||||
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
|
||||
tb.log.info("length %d, offset %d, size %d", length, offset, size)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axi_master.write(addr-4, b'\xaa'*(length+8))
|
||||
|
||||
await tb.axi_master.write(addr, test_data, size=size)
|
||||
|
||||
data = await tb.axi_master.read(addr-1, length+2)
|
||||
|
||||
assert data.data == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axi_master.write_if.byte_lanes
|
||||
max_burst_size = tb.axi_master.write_if.max_burst_size
|
||||
|
||||
if size is None:
|
||||
size = max_burst_size
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in list(range(1, byte_lanes*2))+[1024]:
|
||||
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
|
||||
tb.log.info("length %d, offset %d, size %d", length, offset, size)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axi_master.write(addr, test_data)
|
||||
|
||||
data = await tb.axi_master.read(addr, length, size=size)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(512, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0).join()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
data_width = len(cocotb.top.s_axi.wdata)
|
||||
byte_lanes = data_width // 8
|
||||
max_burst_size = (byte_lanes-1).bit_length()
|
||||
|
||||
for test in [run_test_write, run_test_read]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("size", [None]+list(range(max_burst_size)))
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axi_ram(request, data_w):
|
||||
dut = "taxi_axi_ram"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axi_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 16
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['ID_W'] = 8
|
||||
parameters['PIPELINE_OUTPUT'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
57
src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.sv
Normal file
57
src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.sv
Normal file
@@ -0,0 +1,57 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 RAM testbench
|
||||
*/
|
||||
module test_taxi_axi_ram #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 16,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter ID_W = 8,
|
||||
parameter PIPELINE_OUTPUT = 0
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axi_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W+16),
|
||||
.STRB_W(STRB_W),
|
||||
.ID_W(ID_W)
|
||||
) s_axi();
|
||||
|
||||
taxi_axi_ram #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axi_wr(s_axi),
|
||||
.s_axi_rd(s_axi)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
72
src/axi/tb/taxi_axi_register/Makefile
Normal file
72
src/axi/tb/taxi_axi_register/Makefile
Normal file
@@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axi_register
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
REG_TYPE ?= 1
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 32
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_AWUSER_EN := 0
|
||||
export PARAM_AWUSER_W := 1
|
||||
export PARAM_WUSER_EN := 0
|
||||
export PARAM_WUSER_W := 1
|
||||
export PARAM_BUSER_EN := 0
|
||||
export PARAM_BUSER_W := 1
|
||||
export PARAM_ARUSER_EN := 0
|
||||
export PARAM_ARUSER_W := 1
|
||||
export PARAM_RUSER_EN := 0
|
||||
export PARAM_RUSER_W := 1
|
||||
export PARAM_AW_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_W_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_B_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_AR_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_R_REG_TYPE := $(REG_TYPE)
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
265
src/axi/tb/taxi_axi_register/test_taxi_axi_register.py
Normal file
265
src/axi/tb/taxi_axi_register/test_taxi_axi_register.py
Normal file
@@ -0,0 +1,265 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiBus, AxiMaster, AxiRam
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.axi_master = AxiMaster(AxiBus.from_entity(dut.s_axi), dut.clk, dut.rst)
|
||||
self.axi_ram = AxiRam(AxiBus.from_entity(dut.m_axi), dut.clk, dut.rst, size=2**16)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axi_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axi_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axi_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
self.axi_ram.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axi_ram.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axi_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axi_master.read_if.r_channel.set_pause_generator(generator())
|
||||
self.axi_ram.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axi_ram.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axi_ram.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axi_master.write_if.byte_lanes
|
||||
max_burst_size = tb.axi_master.write_if.max_burst_size
|
||||
|
||||
if size is None:
|
||||
size = max_burst_size
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in list(range(1, byte_lanes*2))+[1024]:
|
||||
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
|
||||
tb.log.info("length %d, offset %d, size %d", length, offset, size)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axi_ram.write(addr-128, b'\xaa'*(length+256))
|
||||
|
||||
await tb.axi_master.write(addr, test_data, size=size)
|
||||
|
||||
tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
assert tb.axi_ram.read(addr, length) == test_data
|
||||
assert tb.axi_ram.read(addr-1, 1) == b'\xaa'
|
||||
assert tb.axi_ram.read(addr+length, 1) == b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axi_master.write_if.byte_lanes
|
||||
max_burst_size = tb.axi_master.write_if.max_burst_size
|
||||
|
||||
if size is None:
|
||||
size = max_burst_size
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in list(range(1, byte_lanes*2))+[1024]:
|
||||
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
|
||||
tb.log.info("length %d, offset %d, size %d", length, offset, size)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axi_ram.write(addr, test_data)
|
||||
|
||||
data = await tb.axi_master.read(addr, length, size=size)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(512, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
data_width = len(cocotb.top.s_axi.wdata)
|
||||
byte_lanes = data_width // 8
|
||||
max_burst_size = (byte_lanes-1).bit_length()
|
||||
|
||||
for test in [run_test_write, run_test_read]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("size", [None]+list(range(max_burst_size)))
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("reg_type", [None, 0, 1, 2])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axi_register(request, data_w, reg_type):
|
||||
dut = "taxi_axi_register"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 32
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['ID_W'] = 8
|
||||
parameters['AWUSER_EN'] = 0
|
||||
parameters['AWUSER_W'] = 1
|
||||
parameters['WUSER_EN'] = 0
|
||||
parameters['WUSER_W'] = 1
|
||||
parameters['BUSER_EN'] = 0
|
||||
parameters['BUSER_W'] = 1
|
||||
parameters['ARUSER_EN'] = 0
|
||||
parameters['ARUSER_W'] = 1
|
||||
parameters['RUSER_EN'] = 0
|
||||
parameters['RUSER_W'] = 1
|
||||
parameters['AW_REG_TYPE'] = 1 if reg_type is None else reg_type
|
||||
parameters['W_REG_TYPE'] = 2 if reg_type is None else reg_type
|
||||
parameters['B_REG_TYPE'] = 1 if reg_type is None else reg_type
|
||||
parameters['AR_REG_TYPE'] = 1 if reg_type is None else reg_type
|
||||
parameters['R_REG_TYPE'] = 2 if reg_type is None else reg_type
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
90
src/axi/tb/taxi_axi_register/test_taxi_axi_register.sv
Normal file
90
src/axi/tb/taxi_axi_register/test_taxi_axi_register.sv
Normal file
@@ -0,0 +1,90 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 register testbench
|
||||
*/
|
||||
module test_taxi_axi_register #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 32,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter ID_W = 8,
|
||||
parameter logic AWUSER_EN = 1'b0,
|
||||
parameter AWUSER_W = 1,
|
||||
parameter logic WUSER_EN = 1'b0,
|
||||
parameter WUSER_W = 1,
|
||||
parameter logic BUSER_EN = 1'b0,
|
||||
parameter BUSER_W = 1,
|
||||
parameter logic ARUSER_EN = 1'b0,
|
||||
parameter ARUSER_W = 1,
|
||||
parameter logic RUSER_EN = 1'b0,
|
||||
parameter RUSER_W = 1,
|
||||
parameter AW_REG_TYPE = 1,
|
||||
parameter W_REG_TYPE = 2,
|
||||
parameter B_REG_TYPE = 1,
|
||||
parameter AR_REG_TYPE = 1,
|
||||
parameter R_REG_TYPE = 2
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axi_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W),
|
||||
.STRB_W(STRB_W),
|
||||
.ID_W(ID_W),
|
||||
.AWUSER_EN(AWUSER_EN),
|
||||
.AWUSER_W(AWUSER_W),
|
||||
.WUSER_EN(WUSER_EN),
|
||||
.WUSER_W(WUSER_W),
|
||||
.BUSER_EN(BUSER_EN),
|
||||
.BUSER_W(BUSER_W),
|
||||
.ARUSER_EN(ARUSER_EN),
|
||||
.ARUSER_W(ARUSER_W),
|
||||
.RUSER_EN(RUSER_EN),
|
||||
.RUSER_W(RUSER_W)
|
||||
) s_axi(), m_axi();
|
||||
|
||||
taxi_axi_register #(
|
||||
.AW_REG_TYPE(AW_REG_TYPE),
|
||||
.W_REG_TYPE(W_REG_TYPE),
|
||||
.B_REG_TYPE(B_REG_TYPE),
|
||||
.AR_REG_TYPE(AR_REG_TYPE),
|
||||
.R_REG_TYPE(R_REG_TYPE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4 slave interface
|
||||
*/
|
||||
.s_axi_wr(s_axi),
|
||||
.s_axi_rd(s_axi),
|
||||
|
||||
/*
|
||||
* AXI4 master interface
|
||||
*/
|
||||
.m_axi_wr(m_axi),
|
||||
.m_axi_rd(m_axi)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
54
src/axi/tb/taxi_axil_dp_ram/Makefile
Normal file
54
src/axi/tb/taxi_axil_dp_ram/Makefile
Normal file
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axil_dp_ram
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 16
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_PIPELINE_OUTPUT := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
276
src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py
Normal file
276
src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py
Normal file
@@ -0,0 +1,276 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.a_clk, 8, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.b_clk, 10, units="ns").start())
|
||||
|
||||
self.axil_master = []
|
||||
|
||||
self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil_a), dut.a_clk, dut.a_rst))
|
||||
self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil_b), dut.b_clk, dut.b_rst))
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
for axil_master in self.axil_master:
|
||||
axil_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
axil_master.write_if.w_channel.set_pause_generator(generator())
|
||||
axil_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
for axil_master in self.axil_master:
|
||||
axil_master.write_if.b_channel.set_pause_generator(generator())
|
||||
axil_master.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.a_rst.setimmediatevalue(0)
|
||||
self.dut.b_rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
self.dut.a_rst.value = 1
|
||||
self.dut.b_rst.value = 1
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
self.dut.a_rst.value = 0
|
||||
await RisingEdge(self.dut.b_clk)
|
||||
self.dut.b_rst.value = 0
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
await RisingEdge(self.dut.a_clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, port=0, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
axil_master = tb.axil_master[port]
|
||||
byte_lanes = axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await axil_master.write(addr-4, b'\xaa'*(length+8))
|
||||
|
||||
await axil_master.write(addr, test_data)
|
||||
|
||||
data = await axil_master.read(addr-1, length+2)
|
||||
|
||||
assert data.data == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
await RisingEdge(dut.a_clk)
|
||||
await RisingEdge(dut.a_clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, port=0, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
axil_master = tb.axil_master[port]
|
||||
byte_lanes = axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await axil_master.write(addr, test_data)
|
||||
|
||||
data = await axil_master.read(addr, length)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.a_clk)
|
||||
await RisingEdge(dut.a_clk)
|
||||
|
||||
|
||||
async def run_test_arb(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset):
|
||||
wr_op = master.init_write(offset, b'\x11\x22\x33\x44')
|
||||
rd_op = master.init_read(offset, 4)
|
||||
|
||||
await wr_op.wait()
|
||||
await rd_op.wait()
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(10):
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master[0], k*256)))
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master[1], k*256)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0).join()
|
||||
|
||||
await RisingEdge(dut.a_clk)
|
||||
await RisingEdge(dut.a_clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(32, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master[k%len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0).join()
|
||||
|
||||
await RisingEdge(dut.a_clk)
|
||||
await RisingEdge(dut.a_clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
for test in [run_test_write, run_test_read]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("port", [0, 1])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_test_arb)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axil_dp_ram(request, data_w):
|
||||
dut = "taxi_axil_dp_ram"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axil_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 16
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['PIPELINE_OUTPUT'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
64
src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv
Normal file
64
src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv
Normal file
@@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite dual-port RAM testbench
|
||||
*/
|
||||
module test_taxi_axil_dp_ram #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 16,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter PIPELINE_OUTPUT = 0
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic a_clk;
|
||||
logic a_rst;
|
||||
logic b_clk;
|
||||
logic b_rst;
|
||||
|
||||
taxi_axil_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W+16),
|
||||
.STRB_W(STRB_W)
|
||||
) s_axil_a(), s_axil_b();
|
||||
|
||||
taxi_axil_dp_ram #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
|
||||
)
|
||||
uut (
|
||||
/*
|
||||
* Port A
|
||||
*/
|
||||
.a_clk(a_clk),
|
||||
.a_rst(a_rst),
|
||||
.s_axil_wr_a(s_axil_a),
|
||||
.s_axil_rd_a(s_axil_a),
|
||||
|
||||
/*
|
||||
* Port B
|
||||
*/
|
||||
.b_clk(b_clk),
|
||||
.b_rst(b_rst),
|
||||
.s_axil_wr_b(s_axil_b),
|
||||
.s_axil_rd_b(s_axil_b)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
54
src/axi/tb/taxi_axil_ram/Makefile
Normal file
54
src/axi/tb/taxi_axil_ram/Makefile
Normal file
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axil_ram
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 16
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_PIPELINE_OUTPUT := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
224
src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.py
Normal file
224
src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.py
Normal file
@@ -0,0 +1,224 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axil_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axil_master.write(addr-4, b'\xaa'*(length+8))
|
||||
|
||||
await tb.axil_master.write(addr, test_data)
|
||||
|
||||
data = await tb.axil_master.read(addr-1, length+2)
|
||||
|
||||
assert data.data == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axil_master.write(addr, test_data)
|
||||
|
||||
data = await tb.axil_master.read(addr, length)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(32, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0).join()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
for test in [run_test_write, run_test_read, run_stress_test]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axil_ram(request, data_w):
|
||||
dut = "taxi_axil_ram"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axil_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 16
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['PIPELINE_OUTPUT'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
55
src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.sv
Normal file
55
src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.sv
Normal file
@@ -0,0 +1,55 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite RAM testbench
|
||||
*/
|
||||
module test_taxi_axil_ram #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 16,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter PIPELINE_OUTPUT = 0
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axil_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W+16),
|
||||
.STRB_W(STRB_W)
|
||||
) s_axil();
|
||||
|
||||
taxi_axil_ram #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axil_wr(s_axil),
|
||||
.s_axil_rd(s_axil)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
69
src/axi/tb/taxi_axil_register/Makefile
Normal file
69
src/axi/tb/taxi_axil_register/Makefile
Normal file
@@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axil_register
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
REG_TYPE ?= 1
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 32
|
||||
export PARAM_ADDR_W := 32
|
||||
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
|
||||
export PARAM_AWUSER_EN := 0
|
||||
export PARAM_AWUSER_W := 1
|
||||
export PARAM_WUSER_EN := 0
|
||||
export PARAM_WUSER_W := 1
|
||||
export PARAM_BUSER_EN := 0
|
||||
export PARAM_BUSER_W := 1
|
||||
export PARAM_ARUSER_EN := 0
|
||||
export PARAM_ARUSER_W := 1
|
||||
export PARAM_RUSER_EN := 0
|
||||
export PARAM_RUSER_W := 1
|
||||
export PARAM_AW_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_W_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_B_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_AR_REG_TYPE := $(REG_TYPE)
|
||||
export PARAM_R_REG_TYPE := $(REG_TYPE)
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
246
src/axi/tb/taxi_axil_register/test_taxi_axil_register.py
Normal file
246
src/axi/tb/taxi_axil_register/test_taxi_axil_register.py
Normal file
@@ -0,0 +1,246 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst)
|
||||
self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axil_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
self.axil_ram.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axil_ram.read_if.r_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.r_channel.set_pause_generator(generator())
|
||||
self.axil_ram.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axil_ram.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axil_ram.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axil_ram.write(addr-128, b'\xaa'*(length+256))
|
||||
|
||||
await tb.axil_master.write(addr, test_data)
|
||||
|
||||
tb.log.debug("%s", tb.axil_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
assert tb.axil_ram.read(addr, length) == test_data
|
||||
assert tb.axil_ram.read(addr-1, 1) == b'\xaa'
|
||||
assert tb.axil_ram.read(addr+length, 1) == b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.axil_ram.write(addr, test_data)
|
||||
|
||||
data = await tb.axil_master.read(addr, length)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(32, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
for test in [run_test_write, run_test_read, run_stress_test]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("reg_type", [0, 1, 2])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axil_register(request, data_w, reg_type):
|
||||
dut = "taxi_axil_register"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 32
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['AWUSER_EN'] = 0
|
||||
parameters['AWUSER_W'] = 1
|
||||
parameters['WUSER_EN'] = 0
|
||||
parameters['WUSER_W'] = 1
|
||||
parameters['BUSER_EN'] = 0
|
||||
parameters['BUSER_W'] = 1
|
||||
parameters['ARUSER_EN'] = 0
|
||||
parameters['ARUSER_W'] = 1
|
||||
parameters['RUSER_EN'] = 0
|
||||
parameters['RUSER_W'] = 1
|
||||
parameters['AW_REG_TYPE'] = reg_type
|
||||
parameters['W_REG_TYPE'] = reg_type
|
||||
parameters['B_REG_TYPE'] = reg_type
|
||||
parameters['AR_REG_TYPE'] = reg_type
|
||||
parameters['R_REG_TYPE'] = reg_type
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
88
src/axi/tb/taxi_axil_register/test_taxi_axil_register.sv
Normal file
88
src/axi/tb/taxi_axil_register/test_taxi_axil_register.sv
Normal file
@@ -0,0 +1,88 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite register testbench
|
||||
*/
|
||||
module test_taxi_axil_register #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 32,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter logic AWUSER_EN = 1'b0,
|
||||
parameter AWUSER_W = 1,
|
||||
parameter logic WUSER_EN = 1'b0,
|
||||
parameter WUSER_W = 1,
|
||||
parameter logic BUSER_EN = 1'b0,
|
||||
parameter BUSER_W = 1,
|
||||
parameter logic ARUSER_EN = 1'b0,
|
||||
parameter ARUSER_W = 1,
|
||||
parameter logic RUSER_EN = 1'b0,
|
||||
parameter RUSER_W = 1,
|
||||
parameter AW_REG_TYPE = 1,
|
||||
parameter W_REG_TYPE = 1,
|
||||
parameter B_REG_TYPE = 1,
|
||||
parameter AR_REG_TYPE = 1,
|
||||
parameter R_REG_TYPE = 1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axil_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W),
|
||||
.STRB_W(STRB_W),
|
||||
.AWUSER_EN(AWUSER_EN),
|
||||
.AWUSER_W(AWUSER_W),
|
||||
.WUSER_EN(WUSER_EN),
|
||||
.WUSER_W(WUSER_W),
|
||||
.BUSER_EN(BUSER_EN),
|
||||
.BUSER_W(BUSER_W),
|
||||
.ARUSER_EN(ARUSER_EN),
|
||||
.ARUSER_W(ARUSER_W),
|
||||
.RUSER_EN(RUSER_EN),
|
||||
.RUSER_W(RUSER_W)
|
||||
) s_axil(), m_axil();
|
||||
|
||||
taxi_axil_register #(
|
||||
.AW_REG_TYPE(AW_REG_TYPE),
|
||||
.W_REG_TYPE(W_REG_TYPE),
|
||||
.B_REG_TYPE(B_REG_TYPE),
|
||||
.AR_REG_TYPE(AR_REG_TYPE),
|
||||
.R_REG_TYPE(R_REG_TYPE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axil_wr(s_axil),
|
||||
.s_axil_rd(s_axil),
|
||||
|
||||
/*
|
||||
* AXI4-Lite master interface
|
||||
*/
|
||||
.m_axil_wr(m_axil),
|
||||
.m_axil_rd(m_axil)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user