bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 17:08:38 -08:00
Code Issues Packages Projects Releases Wiki Activity

Reorganize repository

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-05-18 12:25:59 -07:00
parent 8cdae180a1
commit 66b53d98a2
690 changed files with 2314 additions and 1581 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/axis/lib/taxi Symbolic link
View File

@@ -0,0 +1 @@
../../../

290
src/axis/rtl/taxi_axis_adapter.sv Normal file
View File

@@ -0,0 +1,290 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream bus width adapter
*/
module taxi_axis_adapter
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis
);
// extract parameters
localparam S_DATA_W = s_axis.DATA_W;
localparam logic S_KEEP_EN = s_axis.KEEP_EN;
localparam S_KEEP_W = s_axis.KEEP_W;
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
localparam logic LAST_EN = s_axis.LAST_EN;
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
localparam ID_W = s_axis.ID_W;
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
localparam DEST_W = s_axis.DEST_W;
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
localparam USER_W = s_axis.USER_W;
localparam M_DATA_W = m_axis.DATA_W;
localparam logic M_KEEP_EN = m_axis.KEEP_EN;
localparam M_KEEP_W = m_axis.KEEP_W;
// force keep width to 1 when disabled
localparam S_BYTE_LANES = S_KEEP_EN ? S_KEEP_W : 1;
localparam M_BYTE_LANES = M_KEEP_EN ? M_KEEP_W : 1;
// bus byte sizes (must be identical)
localparam S_BYTE_SIZE = S_DATA_W / S_BYTE_LANES;
localparam M_BYTE_SIZE = M_DATA_W / M_BYTE_LANES;
// check configuration
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_W)
$fatal(0, "Error: input data width not evenly divisible (instance %m)");
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_W)
$fatal(0, "Error: output data width not evenly divisible (instance %m)");
if (S_BYTE_SIZE != M_BYTE_SIZE)
$fatal(0, "Error: byte size mismatch (instance %m)");
wire [S_KEEP_W-1:0] s_axis_tkeep_int = S_KEEP_EN ? s_axis.tkeep : '1;
if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass
// same width; bypass
assign s_axis.tready = m_axis.tready;
assign m_axis.tdata = s_axis.tdata;
assign m_axis.tkeep = (M_KEEP_EN && S_KEEP_EN) ? s_axis.tkeep : '1;
assign m_axis.tstrb = STRB_EN ? s_axis.tstrb : m_axis.tkeep;
assign m_axis.tvalid = s_axis.tvalid;
assign m_axis.tlast = LAST_EN ? s_axis.tlast : 1'b1;
assign m_axis.tid = ID_EN ? s_axis.tid : '0;
assign m_axis.tdest = DEST_EN ? s_axis.tdest : '0;
assign m_axis.tuser = USER_EN ? s_axis.tuser : '0;
end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
// output is wider; upsize
// required number of segments in wider bus
localparam SEG_COUNT = M_BYTE_LANES / S_BYTE_LANES;
// data width and keep width per segment
localparam SEG_DATA_W = M_DATA_W / SEG_COUNT;
localparam SEG_KEEP_W = M_BYTE_LANES / SEG_COUNT;
localparam CL_SEG_COUNT = $clog2(SEG_COUNT);
logic [CL_SEG_COUNT-1:0] seg_reg = '0;
logic [S_DATA_W-1:0] s_axis_tdata_reg = '0;
logic [S_KEEP_W-1:0] s_axis_tkeep_reg = '0;
logic [S_KEEP_W-1:0] s_axis_tstrb_reg = '0;
logic s_axis_tvalid_reg = 1'b0;
logic s_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] s_axis_tid_reg = '0;
logic [DEST_W-1:0] s_axis_tdest_reg = '0;
logic [USER_W-1:0] s_axis_tuser_reg = '0;
logic [M_DATA_W-1:0] m_axis_tdata_reg = '0;
logic [M_KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic [M_KEEP_W-1:0] m_axis_tstrb_reg = '0;
logic m_axis_tvalid_reg = 1'b0;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
assign s_axis.tready = !s_axis_tvalid_reg;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = M_KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
assign m_axis.tvalid = m_axis_tvalid_reg;
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
always_ff @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis.tready;
if (!m_axis_tvalid_reg || m_axis.tready) begin
// output register empty
if (seg_reg == 0) begin
m_axis_tdata_reg[seg_reg*SEG_DATA_W +: SEG_DATA_W] <= s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis.tdata;
m_axis_tkeep_reg <= M_KEEP_W'(s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep_int);
m_axis_tstrb_reg <= M_KEEP_W'(s_axis_tvalid_reg ? s_axis_tstrb_reg : s_axis.tstrb);
end else begin
m_axis_tdata_reg[seg_reg*SEG_DATA_W +: SEG_DATA_W] <= s_axis.tdata;
m_axis_tkeep_reg[seg_reg*SEG_KEEP_W +: SEG_KEEP_W] <= s_axis_tkeep_int;
m_axis_tstrb_reg[seg_reg*SEG_KEEP_W +: SEG_KEEP_W] <= s_axis.tstrb;
end
m_axis_tlast_reg <= s_axis_tvalid_reg ? s_axis_tlast_reg : s_axis.tlast;
m_axis_tid_reg <= s_axis_tvalid_reg ? s_axis_tid_reg : s_axis.tid;
m_axis_tdest_reg <= s_axis_tvalid_reg ? s_axis_tdest_reg : s_axis.tdest;
m_axis_tuser_reg <= s_axis_tvalid_reg ? s_axis_tuser_reg : s_axis.tuser;
if (s_axis_tvalid_reg) begin
// consume data from buffer
s_axis_tvalid_reg <= 1'b0;
if ((LAST_EN && s_axis_tlast_reg) || seg_reg == CL_SEG_COUNT'(SEG_COUNT-1)) begin
seg_reg <= '0;
m_axis_tvalid_reg <= 1'b1;
end else begin
seg_reg <= seg_reg + 1;
end
end else if (s_axis.tvalid) begin
// data direct from input
if ((LAST_EN && s_axis.tlast) || seg_reg == CL_SEG_COUNT'(SEG_COUNT-1)) begin
seg_reg <= '0;
m_axis_tvalid_reg <= 1'b1;
end else begin
seg_reg <= seg_reg + 1;
end
end
end else if (s_axis.tvalid && s_axis.tready) begin
// store input data in skid buffer
s_axis_tdata_reg <= s_axis.tdata;
s_axis_tkeep_reg <= s_axis_tkeep_int;
s_axis_tstrb_reg <= s_axis.tstrb;
s_axis_tvalid_reg <= 1'b1;
s_axis_tlast_reg <= s_axis.tlast;
s_axis_tid_reg <= s_axis.tid;
s_axis_tdest_reg <= s_axis.tdest;
s_axis_tuser_reg <= s_axis.tuser;
end
if (rst) begin
seg_reg <= '0;
s_axis_tvalid_reg <= 1'b0;
m_axis_tvalid_reg <= 1'b0;
end
end
end else begin : downsize
// output is narrower; downsize
// required number of segments in wider bus
localparam SEG_COUNT = S_BYTE_LANES / M_BYTE_LANES;
// data width and keep width per segment
localparam SEG_DATA_W = S_DATA_W / SEG_COUNT;
localparam SEG_KEEP_W = S_BYTE_LANES / SEG_COUNT;
logic [S_DATA_W-1:0] s_axis_tdata_reg = '0;
logic [S_KEEP_W-1:0] s_axis_tkeep_reg = '0;
logic [S_KEEP_W-1:0] s_axis_tstrb_reg = '0;
logic s_axis_tvalid_reg = 1'b0;
logic s_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] s_axis_tid_reg = '0;
logic [DEST_W-1:0] s_axis_tdest_reg = '0;
logic [USER_W-1:0] s_axis_tuser_reg = '0;
logic [M_DATA_W-1:0] m_axis_tdata_reg = '0;
logic [M_KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic [M_KEEP_W-1:0] m_axis_tstrb_reg = '0;
logic m_axis_tvalid_reg = 1'b0;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
assign s_axis.tready = !s_axis_tvalid_reg;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = M_KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
assign m_axis.tvalid = m_axis_tvalid_reg;
assign m_axis.tlast = m_axis_tlast_reg;
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
always_ff @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis.tready;
if (!m_axis_tvalid_reg || m_axis.tready) begin
// output register empty
m_axis_tdata_reg <= M_DATA_W'(s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis.tdata);
m_axis_tkeep_reg <= M_KEEP_W'(s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep_int);
m_axis_tstrb_reg <= M_KEEP_W'(s_axis_tvalid_reg ? s_axis_tstrb_reg : s_axis.tstrb);
m_axis_tlast_reg <= 1'b0;
m_axis_tid_reg <= s_axis_tvalid_reg ? s_axis_tid_reg : s_axis.tid;
m_axis_tdest_reg <= s_axis_tvalid_reg ? s_axis_tdest_reg : s_axis.tdest;
m_axis_tuser_reg <= s_axis_tvalid_reg ? s_axis_tuser_reg : s_axis.tuser;
if (s_axis_tvalid_reg) begin
// buffer has data; shift out from buffer
s_axis_tdata_reg <= s_axis_tdata_reg >> SEG_DATA_W;
s_axis_tkeep_reg <= s_axis_tkeep_reg >> SEG_KEEP_W;
s_axis_tstrb_reg <= s_axis_tstrb_reg >> SEG_KEEP_W;
m_axis_tvalid_reg <= 1'b1;
if ((s_axis_tkeep_reg >> SEG_KEEP_W) == 0) begin
s_axis_tvalid_reg <= 1'b0;
m_axis_tlast_reg <= s_axis_tlast_reg;
end
end else if (s_axis.tvalid && s_axis.tready) begin
// buffer is empty; store from input
s_axis_tdata_reg <= s_axis.tdata >> SEG_DATA_W;
s_axis_tkeep_reg <= s_axis_tkeep_int >> SEG_KEEP_W;
s_axis_tstrb_reg <= s_axis.tstrb >> SEG_KEEP_W;
s_axis_tlast_reg <= s_axis.tlast;
s_axis_tid_reg <= s_axis.tid;
s_axis_tdest_reg <= s_axis.tdest;
s_axis_tuser_reg <= s_axis.tuser;
m_axis_tvalid_reg <= 1'b1;
if (S_KEEP_EN && (s_axis_tkeep_int >> SEG_KEEP_W) == 0) begin
s_axis_tvalid_reg <= 1'b0;
m_axis_tlast_reg <= s_axis.tlast;
end else begin
s_axis_tvalid_reg <= 1'b1;
end
end
end else if (s_axis.tvalid && s_axis.tready) begin
// store input data
s_axis_tdata_reg <= s_axis.tdata;
s_axis_tkeep_reg <= s_axis_tkeep_int;
s_axis_tstrb_reg <= s_axis.tstrb;
s_axis_tvalid_reg <= 1'b1;
s_axis_tlast_reg <= s_axis.tlast;
s_axis_tid_reg <= s_axis.tid;
s_axis_tdest_reg <= s_axis.tdest;
s_axis_tuser_reg <= s_axis.tuser;
end
if (rst) begin
s_axis_tvalid_reg <= 1'b0;
m_axis_tvalid_reg <= 1'b0;
end
end
end
endmodule
`resetall

4
src/axis/rtl/taxi_axis_arb_mux.f Normal file
View File

@@ -0,0 +1,4 @@
taxi_axis_arb_mux.sv
taxi_axis_if.sv
../lib/taxi/src/prim/rtl/taxi_arbiter.sv
../lib/taxi/src/prim/rtl/taxi_penc.sv

306
src/axis/rtl/taxi_axis_arb_mux.sv Normal file
View File

@@ -0,0 +1,306 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream arbitrated multiplexer
*/
module taxi_axis_arb_mux #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Update tid with routing information
parameter logic UPDATE_TID = 1'b0,
// select round robin arbitration
parameter logic ARB_ROUND_ROBIN = 1'b0,
// LSB priority selection
parameter logic ARB_LSB_HIGH_PRIO = 1'b1
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream inputs (sink)
*/
taxi_axis_if.snk s_axis[S_COUNT],
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis
);
// extract parameters
localparam DATA_W = s_axis[0].DATA_W;
localparam logic KEEP_EN = s_axis[0].KEEP_EN && m_axis.KEEP_EN;
localparam KEEP_W = s_axis[0].KEEP_W;
localparam logic STRB_EN = s_axis[0].STRB_EN && m_axis.STRB_EN;
localparam logic LAST_EN = s_axis[0].LAST_EN && m_axis.LAST_EN;
localparam logic ID_EN = s_axis[0].ID_EN && m_axis.ID_EN;
localparam S_ID_W = s_axis[0].ID_W;
localparam logic DEST_EN = s_axis[0].DEST_EN && m_axis.DEST_EN;
localparam DEST_W = s_axis[0].DEST_W;
localparam logic USER_EN = s_axis[0].USER_EN && m_axis.USER_EN;
localparam USER_W = s_axis[0].USER_W;
localparam M_ID_W = m_axis.ID_W;
localparam CL_S_COUNT = $clog2(S_COUNT);
localparam S_ID_W_INT = S_ID_W > 0 ? S_ID_W : 1;
// check configuration
if (UPDATE_TID) begin
if (!ID_EN)
$fatal(0, "Error: UPDATE_TID set requires ID_EN set (instance %m)");
if (M_ID_W < CL_S_COUNT)
$fatal(0, "Error: M_ID_W too small for port count (instance %m)");
end
// internal datapath
logic [DATA_W-1:0] m_axis_tdata_int;
logic [KEEP_W-1:0] m_axis_tkeep_int;
logic [KEEP_W-1:0] m_axis_tstrb_int;
logic m_axis_tvalid_int;
logic m_axis_tready_int_reg = 1'b0;
logic m_axis_tlast_int;
logic [M_ID_W-1:0] m_axis_tid_int;
logic [DEST_W-1:0] m_axis_tdest_int;
logic [USER_W-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
if (S_COUNT == 1) begin
// degenerate case
assign s_axis[0].tready = m_axis_tready_int_reg;
always_comb begin
// pass through selected packet data
m_axis_tdata_int = s_axis[0].tdata;
m_axis_tkeep_int = s_axis[0].tkeep;
m_axis_tstrb_int = s_axis[0].tstrb;
m_axis_tvalid_int = s_axis[0].tvalid && m_axis_tready_int_reg;
m_axis_tlast_int = s_axis[0].tlast;
m_axis_tid_int = M_ID_W'(s_axis[0].tid);
m_axis_tdest_int = s_axis[0].tdest;
m_axis_tuser_int = s_axis[0].tuser;
end
end else begin
wire [S_COUNT-1:0] req;
wire [S_COUNT-1:0] ack;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_index;
// input registers to pipeline arbitration delay
logic [DATA_W-1:0] s_axis_tdata_reg[S_COUNT] = '{S_COUNT{'0}};
logic [KEEP_W-1:0] s_axis_tkeep_reg[S_COUNT] = '{S_COUNT{'0}};
logic [KEEP_W-1:0] s_axis_tstrb_reg[S_COUNT] = '{S_COUNT{'0}};
logic [S_COUNT-1:0] s_axis_tvalid_reg = '0;
logic [S_COUNT-1:0] s_axis_tlast_reg = '0;
logic [S_ID_W-1:0] s_axis_tid_reg[S_COUNT] = '{S_COUNT{'0}};
logic [DEST_W-1:0] s_axis_tdest_reg[S_COUNT] = '{S_COUNT{'0}};
logic [USER_W-1:0] s_axis_tuser_reg[S_COUNT] = '{S_COUNT{'0}};
// unpack interface array
wire [S_COUNT-1:0] s_axis_tvalid;
wire [S_COUNT-1:0] s_axis_tready;
for (genvar n = 0; n < S_COUNT; n = n + 1) begin
assign s_axis_tvalid[n] = s_axis[n].tvalid;
assign s_axis[n].tready = s_axis_tready[n];
end
assign s_axis_tready = ~s_axis_tvalid_reg | ({S_COUNT{m_axis_tready_int_reg}} & grant);
// mux for incoming packet
wire [DATA_W-1:0] current_s_tdata = s_axis_tdata_reg[grant_index];
wire [KEEP_W-1:0] current_s_tkeep = s_axis_tkeep_reg[grant_index];
wire [KEEP_W-1:0] current_s_tstrb = s_axis_tstrb_reg[grant_index];
wire current_s_tvalid = s_axis_tvalid_reg[grant_index];
wire current_s_tready = s_axis_tready[grant_index];
wire current_s_tlast = s_axis_tlast_reg[grant_index];
wire [S_ID_W-1:0] current_s_tid = s_axis_tid_reg[grant_index];
wire [DEST_W-1:0] current_s_tdest = s_axis_tdest_reg[grant_index];
wire [USER_W-1:0] current_s_tuser = s_axis_tuser_reg[grant_index];
// arbiter instance
taxi_arbiter #(
.PORTS(S_COUNT),
.ARB_ROUND_ROBIN(ARB_ROUND_ROBIN),
.ARB_BLOCK(1'b1),
.ARB_BLOCK_ACK(1'b1),
.LSB_HIGH_PRIO(ARB_LSB_HIGH_PRIO)
)
arb_inst (
.clk(clk),
.rst(rst),
.req(req),
.ack(ack),
.grant(grant),
.grant_valid(grant_valid),
.grant_index(grant_index)
);
assign req = s_axis_tvalid | (s_axis_tvalid_reg & ~grant);
assign ack = grant & s_axis_tvalid_reg & {S_COUNT{m_axis_tready_int_reg}} & (LAST_EN ? s_axis_tlast_reg : {S_COUNT{1'b1}});
always_comb begin
// pass through selected packet data
m_axis_tdata_int = current_s_tdata;
m_axis_tkeep_int = current_s_tkeep;
m_axis_tstrb_int = current_s_tstrb;
m_axis_tvalid_int = current_s_tvalid && m_axis_tready_int_reg && grant_valid;
m_axis_tlast_int = current_s_tlast;
m_axis_tid_int = M_ID_W'(current_s_tid);
if (UPDATE_TID && S_COUNT > 1) begin
m_axis_tid_int[M_ID_W-1:M_ID_W-CL_S_COUNT] = grant_index;
end
m_axis_tdest_int = current_s_tdest;
m_axis_tuser_int = current_s_tuser;
end
for (genvar n = 0; n < S_COUNT; n = n + 1) begin
always_ff @(posedge clk) begin
// register inputs
if (s_axis_tready[n]) begin
s_axis_tdata_reg[n] <= s_axis[n].tdata;
s_axis_tkeep_reg[n] <= s_axis[n].tkeep;
s_axis_tstrb_reg[n] <= s_axis[n].tstrb;
s_axis_tvalid_reg[n] <= s_axis[n].tvalid;
s_axis_tlast_reg[n] <= s_axis[n].tlast;
s_axis_tid_reg[n] <= s_axis[n].tid;
s_axis_tdest_reg[n] <= s_axis[n].tdest;
s_axis_tuser_reg[n] <= s_axis[n].tuser;
end
if (rst) begin
s_axis_tvalid_reg[n] <= 1'b0;
end
end
end
end
// output datapath logic
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
logic m_axis_tlast_reg = 1'b0;
logic [M_ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
logic temp_m_axis_tlast_reg = 1'b0;
logic [M_ID_W-1:0] temp_m_axis_tid_reg = '0;
logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
// datapath control
logic store_axis_int_to_output;
logic store_axis_int_to_temp;
logic store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
assign m_axis.tvalid = m_axis_tvalid_reg;
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always_comb begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis.tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis.tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tstrb_reg <= m_axis_tstrb_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tstrb_reg <= m_axis_tstrb_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

4
src/axis/rtl/taxi_axis_async_fifo.f Normal file
View File

@@ -0,0 +1,4 @@
taxi_axis_async_fifo.sv
../lib/taxi/src/sync/rtl/taxi_sync_reset.sv
../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
taxi_axis_if.sv

887
src/axis/rtl/taxi_axis_async_fifo.sv Normal file
View File

@@ -0,0 +1,887 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream asynchronous FIFO
*/
module taxi_axis_async_fifo #
(
// FIFO depth in words
// KEEP_W words per cycle if KEEP_EN set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// FIFO ramstyle attribute
parameter FIFO_RAMSTYLE = "auto",
// number of RAM pipeline registers
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter logic OUTPUT_FIFO_EN = 1'b0,
// output FIFO ramstyle attribute
parameter OUTPUT_FIFO_RAMSTYLE = "distributed",
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_EN set
parameter logic FRAME_FIFO = 1'b0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_BAD_FRAME = 1'b0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_WHEN_FULL = 1'b0,
// Mark incoming frames as bad frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO to be clear
parameter logic MARK_WHEN_FULL = 1'b0,
// Enable pause request input
parameter logic PAUSE_EN = 1'b0,
// Pause between frames
parameter logic FRAME_PAUSE = FRAME_FIFO
)
(
/*
* AXI4-Stream input (sink)
*/
input wire logic s_clk,
input wire logic s_rst,
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
input wire logic m_clk,
input wire logic m_rst,
taxi_axis_if.src m_axis,
/*
* Pause
*/
input wire logic s_pause_req = 1'b0,
output wire logic s_pause_ack,
input wire logic m_pause_req = 1'b0,
output wire logic m_pause_ack,
/*
* Status
*/
output wire logic [$clog2(DEPTH):0] s_status_depth,
output wire logic [$clog2(DEPTH):0] s_status_depth_commit,
output wire logic s_status_overflow,
output wire logic s_status_bad_frame,
output wire logic s_status_good_frame,
output wire logic [$clog2(DEPTH):0] m_status_depth,
output wire logic [$clog2(DEPTH):0] m_status_depth_commit,
output wire logic m_status_overflow,
output wire logic m_status_bad_frame,
output wire logic m_status_good_frame
);
// extract parameters
localparam DATA_W = s_axis.DATA_W;
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
localparam KEEP_W = s_axis.KEEP_W;
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
localparam ID_W = s_axis.ID_W;
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
localparam DEST_W = s_axis.DEST_W;
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
localparam USER_W = s_axis.USER_W;
localparam CL_DEPTH = $clog2(DEPTH);
localparam CL_KEEP_W = $clog2(KEEP_W);
localparam FIFO_AW = (KEEP_EN && KEEP_W > 1) ? $clog2(DEPTH/KEEP_W) : CL_DEPTH;
localparam OUTPUT_FIFO_AW = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
// check configuration
if (FRAME_FIFO && !LAST_EN)
$fatal(0, "Error: FRAME_FIFO set requires LAST_EN set (instance %m)");
if (DROP_OVERSIZE_FRAME && !FRAME_FIFO)
$fatal(0, "Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
$fatal(0, "Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
$fatal(0, "Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_W'(USER_BAD_FRAME_MASK) & {USER_W{1'b1}}) == 0)
$fatal(0, "Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
if (MARK_WHEN_FULL && FRAME_FIFO)
$fatal(0, "Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)");
if (MARK_WHEN_FULL && !LAST_EN)
$fatal(0, "Error: MARK_WHEN_FULL set requires LAST_EN set (instance %m)");
if (m_axis.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
localparam KEEP_OFFSET = DATA_W;
localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0);
localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_EN ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_EN ? ID_W : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_EN ? DEST_W : 0);
localparam WIDTH = USER_OFFSET + (USER_EN ? USER_W : 0);
function [FIFO_AW:0] bin2gray(input [FIFO_AW:0] b);
bin2gray = b ^ (b >> 1);
endfunction
function [FIFO_AW:0] gray2bin(input [FIFO_AW:0] g);
for (integer i = 0; i <= FIFO_AW; i = i + 1) begin
gray2bin[i] = ^(g >> i);
end
endfunction
logic [FIFO_AW:0] wr_ptr_reg = '0;
logic [FIFO_AW:0] wr_ptr_commit_reg = '0;
logic [FIFO_AW:0] wr_ptr_gray_reg = '0;
logic [FIFO_AW:0] wr_ptr_sync_commit_reg = '0;
logic [FIFO_AW:0] rd_ptr_reg = '0;
logic [FIFO_AW:0] rd_ptr_gray_reg = '0;
logic [FIFO_AW:0] wr_ptr_conv_reg = '0;
logic [FIFO_AW:0] rd_ptr_conv_reg = '0;
logic [FIFO_AW:0] wr_ptr_temp;
logic [FIFO_AW:0] rd_ptr_temp;
(* SHREG_EXTRACT = "NO" *)
logic [FIFO_AW:0] wr_ptr_gray_sync1_reg = '0;
(* SHREG_EXTRACT = "NO" *)
logic [FIFO_AW:0] wr_ptr_gray_sync2_reg = '0;
(* SHREG_EXTRACT = "NO" *)
logic [FIFO_AW:0] wr_ptr_commit_sync_reg = '0;
(* SHREG_EXTRACT = "NO" *)
logic [FIFO_AW:0] rd_ptr_gray_sync1_reg = '0;
(* SHREG_EXTRACT = "NO" *)
logic [FIFO_AW:0] rd_ptr_gray_sync2_reg = '0;
logic wr_ptr_update_valid_reg = 1'b0;
logic wr_ptr_update_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
logic wr_ptr_update_sync1_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
logic wr_ptr_update_sync2_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
logic wr_ptr_update_sync3_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
logic wr_ptr_update_ack_sync1_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
logic wr_ptr_update_ack_sync2_reg = 1'b0;
wire s_rst_sync;
wire m_rst_sync;
(* ramstyle = "no_rw_check" *)
logic [WIDTH-1:0] mem[2**FIFO_AW];
logic mem_read_data_valid_reg = 1'b0;
(* shreg_extract = "no" *)
logic [WIDTH-1:0] mem_rd_data_pipe_reg[RAM_PIPELINE+1-1:0];
logic [RAM_PIPELINE+1-1:0] mem_rd_valid_pipe_reg = 0;
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = wr_ptr_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {FIFO_AW-1{1'b0}}});
// empty when pointers match exactly
wire empty = FRAME_FIFO ? (rd_ptr_reg == wr_ptr_commit_sync_reg) : (rd_ptr_gray_reg == wr_ptr_gray_sync2_reg);
// overflow within packet
wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {FIFO_AW{1'b0}}});
// control signals
logic write;
logic read;
logic store_output;
logic s_frame_reg = 1'b0;
logic m_frame_reg = 1'b0;
logic drop_frame_reg = 1'b0;
logic mark_frame_reg = 1'b0;
logic send_frame_reg = 1'b0;
logic overflow_reg = 1'b0;
logic bad_frame_reg = 1'b0;
logic good_frame_reg = 1'b0;
logic m_empty_pipe_reg = 1'b0;
logic m_terminate_frame_reg = 1'b0;
logic [FIFO_AW:0] s_depth_reg = '0;
logic [FIFO_AW:0] s_depth_commit_reg = '0;
logic [FIFO_AW:0] m_depth_reg = '0;
logic [FIFO_AW:0] m_depth_commit_reg = '0;
logic overflow_sync1_reg = 1'b0;
logic overflow_sync2_reg = 1'b0;
logic overflow_sync3_reg = 1'b0;
logic overflow_sync4_reg = 1'b0;
logic bad_frame_sync1_reg = 1'b0;
logic bad_frame_sync2_reg = 1'b0;
logic bad_frame_sync3_reg = 1'b0;
logic bad_frame_sync4_reg = 1'b0;
logic good_frame_sync1_reg = 1'b0;
logic good_frame_sync2_reg = 1'b0;
logic good_frame_sync3_reg = 1'b0;
logic good_frame_sync4_reg = 1'b0;
assign s_axis.tready = (FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL)) && !s_rst_sync;
wire [WIDTH-1:0] mem_wr_data;
generate
assign mem_wr_data[DATA_W-1:0] = s_axis.tdata;
if (KEEP_EN) assign mem_wr_data[KEEP_OFFSET +: KEEP_W] = s_axis.tkeep;
if (STRB_EN) assign mem_wr_data[STRB_OFFSET +: KEEP_W] = s_axis.tstrb;
if (LAST_EN) assign mem_wr_data[LAST_OFFSET] = s_axis.tlast | mark_frame_reg;
if (ID_EN) assign mem_wr_data[ID_OFFSET +: ID_W] = s_axis.tid;
if (DEST_EN) assign mem_wr_data[DEST_OFFSET +: DEST_W] = s_axis.tdest;
if (USER_EN) assign mem_wr_data[USER_OFFSET +: USER_W] = mark_frame_reg ? USER_W'(USER_BAD_FRAME_VALUE) : s_axis.tuser;
endgenerate
wire [WIDTH-1:0] mem_rd_data = mem_rd_data_pipe_reg[RAM_PIPELINE+1-1];
wire m_axis_tready_pipe;
wire m_axis_tvalid_pipe = mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1];
wire [DATA_W-1:0] m_axis_tdata_pipe = mem_rd_data[DATA_W-1:0];
wire [KEEP_W-1:0] m_axis_tkeep_pipe;
wire [KEEP_W-1:0] m_axis_tstrb_pipe;
wire m_axis_tlast_pipe;
wire [ID_W-1:0] m_axis_tid_pipe;
wire [DEST_W-1:0] m_axis_tdest_pipe;
wire [USER_W-1:0] m_axis_tuser_pipe;
if (KEEP_EN) begin
assign m_axis_tkeep_pipe = mem_rd_data[KEEP_OFFSET +: KEEP_W];
end else begin
assign m_axis_tkeep_pipe = '1;
end
if (STRB_EN) begin
assign m_axis_tstrb_pipe = mem_rd_data[STRB_OFFSET +: KEEP_W];
end else begin
assign m_axis_tstrb_pipe = m_axis_tkeep_pipe;
end
if (LAST_EN) begin
assign m_axis_tlast_pipe = mem_rd_data[LAST_OFFSET] | m_terminate_frame_reg;
end else begin
assign m_axis_tlast_pipe = 1'b1;
end
if (ID_EN) begin
assign m_axis_tid_pipe = mem_rd_data[ID_OFFSET +: ID_W];
end else begin
assign m_axis_tid_pipe = '0;
end
if (DEST_EN) begin
assign m_axis_tdest_pipe = mem_rd_data[DEST_OFFSET +: DEST_W];
end else begin
assign m_axis_tdest_pipe = '0;
end
if (USER_EN) begin
assign m_axis_tuser_pipe = m_terminate_frame_reg ? USER_W'(USER_BAD_FRAME_VALUE) : mem_rd_data[USER_OFFSET +: USER_W];
end else begin
assign m_axis_tuser_pipe = '0;
end
wire m_axis_tready_out;
wire m_axis_tvalid_out;
wire [DATA_W-1:0] m_axis_tdata_out;
wire [KEEP_W-1:0] m_axis_tkeep_out;
wire [KEEP_W-1:0] m_axis_tstrb_out;
wire m_axis_tlast_out;
wire [ID_W-1:0] m_axis_tid_out;
wire [DEST_W-1:0] m_axis_tdest_out;
wire [USER_W-1:0] m_axis_tuser_out;
wire pipe_ready;
assign s_status_depth = (KEEP_EN && KEEP_W > 1) ? {s_depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(s_depth_reg);
assign s_status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {s_depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(s_depth_commit_reg);
assign s_status_overflow = overflow_reg;
assign s_status_bad_frame = bad_frame_reg;
assign s_status_good_frame = good_frame_reg;
assign m_status_depth = (KEEP_EN && KEEP_W > 1) ? {m_depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(m_depth_reg);
assign m_status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {m_depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(m_depth_commit_reg);
assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg;
assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg;
assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg;
// reset synchronization
taxi_sync_reset #(
.N(4)
)
s_reset_sync_inst (
.clk(s_clk),
.rst(m_rst),
.out(s_rst_sync)
);
taxi_sync_reset #(
.N(4)
)
m_reset_sync_inst (
.clk(m_clk),
.rst(s_rst),
.out(m_rst_sync)
);
// Write logic
always_ff @(posedge s_clk) begin
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
if (FRAME_FIFO && wr_ptr_update_valid_reg) begin
// have updated pointer to sync
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_sync_commit_reg <= wr_ptr_commit_reg;
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
end
end
if (s_axis.tready && s_axis.tvalid && LAST_EN) begin
// track input frame status
s_frame_reg <= !s_axis.tlast;
end
if (s_rst_sync && LAST_EN) begin
// if sink side is reset during transfer, drop partial frame
if (s_frame_reg && !(s_axis.tready && s_axis.tvalid && s_axis.tlast)) begin
drop_frame_reg <= 1'b1;
end
if (s_axis.tready && s_axis.tvalid && !s_axis.tlast) begin
drop_frame_reg <= 1'b1;
end
end
if (FRAME_FIFO) begin
// frame FIFO mode
if (s_axis.tready && s_axis.tvalid) begin
// transfer in
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
if (s_axis.tlast) begin
// end of frame, reset write pointer
wr_ptr_temp = wr_ptr_commit_reg;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
if (s_axis.tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
// end of frame or send frame
send_frame_reg <= !s_axis.tlast;
if (s_axis.tlast && DROP_BAD_FRAME && (USER_W'(USER_BAD_FRAME_MASK) & ~(s_axis.tuser ^ USER_W'(USER_BAD_FRAME_VALUE))) != 0) begin
// bad packet, reset write pointer
wr_ptr_temp = wr_ptr_commit_reg;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
bad_frame_reg <= 1'b1;
end else begin
// good packet or packet overflow, update write pointer
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_sync_commit_reg <= wr_ptr_temp;
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
end else begin
// sync in progress; flag it for later
wr_ptr_update_valid_reg <= 1'b1;
end
good_frame_reg <= s_axis.tlast;
end
end
end
end else if (s_axis.tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
// data valid with packet overflow
// update write pointer
send_frame_reg <= 1'b1;
wr_ptr_temp = wr_ptr_reg;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_sync_commit_reg <= wr_ptr_temp;
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
end else begin
// sync in progress; flag it for later
wr_ptr_update_valid_reg <= 1'b1;
end
end
end else begin
// normal FIFO mode
if (s_axis.tready && s_axis.tvalid) begin
if (drop_frame_reg && LAST_EN) begin
// currently dropping frame
if (s_axis.tlast) begin
// end of frame
if (!full && mark_frame_reg && MARK_WHEN_FULL) begin
// terminate marked frame
mark_frame_reg <= 1'b0;
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
end
// end of frame, clear drop flag
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin
// full or marking frame
// drop frame; mark if this isn't the first cycle
drop_frame_reg <= 1'b1;
mark_frame_reg <= mark_frame_reg || s_frame_reg;
if (s_axis.tlast) begin
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
// transfer in
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
end
end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin
// terminate marked frame
mark_frame_reg <= 1'b0;
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
end
end
if (s_rst_sync) begin
wr_ptr_reg <= '0;
wr_ptr_commit_reg <= '0;
wr_ptr_gray_reg <= '0;
wr_ptr_sync_commit_reg <= '0;
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_update_reg <= 1'b0;
end
if (s_rst) begin
wr_ptr_reg <= '0;
wr_ptr_commit_reg <= '0;
wr_ptr_gray_reg <= '0;
wr_ptr_sync_commit_reg <= '0;
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_update_reg <= 1'b0;
s_frame_reg <= 1'b0;
drop_frame_reg <= 1'b0;
mark_frame_reg <= 1'b0;
send_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end
end
// Write-side status
always_ff @(posedge s_clk) begin
rd_ptr_conv_reg <= gray2bin(rd_ptr_gray_sync2_reg);
s_depth_reg <= wr_ptr_reg - rd_ptr_conv_reg;
s_depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_conv_reg;
end
// pointer synchronization
always_ff @(posedge s_clk) begin
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
if (s_rst) begin
rd_ptr_gray_sync1_reg <= '0;
rd_ptr_gray_sync2_reg <= '0;
wr_ptr_update_ack_sync1_reg <= 1'b0;
wr_ptr_update_ack_sync2_reg <= 1'b0;
end
end
always_ff @(posedge m_clk) begin
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
if (FRAME_FIFO && wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin
wr_ptr_commit_sync_reg <= wr_ptr_sync_commit_reg;
end
wr_ptr_update_sync1_reg <= wr_ptr_update_reg;
wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
if (FRAME_FIFO && m_rst_sync) begin
wr_ptr_gray_sync1_reg <= '0;
end
if (m_rst) begin
wr_ptr_gray_sync1_reg <= '0;
wr_ptr_gray_sync2_reg <= '0;
wr_ptr_commit_sync_reg <= '0;
wr_ptr_update_sync1_reg <= 1'b0;
wr_ptr_update_sync2_reg <= 1'b0;
wr_ptr_update_sync3_reg <= 1'b0;
end
end
// status synchronization
always_ff @(posedge s_clk) begin
overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg;
bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg;
good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg;
if (s_rst) begin
overflow_sync1_reg <= 1'b0;
bad_frame_sync1_reg <= 1'b0;
good_frame_sync1_reg <= 1'b0;
end
end
always_ff @(posedge m_clk) begin
overflow_sync2_reg <= overflow_sync1_reg;
overflow_sync3_reg <= overflow_sync2_reg;
overflow_sync4_reg <= overflow_sync3_reg;
bad_frame_sync2_reg <= bad_frame_sync1_reg;
bad_frame_sync3_reg <= bad_frame_sync2_reg;
bad_frame_sync4_reg <= bad_frame_sync3_reg;
good_frame_sync2_reg <= good_frame_sync1_reg;
good_frame_sync3_reg <= good_frame_sync2_reg;
good_frame_sync4_reg <= good_frame_sync3_reg;
if (m_rst) begin
overflow_sync2_reg <= 1'b0;
overflow_sync3_reg <= 1'b0;
overflow_sync4_reg <= 1'b0;
bad_frame_sync2_reg <= 1'b0;
bad_frame_sync3_reg <= 1'b0;
bad_frame_sync4_reg <= 1'b0;
good_frame_sync2_reg <= 1'b0;
good_frame_sync3_reg <= 1'b0;
good_frame_sync4_reg <= 1'b0;
end
end
// Read logic
always_ff @(posedge m_clk) begin
if (m_axis_tready_pipe) begin
// output ready; invalidate stage
mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
m_terminate_frame_reg <= 1'b0;
end
for (integer j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
// if (m_axis_tready_pipe || ((~mem_rd_valid_pipe_reg) >> j)) begin
if (m_axis_tready_pipe || ((RAM_PIPELINE+1)'(~mem_rd_valid_pipe_reg) >> j) != 0) begin
// output ready or bubble in pipeline; transfer down pipeline
mem_rd_valid_pipe_reg[j] <= mem_rd_valid_pipe_reg[j-1];
mem_rd_data_pipe_reg[j] <= mem_rd_data_pipe_reg[j-1];
mem_rd_valid_pipe_reg[j-1] <= 1'b0;
end
end
if (m_axis_tready_pipe || &mem_rd_valid_pipe_reg == 0) begin
// output ready or bubble in pipeline; read new data from FIFO
mem_rd_valid_pipe_reg[0] <= 1'b0;
mem_rd_data_pipe_reg[0] <= mem[rd_ptr_reg[FIFO_AW-1:0]];
if (!empty && !m_rst_sync && !m_empty_pipe_reg && pipe_ready) begin
// not empty, increment pointer
mem_rd_valid_pipe_reg[0] <= 1'b1;
rd_ptr_temp = rd_ptr_reg + 1;
rd_ptr_reg <= rd_ptr_temp;
rd_ptr_gray_reg <= rd_ptr_temp ^ (rd_ptr_temp >> 1);
end
end
if (m_axis_tvalid_pipe && LAST_EN) begin
// track output frame status
if (m_axis_tlast_pipe && m_axis_tready_pipe) begin
m_frame_reg <= 1'b0;
end else begin
m_frame_reg <= 1'b1;
end
end
if (m_empty_pipe_reg && mem_rd_valid_pipe_reg == 0 && LAST_EN) begin
// terminate frame
// (only for frame transfers interrupted by source reset)
if (m_frame_reg) begin
mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b1;
m_terminate_frame_reg <= 1'b1;
end
m_empty_pipe_reg <= 1'b0;
end
if (m_rst_sync && LAST_EN) begin
// if source side is reset during transfer, drop partial frame
m_empty_pipe_reg <= 1'b1;
end
if (m_rst_sync) begin
rd_ptr_reg <= '0;
rd_ptr_gray_reg <= '0;
end
if (m_rst) begin
rd_ptr_reg <= '0;
rd_ptr_gray_reg <= '0;
mem_rd_valid_pipe_reg <= '0;
m_frame_reg <= 1'b0;
m_empty_pipe_reg <= 1'b0;
m_terminate_frame_reg <= 1'b0;
end
end
// Read-side status
always_ff @(posedge m_clk) begin
wr_ptr_conv_reg <= gray2bin(wr_ptr_gray_sync2_reg);
m_depth_reg <= wr_ptr_conv_reg - rd_ptr_reg;
m_depth_commit_reg <= FRAME_FIFO ? wr_ptr_commit_sync_reg - rd_ptr_reg : wr_ptr_conv_reg - rd_ptr_reg;
end
if (!OUTPUT_FIFO_EN) begin
assign pipe_ready = 1'b1;
assign m_axis_tready_pipe = m_axis_tready_out;
assign m_axis_tvalid_out = m_axis_tvalid_pipe;
assign m_axis_tdata_out = m_axis_tdata_pipe;
assign m_axis_tkeep_out = m_axis_tkeep_pipe;
assign m_axis_tstrb_out = m_axis_tstrb_pipe;
assign m_axis_tlast_out = m_axis_tlast_pipe;
assign m_axis_tid_out = m_axis_tid_pipe;
assign m_axis_tdest_out = m_axis_tdest_pipe;
assign m_axis_tuser_out = m_axis_tuser_pipe;
end else begin : output_fifo
// output datapath logic
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
logic m_axis_tvalid_reg = 1'b0;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = 0;
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = 0;
logic out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic out_fifo_tlast[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [ID_W-1:0] out_fifo_tid[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW];
assign pipe_ready = !out_fifo_half_full_reg;
assign m_axis_tready_pipe = 1'b1;
assign m_axis_tdata_out = m_axis_tdata_reg;
assign m_axis_tkeep_out = KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis_tstrb_out = STRB_EN ? m_axis_tkeep_reg : m_axis_tkeep_out;
assign m_axis_tvalid_out = m_axis_tvalid_reg;
assign m_axis_tlast_out = LAST_EN ? m_axis_tlast_reg : 1'b1;
assign m_axis_tid_out = ID_EN ? m_axis_tid_reg : '0;
assign m_axis_tdest_out = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis_tuser_out = USER_EN ? m_axis_tuser_reg : '0;
always_ff @(posedge m_clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out;
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_AW-1);
if (!out_fifo_full && m_axis_tvalid_pipe) begin
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdata_pipe;
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tkeep_pipe;
out_fifo_tstrb[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tstrb_pipe;
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tlast_pipe;
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tid_pipe;
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdest_pipe;
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tuser_pipe;
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tstrb_reg <= out_fifo_tstrb[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tvalid_reg <= 1'b1;
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (m_rst) begin
out_fifo_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
m_axis_tvalid_reg <= 1'b0;
end
end
end
if (PAUSE_EN) begin : pause
// Pause logic
logic pause_reg = 1'b0;
logic pause_frame_reg = 1'b0;
wire s_pause_req_sync;
taxi_sync_signal #(
.WIDTH(1),
.N(2)
)
pause_req_sync_inst (
.clk(m_clk),
.in(s_pause_req),
.out(s_pause_req_sync)
);
taxi_sync_signal #(
.WIDTH(1),
.N(2)
)
pause_ack_sync_inst (
.clk(s_clk),
.in(pause_reg),
.out(s_pause_ack)
);
assign m_axis_tready_out = m_axis.tready && !pause_reg;
assign m_axis.tvalid = m_axis_tvalid_out && !pause_reg;
assign m_axis.tdata = m_axis_tdata_out;
assign m_axis.tkeep = m_axis_tkeep_out;
assign m_axis.tstrb = m_axis_tstrb_out;
assign m_axis.tlast = m_axis_tlast_out;
assign m_axis.tid = m_axis_tid_out;
assign m_axis.tdest = m_axis_tdest_out;
assign m_axis.tuser = m_axis_tuser_out;
assign m_pause_ack = pause_reg;
always_ff @(posedge m_clk) begin
if (FRAME_PAUSE) begin
if (pause_reg) begin
// paused; update pause status
pause_reg <= m_pause_req || s_pause_req_sync;
end else if (m_axis_tvalid_out) begin
// frame transfer; set frame bit
pause_frame_reg <= 1'b1;
if (m_axis.tready && m_axis.tlast) begin
// end of frame; clear frame bit and update pause status
pause_frame_reg <= 1'b0;
pause_reg <= m_pause_req || s_pause_req_sync;
end
end else if (!pause_frame_reg) begin
// idle; update pause status
pause_reg <= m_pause_req || s_pause_req_sync;
end
end else begin
pause_reg <= m_pause_req || s_pause_req_sync;
end
if (m_rst) begin
pause_frame_reg <= 1'b0;
pause_reg <= 1'b0;
end
end
end else begin
assign m_axis_tready_out = m_axis.tready;
assign m_axis.tvalid = m_axis_tvalid_out;
assign m_axis.tdata = m_axis_tdata_out;
assign m_axis.tkeep = m_axis_tkeep_out;
assign m_axis.tstrb = m_axis_tstrb_out;
assign m_axis.tlast = m_axis_tlast_out;
assign m_axis.tid = m_axis_tid_out;
assign m_axis.tdest = m_axis_tdest_out;
assign m_axis.tuser = m_axis_tuser_out;
assign s_pause_ack = 1'b0;
assign m_pause_ack = 1'b0;
end
endmodule
`resetall

3
src/axis/rtl/taxi_axis_async_fifo_adapter.f Normal file
View File

@@ -0,0 +1,3 @@
taxi_axis_async_fifo_adapter.sv
taxi_axis_async_fifo.f
taxi_axis_adapter.sv

244
src/axis/rtl/taxi_axis_async_fifo_adapter.sv Normal file
View File

@@ -0,0 +1,244 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2019-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream asynchronous FIFO with width converter
*/
module taxi_axis_async_fifo_adapter #
(
// FIFO depth in words
// KEEP_W words per cycle if KEEP_EN set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// number of RAM pipeline registers in FIFO
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter logic OUTPUT_FIFO_EN = 1'b0,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_EN set
parameter logic FRAME_FIFO = 1'b0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_BAD_FRAME = 1'b0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_WHEN_FULL = 1'b0,
// Mark incoming frames as bad frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO to be clear
parameter logic MARK_WHEN_FULL = 1'b0,
// Enable pause request input
parameter logic PAUSE_EN = 1'b0,
// Pause between frames
parameter logic FRAME_PAUSE = FRAME_FIFO
)
(
/*
* AXI4-Stream input (sink)
*/
input wire logic s_clk,
input wire logic s_rst,
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
input wire logic m_clk,
input wire logic m_rst,
taxi_axis_if.src m_axis,
/*
* Pause
*/
input wire logic s_pause_req = 1'b0,
output wire logic s_pause_ack,
input wire logic m_pause_req = 1'b0,
output wire logic m_pause_ack,
/*
* Status
*/
output wire logic [$clog2(DEPTH):0] s_status_depth,
output wire logic [$clog2(DEPTH):0] s_status_depth_commit,
output wire logic s_status_overflow,
output wire logic s_status_bad_frame,
output wire logic s_status_good_frame,
output wire logic [$clog2(DEPTH):0] m_status_depth,
output wire logic [$clog2(DEPTH):0] m_status_depth_commit,
output wire logic m_status_overflow,
output wire logic m_status_bad_frame,
output wire logic m_status_good_frame
);
// extract parameters
localparam S_DATA_W = s_axis.DATA_W;
localparam logic S_KEEP_EN = s_axis.KEEP_EN;
localparam S_KEEP_W = s_axis.KEEP_W;
localparam logic S_STRB_EN = s_axis.STRB_EN;
localparam M_DATA_W = m_axis.DATA_W;
localparam logic M_KEEP_EN = m_axis.KEEP_EN;
localparam M_KEEP_W = m_axis.KEEP_W;
localparam logic M_STRB_EN = m_axis.STRB_EN;
// force keep width to 1 when disabled
localparam S_BYTE_LANES = S_KEEP_EN ? S_KEEP_W : 1;
localparam M_BYTE_LANES = M_KEEP_EN ? M_KEEP_W : 1;
// bus byte sizes (must be identical)
localparam S_BYTE_SIZE = S_DATA_W / S_BYTE_LANES;
localparam M_BYTE_SIZE = M_DATA_W / M_BYTE_LANES;
// output bus is wider
localparam EXPAND_BUS = M_BYTE_LANES > S_BYTE_LANES;
// total data and keep widths
localparam DATA_W = EXPAND_BUS ? M_DATA_W : S_DATA_W;
localparam KEEP_W = EXPAND_BUS ? M_BYTE_LANES : S_BYTE_LANES;
localparam KEEP_EN = EXPAND_BUS ? M_KEEP_EN : S_KEEP_EN;
localparam STRB_EN = M_STRB_EN && S_STRB_EN;
// check configuration
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_W)
$fatal(0, "Error: input data width not evenly divisible (instance %m)");
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_W)
$fatal(0, "Error: output data width not evenly divisible (instance %m)");
if (S_BYTE_SIZE != M_BYTE_SIZE)
$fatal(0, "Error: byte size mismatch (instance %m)");
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(s_axis.STRB_EN),
.LAST_EN(s_axis.LAST_EN),
.ID_EN(s_axis.ID_EN),
.ID_W(s_axis.ID_W),
.DEST_EN(s_axis.DEST_EN),
.DEST_W(s_axis.DEST_W),
.USER_EN(s_axis.USER_EN),
.USER_W(s_axis.USER_W)
) axis_pre_fifo();
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(m_axis.STRB_EN),
.LAST_EN(m_axis.LAST_EN),
.ID_EN(m_axis.ID_EN),
.ID_W(m_axis.ID_W),
.DEST_EN(m_axis.DEST_EN),
.DEST_W(m_axis.DEST_W),
.USER_EN(m_axis.USER_EN),
.USER_W(m_axis.USER_W)
) axis_post_fifo();
taxi_axis_adapter
pre_fifo_adapter_inst (
.clk(s_clk),
.rst(s_rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(axis_pre_fifo)
);
taxi_axis_async_fifo #(
.DEPTH(DEPTH),
.RAM_PIPELINE(RAM_PIPELINE),
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.MARK_WHEN_FULL(MARK_WHEN_FULL),
.PAUSE_EN(PAUSE_EN),
.FRAME_PAUSE(FRAME_PAUSE)
)
fifo_inst (
/*
* AXI4-Stream input (sink)
*/
.s_clk(s_clk),
.s_rst(s_rst),
.s_axis(axis_pre_fifo),
/*
* AXI4-Stream output (source)
*/
.m_clk(m_clk),
.m_rst(m_rst),
.m_axis(axis_post_fifo),
/*
* Pause
*/
.s_pause_req(s_pause_req),
.s_pause_ack(s_pause_ack),
.m_pause_req(m_pause_req),
.m_pause_ack(m_pause_ack),
/*
* Status
*/
.s_status_depth(s_status_depth),
.s_status_depth_commit(s_status_depth_commit),
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_depth(m_status_depth),
.m_status_depth_commit(m_status_depth_commit),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
taxi_axis_adapter
post_fifo_adapter_inst (
.clk(m_clk),
.rst(m_rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(axis_post_fifo),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

179
src/axis/rtl/taxi_axis_broadcast.sv Normal file
View File

@@ -0,0 +1,179 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2019-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream broadcaster
*/
module taxi_axis_broadcast #
(
// Number of AXI stream outputs
parameter M_COUNT = 4
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream outputs (sources)
*/
taxi_axis_if.src m_axis[M_COUNT]
);
// extract parameters
localparam DATA_W = s_axis.DATA_W;
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis[0].KEEP_EN;
localparam KEEP_W = s_axis.KEEP_W;
localparam logic STRB_EN = s_axis.STRB_EN && m_axis[0].STRB_EN;
localparam logic LAST_EN = s_axis.LAST_EN && m_axis[0].LAST_EN;
localparam logic ID_EN = s_axis.ID_EN && m_axis[0].ID_EN;
localparam ID_W = s_axis.ID_W;
localparam logic DEST_EN = s_axis.DEST_EN && m_axis[0].DEST_EN;
localparam DEST_W = s_axis.DEST_W;
localparam logic USER_EN = s_axis.USER_EN && m_axis[0].USER_EN;
localparam USER_W = s_axis.USER_W;
// check configuration
if (m_axis[0].DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (KEEP_EN && m_axis[0].KEEP_W != KEEP_W)
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
// datapath registers
logic s_axis_tready_reg = 1'b0, s_axis_tready_next;
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
logic [M_COUNT-1:0] m_axis_tvalid_reg = '0, m_axis_tvalid_next;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
logic temp_m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
// // datapath control
logic store_axis_input_to_output;
logic store_axis_input_to_temp;
logic store_axis_temp_to_output;
assign s_axis.tready = s_axis_tready_reg;
wire [M_COUNT-1:0] m_axis_tready;
wire [M_COUNT-1:0] m_axis_tvalid;
for (genvar n = 0; n < M_COUNT; n = n + 1) begin
assign m_axis[n].tdata = m_axis_tdata_reg;
assign m_axis[n].tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis[n].tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis[n].tkeep;
assign m_axis[n].tvalid = m_axis_tvalid_reg[n];
assign m_axis[n].tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
assign m_axis[n].tid = ID_EN ? m_axis_tid_reg : '0;
assign m_axis[n].tdest = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis[n].tuser = USER_EN ? m_axis_tuser_reg : '0;
assign m_axis_tready[n] = m_axis[n].tready;
assign m_axis_tvalid[n] = m_axis[n].tvalid;
end
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (m_axis_tvalid == 0 || !s_axis.tvalid));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_input_to_output = 1'b0;
store_axis_input_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (s_axis_tready_reg) begin
// input is ready
if (((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || m_axis_tvalid == 0) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = {M_COUNT{s_axis.tvalid}};
store_axis_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = s_axis.tvalid;
store_axis_input_to_temp = 1'b1;
end
end else if ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) begin
// input is not ready, but output is ready
m_axis_tvalid_next = {M_COUNT{temp_m_axis_tvalid_reg}};
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
s_axis_tready_reg <= s_axis_tready_early;
m_axis_tvalid_reg <= m_axis_tvalid_next;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
// datapath
if (store_axis_input_to_output) begin
m_axis_tdata_reg <= s_axis.tdata;
m_axis_tkeep_reg <= s_axis.tkeep;
m_axis_tstrb_reg <= s_axis.tstrb;
m_axis_tlast_reg <= s_axis.tlast;
m_axis_tid_reg <= s_axis.tid;
m_axis_tdest_reg <= s_axis.tdest;
m_axis_tuser_reg <= s_axis.tuser;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_input_to_temp) begin
temp_m_axis_tdata_reg <= s_axis.tdata;
temp_m_axis_tkeep_reg <= s_axis.tkeep;
temp_m_axis_tstrb_reg <= s_axis.tstrb;
temp_m_axis_tlast_reg <= s_axis.tlast;
temp_m_axis_tid_reg <= s_axis.tid;
temp_m_axis_tdest_reg <= s_axis.tdest;
temp_m_axis_tuser_reg <= s_axis.tuser;
end
if (rst) begin
s_axis_tready_reg <= 1'b0;
m_axis_tvalid_reg <= '0;
temp_m_axis_tvalid_reg <= '0;
end
end
endmodule
`resetall

321
src/axis/rtl/taxi_axis_cobs_decode.sv Normal file
View File

@@ -0,0 +1,321 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2016-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream consistent overhead byte stuffing (COBS) decoder
*/
module taxi_axis_cobs_decode
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis
);
// check configuration
if (m_axis.DATA_W != 8 || s_axis.DATA_W != 8)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_SEGMENT = 2'd1,
STATE_NEXT_SEGMENT = 2'd2;
logic [1:0] state_reg = STATE_IDLE, state_next;
logic [7:0] count_reg = 8'd0, count_next;
logic suppress_zero_reg = 1'b0, suppress_zero_next;
logic [7:0] temp_tdata_reg = 8'd0, temp_tdata_next;
logic temp_tvalid_reg = 1'b0, temp_tvalid_next;
// internal datapath
logic [7:0] m_axis_tdata_int;
logic m_axis_tvalid_int;
logic m_axis_tready_int_reg = 1'b0;
logic m_axis_tlast_int;
logic m_axis_tuser_int;
wire m_axis_tready_int_early;
logic s_axis_tready_reg = 1'b0, s_axis_tready_next;
assign s_axis.tready = s_axis_tready_reg;
always_comb begin
state_next = STATE_IDLE;
count_next = count_reg;
suppress_zero_next = suppress_zero_reg;
temp_tdata_next = temp_tdata_reg;
temp_tvalid_next = temp_tvalid_reg;
m_axis_tdata_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
s_axis_tready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state
s_axis_tready_next = m_axis_tready_int_early || !temp_tvalid_reg;
// output final word
m_axis_tdata_int = temp_tdata_reg;
m_axis_tvalid_int = temp_tvalid_reg;
m_axis_tlast_int = temp_tvalid_reg;
temp_tvalid_next = temp_tvalid_reg && !m_axis_tready_int_reg;
if (s_axis.tready && s_axis.tvalid) begin
// valid input data
// skip any leading zeros
if (s_axis.tdata != 8'd0) begin
// store count value and zero suppress
count_next = s_axis.tdata-1;
suppress_zero_next = (s_axis.tdata == 8'd255);
s_axis_tready_next = m_axis_tready_int_early;
if (s_axis.tdata == 8'd1) begin
// next byte will be count value
state_next = STATE_NEXT_SEGMENT;
end else begin
// next byte will be data
state_next = STATE_SEGMENT;
end
end else begin
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_SEGMENT: begin
// receive segment
s_axis_tready_next = m_axis_tready_int_early;
if (s_axis.tready && s_axis.tvalid) begin
// valid input data
// store in temp register
temp_tdata_next = s_axis.tdata;
temp_tvalid_next = 1'b1;
// move temp to output
m_axis_tdata_int = temp_tdata_reg;
m_axis_tvalid_int = temp_tvalid_reg;
// decrement count
count_next = count_reg - 1;
if (s_axis.tdata == 8'd0) begin
// got a zero byte in a frame - mark it as an error and re-sync
temp_tvalid_next = 1'b0;
m_axis_tvalid_int = 1'b1;
m_axis_tuser_int = 1'b1;
m_axis_tlast_int = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end else if (s_axis.LAST_EN && s_axis.tlast) begin
// end of frame
if (count_reg == 8'd1 && (!s_axis.USER_EN || !s_axis.tuser)) begin
// end of frame indication at correct time, go to idle to output final byte
state_next = STATE_IDLE;
end else begin
// end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
temp_tvalid_next = 1'b0;
m_axis_tvalid_int = 1'b1;
m_axis_tuser_int = 1'b1;
m_axis_tlast_int = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else if (count_reg == 8'd1) begin
// next byte will be count value
state_next = STATE_NEXT_SEGMENT;
end else begin
// next byte will be data
state_next = STATE_SEGMENT;
end
end else begin
state_next = STATE_SEGMENT;
end
end
STATE_NEXT_SEGMENT: begin
// next segment
s_axis_tready_next = m_axis_tready_int_early;
if (s_axis.tready && s_axis.tvalid) begin
// valid input data
// store zero in temp if not suppressed
temp_tdata_next = 8'd0;
temp_tvalid_next = !suppress_zero_reg;
// move temp to output
m_axis_tdata_int = temp_tdata_reg;
m_axis_tvalid_int = temp_tvalid_reg;
if (s_axis.tdata == 8'd0) begin
// got a zero byte delineating the end of the frame, so mark as such and re-sync
temp_tvalid_next = 1'b0;
m_axis_tuser_int = s_axis.tuser;
m_axis_tlast_int = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end else if (s_axis.LAST_EN && s_axis.tlast) begin
if (s_axis.tdata == 8'd1 && (!s_axis.USER_EN || !s_axis.tuser)) begin
// end of frame indication at correct time, go to idle to output final byte
state_next = STATE_IDLE;
end else begin
// end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
temp_tvalid_next = 1'b0;
m_axis_tvalid_int = 1'b1;
m_axis_tuser_int = 1'b1;
m_axis_tlast_int = 1'b1;
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
// otherwise, store count value and zero suppress
count_next = s_axis.tdata-1;
suppress_zero_next = (s_axis.tdata == 8'd255);
s_axis_tready_next = m_axis_tready_int_early;
if (s_axis.tdata == 8'd1) begin
// next byte will be count value
state_next = STATE_NEXT_SEGMENT;
end else begin
// next byte will be data
state_next = STATE_SEGMENT;
end
end
end else begin
state_next = STATE_NEXT_SEGMENT;
end
end
default: begin
// invalid state
state_next = STATE_IDLE;
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
count_reg <= count_next;
suppress_zero_reg <= suppress_zero_next;
temp_tdata_reg <= temp_tdata_next;
temp_tvalid_reg <= temp_tvalid_next;
s_axis_tready_reg <= s_axis_tready_next;
if (rst) begin
state_reg <= STATE_IDLE;
temp_tvalid_reg <= 1'b0;
s_axis_tready_reg <= 1'b0;
end
end
// output datapath logic
logic [7:0] m_axis_tdata_reg = 8'd0;
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
logic m_axis_tlast_reg = 1'b0;
logic m_axis_tuser_reg = 1'b0;
logic [7:0] temp_m_axis_tdata_reg = 8'd0;
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
logic temp_m_axis_tlast_reg = 1'b0;
logic temp_m_axis_tuser_reg = 1'b0;
// datapath control
logic store_axis_int_to_output;
logic store_axis_int_to_temp;
logic store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = 1'b1;
assign m_axis.tstrb = m_axis.tkeep;
assign m_axis.tvalid = m_axis_tvalid_reg;
assign m_axis.tlast = m_axis_tlast_reg;
assign m_axis.tid = '0;
assign m_axis.tdest = '0;
assign m_axis.tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always_comb begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis.tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis.tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

3
src/axis/rtl/taxi_axis_cobs_encode.f Normal file
View File

@@ -0,0 +1,3 @@
taxi_axis_cobs_encode.sv
taxi_axis_fifo.sv
taxi_axis_if.sv

469
src/axis/rtl/taxi_axis_cobs_encode.sv Normal file
View File

@@ -0,0 +1,469 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2016-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream consistent overhead byte stuffing (COBS) encoder
*/
module taxi_axis_cobs_encode #
(
// append zero for in band framing
parameter logic APPEND_ZERO = 1'b1
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis
);
// check configuration
if (m_axis.DATA_W != 8 || s_axis.DATA_W != 8)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
// state register
localparam [1:0]
INPUT_STATE_IDLE = 2'd0,
INPUT_STATE_SEGMENT = 2'd1,
INPUT_STATE_FINAL_ZERO = 2'd2,
INPUT_STATE_APPEND_ZERO = 2'd3;
logic [1:0] input_state_reg = INPUT_STATE_IDLE, input_state_next;
localparam [0:0]
OUTPUT_STATE_IDLE = 1'd0,
OUTPUT_STATE_SEGMENT = 1'd1;
logic [0:0] output_state_reg = OUTPUT_STATE_IDLE, output_state_next;
logic [7:0] input_count_reg = 8'd0, input_count_next;
logic [7:0] output_count_reg = 8'd0, output_count_next;
logic fail_frame_reg = 1'b0, fail_frame_next;
// internal datapath
logic [7:0] m_axis_tdata_int;
logic m_axis_tvalid_int;
logic m_axis_tready_int_reg = 1'b0;
logic m_axis_tlast_int;
logic m_axis_tuser_int;
wire m_axis_tready_int_early;
logic s_axis_tready_mask;
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) code_fifo_in(), code_fifo_out();
taxi_axis_if #(.DATA_W(8)) data_fifo_in(), data_fifo_out();
assign s_axis.tready = code_fifo_in.tready && data_fifo_in.tready && s_axis_tready_mask;
taxi_axis_fifo #(
.DEPTH(256),
.FRAME_FIFO(0)
)
code_fifo_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(code_fifo_in),
/*
* AXI4-Stream output (source)
*/
.m_axis(code_fifo_out),
/*
* Pause
*/
.pause_req(),
.pause_ack(),
/*
* Status
*/
.status_depth(),
.status_depth_commit(),
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
taxi_axis_fifo #(
.DEPTH(256),
.FRAME_FIFO(0)
)
data_fifo_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(data_fifo_in),
/*
* AXI4-Stream output (source)
*/
.m_axis(data_fifo_out),
/*
* Pause
*/
.pause_req(),
.pause_ack(),
/*
* Status
*/
.status_depth(),
.status_depth_commit(),
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
always @* begin
input_state_next = INPUT_STATE_IDLE;
input_count_next = input_count_reg;
fail_frame_next = fail_frame_reg;
s_axis_tready_mask = 1'b0;
code_fifo_in.tdata = 8'd0;
code_fifo_in.tvalid = 1'b0;
code_fifo_in.tlast = 1'b0;
code_fifo_in.tuser = 1'b0;
data_fifo_in.tdata = s_axis.tdata;
data_fifo_in.tvalid = 1'b0;
data_fifo_in.tlast = 1'b0;
data_fifo_in.tuser = 1'b0;
case (input_state_reg)
INPUT_STATE_IDLE: begin
// idle state
s_axis_tready_mask = 1'b1;
fail_frame_next = 1'b0;
if (s_axis.tready && s_axis.tvalid) begin
// valid input data
if (s_axis.tdata == 8'd0 || (s_axis.tlast && s_axis.tuser)) begin
// got a zero or propagated error, so store a zero code
code_fifo_in.tdata = 8'd1;
code_fifo_in.tvalid = 1'b1;
if (s_axis.tlast) begin
// last byte, so close out the frame
fail_frame_next = s_axis.tuser;
input_state_next = INPUT_STATE_FINAL_ZERO;
end else begin
// return to idle to await next segment
input_state_next = INPUT_STATE_IDLE;
end
end else begin
// got something other than a zero, so store it and init the segment counter
input_count_next = 8'd2;
data_fifo_in.tdata = s_axis.tdata;
data_fifo_in.tvalid = 1'b1;
if (s_axis.tlast) begin
// last byte, so store the code and close out the frame
code_fifo_in.tdata = 8'd2;
code_fifo_in.tvalid = 1'b1;
if (APPEND_ZERO) begin
// zero frame mode, need to add a zero code to end the frame
input_state_next = INPUT_STATE_APPEND_ZERO;
end else begin
// normal frame mode, close out the frame
data_fifo_in.tlast = 1'b1;
input_state_next = INPUT_STATE_IDLE;
end
end else begin
// await more segment data
input_state_next = INPUT_STATE_SEGMENT;
end
end
end else begin
input_state_next = INPUT_STATE_IDLE;
end
end
INPUT_STATE_SEGMENT: begin
// encode segment
s_axis_tready_mask = 1'b1;
fail_frame_next = 1'b0;
if (s_axis.tready && s_axis.tvalid) begin
// valid input data
if (s_axis.tdata == 8'd0 || (s_axis.tlast && s_axis.tuser)) begin
// got a zero or propagated error, so store the code
code_fifo_in.tdata = input_count_reg;
code_fifo_in.tvalid = 1'b1;
if (s_axis.tlast) begin
// last byte, so close out the frame
fail_frame_next = s_axis.tuser;
input_state_next = INPUT_STATE_FINAL_ZERO;
end else begin
// return to idle to await next segment
input_state_next = INPUT_STATE_IDLE;
end
end else begin
// got something other than a zero, so store it and increment the segment counter
input_count_next = input_count_reg+1;
data_fifo_in.tdata = s_axis.tdata;
data_fifo_in.tvalid = 1'b1;
if (input_count_reg == 8'd254) begin
// 254 bytes in frame, so dump and reset counter
code_fifo_in.tdata = input_count_reg+1;
code_fifo_in.tvalid = 1'b1;
input_count_next = 8'd1;
end
if (s_axis.tlast) begin
// last byte, so store the code and close out the frame
code_fifo_in.tdata = input_count_reg+1;
code_fifo_in.tvalid = 1'b1;
if (APPEND_ZERO) begin
// zero frame mode, need to add a zero code to end the frame
input_state_next = INPUT_STATE_APPEND_ZERO;
end else begin
// normal frame mode, close out the frame
data_fifo_in.tlast = 1'b1;
input_state_next = INPUT_STATE_IDLE;
end
end else begin
// await more segment data
input_state_next = INPUT_STATE_SEGMENT;
end
end
end else begin
input_state_next = INPUT_STATE_SEGMENT;
end
end
INPUT_STATE_FINAL_ZERO: begin
// final zero code required
s_axis_tready_mask = 1'b0;
if (code_fifo_in.tready) begin
// push a zero code and close out frame
if (fail_frame_reg) begin
code_fifo_in.tdata = 8'd2;
code_fifo_in.tuser = 1'b1;
end else begin
code_fifo_in.tdata = 8'd1;
end
code_fifo_in.tvalid = 1'b1;
if (APPEND_ZERO) begin
// zero frame mode, need to add a zero code to end the frame
input_state_next = INPUT_STATE_APPEND_ZERO;
end else begin
// normal frame mode, close out the frame
code_fifo_in.tlast = 1'b1;
fail_frame_next = 1'b0;
input_state_next = INPUT_STATE_IDLE;
end
end else begin
input_state_next = INPUT_STATE_FINAL_ZERO;
end
end
INPUT_STATE_APPEND_ZERO: begin
// append zero for zero framing
s_axis_tready_mask = 1'b0;
if (code_fifo_in.tready) begin
// push frame termination code and close out frame
code_fifo_in.tdata = 8'd0;
code_fifo_in.tlast = 1'b1;
code_fifo_in.tuser = fail_frame_reg;
code_fifo_in.tvalid = 1'b1;
fail_frame_next = 1'b0;
input_state_next = INPUT_STATE_IDLE;
end else begin
input_state_next = INPUT_STATE_APPEND_ZERO;
end
end
endcase
end
always @* begin
output_state_next = OUTPUT_STATE_IDLE;
output_count_next = output_count_reg;
m_axis_tdata_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
code_fifo_out.tready = 1'b0;
data_fifo_out.tready = 1'b0;
case (output_state_reg)
OUTPUT_STATE_IDLE: begin
// idle state
if (m_axis_tready_int_reg && code_fifo_out.tvalid) begin
// transfer out code byte and load counter
m_axis_tdata_int = code_fifo_out.tdata;
m_axis_tlast_int = code_fifo_out.tlast;
m_axis_tuser_int = code_fifo_out.tuser && code_fifo_out.tlast;
output_count_next = code_fifo_out.tdata-1;
m_axis_tvalid_int = 1'b1;
code_fifo_out.tready = 1'b1;
if (code_fifo_out.tdata == 8'd0 || code_fifo_out.tdata == 8'd1 || code_fifo_out.tuser) begin
// frame termination and zero codes will be followed by codes
output_state_next = OUTPUT_STATE_IDLE;
end else begin
// transfer out data
output_state_next = OUTPUT_STATE_SEGMENT;
end
end else begin
output_state_next = OUTPUT_STATE_IDLE;
end
end
OUTPUT_STATE_SEGMENT: begin
// segment output
if (m_axis_tready_int_reg && data_fifo_out.tvalid) begin
// transfer out data byte and decrement counter
m_axis_tdata_int = data_fifo_out.tdata;
m_axis_tlast_int = data_fifo_out.tlast;
output_count_next = output_count_reg - 1;
m_axis_tvalid_int = 1'b1;
data_fifo_out.tready = 1'b1;
if (output_count_reg == 1) begin
// done with segment, get a code byte next
output_state_next = OUTPUT_STATE_IDLE;
end else begin
// more data to transfer
output_state_next = OUTPUT_STATE_SEGMENT;
end
end else begin
output_state_next = OUTPUT_STATE_SEGMENT;
end
end
endcase
end
always @(posedge clk) begin
input_state_reg <= input_state_next;
output_state_reg <= output_state_next;
input_count_reg <= input_count_next;
output_count_reg <= output_count_next;
fail_frame_reg <= fail_frame_next;
if (rst) begin
input_state_reg <= INPUT_STATE_IDLE;
output_state_reg <= OUTPUT_STATE_IDLE;
end
end
// output datapath logic
reg [7:0] m_axis_tdata_reg = 8'd0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_axis_tdata_reg = 8'd0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = 1'b1;
assign m_axis.tstrb = m_axis.tkeep;
assign m_axis.tvalid = m_axis_tvalid_reg;
assign m_axis.tlast = m_axis_tlast_reg;
assign m_axis.tid = '0;
assign m_axis.tdest = '0;
assign m_axis.tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis.tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis.tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

560
src/axis/rtl/taxi_axis_fifo.sv Normal file
View File

@@ -0,0 +1,560 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2013-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream FIFO
*/
module taxi_axis_fifo #
(
// FIFO depth in words
// KEEP_W words per cycle if KEEP_EN set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// number of RAM pipeline registers
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter logic OUTPUT_FIFO_EN = 1'b0,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_EN set
parameter logic FRAME_FIFO = 1'b0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_BAD_FRAME = 1'b0,
// Drop incoming frames when full
// When set, s_axis.tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_WHEN_FULL = 1'b0,
// Mark incoming frames as bad frames when full
// When set, s_axis.tready is always asserted
// Requires FRAME_FIFO to be clear
parameter logic MARK_WHEN_FULL = 1'b0,
// Enable pause request input
parameter logic PAUSE_EN = 1'b0,
// Pause between frames
parameter logic FRAME_PAUSE = FRAME_FIFO
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis,
/*
* Pause
*/
input wire logic pause_req = 1'b0,
output wire logic pause_ack,
/*
* Status
*/
output wire logic [$clog2(DEPTH):0] status_depth,
output wire logic [$clog2(DEPTH):0] status_depth_commit,
output wire logic status_overflow,
output wire logic status_bad_frame,
output wire logic status_good_frame
);
// extract parameters
localparam DATA_W = s_axis.DATA_W;
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
localparam KEEP_W = s_axis.KEEP_W;
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
localparam ID_W = s_axis.ID_W;
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
localparam DEST_W = s_axis.DEST_W;
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
localparam USER_W = s_axis.USER_W;
localparam CL_DEPTH = $clog2(DEPTH);
localparam CL_KEEP_W = $clog2(KEEP_W);
localparam FIFO_AW = (KEEP_EN && KEEP_W > 1) ? $clog2(DEPTH/KEEP_W) : CL_DEPTH;
localparam OUTPUT_FIFO_AW = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
// check configuration
if (FRAME_FIFO && !LAST_EN)
$fatal(0, "Error: FRAME_FIFO set requires LAST_EN set (instance %m)");
if (DROP_OVERSIZE_FRAME && !FRAME_FIFO)
$fatal(0, "Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
$fatal(0, "Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME))
$fatal(0, "Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
if ((DROP_BAD_FRAME || MARK_WHEN_FULL) && (USER_W'(USER_BAD_FRAME_MASK) & {USER_W{1'b1}}) == 0)
$fatal(0, "Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
if (MARK_WHEN_FULL && FRAME_FIFO)
$fatal(0, "Error: MARK_WHEN_FULL is not compatible with FRAME_FIFO (instance %m)");
if (MARK_WHEN_FULL && !LAST_EN)
$fatal(0, "Error: MARK_WHEN_FULL set requires LAST_EN set (instance %m)");
if (m_axis.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
localparam KEEP_OFFSET = DATA_W;
localparam STRB_OFFSET = KEEP_OFFSET + (KEEP_EN ? KEEP_W : 0);
localparam LAST_OFFSET = STRB_OFFSET + (STRB_EN ? KEEP_W : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_EN ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_EN ? ID_W : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_EN ? DEST_W : 0);
localparam WIDTH = USER_OFFSET + (USER_EN ? USER_W : 0);
logic [FIFO_AW:0] wr_ptr_reg = '0;
logic [FIFO_AW:0] wr_ptr_commit_reg = '0;
logic [FIFO_AW:0] rd_ptr_reg = '0;
(* ramstyle = "no_rw_check" *)
logic [WIDTH-1:0] mem[2**FIFO_AW];
(* shreg_extract = "no" *)
logic [WIDTH-1:0] mem_rd_data_pipe_reg[RAM_PIPELINE+1-1:0];
logic [RAM_PIPELINE+1-1:0] mem_rd_valid_pipe_reg = '0;
// full when first MSB differs but the rest match
wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {FIFO_AW{1'b0}}});
// empty when pointers match exactly
wire empty = wr_ptr_commit_reg == rd_ptr_reg;
// overflow within packet, same as full but based on write commit
wire full_wr = wr_ptr_reg == (wr_ptr_commit_reg ^ {1'b1, {FIFO_AW{1'b0}}});
logic s_frame_reg = 1'b0;
logic drop_frame_reg = 1'b0;
logic mark_frame_reg = 1'b0;
logic send_frame_reg = 1'b0;
logic [FIFO_AW:0] depth_reg = '0;
logic [FIFO_AW:0] depth_commit_reg = '0;
logic overflow_reg = 1'b0;
logic bad_frame_reg = 1'b0;
logic good_frame_reg = 1'b0;
assign s_axis.tready = FRAME_FIFO ? (!full || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : (!full || MARK_WHEN_FULL);
wire [WIDTH-1:0] mem_wr_data;
assign mem_wr_data[DATA_W-1:0] = s_axis.tdata;
if (KEEP_EN) assign mem_wr_data[KEEP_OFFSET +: KEEP_W] = s_axis.tkeep;
if (STRB_EN) assign mem_wr_data[STRB_OFFSET +: KEEP_W] = s_axis.tkeep;
if (LAST_EN) assign mem_wr_data[LAST_OFFSET] = s_axis.tlast | mark_frame_reg;
if (ID_EN) assign mem_wr_data[ID_OFFSET +: ID_W] = s_axis.tid;
if (DEST_EN) assign mem_wr_data[DEST_OFFSET +: DEST_W] = s_axis.tdest;
if (USER_EN) assign mem_wr_data[USER_OFFSET +: USER_W] = mark_frame_reg ? USER_W'(USER_BAD_FRAME_VALUE) : s_axis.tuser;
wire [WIDTH-1:0] mem_rd_data = mem_rd_data_pipe_reg[RAM_PIPELINE+1-1];
wire m_axis_tready_pipe;
wire m_axis_tvalid_pipe = mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1];
wire [DATA_W-1:0] m_axis_tdata_pipe = mem_rd_data[DATA_W-1:0];
wire [KEEP_W-1:0] m_axis_tkeep_pipe;
wire [KEEP_W-1:0] m_axis_tstrb_pipe;
wire m_axis_tlast_pipe;
wire [ID_W-1:0] m_axis_tid_pipe;
wire [DEST_W-1:0] m_axis_tdest_pipe;
wire [USER_W-1:0] m_axis_tuser_pipe;
if (KEEP_EN) begin
assign m_axis_tkeep_pipe = mem_rd_data[KEEP_OFFSET +: KEEP_W];
end else begin
assign m_axis_tkeep_pipe = '1;
end
if (STRB_EN) begin
assign m_axis_tstrb_pipe = mem_rd_data[STRB_OFFSET +: KEEP_W];
end else begin
assign m_axis_tstrb_pipe = m_axis_tkeep_pipe;
end
if (LAST_EN) begin
assign m_axis_tlast_pipe = mem_rd_data[LAST_OFFSET];
end else begin
assign m_axis_tlast_pipe = 1'b1;
end
if (ID_EN) begin
assign m_axis_tid_pipe = mem_rd_data[ID_OFFSET +: ID_W];
end else begin
assign m_axis_tid_pipe = '0;
end
if (DEST_EN) begin
assign m_axis_tdest_pipe = mem_rd_data[DEST_OFFSET +: DEST_W];
end else begin
assign m_axis_tdest_pipe = '0;
end
if (USER_EN) begin
assign m_axis_tuser_pipe = mem_rd_data[USER_OFFSET +: USER_W];
end else begin
assign m_axis_tuser_pipe = '0;
end
wire m_axis_tready_out;
wire m_axis_tvalid_out;
wire [DATA_W-1:0] m_axis_tdata_out;
wire [KEEP_W-1:0] m_axis_tkeep_out;
wire [KEEP_W-1:0] m_axis_tstrb_out;
wire m_axis_tlast_out;
wire [ID_W-1:0] m_axis_tid_out;
wire [DEST_W-1:0] m_axis_tdest_out;
wire [USER_W-1:0] m_axis_tuser_out;
wire pipe_ready;
assign status_depth = (KEEP_EN && KEEP_W > 1) ? {depth_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(depth_reg);
assign status_depth_commit = (KEEP_EN && KEEP_W > 1) ? {depth_commit_reg, {CL_KEEP_W{1'b0}}} : (CL_DEPTH+1)'(depth_commit_reg);
assign status_overflow = overflow_reg;
assign status_bad_frame = bad_frame_reg;
assign status_good_frame = good_frame_reg;
// Write logic
always_ff @(posedge clk) begin
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
if (s_axis.tready && s_axis.tvalid && LAST_EN) begin
// track input frame status
s_frame_reg <= !s_axis.tlast;
end
if (FRAME_FIFO) begin
// frame FIFO mode
if (s_axis.tready && s_axis.tvalid) begin
// transfer in
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
if (s_axis.tlast) begin
// end of frame, reset write pointer
wr_ptr_reg <= wr_ptr_commit_reg;
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
// store it
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
wr_ptr_reg <= wr_ptr_reg + 1;
if (s_axis.tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
// end of frame or send frame
send_frame_reg <= !s_axis.tlast;
if (s_axis.tlast && DROP_BAD_FRAME && (USER_W'(USER_BAD_FRAME_MASK) & ~(s_axis.tuser ^ USER_W'(USER_BAD_FRAME_VALUE))) != 0) begin
// bad packet, reset write pointer
wr_ptr_reg <= wr_ptr_commit_reg;
bad_frame_reg <= 1'b1;
end else begin
// good packet or packet overflow, update write pointer
wr_ptr_commit_reg <= wr_ptr_reg + 1;
good_frame_reg <= s_axis.tlast;
end
end
end
end else if (s_axis.tvalid && full_wr && !DROP_OVERSIZE_FRAME) begin
// data valid with packet overflow
// update write pointer
send_frame_reg <= 1'b1;
wr_ptr_commit_reg <= wr_ptr_reg;
end
end else begin
// normal FIFO mode
if (s_axis.tready && s_axis.tvalid) begin
if (drop_frame_reg && MARK_WHEN_FULL) begin
// currently dropping frame
if (s_axis.tlast) begin
// end of frame
if (!full && mark_frame_reg) begin
// terminate marked frame
mark_frame_reg <= 1'b0;
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
wr_ptr_reg <= wr_ptr_reg + 1;
wr_ptr_commit_reg <= wr_ptr_reg + 1;
end
// end of frame, clear drop flag
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else if ((full || mark_frame_reg) && MARK_WHEN_FULL) begin
// full or marking frame
// drop frame; mark if this isn't the first cycle
drop_frame_reg <= 1'b1;
mark_frame_reg <= mark_frame_reg || s_frame_reg;
if (s_axis.tlast) begin
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
// transfer in
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
wr_ptr_reg <= wr_ptr_reg + 1;
wr_ptr_commit_reg <= wr_ptr_reg + 1;
end
end else if ((!full && !drop_frame_reg && mark_frame_reg) && MARK_WHEN_FULL) begin
// terminate marked frame
mark_frame_reg <= 1'b0;
mem[wr_ptr_reg[FIFO_AW-1:0]] <= mem_wr_data;
wr_ptr_reg <= wr_ptr_reg + 1;
wr_ptr_commit_reg <= wr_ptr_reg + 1;
end
end
if (rst) begin
wr_ptr_reg <= '0;
wr_ptr_commit_reg <= '0;
s_frame_reg <= 1'b0;
drop_frame_reg <= 1'b0;
mark_frame_reg <= 1'b0;
send_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end
end
// Status
always_ff @(posedge clk) begin
depth_reg <= wr_ptr_reg - rd_ptr_reg;
depth_commit_reg <= wr_ptr_commit_reg - rd_ptr_reg;
end
// Read logic
always_ff @(posedge clk) begin
if (m_axis_tready_pipe) begin
// output ready; invalidate stage
mem_rd_valid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
end
for (integer j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
if (m_axis_tready_pipe || ((RAM_PIPELINE+1)'(~mem_rd_valid_pipe_reg) >> j) != 0) begin
// if (m_axis_tready_pipe || &mem_rd_valid_pipe_reg[1:1] == 0) begin
// output ready or bubble in pipeline; transfer down pipeline
mem_rd_valid_pipe_reg[j] <= mem_rd_valid_pipe_reg[j-1];
mem_rd_data_pipe_reg[j] <= mem_rd_data_pipe_reg[j-1];
mem_rd_valid_pipe_reg[j-1] <= 1'b0;
end
end
if (m_axis_tready_pipe || &mem_rd_valid_pipe_reg == 0) begin
// output ready or bubble in pipeline; read new data from FIFO
mem_rd_valid_pipe_reg[0] <= 1'b0;
mem_rd_data_pipe_reg[0] <= mem[rd_ptr_reg[FIFO_AW-1:0]];
if (!empty && pipe_ready) begin
// not empty, increment pointer
mem_rd_valid_pipe_reg[0] <= 1'b1;
rd_ptr_reg <= rd_ptr_reg + 1;
end
end
if (rst) begin
rd_ptr_reg <= '0;
mem_rd_valid_pipe_reg <= '0;
end
end
if (!OUTPUT_FIFO_EN) begin
assign pipe_ready = 1'b1;
assign m_axis_tready_pipe = m_axis_tready_out;
assign m_axis_tvalid_out = m_axis_tvalid_pipe;
assign m_axis_tdata_out = m_axis_tdata_pipe;
assign m_axis_tkeep_out = m_axis_tkeep_pipe;
assign m_axis_tstrb_out = m_axis_tstrb_pipe;
assign m_axis_tlast_out = m_axis_tlast_pipe;
assign m_axis_tid_out = m_axis_tid_pipe;
assign m_axis_tdest_out = m_axis_tdest_pipe;
assign m_axis_tuser_out = m_axis_tuser_pipe;
end else begin : output_fifo
// output datapath logic
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
logic m_axis_tvalid_reg = 1'b0;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = '0;
logic [OUTPUT_FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = '0;
logic out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_AW{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic out_fifo_tlast[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [ID_W-1:0] out_fifo_tid[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW];
assign pipe_ready = !out_fifo_half_full_reg;
assign m_axis_tready_pipe = 1'b1;
assign m_axis_tdata_out = m_axis_tdata_reg;
assign m_axis_tkeep_out = KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis_tstrb_out = STRB_EN ? m_axis_tstrb_reg : m_axis_tkeep_out;
assign m_axis_tvalid_out = m_axis_tvalid_reg;
assign m_axis_tlast_out = LAST_EN ? m_axis_tlast_reg : 1'b1;
assign m_axis_tid_out = ID_EN ? m_axis_tid_reg : '0;
assign m_axis_tdest_out = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis_tuser_out = USER_EN ? m_axis_tuser_reg : '0;
always_ff @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready_out;
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_AW-1);
if (!out_fifo_full && m_axis_tvalid_pipe) begin
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdata_pipe;
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tkeep_pipe;
out_fifo_tstrb[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tstrb_pipe;
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tlast_pipe;
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tid_pipe;
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tdest_pipe;
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_AW-1:0]] <= m_axis_tuser_pipe;
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready_out)) begin
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tstrb_reg <= out_fifo_tstrb[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tvalid_reg <= 1'b1;
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_AW-1:0]];
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (rst) begin
out_fifo_wr_ptr_reg <= '0;
out_fifo_rd_ptr_reg <= '0;
m_axis_tvalid_reg <= 1'b0;
end
end
end
if (PAUSE_EN) begin : pause
// Pause logic
logic pause_reg = 1'b0;
logic pause_frame_reg = 1'b0;
assign m_axis_tready_out = m_axis.tready && !pause_reg;
assign m_axis.tvalid = m_axis_tvalid_out && !pause_reg;
assign m_axis.tdata = m_axis_tdata_out;
assign m_axis.tkeep = m_axis_tkeep_out;
assign m_axis.tstrb = m_axis_tstrb_out;
assign m_axis.tlast = m_axis_tlast_out;
assign m_axis.tid = m_axis_tid_out;
assign m_axis.tdest = m_axis_tdest_out;
assign m_axis.tuser = m_axis_tuser_out;
assign pause_ack = pause_reg;
always_ff @(posedge clk) begin
if (FRAME_PAUSE) begin
if (pause_reg) begin
// paused; update pause status
pause_reg <= pause_req;
end else if (m_axis_tvalid_out) begin
// frame transfer; set frame bit
pause_frame_reg <= 1'b1;
if (m_axis.tready && m_axis.tlast) begin
// end of frame; clear frame bit and update pause status
pause_frame_reg <= 1'b0;
pause_reg <= pause_req;
end
end else if (!pause_frame_reg) begin
// idle; update pause status
pause_reg <= pause_req;
end
end else begin
pause_reg <= pause_req;
end
if (rst) begin
pause_frame_reg <= 1'b0;
pause_reg <= 1'b0;
end
end
end else begin
assign m_axis_tready_out = m_axis.tready;
assign m_axis.tvalid = m_axis_tvalid_out;
assign m_axis.tdata = m_axis_tdata_out;
assign m_axis.tkeep = m_axis_tkeep_out;
assign m_axis.tstrb = m_axis_tstrb_out;
assign m_axis.tlast = m_axis_tlast_out;
assign m_axis.tid = m_axis_tid_out;
assign m_axis.tdest = m_axis_tdest_out;
assign m_axis.tuser = m_axis_tuser_out;
assign pause_ack = 1'b0;
end
endmodule
`resetall

4
src/axis/rtl/taxi_axis_fifo_adapter.f Normal file
View File

@@ -0,0 +1,4 @@
taxi_axis_fifo_adapter.sv
taxi_axis_fifo.sv
taxi_axis_adapter.sv
taxi_axis_if.sv

228
src/axis/rtl/taxi_axis_fifo_adapter.sv Normal file
View File

@@ -0,0 +1,228 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2019-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream FIFO with width converter
*/
module taxi_axis_fifo_adapter #
(
// FIFO depth in words
// KEEP_W words per cycle if KEEP_EN set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// number of RAM pipeline registers in FIFO
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter logic OUTPUT_FIFO_EN = 1'b0,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires logic LAST_EN set
parameter logic FRAME_FIFO = 1'b0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_BAD_FRAME = 1'b0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_WHEN_FULL = 1'b0,
// Mark incoming frames as bad frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO to be clear
parameter logic MARK_WHEN_FULL = 1'b0,
// Enable pause request input
parameter logic PAUSE_EN = 1'b0,
// Pause between frames
parameter logic FRAME_PAUSE = FRAME_FIFO
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis,
/*
* Pause
*/
input wire logic pause_req = 1'b0,
output wire logic pause_ack,
/*
* Status
*/
output wire logic [$clog2(DEPTH):0] status_depth,
output wire logic [$clog2(DEPTH):0] status_depth_commit,
output wire logic status_overflow,
output wire logic status_bad_frame,
output wire logic status_good_frame
);
// extract parameters
localparam S_DATA_W = s_axis.DATA_W;
localparam logic S_KEEP_EN = s_axis.KEEP_EN;
localparam S_KEEP_W = s_axis.KEEP_W;
localparam logic S_STRB_EN = s_axis.STRB_EN;
localparam M_DATA_W = m_axis.DATA_W;
localparam logic M_KEEP_EN = m_axis.KEEP_EN;
localparam M_KEEP_W = m_axis.KEEP_W;
localparam logic M_STRB_EN = m_axis.STRB_EN;
// force keep width to 1 when disabled
localparam S_BYTE_LANES = S_KEEP_EN ? S_KEEP_W : 1;
localparam M_BYTE_LANES = M_KEEP_EN ? M_KEEP_W : 1;
// bus byte sizes (must be identical)
localparam S_BYTE_SIZE = S_DATA_W / S_BYTE_LANES;
localparam M_BYTE_SIZE = M_DATA_W / M_BYTE_LANES;
// output bus is wider
localparam EXPAND_BUS = M_BYTE_LANES > S_BYTE_LANES;
// total data and keep widths
localparam DATA_W = EXPAND_BUS ? M_DATA_W : S_DATA_W;
localparam KEEP_W = EXPAND_BUS ? M_BYTE_LANES : S_BYTE_LANES;
localparam KEEP_EN = EXPAND_BUS ? M_KEEP_EN : S_KEEP_EN;
localparam STRB_EN = EXPAND_BUS ? M_STRB_EN : S_STRB_EN;
// check configuration
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_W)
$fatal(0, "Error: input data width not evenly divisible (instance %m)");
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_W)
$fatal(0, "Error: output data width not evenly divisible (instance %m)");
if (S_BYTE_SIZE != M_BYTE_SIZE)
$fatal(0, "Error: byte size mismatch (instance %m)");
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(s_axis.STRB_EN),
.LAST_EN(s_axis.LAST_EN),
.ID_EN(s_axis.ID_EN),
.ID_W(s_axis.ID_W),
.DEST_EN(s_axis.DEST_EN),
.DEST_W(s_axis.DEST_W),
.USER_EN(s_axis.USER_EN),
.USER_W(s_axis.USER_W)
) axis_pre_fifo();
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(m_axis.STRB_EN),
.LAST_EN(m_axis.LAST_EN),
.ID_EN(m_axis.ID_EN),
.ID_W(m_axis.ID_W),
.DEST_EN(m_axis.DEST_EN),
.DEST_W(m_axis.DEST_W),
.USER_EN(m_axis.USER_EN),
.USER_W(m_axis.USER_W)
) axis_post_fifo();
taxi_axis_adapter
pre_fifo_adapter_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(axis_pre_fifo)
);
taxi_axis_fifo #(
.DEPTH(DEPTH),
.RAM_PIPELINE(RAM_PIPELINE),
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.MARK_WHEN_FULL(MARK_WHEN_FULL),
.PAUSE_EN(PAUSE_EN),
.FRAME_PAUSE(FRAME_PAUSE)
)
fifo_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(axis_pre_fifo),
/*
* AXI4-Stream output (source)
*/
.m_axis(axis_post_fifo),
/*
* Pause
*/
.pause_req(pause_req),
.pause_ack(pause_ack),
/*
* Status
*/
.status_depth(status_depth),
.status_depth_commit(status_depth_commit),
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
taxi_axis_adapter
post_fifo_adapter_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(axis_post_fifo),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

82
src/axis/rtl/taxi_axis_if.sv Normal file
View File

@@ -0,0 +1,82 @@
// SPDX-License-Identifier: MIT
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
interface taxi_axis_if #(
// Width of AXI stream interfaces in bits
parameter DATA_W = 8,
// tkeep signal width (bytes per cycle)
parameter KEEP_W = ((DATA_W+7)/8),
// Use tkeep signal
parameter logic KEEP_EN = KEEP_W > 1,
// Use tstrb signal
parameter logic STRB_EN = 1'b0,
// Use tlast signal
parameter logic LAST_EN = 1'b1,
// Use tid signal
parameter logic ID_EN = 0,
// tid signal width
parameter ID_W = 8,
// Use tdest signal
parameter logic DEST_EN = 0,
// tdest signal width
parameter DEST_W = 8,
// Use tuser signal
parameter logic USER_EN = 0,
// tuser signal width
parameter USER_W = 1
)
();
logic [DATA_W-1:0] tdata;
logic [KEEP_W-1:0] tkeep;
logic [KEEP_W-1:0] tstrb;
logic [ID_W-1:0] tid;
logic [DEST_W-1:0] tdest;
logic [USER_W-1:0] tuser;
logic tlast;
logic tvalid;
logic tready;
modport src (
output tdata,
output tkeep,
output tstrb,
output tid,
output tdest,
output tuser,
output tlast,
output tvalid,
input tready
);
modport snk (
input tdata,
input tkeep,
input tstrb,
input tid,
input tdest,
input tuser,
input tlast,
input tvalid,
output tready
);
modport mon (
input tdata,
input tkeep,
input tstrb,
input tid,
input tdest,
input tuser,
input tlast,
input tvalid,
input tready
);
endinterface

272
src/axis/rtl/taxi_axis_mux.sv Normal file
View File

@@ -0,0 +1,272 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream multiplexer
*/
module taxi_axis_mux #
(
// Number of AXI stream inputs
parameter S_COUNT = 4
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream inputs (sinks)
*/
taxi_axis_if.snk s_axis[S_COUNT],
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis,
/*
* Control
*/
input wire logic enable,
input wire logic [$clog2(S_COUNT)-1:0] select
);
// extract parameters
localparam DATA_W = s_axis[0].DATA_W;
localparam logic KEEP_EN = s_axis[0].KEEP_EN && m_axis.KEEP_EN;
localparam KEEP_W = s_axis[0].KEEP_W;
localparam logic STRB_EN = s_axis[0].STRB_EN && m_axis.STRB_EN;
localparam logic LAST_EN = s_axis[0].LAST_EN && m_axis.LAST_EN;
localparam logic ID_EN = s_axis[0].ID_EN && m_axis.ID_EN;
localparam ID_W = s_axis[0].ID_W;
localparam logic DEST_EN = s_axis[0].DEST_EN && m_axis.DEST_EN;
localparam DEST_W = s_axis[0].DEST_W;
localparam logic USER_EN = s_axis[0].USER_EN && m_axis.USER_EN;
localparam USER_W = s_axis[0].USER_W;
// check configuration
if (m_axis.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
// internal datapath
reg [DATA_W-1:0] m_axis_tdata_int;
reg [KEEP_W-1:0] m_axis_tkeep_int;
reg [KEEP_W-1:0] m_axis_tstrb_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_W-1:0] m_axis_tid_int;
reg [DEST_W-1:0] m_axis_tdest_int;
reg [USER_W-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
// unpack interface array
wire [DATA_W-1:0] s_axis_tdata[S_COUNT];
wire [KEEP_W-1:0] s_axis_tkeep[S_COUNT];
wire [KEEP_W-1:0] s_axis_tstrb[S_COUNT];
wire [S_COUNT-1:0] s_axis_tvalid;
wire [S_COUNT-1:0] s_axis_tready;
wire [S_COUNT-1:0] s_axis_tlast;
wire [ID_W-1:0] s_axis_tid[S_COUNT];
wire [DEST_W-1:0] s_axis_tdest[S_COUNT];
wire [USER_W-1:0] s_axis_tuser[S_COUNT];
for (genvar n = 0; n < S_COUNT; n = n + 1) begin
assign s_axis_tdata[n] = s_axis[n].tdata;
assign s_axis_tkeep[n] = s_axis[n].tkeep;
assign s_axis_tstrb[n] = s_axis[n].tstrb;
assign s_axis_tvalid[n] = s_axis[n].tvalid;
assign s_axis[n].tready = s_axis_tready[n];
assign s_axis_tlast[n] = s_axis[n].tlast;
assign s_axis_tid[n] = s_axis[n].tid;
assign s_axis_tdest[n] = s_axis[n].tdest;
assign s_axis_tuser[n] = s_axis[n].tuser;
end
assign s_axis_tready = s_axis_tready_reg;
// mux for incoming packet
wire [DATA_W-1:0] current_s_tdata = s_axis_tdata[select_reg];
wire [KEEP_W-1:0] current_s_tkeep = s_axis_tkeep[select_reg];
wire [KEEP_W-1:0] current_s_tstrb = s_axis_tstrb[select_reg];
wire current_s_tvalid = s_axis_tvalid[select_reg];
wire current_s_tready = s_axis_tready[select_reg];
wire current_s_tlast = s_axis_tlast[select_reg];
wire [ID_W-1:0] current_s_tid = s_axis_tid[select_reg];
wire [DEST_W-1:0] current_s_tdest = s_axis_tdest[select_reg];
wire [USER_W-1:0] current_s_tuser = s_axis_tuser[select_reg];
always_comb begin
select_next = select_reg;
frame_next = frame_reg;
s_axis_tready_next = 0;
if (current_s_tvalid & current_s_tready) begin
// end of frame detection
if (current_s_tlast) begin
frame_next = 1'b0;
end
end
if (!frame_reg && enable && s_axis_tvalid[select]) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
end
// generate ready signal on selected port
s_axis_tready_next[select_next] = m_axis_tready_int_early && frame_next;
// pass through selected packet data
m_axis_tdata_int = current_s_tdata;
m_axis_tkeep_int = current_s_tkeep;
m_axis_tstrb_int = current_s_tstrb;
m_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
m_axis_tlast_int = current_s_tlast;
m_axis_tid_int = current_s_tid;
m_axis_tdest_int = current_s_tdest;
m_axis_tuser_int = current_s_tuser;
end
always_ff @(posedge clk) begin
select_reg <= select_next;
frame_reg <= frame_next;
s_axis_tready_reg <= s_axis_tready_next;
if (rst) begin
select_reg <= 0;
frame_reg <= 1'b0;
s_axis_tready_reg <= 0;
end
end
// output datapath logic
reg [DATA_W-1:0] m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] m_axis_tkeep_reg = '0;
reg [KEEP_W-1:0] m_axis_tstrb_reg = '0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] m_axis_tid_reg = '0;
reg [DEST_W-1:0] m_axis_tdest_reg = '0;
reg [USER_W-1:0] m_axis_tuser_reg = '0;
reg [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
reg [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
reg [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_W-1:0] temp_m_axis_tid_reg = '0;
reg [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
reg [USER_W-1:0] temp_m_axis_tuser_reg = '0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
assign m_axis.tvalid = m_axis_tvalid_reg;
assign m_axis.tlast = m_axis_tlast_reg;
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always_comb begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis.tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis.tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tstrb_reg <= m_axis_tstrb_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tstrb_reg <= m_axis_tstrb_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

235
src/axis/rtl/taxi_axis_pipeline_fifo.sv Normal file
View File

@@ -0,0 +1,235 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream pipeline FIFO
*/
module taxi_axis_pipeline_fifo #
(
// Number of registers in pipeline
parameter LENGTH = 2
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis
);
// extract parameters
localparam DATA_W = s_axis.DATA_W;
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
localparam KEEP_W = s_axis.KEEP_W;
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
localparam ID_W = s_axis.ID_W;
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
localparam DEST_W = s_axis.DEST_W;
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
localparam USER_W = s_axis.USER_W;
// check configuration
if (m_axis.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
localparam FIFO_AW = LENGTH < 2 ? 3 : $clog2(LENGTH*4+1);
taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .ID_W(ID_W), .DEST_W(DEST_W), .USER_W(USER_W)) axis_pipe[LENGTH+1]();
for (genvar n = 0; n < LENGTH; n = n + 1) begin : stage
(* shreg_extract = "no" *)
logic [DATA_W-1:0] axis_tdata_reg = 0;
(* shreg_extract = "no" *)
logic [KEEP_W-1:0] axis_tkeep_reg = 0;
(* shreg_extract = "no" *)
logic [KEEP_W-1:0] axis_tstrb_reg = 0;
(* shreg_extract = "no" *)
logic axis_tvalid_reg = 0;
(* shreg_extract = "no" *)
logic axis_tready_reg = 0;
(* shreg_extract = "no" *)
logic axis_tlast_reg = 0;
(* shreg_extract = "no" *)
logic [ID_W-1:0] axis_tid_reg = 0;
(* shreg_extract = "no" *)
logic [DEST_W-1:0] axis_tdest_reg = 0;
(* shreg_extract = "no" *)
logic [USER_W-1:0] axis_tuser_reg = 0;
assign axis_pipe[n+1].tdata = axis_tdata_reg;
assign axis_pipe[n+1].tkeep = axis_tkeep_reg;
assign axis_pipe[n+1].tstrb = axis_tstrb_reg;
assign axis_pipe[n+1].tvalid = axis_tvalid_reg;
assign axis_pipe[n+1].tlast = axis_tlast_reg;
assign axis_pipe[n+1].tid = axis_tid_reg;
assign axis_pipe[n+1].tdest = axis_tdest_reg;
assign axis_pipe[n+1].tuser = axis_tuser_reg;
assign axis_pipe[n].tready = axis_tready_reg;
always_ff @(posedge clk) begin
axis_tdata_reg <= axis_pipe[n].tdata;
axis_tkeep_reg <= axis_pipe[n].tkeep;
axis_tstrb_reg <= axis_pipe[n].tstrb;
axis_tvalid_reg <= axis_pipe[n].tvalid;
axis_tlast_reg <= axis_pipe[n].tlast;
axis_tid_reg <= axis_pipe[n].tid;
axis_tdest_reg <= axis_pipe[n].tdest;
axis_tuser_reg <= axis_pipe[n].tuser;
axis_tready_reg <= axis_pipe[n+1].tready;
if (rst) begin
axis_tvalid_reg <= 1'b0;
axis_tready_reg <= 1'b0;
end
end
end
if (LENGTH > 0) begin : fifo
assign axis_pipe[0].tdata = s_axis.tdata;
assign axis_pipe[0].tkeep = s_axis.tkeep;
assign axis_pipe[0].tstrb = s_axis.tstrb;
assign axis_pipe[0].tvalid = s_axis.tvalid & s_axis.tready;
assign axis_pipe[0].tlast = s_axis.tlast;
assign axis_pipe[0].tid = s_axis.tid;
assign axis_pipe[0].tdest = s_axis.tdest;
assign axis_pipe[0].tuser = s_axis.tuser;
assign s_axis.tready = axis_pipe[0].tready;
wire [DATA_W-1:0] m_axis_tdata_int = axis_pipe[LENGTH].tdata;
wire [KEEP_W-1:0] m_axis_tkeep_int = axis_pipe[LENGTH].tkeep;
wire [KEEP_W-1:0] m_axis_tstrb_int = axis_pipe[LENGTH].tstrb;
wire m_axis_tvalid_int = axis_pipe[LENGTH].tvalid;
wire m_axis_tready_int;
wire m_axis_tlast_int = axis_pipe[LENGTH].tlast;
wire [ID_W-1:0] m_axis_tid_int = axis_pipe[LENGTH].tid;
wire [DEST_W-1:0] m_axis_tdest_int = axis_pipe[LENGTH].tdest;
wire [USER_W-1:0] m_axis_tuser_int = axis_pipe[LENGTH].tuser;
assign axis_pipe[LENGTH].tready = m_axis_tready_int;
// output datapath logic
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
logic m_axis_tvalid_reg = 1'b0;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
logic [FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = 0;
logic [FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = 0;
logic out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {FIFO_AW{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [DATA_W-1:0] out_fifo_tdata[2**FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [KEEP_W-1:0] out_fifo_tkeep[2**FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [KEEP_W-1:0] out_fifo_tstrb[2**FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic out_fifo_tlast[2**FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [ID_W-1:0] out_fifo_tid[2**FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [DEST_W-1:0] out_fifo_tdest[2**FIFO_AW];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [USER_W-1:0] out_fifo_tuser[2**FIFO_AW];
assign m_axis_tready_int = !out_fifo_half_full_reg;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
assign m_axis.tvalid = m_axis_tvalid_reg;
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
always_ff @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis.tready;
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
if (!out_fifo_full && m_axis_tvalid_int) begin
out_fifo_tdata[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tdata_int;
out_fifo_tkeep[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tkeep_int;
out_fifo_tstrb[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tstrb_int;
out_fifo_tlast[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tlast_int;
out_fifo_tid[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tid_int;
out_fifo_tdest[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tdest_int;
out_fifo_tuser[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tuser_int;
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis.tready)) begin
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
m_axis_tstrb_reg <= out_fifo_tstrb[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
m_axis_tvalid_reg <= 1'b1;
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (rst) begin
out_fifo_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
m_axis_tvalid_reg <= 1'b0;
end
end
end else begin
// bypass
assign m_axis.tdata = s_axis.tdata;
assign m_axis.tkeep = KEEP_EN ? s_axis.tkeep : '1;
assign m_axis.tstrb = STRB_EN ? s_axis.tstrb : m_axis.tkeep;
assign m_axis.tvalid = s_axis.tvalid;
assign m_axis.tlast = LAST_EN ? s_axis.tlast : 1'b1;
assign m_axis.tid = ID_EN ? s_axis.tid : '0;
assign m_axis.tdest = DEST_EN ? s_axis.tdest : '0;
assign m_axis.tuser = USER_EN ? s_axis.tuser : '0;
assign s_axis.tready = m_axis.tready;
end
endmodule
`resetall

3
src/axis/rtl/taxi_axis_pipeline_register.f Normal file
View File

@@ -0,0 +1,3 @@
taxi_axis_pipeline_register.sv
taxi_axis_register.sv
taxi_axis_if.sv

119
src/axis/rtl/taxi_axis_pipeline_register.sv Normal file
View File

@@ -0,0 +1,119 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream pipeline register
*/
module taxi_axis_pipeline_register #
(
// Register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter REG_TYPE = 2,
// Number of registers in pipeline
parameter LENGTH = 2
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis
);
// extract parameters
localparam DATA_W = s_axis.DATA_W;
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
localparam KEEP_W = s_axis.KEEP_W;
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
localparam ID_W = s_axis.ID_W;
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
localparam DEST_W = s_axis.DEST_W;
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
localparam USER_W = s_axis.USER_W;
// check configuration
if (m_axis.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) axis_pipe[LENGTH+1]();
assign axis_pipe[0].tdata = s_axis.tdata;
assign axis_pipe[0].tkeep = s_axis.tkeep;
assign axis_pipe[0].tstrb = s_axis.tstrb;
assign axis_pipe[0].tvalid = s_axis.tvalid;
assign s_axis.tready = axis_pipe[0].tready;
assign axis_pipe[0].tlast = s_axis.tlast;
assign axis_pipe[0].tid = s_axis.tid;
assign axis_pipe[0].tdest = s_axis.tdest;
assign axis_pipe[0].tuser = s_axis.tuser;
assign m_axis.tdata = axis_pipe[LENGTH].tdata;
assign m_axis.tkeep = axis_pipe[LENGTH].tkeep;
assign m_axis.tstrb = axis_pipe[LENGTH].tstrb;
assign m_axis.tvalid = axis_pipe[LENGTH].tvalid;
assign axis_pipe[LENGTH].tready = m_axis.tready;
assign m_axis.tlast = axis_pipe[LENGTH].tlast;
assign m_axis.tid = axis_pipe[LENGTH].tid;
assign m_axis.tdest = axis_pipe[LENGTH].tdest;
assign m_axis.tuser = axis_pipe[LENGTH].tuser;
for (genvar i = 0; i < LENGTH; i = i + 1) begin : pipe_reg
taxi_axis_register #(
.REG_TYPE(REG_TYPE)
)
reg_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(axis_pipe[i]),
/*
* AXI4-Stream output (source)
*/
.m_axis(axis_pipe[i+1])
);
end
endmodule
`resetall

256
src/axis/rtl/taxi_axis_register.sv Normal file
View File

@@ -0,0 +1,256 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream register
*/
module taxi_axis_register #
(
// Register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter REG_TYPE = 2
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis
);
// extract parameters
localparam DATA_W = s_axis.DATA_W;
localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
localparam KEEP_W = s_axis.KEEP_W;
localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
localparam ID_W = s_axis.ID_W;
localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
localparam DEST_W = s_axis.DEST_W;
localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
localparam USER_W = s_axis.USER_W;
// check configuration
if (m_axis.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
if (REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
logic s_axis_tready_reg = 1'b0;
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
logic temp_m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
// datapath control
logic store_axis_input_to_output;
logic store_axis_input_to_temp;
logic store_axis_temp_to_output;
assign s_axis.tready = s_axis_tready_reg;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : s_axis.tkeep;
assign m_axis.tvalid = m_axis_tvalid_reg;
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axis_tready_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis.tvalid));
always_comb begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_input_to_output = 1'b0;
store_axis_input_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (s_axis_tready_reg) begin
// input is ready
if (m_axis.tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = s_axis.tvalid;
store_axis_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = s_axis.tvalid;
store_axis_input_to_temp = 1'b1;
end
end else if (m_axis.tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
s_axis_tready_reg <= s_axis_tready_early;
m_axis_tvalid_reg <= m_axis_tvalid_next;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
// datapath
if (store_axis_input_to_output) begin
m_axis_tdata_reg <= s_axis.tdata;
m_axis_tkeep_reg <= s_axis.tkeep;
m_axis_tstrb_reg <= s_axis.tstrb;
m_axis_tlast_reg <= s_axis.tlast;
m_axis_tid_reg <= s_axis.tid;
m_axis_tdest_reg <= s_axis.tdest;
m_axis_tuser_reg <= s_axis.tuser;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_input_to_temp) begin
temp_m_axis_tdata_reg <= s_axis.tdata;
temp_m_axis_tkeep_reg <= s_axis.tkeep;
temp_m_axis_tstrb_reg <= s_axis.tstrb;
temp_m_axis_tlast_reg <= s_axis.tlast;
temp_m_axis_tid_reg <= s_axis.tid;
temp_m_axis_tdest_reg <= s_axis.tdest;
temp_m_axis_tuser_reg <= s_axis.tuser;
end
if (rst) begin
s_axis_tready_reg <= 1'b0;
m_axis_tvalid_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end
end
end else if (REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
logic s_axis_tready_reg = 1'b0;
logic [DATA_W-1:0] m_axis_tdata_reg = '0;
logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
logic m_axis_tlast_reg = 1'b0;
logic [ID_W-1:0] m_axis_tid_reg = '0;
logic [DEST_W-1:0] m_axis_tdest_reg = '0;
logic [USER_W-1:0] m_axis_tuser_reg = '0;
// datapath control
logic store_axis_input_to_output;
assign s_axis.tready = s_axis_tready_reg;
assign m_axis.tdata = m_axis_tdata_reg;
assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
assign m_axis.tstrb = STRB_EN ? s_axis.tstrb : s_axis.tkeep;
assign m_axis.tvalid = m_axis_tvalid_reg;
assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
// enable ready input next cycle if output buffer will be empty
wire s_axis_tready_early = !m_axis_tvalid_next;
always_comb begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
store_axis_input_to_output = 1'b0;
if (s_axis_tready_reg) begin
m_axis_tvalid_next = s_axis.tvalid;
store_axis_input_to_output = 1'b1;
end else if (m_axis.tready) begin
m_axis_tvalid_next = 1'b0;
end
end
always_ff @(posedge clk) begin
s_axis_tready_reg <= s_axis_tready_early;
m_axis_tvalid_reg <= m_axis_tvalid_next;
// datapath
if (store_axis_input_to_output) begin
m_axis_tdata_reg <= s_axis.tdata;
m_axis_tkeep_reg <= s_axis.tkeep;
m_axis_tstrb_reg <= s_axis.tstrb;
m_axis_tlast_reg <= s_axis.tlast;
m_axis_tid_reg <= s_axis.tid;
m_axis_tdest_reg <= s_axis.tdest;
m_axis_tuser_reg <= s_axis.tuser;
end
if (rst) begin
s_axis_tready_reg <= 1'b0;
m_axis_tvalid_reg <= 1'b0;
end
end
end else begin
// bypass
assign m_axis.tdata = s_axis.tdata;
assign m_axis.tkeep = KEEP_EN ? s_axis.tkeep : '1;
assign m_axis.tstrb = STRB_EN ? s_axis.tstrb : s_axis.tkeep;
assign m_axis.tvalid = s_axis.tvalid;
assign m_axis.tlast = LAST_EN ? s_axis.tlast : 1'b1;
assign m_axis.tid = ID_EN ? s_axis.tid : '0;
assign m_axis.tdest = DEST_EN ? s_axis.tdest : '0;
assign m_axis.tuser = USER_EN ? s_axis.tuser : '0;
assign s_axis.tready = m_axis.tready;
end
endmodule
`resetall

80
src/axis/syn/vivado/taxi_axis_async_fifo.tcl Normal file
View File

@@ -0,0 +1,80 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2019-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# AXI stream asynchronous FIFO timing constraints
foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_axis_async_fifo || REF_NAME == taxi_axis_async_fifo)}] {
puts "Inserting timing constraints for taxi_axis_async_fifo instance $fifo_inst"
# get clock periods
set write_clk [get_clocks -of_objects [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/rd_ptr_gray_sync1_reg_reg[*]"]]
set read_clk [get_clocks -of_objects [get_cells -quiet "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"]]
set write_clk_period [if {[llength $write_clk]} {get_property -min PERIOD $write_clk} {expr 1.0}]
set read_clk_period [if {[llength $read_clk]} {get_property -min PERIOD $read_clk} {expr 1.0}]
set min_clk_period [expr min($write_clk_period, $read_clk_period)]
# pointer synchronization
set sync_ffs [get_cells -quiet -hier -regexp ".*/rd_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"]
if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs
set_max_delay -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/rd_ptr_gray_sync1_reg_reg[*]"] -datapath_only $read_clk_period
set_bus_skew -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/rd_ptr_gray_sync1_reg_reg[*]"] $write_clk_period
}
set sync_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"]
if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs
set_max_delay -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] -datapath_only $write_clk_period
set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_gray_sync1_reg_reg[*]"] $read_clk_period
}
set sync_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_commit_sync_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"]
if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs
set_max_delay -from [get_cells -quiet "$fifo_inst/wr_ptr_sync_commit_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_commit_sync_reg_reg[*]"] -datapath_only $write_clk_period
set_bus_skew -from [get_cells -quiet "$fifo_inst/wr_ptr_sync_commit_reg_reg[*]"] -to [get_cells "$fifo_inst/wr_ptr_commit_sync_reg_reg[*]"] $read_clk_period
}
# output register (needed for distributed RAM sync write/async read)
set output_reg_ffs [get_cells -quiet "$fifo_inst/mem_rd_data_pipe_reg_reg[0][*]"]
if {[llength $output_reg_ffs]} {
if {[llength $write_clk]} {
set_false_path -from $write_clk -to $output_reg_ffs
}
}
# frame FIFO pointer update synchronization
set update_ffs [get_cells -quiet -hier -regexp ".*/wr_ptr_update(_ack)?_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
if {[llength $update_ffs]} {
set_property ASYNC_REG TRUE $update_ffs
set_max_delay -from [get_cells "$fifo_inst/wr_ptr_update_reg_reg"] -to [get_cells "$fifo_inst/wr_ptr_update_sync1_reg_reg"] -datapath_only $write_clk_period
set_max_delay -from [get_cells "$fifo_inst/wr_ptr_update_sync3_reg_reg"] -to [get_cells "$fifo_inst/wr_ptr_update_ack_sync1_reg_reg"] -datapath_only $read_clk_period
}
# status synchronization
foreach i {overflow bad_frame good_frame} {
set status_sync_regs [get_cells -quiet -hier -regexp ".*/${i}_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"]
if {[llength $status_sync_regs]} {
set_property ASYNC_REG TRUE $status_sync_regs
set_max_delay -from [get_cells "$fifo_inst/${i}_sync1_reg_reg"] -to [get_cells "$fifo_inst/${i}_sync2_reg_reg"] -datapath_only $read_clk_period
}
}
}

64
src/axis/tb/taxi_axis_adapter/Makefile Normal file
View File

@@ -0,0 +1,64 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_adapter
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_S_DATA_W := 8
export PARAM_S_KEEP_EN := $(shell expr $(PARAM_S_DATA_W) \> 8 )
export PARAM_S_KEEP_W := $(shell expr \( $(PARAM_S_DATA_W) + 7 \) / 8 )
export PARAM_S_STRB_EN := 0
export PARAM_M_DATA_W := 8
export PARAM_M_KEEP_EN := $(shell expr $(PARAM_M_DATA_W) \> 8 )
export PARAM_M_KEEP_W := $(shell expr \( $(PARAM_M_DATA_W) + 7 \) / 8 )
export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

266
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.py Normal file
View File

@@ -0,0 +1,266 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
# set tkeep to all zeros when disabled to verify correct handling
if not int(dut.S_KEEP_EN.value):
test_frame.tkeep = [0]*len(test_data)
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_tuser_assert(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source.send(test_frame)
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for k in range(128):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = max(len(cocotb.top.s_axis.tdata), len(cocotb.top.m_axis.tdata))
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [run_test_tuser_assert]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("m_data_width", [8, 16, 32])
@pytest.mark.parametrize("s_data_width", [8, 16, 32])
def test_taxi_axis_register(request, s_data_width, m_data_width):
dut = "taxi_axis_adapter"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(rtl_dir, "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['S_DATA_W'] = s_data_width
parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
parameters['S_STRB_EN'] = 0
parameters['M_DATA_W'] = m_data_width
parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
parameters['M_STRB_EN'] = parameters['S_STRB_EN']
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

88
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv Normal file
View File

@@ -0,0 +1,88 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream FIFO testbench
*/
module test_taxi_axis_adapter #
(
/* verilator lint_off WIDTHTRUNC */
parameter S_DATA_W = 8,
parameter logic S_KEEP_EN = (S_DATA_W>8),
parameter S_KEEP_W = ((S_DATA_W+7)/8),
parameter logic S_STRB_EN = 0,
parameter M_DATA_W = 8,
parameter logic M_KEEP_EN = (M_DATA_W>8),
parameter M_KEEP_W = ((M_DATA_W+7)/8),
parameter logic M_STRB_EN = 0,
parameter logic ID_EN = 0,
parameter ID_W = 8,
parameter logic DEST_EN = 0,
parameter DEST_W = 8,
parameter logic USER_EN = 1,
parameter USER_W = 1
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(S_DATA_W),
.KEEP_EN(S_KEEP_EN),
.KEEP_W(S_KEEP_W),
.STRB_EN(S_STRB_EN),
.LAST_EN(1'b1),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis();
taxi_axis_if #(
.DATA_W(M_DATA_W),
.KEEP_EN(M_KEEP_EN),
.KEEP_W(M_KEEP_W),
.STRB_EN(M_STRB_EN),
.LAST_EN(1'b1),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) m_axis();
taxi_axis_adapter
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

65
src/axis/tb/taxi_axis_arb_mux/Makefile Normal file
View File

@@ -0,0 +1,65 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_arb_mux
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_S_COUNT := 4
export PARAM_DATA_W := 8
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
export PARAM_STRB_EN := 0
export PARAM_LAST_EN := 1
export PARAM_ID_EN := 1
export PARAM_S_ID_W := 8
export PARAM_M_ID_W := $(shell python -c "print($(PARAM_S_ID_W) + ($(PARAM_S_COUNT)-1).bit_length())")
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
export PARAM_UPDATE_TID := 1
export PARAM_ARB_ROUND_ROBIN := 0
export PARAM_ARB_LSB_HIGH_PRIO := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

365
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py Normal file
View File

@@ -0,0 +1,365 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Event
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.s_axis]
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
def set_idle_generator(self, generator=None):
if generator:
for source in self.source:
source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, port=0):
tb = TB(dut)
id_width = len(tb.source[0].bus.tid)
id_count = 2**id_width
id_mask = id_count-1
src_width = (len(tb.source)-1).bit_length()
src_mask = 2**src_width-1 if src_width else 0
src_shift = id_width-src_width
max_count = 2**src_shift
count_mask = max_count-1
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id | (port << src_shift)
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source[port].send(test_frame)
cur_id = (cur_id + 1) % max_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert (rx_frame.tid & id_mask) == test_frame.tid
assert ((rx_frame.tid >> src_shift) & src_mask) == port
assert (rx_frame.tid >> id_width) == port
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_tuser_assert(dut, port=0):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source[port].send(test_frame)
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_arb_test(dut):
tb = TB(dut)
byte_lanes = tb.source[0].byte_lanes
id_width = len(tb.source[0].bus.tid)
id_count = 2**id_width
id_mask = id_count-1
src_width = (len(tb.source)-1).bit_length()
src_mask = 2**src_width-1 if src_width else 0
src_shift = id_width-src_width
max_count = 2**src_shift
count_mask = max_count-1
cur_id = 1
await tb.reset()
test_frames = []
length = byte_lanes*16
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
for k in range(5):
test_frame = AxiStreamFrame(test_data, tx_complete=Event())
src_ind = 0
if k == 0:
src_ind = 0
elif k == 4:
await test_frames[1].tx_complete.wait()
for j in range(8):
await RisingEdge(dut.clk)
src_ind = 0
else:
src_ind = 1
test_frame.tid = cur_id | (src_ind << src_shift)
test_frame.tdest = 0
test_frames.append(test_frame)
await tb.source[src_ind].send(test_frame)
cur_id = (cur_id + 1) % max_count
for k in [0, 1, 2, 4, 3]:
test_frame = test_frames[k]
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert (rx_frame.tid & id_mask) == test_frame.tid
assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width)
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.source[0].byte_lanes
id_width = len(tb.source[0].bus.tid)
id_count = 2**id_width
id_mask = id_count-1
src_width = (len(tb.source)-1).bit_length()
src_mask = 2**src_width-1 if src_width else 0
src_shift = id_width-src_width
max_count = 2**src_shift
count_mask = max_count-1
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = [list() for x in tb.source]
for p in range(len(tb.source)):
for k in range(128):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id | (p << src_shift)
test_frame.tdest = cur_id
test_frames[p].append(test_frame)
await tb.source[p].send(test_frame)
cur_id = (cur_id + 1) % max_count
while any(test_frames):
rx_frame = await tb.sink.recv()
test_frame = None
for lst in test_frames:
if lst and lst[0].tid == (rx_frame.tid & id_mask):
test_frame = lst.pop(0)
break
assert test_frame is not None
assert rx_frame.tdata == test_frame.tdata
assert (rx_frame.tid & id_mask) == test_frame.tid
assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width)
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = len(cocotb.top.m_axis.tdata)
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
ports = len(cocotb.top.s_axis)
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.add_option("port", list(range(ports)))
factory.generate_tests()
for test in [run_test_tuser_assert]:
factory = TestFactory(test)
factory.add_option("port", list(range(ports)))
factory.generate_tests()
if ports > 1:
factory = TestFactory(run_arb_test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("round_robin", [0, 1])
@pytest.mark.parametrize("data_w", [8, 16, 32])
@pytest.mark.parametrize("s_count", [1, 4])
def test_taxi_axis_arb_mux(request, s_count, data_w, round_robin):
dut = "taxi_axis_arb_mux"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['S_COUNT'] = s_count
parameters['DATA_W'] = data_w
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
parameters['STRB_EN'] = 0
parameters['LAST_EN'] = 1
parameters['ID_EN'] = 1
parameters['S_ID_W'] = 8
parameters['M_ID_W'] = parameters['S_ID_W'] + (s_count-1).bit_length()
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
parameters['UPDATE_TID'] = 1
parameters['ARB_ROUND_ROBIN'] = round_robin
parameters['ARB_LSB_HIGH_PRIO'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

95
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv Normal file
View File

@@ -0,0 +1,95 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream arbitrated multiplexer testbench
*/
module test_taxi_axis_arb_mux #
(
/* verilator lint_off WIDTHTRUNC */
parameter S_COUNT = 4,
parameter DATA_W = 8,
parameter logic KEEP_EN = (DATA_W>8),
parameter KEEP_W = ((DATA_W+7)/8),
parameter logic STRB_EN = 1'b0,
parameter logic LAST_EN = 1'b1,
parameter logic ID_EN = 1'b0,
parameter S_ID_W = 8,
parameter M_ID_W = S_ID_W+$clog2(S_COUNT),
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1,
parameter logic UPDATE_TID = 1'b0,
parameter logic ARB_ROUND_ROBIN = 1'b0,
parameter logic ARB_LSB_HIGH_PRIO = 1'b1
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(S_ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis[S_COUNT]();
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(M_ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) m_axis();
taxi_axis_arb_mux #(
.S_COUNT(S_COUNT),
.UPDATE_TID(UPDATE_TID),
.ARB_ROUND_ROBIN(ARB_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIO(ARB_LSB_HIGH_PRIO)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

72
src/axis/tb/taxi_axis_async_fifo/Makefile Normal file
View File

@@ -0,0 +1,72 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_async_fifo
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 8
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
export PARAM_STRB_EN := 0
export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_W) )))
export PARAM_LAST_EN := 1
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_EN := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
export PARAM_MARK_WHEN_FULL := 0
export PARAM_PAUSE_EN := 1
export PARAM_FRAME_PAUSE := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

735
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py Normal file
View File

@@ -0,0 +1,735 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
s_clk = int(os.getenv("S_CLK_PERIOD", "10"))
m_clk = int(os.getenv("M_CLK_PERIOD", "11"))
cocotb.start_soon(Clock(dut.s_clk, s_clk, units="ns").start())
cocotb.start_soon(Clock(dut.m_clk, m_clk, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.s_clk, dut.s_rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.m_clk, dut.m_rst)
dut.s_pause_req.setimmediatevalue(0)
dut.m_pause_req.setimmediatevalue(0)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.m_rst.setimmediatevalue(0)
self.dut.s_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.m_rst.value = 1
self.dut.s_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.m_rst.value = 0
self.dut.s_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.s_clk)
async def reset_source(self):
self.dut.s_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.s_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.s_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.s_clk)
async def reset_sink(self):
self.dut.m_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.m_clk)
self.dut.m_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.m_clk)
self.dut.m_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.m_clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_tuser_assert(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source.send(test_frame)
if int(dut.DROP_BAD_FRAME.value):
for k in range(64):
await RisingEdge(dut.s_clk)
else:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
tb.sink.pause = False
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
await tb.reset()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause_source_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 512))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(1024):
await RisingEdge(dut.s_clk)
await tb.reset_source()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.s_clk)
rx_frame = await tb.sink.recv()
assert rx_frame.tuser
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause_sink_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
await tb.reset_sink()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_in_source_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_source()
for k in range(64):
await RisingEdge(dut.s_clk)
if int(dut.FRAME_FIFO.value):
assert tb.sink.empty()
else:
rx_frame = await tb.sink.recv()
assert rx_frame.tuser
assert tb.sink.empty()
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_in_sink_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_sink()
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_out_source_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
await RisingEdge(dut.m_axis.tvalid)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_source()
for k in range(64):
await RisingEdge(dut.s_clk)
rx_frame = await tb.sink.recv()
assert rx_frame.tuser
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_out_sink_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
await RisingEdge(dut.m_axis.tvalid)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_sink()
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_pause(dut):
tb = TB(dut)
byte_lanes = tb.source.byte_lanes
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
test_frame = AxiStreamFrame(test_data)
for k in range(16):
await tb.source.send(test_frame)
for k in range(60):
await RisingEdge(dut.s_clk)
dut.m_pause_req.value = 1
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
dut.m_pause_req.value = 0
for k in range(60):
await RisingEdge(dut.s_clk)
dut.s_pause_req.value = 1
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
dut.s_pause_req.value = 0
for k in range(16):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_overflow(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = tb.source.byte_lanes
await tb.reset()
tb.sink.pause = True
size = (16*byte_lanes)
count = depth*2 // size
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
test_frame = AxiStreamFrame(test_data)
for k in range(count):
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.s_clk)
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
assert tb.source.idle()
else:
assert not tb.source.idle()
tb.sink.pause = False
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.s_clk)
rx_count = 0
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
continue
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
rx_count += 1
assert rx_count < count
else:
for k in range(count):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_oversize(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = tb.source.byte_lanes
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.s_clk)
tb.sink.pause = False
if int(dut.DROP_OVERSIZE_FRAME.value):
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.s_clk)
else:
rx_frame = await tb.sink.recv()
if int(dut.MARK_WHEN_FULL.value):
assert rx_frame.tuser
else:
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.source.byte_lanes
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for k in range(512):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
cycles = 0
while cycles < 100:
cycles += 1
if not tb.source.idle() or int(dut.s_axis.tvalid.value) or int(dut.m_axis.tvalid.value) or int(dut.m_status_depth.value):
cycles = 0
await RisingEdge(dut.m_clk)
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
continue
assert not rx_frame.tuser
while True:
test_frame = test_frames.pop(0)
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
break
assert len(test_frames) < 512
else:
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = len(cocotb.top.m_axis.tdata)
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [
run_test_tuser_assert,
run_test_init_sink_pause,
run_test_init_sink_pause_reset,
run_test_init_sink_pause_source_reset,
run_test_init_sink_pause_sink_reset,
run_test_shift_in_source_reset,
run_test_shift_in_sink_reset,
run_test_shift_out_source_reset,
run_test_shift_out_sink_reset,
run_test_pause,
run_test_overflow,
run_test_oversize
]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize(("s_clk", "m_clk"), [(10, 10), (10, 11), (11, 10)])
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
"drop_when_full", "mark_when_full"),
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
@pytest.mark.parametrize(("ram_pipeline", "output_fifo"),
[(0, 0), (1, 0), (4, 0), (0, 1), (1, 1), (4, 1)])
@pytest.mark.parametrize("data_w", [8, 16, 32, 64])
def test_taxi_axis_async_fifo(request, data_w, ram_pipeline, output_fifo,
frame_fifo, drop_oversize_frame, drop_bad_frame,
drop_when_full, mark_when_full, s_clk, m_clk):
dut = "taxi_axis_async_fifo"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DATA_W'] = data_w
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
parameters['STRB_EN'] = 0
parameters['DEPTH'] = 1024 * parameters['KEEP_W']
parameters['LAST_EN'] = 1
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
parameters['RAM_PIPELINE'] = ram_pipeline
parameters['OUTPUT_FIFO_EN'] = output_fifo
parameters['FRAME_FIFO'] = frame_fifo
parameters['USER_BAD_FRAME_VALUE'] = 1
parameters['USER_BAD_FRAME_MASK'] = 1
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
parameters['DROP_BAD_FRAME'] = drop_bad_frame
parameters['DROP_WHEN_FULL'] = drop_when_full
parameters['MARK_WHEN_FULL'] = mark_when_full
parameters['PAUSE_EN'] = 1
parameters['FRAME_PAUSE'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
extra_env['S_CLK_PERIOD'] = str(s_clk)
extra_env['M_CLK_PERIOD'] = str(m_clk)
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

138
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv Normal file
View File

@@ -0,0 +1,138 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream asynchronous FIFO testbench
*/
module test_taxi_axis_async_fifo #
(
/* verilator lint_off WIDTHTRUNC */
parameter DEPTH = 4096,
parameter DATA_W = 8,
parameter logic KEEP_EN = (DATA_W>8),
parameter KEEP_W = ((DATA_W+7)/8),
parameter logic STRB_EN = 1'b0,
parameter logic LAST_EN = 1'b1,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1,
parameter RAM_PIPELINE = 1,
parameter logic OUTPUT_FIFO_EN = 1'b0,
parameter logic FRAME_FIFO = 1'b0,
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
parameter logic DROP_BAD_FRAME = 1'b0,
parameter logic DROP_WHEN_FULL = 1'b0,
parameter logic MARK_WHEN_FULL = 1'b0,
parameter logic PAUSE_EN = 1'b0,
parameter logic FRAME_PAUSE = FRAME_FIFO
/* verilator lint_on WIDTHTRUNC */
)
();
logic s_clk;
logic s_rst;
logic m_clk;
logic m_rst;
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis(), m_axis();
logic s_pause_req;
logic s_pause_ack;
logic m_pause_req;
logic m_pause_ack;
logic [$clog2(DEPTH):0] s_status_depth;
logic [$clog2(DEPTH):0] s_status_depth_commit;
logic s_status_overflow;
logic s_status_bad_frame;
logic s_status_good_frame;
logic [$clog2(DEPTH):0] m_status_depth;
logic [$clog2(DEPTH):0] m_status_depth_commit;
logic m_status_overflow;
logic m_status_bad_frame;
logic m_status_good_frame;
taxi_axis_async_fifo #(
.DEPTH(DEPTH),
.RAM_PIPELINE(RAM_PIPELINE),
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.MARK_WHEN_FULL(MARK_WHEN_FULL),
.PAUSE_EN(PAUSE_EN),
.FRAME_PAUSE(FRAME_PAUSE)
)
uut (
/*
* AXI4-Stream input (sink)
*/
.s_clk(s_clk),
.s_rst(s_rst),
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_clk(m_clk),
.m_rst(m_rst),
.m_axis(m_axis),
/*
* Pause
*/
.s_pause_req(s_pause_req),
.s_pause_ack(s_pause_ack),
.m_pause_req(m_pause_req),
.m_pause_ack(m_pause_ack),
/*
* Status
*/
.s_status_depth(s_status_depth),
.s_status_depth_commit(s_status_depth_commit),
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_depth(m_status_depth),
.m_status_depth_commit(m_status_depth_commit),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
endmodule
`resetall

75
src/axis/tb/taxi_axis_async_fifo_adapter/Makefile Normal file
View File

@@ -0,0 +1,75 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_async_fifo_adapter
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_S_DATA_W := 8
export PARAM_S_KEEP_EN := $(shell echo $$(( $(PARAM_S_DATA_W) > 8 )))
export PARAM_S_KEEP_W := $(shell echo $$(( ( $(PARAM_S_DATA_W) + 7 ) / 8 )))
export PARAM_S_STRB_EN := 0
export PARAM_M_DATA_W := 8
export PARAM_M_KEEP_EN := $(shell echo $$(( $(PARAM_M_DATA_W) > 8 )))
export PARAM_M_KEEP_W := $(shell echo $$(( ( $(PARAM_M_DATA_W) + 7 ) / 8 )))
export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_W) > $(PARAM_M_KEEP_W) ? $(PARAM_S_KEEP_W) : $(PARAM_M_KEEP_W)) )))
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_EN := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
export PARAM_MARK_WHEN_FULL := 0
export PARAM_PAUSE_EN := 1
export PARAM_FRAME_PAUSE := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

731
src/axis/tb/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.py Normal file
View File

@@ -0,0 +1,731 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
s_clk = int(os.getenv("S_CLK_PERIOD", "10"))
m_clk = int(os.getenv("M_CLK_PERIOD", "11"))
cocotb.start_soon(Clock(dut.s_clk, s_clk, units="ns").start())
cocotb.start_soon(Clock(dut.m_clk, m_clk, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.s_clk, dut.s_rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.m_clk, dut.m_rst)
dut.s_pause_req.setimmediatevalue(0)
dut.m_pause_req.setimmediatevalue(0)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.m_rst.setimmediatevalue(0)
self.dut.s_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.m_rst.value = 1
self.dut.s_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.m_rst.value = 0
self.dut.s_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.s_clk)
async def reset_source(self):
self.dut.s_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.s_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.s_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.s_clk)
async def reset_sink(self):
self.dut.m_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.m_clk)
self.dut.m_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.m_clk)
self.dut.m_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.m_clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_tuser_assert(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source.send(test_frame)
if int(dut.DROP_BAD_FRAME.value):
for k in range(64):
await RisingEdge(dut.s_clk)
else:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
tb.sink.pause = False
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
await tb.reset()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause_source_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
await tb.reset_source()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.s_clk)
rx_frame = await tb.sink.recv()
assert rx_frame.tuser
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause_sink_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
await tb.reset_sink()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_in_source_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_source()
for k in range(64):
await RisingEdge(dut.s_clk)
if int(dut.FRAME_FIFO.value):
assert tb.sink.empty()
else:
rx_frame = await tb.sink.recv()
assert rx_frame.tuser
assert tb.sink.empty()
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_in_sink_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_sink()
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_out_source_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
await RisingEdge(dut.m_axis.tvalid)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_source()
for k in range(64):
await RisingEdge(dut.s_clk)
rx_frame = await tb.sink.recv()
assert rx_frame.tuser
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_out_sink_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
await RisingEdge(dut.m_axis.tvalid)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_sink()
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_pause(dut):
tb = TB(dut)
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
test_frame = AxiStreamFrame(test_data)
for k in range(16):
await tb.source.send(test_frame)
for k in range(60):
await RisingEdge(dut.s_clk)
dut.m_pause_req.value = 1
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
dut.m_pause_req.value = 0
for k in range(60):
await RisingEdge(dut.s_clk)
dut.s_pause_req.value = 1
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
dut.s_pause_req.value = 0
for k in range(16):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_overflow(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
await tb.reset()
tb.sink.pause = True
size = (16*byte_lanes)
count = depth*2 // size
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
test_frame = AxiStreamFrame(test_data)
for k in range(count):
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.s_clk)
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
assert tb.source.idle()
else:
assert not tb.source.idle()
tb.sink.pause = False
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.s_clk)
rx_count = 0
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
continue
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
rx_count += 1
assert rx_count < count
else:
for k in range(count):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_oversize(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.s_clk)
tb.sink.pause = False
if int(dut.DROP_OVERSIZE_FRAME.value):
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.s_clk)
else:
rx_frame = await tb.sink.recv()
if int(dut.MARK_WHEN_FULL.value):
assert rx_frame.tuser
else:
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for k in range(512):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
cycles = 0
while cycles < 100:
cycles += 1
if not tb.source.idle() or dut.s_axis.tvalid.value.integer or dut.m_axis.tvalid.value.integer or dut.m_status_depth.value.integer:
cycles = 0
await RisingEdge(dut.m_clk)
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
continue
assert not rx_frame.tuser
while True:
test_frame = test_frames.pop(0)
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
break
assert len(test_frames) < 512
else:
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = max(len(cocotb.top.m_axis.tdata), len(cocotb.top.s_axis.tdata))
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [
run_test_tuser_assert,
run_test_init_sink_pause,
run_test_init_sink_pause_reset,
run_test_init_sink_pause_source_reset,
run_test_init_sink_pause_sink_reset,
run_test_shift_in_source_reset,
run_test_shift_in_sink_reset,
run_test_shift_out_source_reset,
run_test_shift_out_sink_reset,
run_test_pause,
run_test_overflow,
run_test_oversize
]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
"drop_when_full", "mark_when_full"),
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
@pytest.mark.parametrize("m_data_w", [8, 16, 32])
@pytest.mark.parametrize("s_data_w", [8, 16, 32])
def test_taxi_axis_async_fifo_adapter(request, s_data_w, m_data_w,
frame_fifo, drop_oversize_frame, drop_bad_frame,
drop_when_full, mark_when_full):
dut = "taxi_axis_async_fifo_adapter"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['S_DATA_W'] = s_data_w
parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
parameters['M_DATA_W'] = m_data_w
parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
parameters['DEPTH'] = 1024 * max(parameters['S_KEEP_W'], parameters['M_KEEP_W'])
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
parameters['RAM_PIPELINE'] = 1
parameters['OUTPUT_FIFO_EN'] = 0
parameters['FRAME_FIFO'] = frame_fifo
parameters['USER_BAD_FRAME_VALUE'] = 1
parameters['USER_BAD_FRAME_MASK'] = 1
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
parameters['DROP_BAD_FRAME'] = drop_bad_frame
parameters['DROP_WHEN_FULL'] = drop_when_full
parameters['MARK_WHEN_FULL'] = mark_when_full
parameters['PAUSE_EN'] = 1
parameters['FRAME_PAUSE'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

153
src/axis/tb/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.sv Normal file
View File

@@ -0,0 +1,153 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream asynchronous FIFO with width converter testbench
*/
module test_taxi_axis_async_fifo_adapter #
(
/* verilator lint_off WIDTHTRUNC */
parameter DEPTH = 4096,
parameter S_DATA_W = 8,
parameter logic S_KEEP_EN = (S_DATA_W>8),
parameter S_KEEP_W = ((S_DATA_W+7)/8),
parameter logic S_STRB_EN = 0,
parameter M_DATA_W = 8,
parameter logic M_KEEP_EN = (M_DATA_W>8),
parameter M_KEEP_W = ((M_DATA_W+7)/8),
parameter logic M_STRB_EN = 0,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1,
parameter RAM_PIPELINE = 1,
parameter logic OUTPUT_FIFO_EN = 1'b0,
parameter logic FRAME_FIFO = 1'b0,
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
parameter logic DROP_BAD_FRAME = 1'b0,
parameter logic DROP_WHEN_FULL = 1'b0,
parameter logic MARK_WHEN_FULL = 1'b0,
parameter logic PAUSE_EN = 1'b0,
parameter logic FRAME_PAUSE = FRAME_FIFO
/* verilator lint_on WIDTHTRUNC */
)
();
logic s_clk;
logic s_rst;
taxi_axis_if #(
.DATA_W(S_DATA_W),
.KEEP_EN(S_KEEP_EN),
.KEEP_W(S_KEEP_W),
.STRB_EN(S_STRB_EN),
.LAST_EN(1'b1),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis();
logic m_clk;
logic m_rst;
taxi_axis_if #(
.DATA_W(M_DATA_W),
.KEEP_EN(M_KEEP_EN),
.KEEP_W(M_KEEP_W),
.STRB_EN(M_STRB_EN),
.LAST_EN(1'b1),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) m_axis();
logic s_pause_req;
logic s_pause_ack;
logic m_pause_req;
logic m_pause_ack;
logic [$clog2(DEPTH):0] s_status_depth;
logic [$clog2(DEPTH):0] s_status_depth_commit;
logic s_status_overflow;
logic s_status_bad_frame;
logic s_status_good_frame;
logic [$clog2(DEPTH):0] m_status_depth;
logic [$clog2(DEPTH):0] m_status_depth_commit;
logic m_status_overflow;
logic m_status_bad_frame;
logic m_status_good_frame;
taxi_axis_async_fifo_adapter #(
.DEPTH(DEPTH),
.RAM_PIPELINE(RAM_PIPELINE),
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.MARK_WHEN_FULL(MARK_WHEN_FULL),
.PAUSE_EN(PAUSE_EN),
.FRAME_PAUSE(FRAME_PAUSE)
)
uut (
/*
* AXI4-Stream input (sink)
*/
.s_clk(s_clk),
.s_rst(s_rst),
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_clk(m_clk),
.m_rst(m_rst),
.m_axis(m_axis),
/*
* Pause
*/
.s_pause_req(s_pause_req),
.s_pause_ack(s_pause_ack),
.m_pause_req(m_pause_req),
.m_pause_ack(m_pause_ack),
/*
* Status
*/
.s_status_depth(s_status_depth),
.s_status_depth_commit(s_status_depth_commit),
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_depth(m_status_depth),
.m_status_depth_commit(m_status_depth_commit),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
endmodule
`resetall

62
src/axis/tb/taxi_axis_broadcast/Makefile Normal file
View File

@@ -0,0 +1,62 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_broadcast
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_M_COUNT := 4
export PARAM_DATA_W := 8
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
export PARAM_STRB_EN := 0
export PARAM_LAST_EN := 1
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

190
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.py Normal file
View File

@@ -0,0 +1,190 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
self.sink = [AxiStreamSink(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.m_axis]
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
for sink in self.sink:
sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
for sink in tb.sink:
rx_frame = await sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
for sink in tb.sink:
assert sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = len(cocotb.top.s_axis.tdata)
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("data_w", [8, 16, 32])
@pytest.mark.parametrize("m_count", range(1, 4))
def test_taxi_axis_broadcast(request, m_count, data_w):
dut = "taxi_axis_broadcast"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(rtl_dir, "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['M_COUNT'] = m_count
parameters['DATA_W'] = data_w
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
parameters['STRB_EN'] = 0
parameters['LAST_EN'] = 1
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

74
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv Normal file
View File

@@ -0,0 +1,74 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream broadcaster testbench
*/
module test_taxi_axis_broadcast #
(
/* verilator lint_off WIDTHTRUNC */
parameter M_COUNT = 4,
parameter DATA_W = 8,
parameter logic KEEP_EN = (DATA_W>8),
parameter KEEP_W = ((DATA_W+7)/8),
parameter logic STRB_EN = 1'b0,
parameter logic LAST_EN = 1'b1,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis(), m_axis[M_COUNT]();
taxi_axis_broadcast #(
.M_COUNT(M_COUNT)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

51
src/axis/tb/taxi_axis_cobs_decode/Makefile Normal file
View File

@@ -0,0 +1,51 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_cobs_decode
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
#export PARAM_APPEND_ZERO := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

243
src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py Normal file
View File

@@ -0,0 +1,243 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import cocotb_test.simulator
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
def cobs_encode(block):
block = bytearray(block)
enc = bytearray()
seg = bytearray()
code = 1
new_data = True
for b in block:
if b == 0:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = True
else:
code += 1
seg.append(b)
new_data = True
if code == 255:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = False
if new_data:
enc.append(code)
enc.extend(seg)
return bytes(enc)
def cobs_decode(block):
block = bytearray(block)
dec = bytearray()
code = 0
i = 0
if 0 in block:
return None
while i < len(block):
code = block[i]
i += 1
if i+code-1 > len(block):
return None
dec.extend(block[i:i+code-1])
i += code-1
if code < 255 and i < len(block):
dec.append(0)
return bytes(dec)
def prbs31(state=0x7fffffff):
while True:
for i in range(8):
if bool(state & 0x08000000) ^ bool(state & 0x40000000):
state = ((state & 0x3fffffff) << 1) | 1
else:
state = (state & 0x3fffffff) << 1
yield state & 0xff
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = [payload_data(x) for x in payload_lengths()]
for test_data in test_frames:
enc = cobs_encode(test_data)
test_frame = AxiStreamFrame(enc)
await tb.source.send(test_frame)
for test_data in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
return list(range(1, 33))+list(range(253, 259))+[512]+[1]*64
def zero_payload(length):
return bytearray(length)
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
def nonzero_incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(1, 256)), length))
def nonzero_incrementing_payload_zero_framed(length):
return bytearray([0]+list(itertools.islice(itertools.cycle(range(1, 256)), length))+[0])
def prbs_payload(length):
gen = prbs31()
return bytearray([next(gen) for x in range(length)])
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [zero_payload, nonzero_incrementing_payload, nonzero_incrementing_payload_zero_framed, prbs_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
def test_taxi_axis_cobs_decode(request):
dut = "taxi_axis_cobs_decode"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(rtl_dir, "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

48
src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.sv Normal file
View File

@@ -0,0 +1,48 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream COBS decoder testbench
*/
module test_taxi_axis_cobs_decode();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(8),
.LAST_EN(1),
.USER_EN(1),
.USER_W(1)
) s_axis(), m_axis();
taxi_axis_cobs_decode
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

50
src/axis/tb/taxi_axis_cobs_encode/Makefile Normal file
View File

@@ -0,0 +1,50 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_cobs_encode
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_APPEND_ZERO := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

252
src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py Normal file
View File

@@ -0,0 +1,252 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
def cobs_encode(block):
block = bytearray(block)
enc = bytearray()
seg = bytearray()
code = 1
new_data = True
for b in block:
if b == 0:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = True
else:
code += 1
seg.append(b)
new_data = True
if code == 255:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = False
if new_data:
enc.append(code)
enc.extend(seg)
return bytes(enc)
def cobs_decode(block):
block = bytearray(block)
dec = bytearray()
code = 0
i = 0
if 0 in block:
return None
while i < len(block):
code = block[i]
i += 1
if i+code-1 > len(block):
return None
dec.extend(block[i:i+code-1])
i += code-1
if code < 255 and i < len(block):
dec.append(0)
return bytes(dec)
def prbs31(state=0x7fffffff):
while True:
for i in range(8):
if bool(state & 0x08000000) ^ bool(state & 0x40000000):
state = ((state & 0x3fffffff) << 1) | 1
else:
state = (state & 0x3fffffff) << 1
yield state & 0xff
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
append_zero = int(os.getenv("PARAM_APPEND_ZERO"))
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = [payload_data(x) for x in payload_lengths()]
for test_data in test_frames:
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for test_data in test_frames:
rx_frame = await tb.sink.recv()
if append_zero:
assert rx_frame.tdata == cobs_encode(test_data)+b'\x00'
assert cobs_decode(rx_frame.tdata[:-1]) == test_data
else:
assert rx_frame.tdata == cobs_encode(test_data)
assert cobs_decode(rx_frame.tdata) == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
return list(range(1, 33))+list(range(253, 259))+[512]+[1]*64
def zero_payload(length):
return bytearray(length)
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
def nonzero_incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(1, 256)), length))
def nonzero_incrementing_payload_zero_framed(length):
return bytearray([0]+list(itertools.islice(itertools.cycle(range(1, 256)), length))+[0])
def prbs_payload(length):
gen = prbs31()
return bytearray([next(gen) for x in range(length)])
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [zero_payload, nonzero_incrementing_payload, nonzero_incrementing_payload_zero_framed, prbs_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("append_zero", [0, 1])
def test_taxi_axis_cobs_encode(request, append_zero):
dut = "taxi_axis_cobs_encode"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['APPEND_ZERO'] = append_zero
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

56
src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.sv Normal file
View File

@@ -0,0 +1,56 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream COBS encoder testbench
*/
module test_taxi_axis_cobs_encode #
(
/* verilator lint_off WIDTHTRUNC */
parameter logic APPEND_ZERO = 1'b1
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(8),
.LAST_EN(1),
.USER_EN(1),
.USER_W(1)
) s_axis(), m_axis();
taxi_axis_cobs_encode #(
.APPEND_ZERO(APPEND_ZERO)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

73
src/axis/tb/taxi_axis_fifo/Makefile Normal file
View File

@@ -0,0 +1,73 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_fifo
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 8
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
export PARAM_STRB_EN := 0
export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_W) )))
export PARAM_LAST_EN := 1
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_EN := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
export PARAM_MARK_WHEN_FULL := 0
export PARAM_PAUSE_EN := 1
export PARAM_FRAME_PAUSE := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

514
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.py Normal file
View File

@@ -0,0 +1,514 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
dut.pause_req.setimmediatevalue(0)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_tuser_assert(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source.send(test_frame)
if dut.DROP_BAD_FRAME.value:
for k in range(64):
await RisingEdge(dut.clk)
else:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_init_sink_pause(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.clk)
tb.sink.pause = False
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_init_sink_pause_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.clk)
await tb.reset()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.clk)
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_pause(dut):
tb = TB(dut)
byte_lanes = tb.source.byte_lanes
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
test_frame = AxiStreamFrame(test_data)
for k in range(16):
await tb.source.send(test_frame)
for k in range(60):
await RisingEdge(dut.clk)
dut.pause_req.value = 1
for k in range(64):
await RisingEdge(dut.clk)
assert tb.sink.idle()
dut.pause_req.value = 0
for k in range(16):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_overflow(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = tb.source.byte_lanes
await tb.reset()
tb.sink.pause = True
size = (16*byte_lanes)
count = depth*2 // size
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
test_frame = AxiStreamFrame(test_data)
for k in range(count):
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.clk)
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
assert tb.source.idle()
else:
assert not tb.source.idle()
tb.sink.pause = False
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.clk)
rx_count = 0
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
continue
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
rx_count += 1
assert rx_count < count
else:
for k in range(count):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_oversize(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = tb.source.byte_lanes
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.clk)
tb.sink.pause = False
if dut.DROP_OVERSIZE_FRAME.value:
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.clk)
else:
rx_frame = await tb.sink.recv()
if dut.MARK_WHEN_FULL.value:
assert rx_frame.tuser
else:
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.source.byte_lanes
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for k in range(512):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
cycles = 0
while cycles < 100:
cycles += 1
if not tb.source.idle() or dut.s_axis.tvalid.value.integer or dut.m_axis.tvalid.value.integer or dut.status_depth.value.integer:
cycles = 0
await RisingEdge(dut.clk)
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
continue
assert not rx_frame.tuser
assert len(test_frames) > 0
while True:
test_frame = test_frames.pop(0)
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
break
assert len(test_frames) < 512
else:
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = len(cocotb.top.m_axis.tdata)
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [
run_test_tuser_assert,
run_test_init_sink_pause,
run_test_init_sink_pause_reset,
run_test_pause,
run_test_overflow,
run_test_oversize
]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
"drop_when_full", "mark_when_full"),
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
@pytest.mark.parametrize(("ram_pipeline", "output_fifo"),
[(0, 0), (1, 0), (4, 0), (0, 1), (1, 1), (4, 1)])
@pytest.mark.parametrize("data_w", [8, 16, 32, 64])
def test_taxi_axis_fifo(request, data_w, ram_pipeline, output_fifo,
frame_fifo, drop_oversize_frame, drop_bad_frame,
drop_when_full, mark_when_full):
dut = "taxi_axis_fifo"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(rtl_dir, "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DATA_W'] = data_w
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
parameters['STRB_EN'] = 0
parameters['DEPTH'] = 1024 * parameters['KEEP_W']
parameters['LAST_EN'] = 1
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
parameters['RAM_PIPELINE'] = ram_pipeline
parameters['OUTPUT_FIFO_EN'] = output_fifo
parameters['FRAME_FIFO'] = frame_fifo
parameters['USER_BAD_FRAME_VALUE'] = 1
parameters['USER_BAD_FRAME_MASK'] = 1
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
parameters['DROP_BAD_FRAME'] = drop_bad_frame
parameters['DROP_WHEN_FULL'] = drop_when_full
parameters['MARK_WHEN_FULL'] = mark_when_full
parameters['PAUSE_EN'] = 1
parameters['FRAME_PAUSE'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

120
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.sv Normal file
View File

@@ -0,0 +1,120 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream FIFO testbench
*/
module test_taxi_axis_fifo #
(
/* verilator lint_off WIDTHTRUNC */
parameter DEPTH = 4096,
parameter DATA_W = 8,
parameter logic KEEP_EN = (DATA_W>8),
parameter KEEP_W = ((DATA_W+7)/8),
parameter logic STRB_EN = 1'b0,
parameter logic LAST_EN = 1'b1,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1,
parameter RAM_PIPELINE = 1,
parameter logic OUTPUT_FIFO_EN = 1'b0,
parameter logic FRAME_FIFO = 1'b0,
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
parameter logic DROP_BAD_FRAME = 1'b0,
parameter logic DROP_WHEN_FULL = 1'b0,
parameter logic MARK_WHEN_FULL = 1'b0,
parameter logic PAUSE_EN = 1'b0,
parameter logic FRAME_PAUSE = FRAME_FIFO
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis(), m_axis();
logic pause_req;
logic pause_ack;
logic [$clog2(DEPTH):0] status_depth;
logic [$clog2(DEPTH):0] status_depth_commit;
logic status_overflow;
logic status_bad_frame;
logic status_good_frame;
taxi_axis_fifo #(
.DEPTH(DEPTH),
.RAM_PIPELINE(RAM_PIPELINE),
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.MARK_WHEN_FULL(MARK_WHEN_FULL),
.PAUSE_EN(PAUSE_EN),
.FRAME_PAUSE(FRAME_PAUSE)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis),
/*
* Pause
*/
.pause_req(pause_req),
.pause_ack(pause_ack),
/*
* Status
*/
.status_depth(status_depth),
.status_depth_commit(status_depth_commit),
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
`resetall

75
src/axis/tb/taxi_axis_fifo_adapter/Makefile Normal file
View File

@@ -0,0 +1,75 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_fifo_adapter
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_S_DATA_W := 8
export PARAM_S_KEEP_EN := $(shell echo $$(( $(PARAM_S_DATA_W) > 8 )))
export PARAM_S_KEEP_W := $(shell echo $$(( ( $(PARAM_S_DATA_W) + 7 ) / 8 )))
export PARAM_S_STRB_EN := 0
export PARAM_M_DATA_W := 8
export PARAM_M_KEEP_EN := $(shell echo $$(( $(PARAM_M_DATA_W) > 8 )))
export PARAM_M_KEEP_W := $(shell echo $$(( ( $(PARAM_M_DATA_W) + 7 ) / 8 )))
export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_W) > $(PARAM_M_KEEP_W) ? $(PARAM_S_KEEP_W) : $(PARAM_M_KEEP_W)) )))
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_EN := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
export PARAM_MARK_WHEN_FULL := 0
export PARAM_PAUSE_EN := 1
export PARAM_FRAME_PAUSE := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

513
src/axis/tb/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.py Normal file
View File

@@ -0,0 +1,513 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
dut.pause_req.setimmediatevalue(0)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_tuser_assert(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source.send(test_frame)
if int(dut.DROP_BAD_FRAME.value):
for k in range(64):
await RisingEdge(dut.clk)
else:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_init_sink_pause(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.clk)
tb.sink.pause = False
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_init_sink_pause_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.clk)
await tb.reset()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.clk)
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_pause(dut):
tb = TB(dut)
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
test_frame = AxiStreamFrame(test_data)
for k in range(16):
await tb.source.send(test_frame)
for k in range(60):
await RisingEdge(dut.clk)
dut.pause_req.value = 1
for k in range(64):
await RisingEdge(dut.clk)
assert tb.sink.idle()
dut.pause_req.value = 0
for k in range(16):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_overflow(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
await tb.reset()
tb.sink.pause = True
size = (16*byte_lanes)
count = depth*2 // size
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
test_frame = AxiStreamFrame(test_data)
for k in range(count):
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.clk)
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
assert tb.source.idle()
else:
assert not tb.source.idle()
tb.sink.pause = False
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.clk)
rx_count = 0
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
continue
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
rx_count += 1
assert rx_count < count
else:
for k in range(count):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_oversize(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.clk)
tb.sink.pause = False
if dut.DROP_OVERSIZE_FRAME.value:
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.clk)
else:
rx_frame = await tb.sink.recv()
if dut.MARK_WHEN_FULL.value:
assert rx_frame.tuser
else:
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for k in range(512):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
cycles = 0
while cycles < 100:
cycles += 1
if not tb.source.idle() or int(dut.s_axis.tvalid.value) or int(dut.m_axis.tvalid.value) or int(dut.status_depth.value):
cycles = 0
await RisingEdge(dut.clk)
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
continue
assert not rx_frame.tuser
while True:
test_frame = test_frames.pop(0)
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
break
assert len(test_frames) < 512
else:
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = max(len(cocotb.top.m_axis.tdata), len(cocotb.top.s_axis.tdata))
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [
run_test_tuser_assert,
run_test_init_sink_pause,
run_test_init_sink_pause_reset,
run_test_pause,
run_test_overflow,
run_test_oversize
]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
"drop_when_full", "mark_when_full"),
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
@pytest.mark.parametrize("m_data_width", [8, 16, 32])
@pytest.mark.parametrize("s_data_width", [8, 16, 32])
def test_taxi_axis_fifo_adapter(request, s_data_width, m_data_width,
frame_fifo, drop_oversize_frame, drop_bad_frame,
drop_when_full, mark_when_full):
dut = "taxi_axis_fifo_adapter"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['S_DATA_W'] = s_data_width
parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
parameters['S_STRB_EN'] = 0
parameters['M_DATA_W'] = m_data_width
parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
parameters['M_STRB_EN'] = parameters['S_STRB_EN']
parameters['DEPTH'] = 1024 * max(parameters['S_KEEP_W'], parameters['M_KEEP_W'])
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
parameters['RAM_PIPELINE'] = 1
parameters['OUTPUT_FIFO_EN'] = 0
parameters['FRAME_FIFO'] = frame_fifo
parameters['USER_BAD_FRAME_VALUE'] = 1
parameters['USER_BAD_FRAME_MASK'] = 1
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
parameters['DROP_BAD_FRAME'] = drop_bad_frame
parameters['DROP_WHEN_FULL'] = drop_when_full
parameters['MARK_WHEN_FULL'] = mark_when_full
parameters['PAUSE_EN'] = 1
parameters['FRAME_PAUSE'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

137
src/axis/tb/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.sv Normal file
View File

@@ -0,0 +1,137 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream FIFO with width converter testbench
*/
module test_taxi_axis_fifo_adapter #
(
/* verilator lint_off WIDTHTRUNC */
parameter DEPTH = 4096,
parameter S_DATA_W = 8,
parameter logic S_KEEP_EN = (S_DATA_W>8),
parameter S_KEEP_W = ((S_DATA_W+7)/8),
parameter logic S_STRB_EN = 0,
parameter M_DATA_W = 8,
parameter logic M_KEEP_EN = (M_DATA_W>8),
parameter M_KEEP_W = ((M_DATA_W+7)/8),
parameter logic M_STRB_EN = 0,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1,
parameter RAM_PIPELINE = 1,
parameter logic OUTPUT_FIFO_EN = 1'b0,
parameter logic FRAME_FIFO = 1'b0,
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
parameter logic DROP_BAD_FRAME = 1'b0,
parameter logic DROP_WHEN_FULL = 1'b0,
parameter logic MARK_WHEN_FULL = 1'b0,
parameter logic PAUSE_EN = 1'b0,
parameter logic FRAME_PAUSE = FRAME_FIFO
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(S_DATA_W),
.KEEP_EN(S_KEEP_EN),
.KEEP_W(S_KEEP_W),
.STRB_EN(S_STRB_EN),
.LAST_EN(1'b1),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis();
taxi_axis_if #(
.DATA_W(M_DATA_W),
.KEEP_EN(M_KEEP_EN),
.KEEP_W(M_KEEP_W),
.STRB_EN(M_STRB_EN),
.LAST_EN(1'b1),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) m_axis();
logic pause_req;
logic pause_ack;
logic [$clog2(DEPTH):0] status_depth;
logic [$clog2(DEPTH):0] status_depth_commit;
logic status_overflow;
logic status_bad_frame;
logic status_good_frame;
taxi_axis_fifo_adapter #(
.DEPTH(DEPTH),
.RAM_PIPELINE(RAM_PIPELINE),
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.MARK_WHEN_FULL(MARK_WHEN_FULL),
.PAUSE_EN(PAUSE_EN),
.FRAME_PAUSE(FRAME_PAUSE)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis),
/*
* Pause
*/
.pause_req(pause_req),
.pause_ack(pause_ack),
/*
* Status
*/
.status_depth(status_depth),
.status_depth_commit(status_depth_commit),
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
`resetall

62
src/axis/tb/taxi_axis_mux/Makefile Normal file
View File

@@ -0,0 +1,62 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_mux
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_S_COUNT := 4
export PARAM_DATA_W := 8
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
export PARAM_STRB_EN := 0
export PARAM_LAST_EN := 1
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

226
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.py Normal file
View File

@@ -0,0 +1,226 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.s_axis]
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
dut.enable.setimmediatevalue(0)
dut.select.setimmediatevalue(0)
def set_idle_generator(self, generator=None):
if generator:
for source in self.source:
source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, port=0):
tb = TB(dut)
id_count = 2**len(tb.source[port].bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
dut.enable.setimmediatevalue(1)
dut.select.setimmediatevalue(port)
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source[port].send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_tuser_assert(dut, port=0):
tb = TB(dut)
await tb.reset()
dut.enable.setimmediatevalue(1)
dut.select.setimmediatevalue(port)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source[port].send(test_frame)
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = len(cocotb.top.m_axis.tdata)
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
ports = len(cocotb.top.s_axis)
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.add_option("port", list(range(ports)))
factory.generate_tests()
for test in [run_test_tuser_assert]:
factory = TestFactory(test)
factory.add_option("port", list(range(ports)))
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("data_w", [8, 16, 32])
@pytest.mark.parametrize("s_count", [4])
def test_taxi_axis_mux(request, s_count, data_w):
dut = "taxi_axis_mux"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(rtl_dir, "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['S_COUNT'] = s_count
parameters['DATA_W'] = data_w
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
parameters['STRB_EN'] = 0
parameters['LAST_EN'] = 1
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

83
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv Normal file
View File

@@ -0,0 +1,83 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream multiplexer testbench
*/
module test_taxi_axis_mux #
(
/* verilator lint_off WIDTHTRUNC */
parameter S_COUNT = 4,
parameter DATA_W = 8,
parameter logic KEEP_EN = (DATA_W>8),
parameter KEEP_W = ((DATA_W+7)/8),
parameter logic STRB_EN = 1'b0,
parameter logic LAST_EN = 1'b1,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis[S_COUNT](), m_axis();
logic enable;
logic [$clog2(S_COUNT)-1:0] select;
taxi_axis_mux #(
.S_COUNT(S_COUNT)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis),
/*
* Control
*/
.enable(enable),
.select(select)
);
endmodule
`resetall

62
src/axis/tb/taxi_axis_pipeline_fifo/Makefile Normal file
View File

@@ -0,0 +1,62 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_pipeline_fifo
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 8
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
export PARAM_STRB_EN := 0
export PARAM_LAST_EN := 1
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
export PARAM_LENGTH := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

350
src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.py Normal file
View File

@@ -0,0 +1,350 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_tuser_assert(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source.send(test_frame)
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_init_sink_pause(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.clk)
tb.sink.pause = False
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_init_sink_pause_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.clk)
await tb.reset()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.clk)
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_overflow(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 2048))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(2048):
await RisingEdge(dut.clk)
tb.sink.pause = False
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.source.byte_lanes
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for k in range(128):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = len(cocotb.top.m_axis.tdata)
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [
run_test_tuser_assert,
run_test_init_sink_pause,
run_test_init_sink_pause_reset,
run_test_overflow
]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("data_w", [8, 16])
@pytest.mark.parametrize("length", list(range(17)))
def test_taxi_axis_pipeline_fifo(request, length, data_w):
dut = "taxi_axis_pipeline_fifo"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(rtl_dir, "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DATA_W'] = data_w
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
parameters['STRB_EN'] = 0
parameters['LAST_EN'] = 1
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
parameters['LENGTH'] = length
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

74
src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.sv Normal file
View File

@@ -0,0 +1,74 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream pipeline FIFO testbench
*/
module test_taxi_axis_pipeline_fifo #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 8,
parameter logic KEEP_EN = (DATA_W>8),
parameter KEEP_W = ((DATA_W+7)/8),
parameter logic STRB_EN = 1'b0,
parameter logic LAST_EN = 1'b1,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1,
parameter LENGTH = 2
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis(), m_axis();
taxi_axis_pipeline_fifo #(
.LENGTH(LENGTH)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

62
src/axis/tb/taxi_axis_pipeline_register/Makefile Normal file
View File

@@ -0,0 +1,62 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_pipeline_register
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 8
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
export PARAM_STRB_EN := 0
export PARAM_LAST_EN := 1
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
export PARAM_REG_TYPE := 2
export PARAM_LENGTH := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

261
src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.py Normal file
View File

@@ -0,0 +1,261 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_tuser_assert(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source.send(test_frame)
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.source.byte_lanes
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for k in range(128):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = len(cocotb.top.m_axis.tdata)
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [run_test_tuser_assert]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("reg_type", [0, 1, 2])
@pytest.mark.parametrize("data_w", [8, 16, 32])
@pytest.mark.parametrize("length", [0, 1, 2])
def test_taxi_axis_pipeline_register(request, length, data_w, reg_type):
dut = "taxi_axis_pipeline_register"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DATA_W'] = data_w
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
parameters['STRB_EN'] = 0
parameters['LAST_EN'] = 1
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
parameters['REG_TYPE'] = reg_type
parameters['LENGTH'] = length
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

76
src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.sv Normal file
View File

@@ -0,0 +1,76 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream pipeline register testbench
*/
module test_taxi_axis_pipeline_register #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 8,
parameter logic KEEP_EN = (DATA_W>8),
parameter KEEP_W = ((DATA_W+7)/8),
parameter logic STRB_EN = 1'b0,
parameter logic LAST_EN = 1'b1,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1,
parameter REG_TYPE = 2,
parameter LENGTH = 2
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis(), m_axis();
taxi_axis_pipeline_register #(
.REG_TYPE(REG_TYPE),
.LENGTH(LENGTH)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

62
src/axis/tb/taxi_axis_register/Makefile Normal file
View File

@@ -0,0 +1,62 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axis_register
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 8
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
export PARAM_STRB_EN := 0
export PARAM_LAST_EN := 1
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
export PARAM_REG_TYPE := 2
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

260
src/axis/tb/taxi_axis_register/test_taxi_axis_register.py Normal file
View File

@@ -0,0 +1,260 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_tuser_assert(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source.send(test_frame)
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.source.byte_lanes
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for k in range(128):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = len(cocotb.top.m_axis.tdata)
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [run_test_tuser_assert]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("reg_type", [0, 1, 2])
@pytest.mark.parametrize("data_w", [8, 16, 32])
def test_taxi_axis_register(request, data_w, reg_type):
dut = "taxi_axis_register"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(rtl_dir, "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DATA_W'] = data_w
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
parameters['STRB_EN'] = 0
parameters['LAST_EN'] = 1
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
parameters['REG_TYPE'] = reg_type
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

74
src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv Normal file
View File

@@ -0,0 +1,74 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream register testbench
*/
module test_taxi_axis_register #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 8,
parameter logic KEEP_EN = (DATA_W>8),
parameter KEEP_W = ((DATA_W+7)/8),
parameter logic STRB_EN = 1'b0,
parameter logic LAST_EN = 1'b1,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1,
parameter REG_TYPE = 2
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(STRB_EN),
.LAST_EN(LAST_EN),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis(), m_axis();
taxi_axis_register #(
.REG_TYPE(REG_TYPE)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall