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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
32
src/eth/example/ADM_PCIE_9V3/fpga/README.md
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32
src/eth/example/ADM_PCIE_9V3/fpga/README.md
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@@ -0,0 +1,32 @@
|
||||
# Taxi Example Design for ADM-PCIE-9V3
|
||||
|
||||
## Introduction
|
||||
|
||||
This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board.
|
||||
|
||||
The design places looped-back MACs on the QSFP28 ports.
|
||||
|
||||
* QSFP28
|
||||
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
|
||||
|
||||
## Board details
|
||||
|
||||
* FPGA: xcvu3p-ffvc1517-2-i
|
||||
* 25GBASE-R PHY: Soft PCS with GTY transceivers
|
||||
|
||||
## Licensing
|
||||
|
||||
* Toolchain
|
||||
* Vivado Enterprise (requires license)
|
||||
* IP
|
||||
* No licensed vendor IP or 3rd party IP
|
||||
|
||||
## How to build
|
||||
|
||||
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
|
||||
|
||||
## How to test
|
||||
|
||||
Run `make program` to program the board with Vivado.
|
||||
|
||||
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
|
||||
153
src/eth/example/ADM_PCIE_9V3/fpga/common/vivado.mk
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153
src/eth/example/ADM_PCIE_9V3/fpga/common/vivado.mk
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|
||||
# SPDX-License-Identifier: MIT
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016-2025 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - list of source files
|
||||
# INC_FILES - list of include files
|
||||
# XDC_FILES - list of timing constraint files
|
||||
# XCI_FILES - list of IP XCI files
|
||||
# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
|
||||
# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
|
||||
#
|
||||
# Note: both SYN_FILES and INC_FILES support file list files. File list
|
||||
# files are files with a .f extension that contain a list of additional
|
||||
# files to include, one path relative to the .f file location per line.
|
||||
# The .f files are processed recursively, and then the complete file list
|
||||
# is de-duplicated, with later files in the list taking precedence.
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: fpga vivado tmpclean clean distclean
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include $(CONFIG)
|
||||
|
||||
FPGA_TOP ?= fpga
|
||||
PROJECT ?= $(FPGA_TOP)
|
||||
XDC_FILES ?= $(PROJECT).xdc
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
|
||||
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything (fpga)
|
||||
# fpga: build FPGA config
|
||||
# vivado: open project in Vivado
|
||||
# tmpclean: remove intermediate files
|
||||
# clean: remove output files and project files
|
||||
# distclean: remove archived output files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(PROJECT).bit
|
||||
|
||||
vivado: $(PROJECT).xpr
|
||||
vivado $(PROJECT).xpr
|
||||
|
||||
tmpclean::
|
||||
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean:: tmpclean
|
||||
-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
|
||||
|
||||
distclean:: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
|
||||
# create fresh project if Makefile or IP files have changed
|
||||
create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
|
||||
echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
|
||||
echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
|
||||
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
|
||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
# source config TCL scripts if any source file has changed
|
||||
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
||||
echo "open_project -quiet $(PROJECT).xpr" > $@
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
$(PROJECT).xpr: create_project.tcl update_config.tcl
|
||||
vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
|
||||
|
||||
# synthesis run
|
||||
$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
|
||||
echo "open_project $(PROJECT).xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
|
||||
echo "open_project $(PROJECT).xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "open_run impl_1" >> run_impl.tcl
|
||||
echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
|
||||
echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# output files (including potentially bit, bin, ltx, and xsa)
|
||||
$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
|
||||
echo "open_project $(PROJECT).xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
|
||||
echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
|
||||
echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
|
||||
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
|
||||
490
src/eth/example/ADM_PCIE_9V3/fpga/fpga.xdc
Normal file
490
src/eth/example/ADM_PCIE_9V3/fpga/fpga.xdc
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@@ -0,0 +1,490 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the ADM-PCIE-9V3
|
||||
# part: xcvu3p-ffvc1517-2-i
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
# 300 MHz system clock
|
||||
set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
|
||||
set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
|
||||
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}]
|
||||
set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}]
|
||||
set_property -dict {LOC AU23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_r}]
|
||||
set_property -dict {LOC AH24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[0]}]
|
||||
set_property -dict {LOC AJ23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[1]}]
|
||||
|
||||
set_false_path -to [get_ports {user_led_g[*] user_led_r front_led[*]}]
|
||||
set_output_delay 0 [get_ports {user_led_g[*] user_led_r front_led[*]}]
|
||||
|
||||
# Switches
|
||||
set_property -dict {LOC AV27 IOSTANDARD LVCMOS18} [get_ports {user_sw[0]}]
|
||||
set_property -dict {LOC AW27 IOSTANDARD LVCMOS18} [get_ports {user_sw[1]}]
|
||||
|
||||
set_false_path -from [get_ports {user_sw[*]}]
|
||||
set_input_delay 0 [get_ports {user_sw[*]}]
|
||||
|
||||
# GPIO
|
||||
#set_property -dict {LOC G30 IOSTANDARD LVCMOS18} [get_ports gpio_p[0]]
|
||||
#set_property -dict {LOC F30 IOSTANDARD LVCMOS18} [get_ports gpio_n[0]]
|
||||
#set_property -dict {LOC J31 IOSTANDARD LVCMOS18} [get_ports gpio_p[1]]
|
||||
#set_property -dict {LOC H31 IOSTANDARD LVCMOS18} [get_ports gpio_n[1]]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC G38 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC G39 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F35 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC F36 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E38 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC E39 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D35 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC D36 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C38 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C39 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C33 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC C34 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B36 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC B37 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A33 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC A34 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
|
||||
set_property -dict {LOC N33 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ?
|
||||
set_property -dict {LOC N34 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ?
|
||||
set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l]
|
||||
set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_0_sel_l]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
|
||||
|
||||
set_property -dict {LOC R38 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC R39 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P35 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC P36 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N38 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC N39 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC M36 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L38 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC L39 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC K36 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J38 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC J39 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H35 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC H36 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC U33 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ?
|
||||
#set_property -dict {LOC U34 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ?
|
||||
set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l]
|
||||
set_property -dict {LOC D30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_1_sel_l]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
#create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p]
|
||||
|
||||
set_property -dict {LOC B29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_reset_l]
|
||||
set_property -dict {LOC C29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_int_l]
|
||||
#set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_scl]
|
||||
#set_property -dict {LOC A29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_sda]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_0_sel_l qsfp_1_sel_l qsfp_reset_l}]
|
||||
set_output_delay 0 [get_ports {qsfp_0_sel_l qsfp_1_sel_l qsfp_reset_l}]
|
||||
set_false_path -from [get_ports {qsfp_0_modprs_l qsfp_1_modprs_l qsfp_int_l}]
|
||||
set_input_delay 0 [get_ports {qsfp_0_modprs_l qsfp_1_modprs_l qsfp_int_l}]
|
||||
|
||||
#set_false_path -to [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
|
||||
#set_output_delay 0 [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
|
||||
#set_false_path -from [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
|
||||
|
||||
# I2C interface
|
||||
#set_property -dict {LOC AT25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
|
||||
#set_property -dict {LOC AT26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
|
||||
#set_property -dict {LOC AP23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_wp]
|
||||
|
||||
#set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl eeprom_wp}]
|
||||
#set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl eeprom_wp}]
|
||||
#set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC J2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC J1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC H5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC H4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC L2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC L1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC K5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC K4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC N2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC N1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC M5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC M4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC R2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC R1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC P5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC P4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC U2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC U1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC T5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC T4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC W2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC W1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC V5 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC V4 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AA2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AA1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AB5 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AB4 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AC2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AC1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AD5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AD4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AE2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AE1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AF5 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AF4 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AH5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AH4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AK5 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AK4 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AM5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AP5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AW7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AW6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AA7 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_226
|
||||
#set_property -dict {LOC AA6 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_226
|
||||
#set_property -dict {LOC AJ7 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_224
|
||||
#set_property -dict {LOC AJ6 } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_224
|
||||
#set_property -dict {LOC AJ31 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_0]
|
||||
#set_property -dict {LOC AH29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_1]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
|
||||
|
||||
#set_false_path -from [get_ports {perst_0}]
|
||||
#set_input_delay 0 [get_ports {perst_0}]
|
||||
|
||||
# DDR4 C0
|
||||
# 5x K4A8G085WB-RC
|
||||
#set_property -dict {LOC F9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
#set_property -dict {LOC G9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
#set_property -dict {LOC G11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
#set_property -dict {LOC D11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
#set_property -dict {LOC E12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
#set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
#set_property -dict {LOC F10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
#set_property -dict {LOC J9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
#set_property -dict {LOC J8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
#set_property -dict {LOC F12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
#set_property -dict {LOC D9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
#set_property -dict {LOC H11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
#set_property -dict {LOC E8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
#set_property -dict {LOC J11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
#set_property -dict {LOC C9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
#set_property -dict {LOC B11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
#set_property -dict {LOC K12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
#set_property -dict {LOC H9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}]
|
||||
#set_property -dict {LOC F8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
#set_property -dict {LOC H8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
#set_property -dict {LOC D10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
#set_property -dict {LOC E11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
#set_property -dict {LOC B10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}]
|
||||
#set_property -dict {LOC C11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}]
|
||||
#set_property -dict {LOC A9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}]
|
||||
#set_property -dict {LOC H12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}]
|
||||
#set_property -dict {LOC G12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}]
|
||||
#set_property -dict {LOC B9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}]
|
||||
#set_property -dict {LOC E10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}]
|
||||
#set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
#set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}]
|
||||
#set_property -dict {LOC G7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
#set_property -dict {LOC F7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
#set_property -dict {LOC H7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}]
|
||||
#set_property -dict {LOC J10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}]
|
||||
|
||||
#set_property -dict {LOC L10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
#set_property -dict {LOC L9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
#set_property -dict {LOC N9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
#set_property -dict {LOC M9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
#set_property -dict {LOC M10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
#set_property -dict {LOC K11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
#set_property -dict {LOC M11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
#set_property -dict {LOC K10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
#set_property -dict {LOC L17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
#set_property -dict {LOC M15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
#set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
#set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
#set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
#set_property -dict {LOC F17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
#set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
#set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
#set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
#set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
#set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
#set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
#set_property -dict {LOC D21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
#set_property -dict {LOC G19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
#set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
#set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
#set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
#set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
#set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
#set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
#set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
#set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
#set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
#set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
#set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
#set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
#set_property -dict {LOC K13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
#set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
#set_property -dict {LOC M12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
#set_property -dict {LOC L12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
#set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
#set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
#set_property -dict {LOC F13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
#set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
#set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
#set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
#set_property -dict {LOC F22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
#set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
#set_property -dict {LOC C21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
#set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
#set_property -dict {LOC K21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
#set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
#set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
#set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
#set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
#set_property -dict {LOC K16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
#set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC D14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 C1
|
||||
# 5x K4A8G085WB-RC
|
||||
#set_property -dict {LOC AN9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
#set_property -dict {LOC AM9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
#set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
#set_property -dict {LOC AU9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
#set_property -dict {LOC AT10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
#set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
#set_property -dict {LOC AM12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
#set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
#set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
#set_property -dict {LOC AP7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
#set_property -dict {LOC AR8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
#set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
#set_property -dict {LOC AP8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
#set_property -dict {LOC AK11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
#set_property -dict {LOC AP9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
#set_property -dict {LOC AV10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
#set_property -dict {LOC AT11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
#set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}]
|
||||
#set_property -dict {LOC AN11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
#set_property -dict {LOC AR9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
#set_property -dict {LOC AP12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
#set_property -dict {LOC AN10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
#set_property -dict {LOC AW13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}]
|
||||
#set_property -dict {LOC AU10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}]
|
||||
#set_property -dict {LOC AW11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}]
|
||||
#set_property -dict {LOC AM7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
|
||||
#set_property -dict {LOC AN7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
|
||||
#set_property -dict {LOC AU12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
#set_property -dict {LOC AT12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
#set_property -dict {LOC AV9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
#set_property -dict {LOC AR11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
#set_property -dict {LOC AM8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
#set_property -dict {LOC AN12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
#set_property -dict {LOC AR10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}]
|
||||
#set_property -dict {LOC AV11 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}]
|
||||
|
||||
#set_property -dict {LOC AK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
#set_property -dict {LOC AK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
#set_property -dict {LOC AH10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
#set_property -dict {LOC AJ11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
#set_property -dict {LOC AJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
#set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
#set_property -dict {LOC AG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
#set_property -dict {LOC AJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
#set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
#set_property -dict {LOC AL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
#set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
#set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
#set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
#set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
#set_property -dict {LOC AP17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
#set_property -dict {LOC AN15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
#set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
#set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
#set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
#set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
#set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
#set_property -dict {LOC AW17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
#set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
#set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
#set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
#set_property -dict {LOC AN21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
#set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
#set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
#set_property -dict {LOC AR20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
#set_property -dict {LOC AU22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
#set_property -dict {LOC AV19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
#set_property -dict {LOC AW22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
#set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
#set_property -dict {LOC AT22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
#set_property -dict {LOC AW21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
#set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
#set_property -dict {LOC AH19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
#set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
#set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
#set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
#set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
#set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
#set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
#set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
#set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
#set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
#set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
#set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
#set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
#set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
#set_property -dict {LOC AJ14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
#set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
#set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
#set_property -dict {LOC AG17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
#set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
#set_property -dict {LOC AG9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
#set_property -dict {LOC AH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
#set_property -dict {LOC AK16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
#set_property -dict {LOC AL16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
#set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
#set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
#set_property -dict {LOC AU17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
#set_property -dict {LOC AV17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
#set_property -dict {LOC AN22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
#set_property -dict {LOC AP22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
#set_property -dict {LOC AV22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
#set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
#set_property -dict {LOC AG20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
#set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
#set_property -dict {LOC AK21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
#set_property -dict {LOC AL21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
#set_property -dict {LOC AH16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
#set_property -dict {LOC AH15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
#set_property -dict {LOC AG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC AK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC AU20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}]
|
||||
|
||||
# QSPI flash
|
||||
#set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}]
|
||||
#set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}]
|
||||
#set_property -dict {LOC AF28 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}]
|
||||
#set_property -dict {LOC AG28 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}]
|
||||
#set_property -dict {LOC AV30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}]
|
||||
|
||||
#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_false_path -from [get_ports {qspi_1_dq}]
|
||||
#set_input_delay 0 [get_ports {qspi_1_dq}]
|
||||
89
src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile
Normal file
89
src/eth/example/ADM_PCIE_9V3/fpga/fpga/Makefile
Normal file
@@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu3p-ffvc1517-2-i
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
|
||||
|
||||
# Configuration
|
||||
# CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT)_primary.mcs\" \"$(PROJECT)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)_primary.prm\" \"$(PROJECT)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
89
src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile
Normal file
89
src/eth/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile
Normal file
@@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu3p-ffvc1517-2-i
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
|
||||
|
||||
# Configuration
|
||||
# CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT)_primary.mcs\" \"$(PROJECT)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)_primary.prm\" \"$(PROJECT)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
1
src/eth/example/ADM_PCIE_9V3/fpga/lib/taxi
Symbolic link
1
src/eth/example/ADM_PCIE_9V3/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../../../
|
||||
243
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv
Normal file
243
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,243 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 300MHz LVDS
|
||||
*/
|
||||
input wire logic clk_300mhz_p,
|
||||
input wire logic clk_300mhz_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [1:0] user_led_g,
|
||||
output wire logic user_led_r,
|
||||
output wire logic [1:0] front_led,
|
||||
input wire logic [1:0] user_sw,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp_0_tx_p,
|
||||
output wire logic [3:0] qsfp_0_tx_n,
|
||||
input wire logic [3:0] qsfp_0_rx_p,
|
||||
input wire logic [3:0] qsfp_0_rx_n,
|
||||
input wire logic qsfp_0_mgt_refclk_p,
|
||||
input wire logic qsfp_0_mgt_refclk_n,
|
||||
input wire logic qsfp_0_modprs_l,
|
||||
output wire logic qsfp_0_sel_l,
|
||||
|
||||
output wire logic [3:0] qsfp_1_tx_p,
|
||||
output wire logic [3:0] qsfp_1_tx_n,
|
||||
input wire logic [3:0] qsfp_1_rx_p,
|
||||
input wire logic [3:0] qsfp_1_rx_n,
|
||||
// input wire logic qsfp_1_mgt_refclk_p,
|
||||
// input wire logic qsfp_1_mgt_refclk_n,
|
||||
input wire logic qsfp_1_modprs_l,
|
||||
output wire logic qsfp_1_sel_l,
|
||||
|
||||
output wire logic qsfp_reset_l,
|
||||
input wire logic qsfp_int_l
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_300mhz_ibufg;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFGDS #(
|
||||
.DIFF_TERM("FALSE"),
|
||||
.IBUF_LOW_PWR("FALSE")
|
||||
)
|
||||
clk_300mhz_ibufg_inst (
|
||||
.O (clk_300mhz_ibufg),
|
||||
.I (clk_300mhz_p),
|
||||
.IB (clk_300mhz_n)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 300 MHz input
|
||||
.CLKIN1_PERIOD(3.333),
|
||||
.REF_JITTER1(0.010),
|
||||
// 300 MHz input / 3 = 100 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(3),
|
||||
// 100 MHz PFD * 12.5 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(12.5),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(10),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(90),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(20),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(4),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 300 MHz input
|
||||
.CLKIN1(clk_300mhz_ibufg),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire [1:0] user_sw_int;
|
||||
|
||||
taxi_debounce_switch #(
|
||||
.WIDTH(2),
|
||||
.N(4),
|
||||
.RATE(125000)
|
||||
)
|
||||
debounce_switch_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
.in({user_sw}),
|
||||
.out({user_sw_int})
|
||||
);
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.user_led_g(user_led_g),
|
||||
.user_led_r(user_led_r),
|
||||
.front_led(front_led),
|
||||
.user_sw(user_sw_int),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.qsfp_0_tx_p(qsfp_0_tx_p),
|
||||
.qsfp_0_tx_n(qsfp_0_tx_n),
|
||||
.qsfp_0_rx_p(qsfp_0_rx_p),
|
||||
.qsfp_0_rx_n(qsfp_0_rx_n),
|
||||
.qsfp_0_mgt_refclk_p(qsfp_0_mgt_refclk_p),
|
||||
.qsfp_0_mgt_refclk_n(qsfp_0_mgt_refclk_n),
|
||||
.qsfp_0_modprs_l(qsfp_0_modprs_l),
|
||||
.qsfp_0_sel_l(qsfp_0_sel_l),
|
||||
|
||||
.qsfp_1_tx_p(qsfp_1_tx_p),
|
||||
.qsfp_1_tx_n(qsfp_1_tx_n),
|
||||
.qsfp_1_rx_p(qsfp_1_rx_p),
|
||||
.qsfp_1_rx_n(qsfp_1_rx_n),
|
||||
// .qsfp_1_mgt_refclk_p(qsfp_1_mgt_refclk_p),
|
||||
// .qsfp_1_mgt_refclk_n(qsfp_1_mgt_refclk_n),
|
||||
.qsfp_1_modprs_l(qsfp_1_modprs_l),
|
||||
.qsfp_1_sel_l(qsfp_1_sel_l),
|
||||
|
||||
.qsfp_reset_l(qsfp_reset_l),
|
||||
.qsfp_int_l(qsfp_int_l)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
401
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
Normal file
401
src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,401 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk_125mhz,
|
||||
input wire logic rst_125mhz,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [1:0] user_led_g,
|
||||
output wire logic user_led_r,
|
||||
output wire logic [1:0] front_led,
|
||||
input wire logic [1:0] user_sw,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp_0_tx_p,
|
||||
output wire logic [3:0] qsfp_0_tx_n,
|
||||
input wire logic [3:0] qsfp_0_rx_p,
|
||||
input wire logic [3:0] qsfp_0_rx_n,
|
||||
input wire logic qsfp_0_mgt_refclk_p,
|
||||
input wire logic qsfp_0_mgt_refclk_n,
|
||||
input wire logic qsfp_0_modprs_l,
|
||||
output wire logic qsfp_0_sel_l,
|
||||
|
||||
output wire logic [3:0] qsfp_1_tx_p,
|
||||
output wire logic [3:0] qsfp_1_tx_n,
|
||||
input wire logic [3:0] qsfp_1_rx_p,
|
||||
input wire logic [3:0] qsfp_1_rx_n,
|
||||
// input wire logic qsfp_1_mgt_refclk_p,
|
||||
// input wire logic qsfp_1_mgt_refclk_n,
|
||||
input wire logic qsfp_1_modprs_l,
|
||||
output wire logic qsfp_1_sel_l,
|
||||
|
||||
output wire logic qsfp_reset_l,
|
||||
input wire logic qsfp_int_l
|
||||
);
|
||||
|
||||
// QSFP28
|
||||
assign qsfp_0_sel_l = 1'b1;
|
||||
assign qsfp_1_sel_l = 1'b1;
|
||||
assign qsfp_reset_l = 1'b1;
|
||||
|
||||
wire [7:0] qsfp_tx_clk;
|
||||
wire [7:0] qsfp_tx_rst;
|
||||
wire [7:0] qsfp_rx_clk;
|
||||
wire [7:0] qsfp_rx_rst;
|
||||
|
||||
wire [7:0] qsfp_rx_status;
|
||||
|
||||
wire [1:0] qsfp_gtpowergood;
|
||||
|
||||
wire qsfp_0_mgt_refclk;
|
||||
wire qsfp_0_mgt_refclk_int;
|
||||
wire qsfp_0_mgt_refclk_bufg;
|
||||
|
||||
wire qsfp_rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[8]();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[8]();
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[8]();
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_qsfp_stat[2]();
|
||||
|
||||
if (SIM) begin
|
||||
|
||||
assign qsfp_0_mgt_refclk = qsfp_0_mgt_refclk_p;
|
||||
assign qsfp_0_mgt_refclk_int = qsfp_0_mgt_refclk_p;
|
||||
assign qsfp_0_mgt_refclk_bufg = qsfp_0_mgt_refclk_int;
|
||||
|
||||
end else begin
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
|
||||
.I (qsfp_0_mgt_refclk_p),
|
||||
.IB (qsfp_0_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (qsfp_0_mgt_refclk),
|
||||
.ODIV2 (qsfp_0_mgt_refclk_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_qsfp_0_mgt_refclk_inst (
|
||||
.CE (&qsfp_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (qsfp_0_mgt_refclk_int),
|
||||
.O (qsfp_0_mgt_refclk_bufg)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_sync_reset_inst (
|
||||
.clk(qsfp_0_mgt_refclk_bufg),
|
||||
.rst(rst_125mhz),
|
||||
.out(qsfp_rst)
|
||||
);
|
||||
|
||||
wire [7:0] qsfp_tx_p;
|
||||
wire [7:0] qsfp_tx_n;
|
||||
wire [7:0] qsfp_rx_p = {qsfp_1_rx_p, qsfp_0_rx_p};
|
||||
wire [7:0] qsfp_rx_n = {qsfp_1_rx_n, qsfp_0_rx_n};
|
||||
|
||||
assign qsfp_0_tx_p = qsfp_tx_p[3:0];
|
||||
assign qsfp_0_tx_n = qsfp_tx_n[3:0];
|
||||
assign qsfp_1_tx_p = qsfp_tx_p[7:4];
|
||||
assign qsfp_1_tx_n = qsfp_tx_n[7:4];
|
||||
|
||||
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
|
||||
|
||||
localparam CNT = 4;
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(CNT),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4),
|
||||
.STAT_EN(1'b0)
|
||||
)
|
||||
mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(qsfp_rst),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(qsfp_gtpowergood[n]),
|
||||
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp_tx_p[n*CNT +: CNT]),
|
||||
.xcvr_txn(qsfp_tx_n[n*CNT +: CNT]),
|
||||
.xcvr_rxp(qsfp_rx_p[n*CNT +: CNT]),
|
||||
.xcvr_rxn(qsfp_rx_n[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(qsfp_rx_clk[n*CNT +: CNT]),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]),
|
||||
.tx_clk(qsfp_tx_clk[n*CNT +: CNT]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_qsfp_tx[n*CNT +: CNT]),
|
||||
.m_axis_tx_cpl(axis_qsfp_tx_cpl[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('{CNT{'0}}),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('{CNT{'0}}),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('{CNT{'0}}),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('{CNT{'0}}),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('{CNT{'0}}),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk_125mhz),
|
||||
.stat_rst(rst_125mhz),
|
||||
.m_axis_stat(axis_qsfp_stat[n]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(qsfp_rx_status[n*CNT +: CNT]),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(),
|
||||
.stat_rx_err_bad_block(),
|
||||
.stat_rx_err_framing(),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop('0),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
|
||||
.cfg_tx_ifg('{CNT{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
for (genvar n = 0; n < 8; n = n + 1) begin : qsfp_ch
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(16384),
|
||||
.RAM_PIPELINE(2),
|
||||
.FRAME_FIFO(1),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(1),
|
||||
.DROP_BAD_FRAME(1),
|
||||
.DROP_WHEN_FULL(1)
|
||||
)
|
||||
ch_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(qsfp_rx_clk[n]),
|
||||
.s_rst(qsfp_rx_rst[n]),
|
||||
.s_axis(axis_qsfp_rx[n]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(qsfp_tx_clk[n]),
|
||||
.m_rst(qsfp_tx_rst[n]),
|
||||
.m_axis(axis_qsfp_tx[n]),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
56
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile
Normal file
56
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"virtexuplus\""
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py
Symbolic link
1
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/src/eth/tb/baser.py
|
||||
194
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
Normal file
194
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,194 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Combine
|
||||
|
||||
from cocotbext.eth import XgmiiFrame
|
||||
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp_0_mgt_refclk_p, 6.206, units="ns").start())
|
||||
|
||||
self.qsfp_sources = []
|
||||
self.qsfp_sinks = []
|
||||
|
||||
for inst in dut.gty_quad:
|
||||
for ch in inst.mac_inst.ch:
|
||||
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
|
||||
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())
|
||||
|
||||
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
|
||||
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))
|
||||
|
||||
dut.user_sw.setimmediatevalue(0)
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst_125mhz.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 0
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
|
||||
async def mac_test(tb, source, sink):
|
||||
tb.log.info("Test MAC")
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 32
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("MAC test done")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tests = []
|
||||
|
||||
for k in range(len(tb.qsfp_sources)):
|
||||
tb.log.info("Start QSFP %d MAC loopback test", k)
|
||||
|
||||
tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
|
||||
|
||||
await Combine(*tests)
|
||||
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
|
||||
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
|
||||
os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = "1'b1"
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"virtexuplus\""
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
53
src/eth/example/Alveo/fpga/README.md
Normal file
53
src/eth/example/Alveo/fpga/README.md
Normal file
@@ -0,0 +1,53 @@
|
||||
# Taxi Example Design for Alveo
|
||||
|
||||
## Introduction
|
||||
|
||||
This example design targets the Xilinx Alveo series.
|
||||
|
||||
The design places looped-back MACs on the Ethernet ports, as well as XFCP on the USB UART for monitoring and control.
|
||||
|
||||
* USB UART
|
||||
* XFCP (3 Mbaud)
|
||||
* DSFP/QSFP28
|
||||
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
|
||||
|
||||
## Board details
|
||||
|
||||
* FPGA
|
||||
* AU45N/SN1000: xcu26-vsva1365-2LV-e
|
||||
* AU50: xcu50-fsvh2104-2-e
|
||||
* AU55C: xcu55c-fsvh2892-2L-e
|
||||
* AU55N/C1100: xcu55n-fsvh2892-2L-e
|
||||
* AU200: xcu200-fsgd2104-2-e
|
||||
* AU250: xcu250-fsgd2104-2-e
|
||||
* AU280: xcu280-fsvh2892-2L-e
|
||||
* VCU1525: xcvu9p-fsgd2104-2L-e
|
||||
* X3/X3522: xcux35-vsva1365-3-e
|
||||
* USB UART
|
||||
* AU45N/SN1000: FTDI FT4232H (DMB-2)
|
||||
* AU50: FTDI FT4232H (3 via DMB-1)
|
||||
* AU55C: FTDI FT4232H (2 onboard, all 3 via DMB-1)
|
||||
* AU55N/C1100: FTDI FT4232H (2 onboard, all 3 via DMB-1)
|
||||
* AU200: FTDI FT4232H
|
||||
* AU250: FTDI FT4232H
|
||||
* AU280: FTDI FT4232H
|
||||
* VCU1525: FTDI FT4232H
|
||||
* X3/X3522: FTDI FT4232H (DMB-2)
|
||||
* 25GBASE-R PHY: Soft PCS with GTY transceivers
|
||||
|
||||
## Licensing
|
||||
|
||||
* Toolchain
|
||||
* Vivado Standard (enterprise license not required)
|
||||
* IP
|
||||
* No licensed vendor IP or 3rd party IP
|
||||
|
||||
## How to build
|
||||
|
||||
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
|
||||
|
||||
## How to test
|
||||
|
||||
Run `make program` to program the board with Vivado.
|
||||
|
||||
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
|
||||
153
src/eth/example/Alveo/fpga/common/vivado.mk
Normal file
153
src/eth/example/Alveo/fpga/common/vivado.mk
Normal file
@@ -0,0 +1,153 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016-2025 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - list of source files
|
||||
# INC_FILES - list of include files
|
||||
# XDC_FILES - list of timing constraint files
|
||||
# XCI_FILES - list of IP XCI files
|
||||
# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
|
||||
# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
|
||||
#
|
||||
# Note: both SYN_FILES and INC_FILES support file list files. File list
|
||||
# files are files with a .f extension that contain a list of additional
|
||||
# files to include, one path relative to the .f file location per line.
|
||||
# The .f files are processed recursively, and then the complete file list
|
||||
# is de-duplicated, with later files in the list taking precedence.
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: fpga vivado tmpclean clean distclean
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include $(CONFIG)
|
||||
|
||||
FPGA_TOP ?= fpga
|
||||
PROJECT ?= $(FPGA_TOP)
|
||||
XDC_FILES ?= $(PROJECT).xdc
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
|
||||
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything (fpga)
|
||||
# fpga: build FPGA config
|
||||
# vivado: open project in Vivado
|
||||
# tmpclean: remove intermediate files
|
||||
# clean: remove output files and project files
|
||||
# distclean: remove archived output files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(PROJECT).bit
|
||||
|
||||
vivado: $(PROJECT).xpr
|
||||
vivado $(PROJECT).xpr
|
||||
|
||||
tmpclean::
|
||||
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean:: tmpclean
|
||||
-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
|
||||
|
||||
distclean:: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
|
||||
# create fresh project if Makefile or IP files have changed
|
||||
create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
|
||||
echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
|
||||
echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
|
||||
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
|
||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
# source config TCL scripts if any source file has changed
|
||||
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
||||
echo "open_project -quiet $(PROJECT).xpr" > $@
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
$(PROJECT).xpr: create_project.tcl update_config.tcl
|
||||
vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
|
||||
|
||||
# synthesis run
|
||||
$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
|
||||
echo "open_project $(PROJECT).xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
|
||||
echo "open_project $(PROJECT).xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "open_run impl_1" >> run_impl.tcl
|
||||
echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
|
||||
echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# output files (including potentially bit, bin, ltx, and xsa)
|
||||
$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
|
||||
echo "open_project $(PROJECT).xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
|
||||
echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
|
||||
echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
|
||||
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU200/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU200/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu200-fsgd2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au200.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au200.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU200_10g/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu200-fsgd2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au200.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au200.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU250/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU250/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu250-figd2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au200.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au200.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU250_10g/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu250-figd2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au200.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au200.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU280/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU280/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu280-fsvh2892-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au280.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au280.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU280_10g/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu280-fsvh2892-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au280.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au280.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU45N/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU45N/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu26-vsva1365-2LV-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au45n.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au45n.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU45N_10g/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu26-vsva1365-2LV-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au45n.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au45n.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU50/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU50/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu50-fsvh2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au50.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au50.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU50_10g/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu50-fsvh2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au50.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au50.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU55C/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU55C/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu55c-fsvh2892-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au55.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au55.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU55C_10g/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu55c-fsvh2892-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au55.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au55.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU55N/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU55N/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu55n-fsvh2892-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au55.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au55.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_AU55N_10g/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu55n-fsvh2892-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au55.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au55.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
162
src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile
Normal file
162
src/eth/example/Alveo/fpga/fpga_VCU1525/Makefile
Normal file
@@ -0,0 +1,162 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu9p-fsgd2104-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au200.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au200.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
$(PROJECT)_fallback.bit: $(PROJECT).bit
|
||||
echo "open_project $*.xpr" > generate_fallback_bit.tcl
|
||||
echo "open_run impl_1" >> generate_fallback_bit.tcl
|
||||
echo "startgroup" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.TIMER_CFG 0x03000000 [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT ENABLE [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x04000000 [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "endgroup" >> generate_fallback_bit.tcl
|
||||
echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
|
||||
echo "undo" >> generate_fallback_bit.tcl
|
||||
echo "exit" >> generate_fallback_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
|
||||
mkdir -p rev
|
||||
EXT=bit; COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x04000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
$(PROJECT)_fallback.mcs $(PROJECT)_fallback.prm: $(PROJECT)_fallback.bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x00000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
|
||||
echo "exit" >> generate_fallback_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||
|
||||
$(PROJECT)_full.mcs $(PROJECT)_full.prm: $(PROJECT)_fallback.bit $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x00000000 $*_fallback.bit up 0x04000000 $*.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||
echo "exit" >> generate_full_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
flash%: $(PROJECT)%.mcs $(PROJECT)%.prm
|
||||
echo "open_hw_manager" > flash$*.tcl
|
||||
echo "connect_hw_server" >> flash$*.tcl
|
||||
echo "open_hw_target" >> flash$*.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "exit" >> flash$*.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||
162
src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile
Normal file
162
src/eth/example/Alveo/fpga/fpga_VCU1525_10g/Makefile
Normal file
@@ -0,0 +1,162 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu9p-fsgd2104-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_au200.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_au200.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
$(PROJECT)_fallback.bit: $(PROJECT).bit
|
||||
echo "open_project $*.xpr" > generate_fallback_bit.tcl
|
||||
echo "open_run impl_1" >> generate_fallback_bit.tcl
|
||||
echo "startgroup" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.TIMER_CFG 0x03000000 [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT ENABLE [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x04000000 [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "endgroup" >> generate_fallback_bit.tcl
|
||||
echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
|
||||
echo "undo" >> generate_fallback_bit.tcl
|
||||
echo "exit" >> generate_fallback_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
|
||||
mkdir -p rev
|
||||
EXT=bit; COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x04000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
$(PROJECT)_fallback.mcs $(PROJECT)_fallback.prm: $(PROJECT)_fallback.bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x00000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
|
||||
echo "exit" >> generate_fallback_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||
|
||||
$(PROJECT)_full.mcs $(PROJECT)_full.prm: $(PROJECT)_fallback.bit $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x00000000 $*_fallback.bit up 0x04000000 $*.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||
echo "exit" >> generate_full_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
flash%: $(PROJECT)%.mcs $(PROJECT)%.prm
|
||||
echo "open_hw_manager" > flash$*.tcl
|
||||
echo "connect_hw_server" >> flash$*.tcl
|
||||
echo "open_hw_target" >> flash$*.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "exit" >> flash$*.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_X3522/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_X3522/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcux35-vsva1365-3-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_x3522.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_x3522.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
91
src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile
Normal file
91
src/eth/example/Alveo/fpga/fpga_X3522_10g/Makefile
Normal file
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcux35-vsva1365-3-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga_x3522.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_x3522.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
862
src/eth/example/Alveo/fpga/fpga_au200.xdc
Normal file
862
src/eth/example/Alveo/fpga/fpga_au200.xdc
Normal file
@@ -0,0 +1,862 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for Xilinx AU200/AU250/VCU1525
|
||||
# AU200 part: xcu200-fsgd2104-2-e
|
||||
# AU250 part: xcu250-figd2104-2-e
|
||||
# VCU1525 part: xcvu9p-fsgd2104-2L-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 300 MHz (DDR 0)
|
||||
#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
|
||||
#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p]
|
||||
|
||||
# 300 MHz (DDR 1)
|
||||
#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
|
||||
|
||||
# 300 MHz (DDR 2)
|
||||
#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
|
||||
#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
|
||||
|
||||
# 300 MHz (DDR 3)
|
||||
#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
|
||||
#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p]
|
||||
|
||||
# SI570 user clock
|
||||
#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p]
|
||||
#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n]
|
||||
#create_clock -period 6.400 -name clk_user [get_ports clk_user_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
|
||||
set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
|
||||
set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
|
||||
|
||||
set_false_path -to [get_ports {led[*]}]
|
||||
set_output_delay 0 [get_ports {led[*]}]
|
||||
|
||||
# Reset button
|
||||
set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset]
|
||||
|
||||
set_false_path -from [get_ports {reset}]
|
||||
set_input_delay 0 [get_ports {reset}]
|
||||
|
||||
# DIP switches
|
||||
set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
|
||||
set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
|
||||
set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
|
||||
set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
|
||||
|
||||
set_false_path -from [get_ports {sw[*]}]
|
||||
set_input_delay 0 [get_ports {sw[*]}]
|
||||
|
||||
# UART (U27 FT4232H channel CDBUS)
|
||||
set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# U27.39 CDBUS1 RXD
|
||||
set_property -dict {LOC BF18 IOSTANDARD LVCMOS12} [get_ports uart_rxd] ;# U27.38 CDBUS0 TXD
|
||||
|
||||
set_false_path -to [get_ports {uart_txd}]
|
||||
set_output_delay 0 [get_ports {uart_txd}]
|
||||
set_false_path -from [get_ports {uart_rxd}]
|
||||
set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# BMC
|
||||
#set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}]
|
||||
#set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}]
|
||||
#set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}]
|
||||
#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}]
|
||||
#set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}]
|
||||
#set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}]
|
||||
|
||||
#set_false_path -to [get_ports {msp_uart_txd}]
|
||||
#set_output_delay 0 [get_ports {msp_uart_txd}]
|
||||
#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M11 } [get_ports {qsfp0_mgt_refclk_0_p}] ;# MGTREFCLK0P_231 from U14.4 via U43.13
|
||||
set_property -dict {LOC M10 } [get_ports {qsfp0_mgt_refclk_0_n}] ;# MGTREFCLK0N_231 from U14.5 via U43.14
|
||||
#set_property -dict {LOC K11 } [get_ports {qsfp0_mgt_refclk_1_p}] ;# MGTREFCLK1P_231 from U9.18
|
||||
#set_property -dict {LOC K10 } [get_ports {qsfp0_mgt_refclk_1_n}] ;# MGTREFCLK1N_231 from U9.17
|
||||
set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_modsell}]
|
||||
set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_resetl}]
|
||||
set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {qsfp0_modprsl}]
|
||||
set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {qsfp0_intl}]
|
||||
set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_lpmode}]
|
||||
# set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_refclk_reset}]
|
||||
# set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}]
|
||||
# set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI570)
|
||||
create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports {qsfp0_mgt_refclk_0_p}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01)
|
||||
#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports {qsfp0_mgt_refclk_1_p}]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10)
|
||||
#create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports {qsfp0_mgt_refclk_1_p}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
#set_false_path -to [get_ports {qsfp0_refclk_reset qsfp0_fs[*]}]
|
||||
#set_output_delay 0 [get_ports {qsfp0_refclk_reset qsfp0_fs[*]}]
|
||||
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
|
||||
set_property -dict {LOC T11 } [get_ports {qsfp1_mgt_refclk_0_p}] ;# MGTREFCLK0P_230 from U14.4 via U43.15
|
||||
set_property -dict {LOC T10 } [get_ports {qsfp1_mgt_refclk_0_n}] ;# MGTREFCLK0N_230 from U14.5 via U43.16
|
||||
#set_property -dict {LOC P11 } [get_ports {qsfp1_mgt_refclk_1_p}] ;# MGTREFCLK1P_230 from U12.18
|
||||
#set_property -dict {LOC P10 } [get_ports {qsfp1_mgt_refclk_1_n}] ;# MGTREFCLK1N_230 from U12.17
|
||||
set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_modsell}]
|
||||
set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_resetl}]
|
||||
set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {qsfp1_modprsl}]
|
||||
set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {qsfp1_intl}]
|
||||
set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_lpmode}]
|
||||
# set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_refclk_reset}]
|
||||
# set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}]
|
||||
# set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI570)
|
||||
create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports {qsfp1_mgt_refclk_0_p}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01)
|
||||
#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports {qsfp1_mgt_refclk_1_p}]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10)
|
||||
#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports {qsfp1_mgt_refclk_1_p}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
#set_false_path -to [get_ports {qsfp1_refclk_reset qsfp1_fs[*]}]
|
||||
#set_output_delay 0 [get_ports {qsfp1_refclk_reset qsfp1_fs[*]}]
|
||||
|
||||
# I2C interface
|
||||
#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset]
|
||||
set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
|
||||
set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
|
||||
|
||||
set_false_path -to [get_ports {i2c_sda i2c_scl}]
|
||||
set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||
set_false_path -from [get_ports {i2c_sda i2c_scl}]
|
||||
set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AM11 } [get_ports {pcie_refclk_p}] ;# MGTREFCLK0P_226
|
||||
#set_property -dict {LOC AM10 } [get_ports {pcie_refclk_n}] ;# MGTREFCLK0N_226
|
||||
#set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {pcie_reset_n}]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports {pcie_refclk_p}]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
#set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
#set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
#set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
#set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
#set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
#set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
#set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
#set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
#set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
#set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
#set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
#set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
#set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
#set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
#set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
#set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
#set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
#set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
#set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
#set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
#set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
#set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}]
|
||||
#set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}]
|
||||
#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}]
|
||||
#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}]
|
||||
#set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}]
|
||||
#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}]
|
||||
#set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}]
|
||||
#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}]
|
||||
#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}]
|
||||
#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}]
|
||||
#set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
#set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}]
|
||||
#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}]
|
||||
#set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
#set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
#set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
#set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
#set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
#set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
#set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
#set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
#set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
#set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
#set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
#set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
#set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
#set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
#set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
#set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
#set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
#set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
#set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
#set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
#set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
#set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
#set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
#set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
#set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
#set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
#set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
#set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
#set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
#set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
#set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
#set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
#set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
#set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
#set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
#set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
#set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
#set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
#set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
#set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
#set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
#set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
#set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
#set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
#set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
#set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
#set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
#set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
#set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
#set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
#set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
#set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
#set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
#set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
#set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
#set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
#set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
#set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
#set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
#set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
#set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
#set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
#set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
#set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
#set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
#set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
#set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
#set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
#set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
#set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
#set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
#set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
#set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
#set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
#set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
#set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
#set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
#set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
#set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
#set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
#set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
#set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
#set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
#set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
#set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
#set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
#set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
#set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
#set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
#set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
#set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}]
|
||||
#set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}]
|
||||
#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}]
|
||||
#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}]
|
||||
#set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}]
|
||||
#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}]
|
||||
#set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}]
|
||||
#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}]
|
||||
#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}]
|
||||
#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}]
|
||||
#set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
#set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}]
|
||||
#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}]
|
||||
#set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
#set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
#set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
#set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
#set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
#set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
#set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
#set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
#set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
#set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
#set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
#set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
#set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
#set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
#set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
#set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
#set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
#set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
#set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
#set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
#set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
#set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
#set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
#set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
#set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
#set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
#set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
#set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
#set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
#set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
#set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
#set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
#set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
#set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
#set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
#set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
#set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
#set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
#set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
#set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
#set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
#set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
#set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
#set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
#set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
#set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
#set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
#set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
#set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
#set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
#set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
#set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
#set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
#set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
#set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
#set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
#set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
#set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
#set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
#set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
#set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
#set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
#set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
#set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
#set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
#set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
#set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
#set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
#set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
#set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
#set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
#set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
#set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
#set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
#set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
#set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
#set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
#set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
#set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
#set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
#set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
#set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
#set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
#set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
#set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
#set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
#set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
#set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
#set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
#set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
#set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
#set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
#set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
#set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
|
||||
# DDR4 C2
|
||||
#set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||
#set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||
#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||
#set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||
#set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||
#set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||
#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||
#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||
#set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||
#set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||
#set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||
#set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||
#set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||
#set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||
#set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||
#set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||
#set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||
#set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||
#set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||
#set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||
#set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}]
|
||||
#set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}]
|
||||
#set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}]
|
||||
#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}]
|
||||
#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}]
|
||||
#set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}]
|
||||
#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}]
|
||||
#set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}]
|
||||
#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}]
|
||||
#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}]
|
||||
#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}]
|
||||
#set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||
#set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}]
|
||||
#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}]
|
||||
#set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||
#set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}]
|
||||
|
||||
#set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}]
|
||||
#set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}]
|
||||
#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}]
|
||||
#set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}]
|
||||
#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}]
|
||||
#set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}]
|
||||
#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}]
|
||||
#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}]
|
||||
#set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}]
|
||||
#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}]
|
||||
#set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}]
|
||||
#set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}]
|
||||
#set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}]
|
||||
#set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}]
|
||||
#set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}]
|
||||
#set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}]
|
||||
#set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}]
|
||||
#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}]
|
||||
#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}]
|
||||
#set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}]
|
||||
#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}]
|
||||
#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}]
|
||||
#set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}]
|
||||
#set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}]
|
||||
#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}]
|
||||
#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}]
|
||||
#set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}]
|
||||
#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}]
|
||||
#set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}]
|
||||
#set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}]
|
||||
#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}]
|
||||
#set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}]
|
||||
#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}]
|
||||
#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}]
|
||||
#set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}]
|
||||
#set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}]
|
||||
#set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}]
|
||||
#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}]
|
||||
#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}]
|
||||
#set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}]
|
||||
#set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}]
|
||||
#set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}]
|
||||
#set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}]
|
||||
#set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}]
|
||||
#set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}]
|
||||
#set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}]
|
||||
#set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}]
|
||||
#set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}]
|
||||
#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}]
|
||||
#set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}]
|
||||
#set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}]
|
||||
#set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}]
|
||||
#set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}]
|
||||
#set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}]
|
||||
#set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}]
|
||||
#set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}]
|
||||
#set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}]
|
||||
#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}]
|
||||
#set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}]
|
||||
#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}]
|
||||
#set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}]
|
||||
#set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}]
|
||||
#set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}]
|
||||
#set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}]
|
||||
#set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}]
|
||||
#set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}]
|
||||
#set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}]
|
||||
#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}]
|
||||
#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}]
|
||||
#set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}]
|
||||
#set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}]
|
||||
#set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}]
|
||||
#set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}]
|
||||
#set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}]
|
||||
#set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}]
|
||||
#set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}]
|
||||
#set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}]
|
||||
#set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}]
|
||||
#set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}]
|
||||
#set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}]
|
||||
#set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}]
|
||||
#set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}]
|
||||
#set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}]
|
||||
#set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}]
|
||||
#set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}]
|
||||
#set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}]
|
||||
#set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}]
|
||||
#set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}]
|
||||
#set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}]
|
||||
#set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}]
|
||||
#set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}]
|
||||
#set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}]
|
||||
#set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}]
|
||||
#set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}]
|
||||
#set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}]
|
||||
#set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}]
|
||||
#set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}]
|
||||
#set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}]
|
||||
#set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}]
|
||||
#set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}]
|
||||
#set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}]
|
||||
#set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}]
|
||||
#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}]
|
||||
#set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}]
|
||||
#set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}]
|
||||
#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}]
|
||||
#set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}]
|
||||
#set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}]
|
||||
|
||||
# DDR4 C3
|
||||
#set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}]
|
||||
#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}]
|
||||
#set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}]
|
||||
#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}]
|
||||
#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}]
|
||||
#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}]
|
||||
#set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}]
|
||||
#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}]
|
||||
#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}]
|
||||
#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}]
|
||||
#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}]
|
||||
#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}]
|
||||
#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}]
|
||||
#set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}]
|
||||
#set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}]
|
||||
#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}]
|
||||
#set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}]
|
||||
#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}]
|
||||
#set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}]
|
||||
#set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}]
|
||||
#set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}]
|
||||
#set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}]
|
||||
#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}]
|
||||
#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}]
|
||||
#set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}]
|
||||
#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}]
|
||||
#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}]
|
||||
#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}]
|
||||
#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}]
|
||||
#set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}]
|
||||
#set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}]
|
||||
#set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}]
|
||||
|
||||
#set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}]
|
||||
#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}]
|
||||
#set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}]
|
||||
#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}]
|
||||
#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}]
|
||||
#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}]
|
||||
#set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}]
|
||||
#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}]
|
||||
#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}]
|
||||
#set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}]
|
||||
#set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}]
|
||||
#set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}]
|
||||
#set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}]
|
||||
#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}]
|
||||
#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}]
|
||||
#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}]
|
||||
#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}]
|
||||
#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}]
|
||||
#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}]
|
||||
#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}]
|
||||
#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}]
|
||||
#set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}]
|
||||
#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}]
|
||||
#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}]
|
||||
#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}]
|
||||
#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}]
|
||||
#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}]
|
||||
#set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}]
|
||||
#set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}]
|
||||
#set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}]
|
||||
#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}]
|
||||
#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}]
|
||||
#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}]
|
||||
#set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}]
|
||||
#set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}]
|
||||
#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}]
|
||||
#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}]
|
||||
#set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}]
|
||||
#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}]
|
||||
#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}]
|
||||
#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}]
|
||||
#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}]
|
||||
#set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}]
|
||||
#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}]
|
||||
#set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}]
|
||||
#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}]
|
||||
#set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}]
|
||||
#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}]
|
||||
#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}]
|
||||
#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}]
|
||||
#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}]
|
||||
#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}]
|
||||
#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}]
|
||||
#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}]
|
||||
#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}]
|
||||
#set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}]
|
||||
#set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}]
|
||||
#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}]
|
||||
#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}]
|
||||
#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}]
|
||||
#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}]
|
||||
#set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}]
|
||||
#set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}]
|
||||
#set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}]
|
||||
#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}]
|
||||
#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}]
|
||||
#set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}]
|
||||
#set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}]
|
||||
#set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}]
|
||||
#set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}]
|
||||
#set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}]
|
||||
#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}]
|
||||
#set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}]
|
||||
#set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}]
|
||||
#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}]
|
||||
#set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}]
|
||||
#set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}]
|
||||
#set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}]
|
||||
#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}]
|
||||
#set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}]
|
||||
#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}]
|
||||
#set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}]
|
||||
#set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}]
|
||||
#set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}]
|
||||
#set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}]
|
||||
#set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}]
|
||||
#set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}]
|
||||
#set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}]
|
||||
#set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}]
|
||||
#set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}]
|
||||
#set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}]
|
||||
#set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}]
|
||||
#set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}]
|
||||
#set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}]
|
||||
#set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}]
|
||||
#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}]
|
||||
#set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}]
|
||||
#set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}]
|
||||
#set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}]
|
||||
#set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}]
|
||||
#set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}]
|
||||
#set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}]
|
||||
#set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}]
|
||||
#set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}]
|
||||
#set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}]
|
||||
#set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}]
|
||||
#set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}]
|
||||
#set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}]
|
||||
503
src/eth/example/Alveo/fpga/fpga_au280.xdc
Normal file
503
src/eth/example/Alveo/fpga/fpga_au280.xdc
Normal file
@@ -0,0 +1,503 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Xilinx Alveo U280 board
|
||||
# part: xcu280-fsvh2892-2L-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p]
|
||||
#set_property -dict {LOC F31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_n]
|
||||
#create_clock -period 10 -name clk_100mhz_2 [get_ports clk_100mhz_2_p]
|
||||
|
||||
# SI570 user clock
|
||||
#set_property -dict {LOC G30 IOSTANDARD LVDS} [get_ports clk_si570_p]
|
||||
#set_property -dict {LOC F30 IOSTANDARD LVDS} [get_ports clk_si570_n]
|
||||
#create_clock -period 6.4 -name clk_si570 [get_ports clk_si570_p]
|
||||
|
||||
# Reset button
|
||||
set_property -dict {LOC L30 IOSTANDARD LVCMOS18} [get_ports reset]
|
||||
|
||||
set_false_path -from [get_ports {reset}]
|
||||
set_input_delay 0 [get_ports {reset}]
|
||||
|
||||
# UART (U34 FT4232H channel CDBUS)
|
||||
set_property -dict {LOC B33 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.39 CDBUS1 RXD
|
||||
set_property -dict {LOC A28 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.38 CDBUS0 TXD
|
||||
|
||||
set_false_path -to [get_ports {uart_txd}]
|
||||
set_output_delay 0 [get_ports {uart_txd}]
|
||||
set_false_path -from [get_ports {uart_rxd}]
|
||||
set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# HBM overtemp
|
||||
set_property -dict {LOC D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip]
|
||||
|
||||
set_false_path -to [get_ports {hbm_cattrip}]
|
||||
set_output_delay 0 [get_ports {hbm_cattrip}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC L53 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L54 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L48 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L49 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K51 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K52 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L44 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J53 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J54 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K46 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC K47 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H51 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC H52 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J48 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC J49 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10
|
||||
set_property -dict {LOC T42 } [get_ports {qsfp0_mgt_refclk_0_p}] ;# MGTREFCLK0P_134 from SI570
|
||||
set_property -dict {LOC T43 } [get_ports {qsfp0_mgt_refclk_0_n}] ;# MGTREFCLK0N_134 from SI570
|
||||
#set_property -dict {LOC R40 } [get_ports {qsfp0_mgt_refclk_1_p}] ;# MGTREFCLK1P_134 from SI546
|
||||
#set_property -dict {LOC R41 } [get_ports {qsfp0_mgt_refclk_1_n}] ;# MGTREFCLK1N_134 from SI546
|
||||
set_property -dict {LOC H32 IOSTANDARD LVCMOS18} [get_ports {qsfp0_refclk_oe_b}]
|
||||
set_property -dict {LOC G32 IOSTANDARD LVCMOS18} [get_ports {qsfp0_refclk_fs}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI570)
|
||||
create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports {qsfp0_mgt_refclk_0_p}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI546, fs = 0)
|
||||
#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports {qsfp0_mgt_refclk_1_p}]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (from SI546, fs = 1)
|
||||
#create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports {qsfp0_mgt_refclk_1_p}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}]
|
||||
set_output_delay 0 [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}]
|
||||
|
||||
set_property -dict {LOC G53 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G54 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G48 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC G49 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F51 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC F52 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E48 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E49 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E53 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC E54 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C48 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC C49 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D51 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC D52 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A49 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC A50 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11
|
||||
set_property -dict {LOC P42 } [get_ports {qsfp1_mgt_refclk_0_p}] ;# MGTREFCLK0P_135 from SI570
|
||||
set_property -dict {LOC P43 } [get_ports {qsfp1_mgt_refclk_0_n}] ;# MGTREFCLK0N_135 from SI570
|
||||
#set_property -dict {LOC M42 } [get_ports {qsfp1_mgt_refclk_1_p}] ;# MGTREFCLK1P_135 from SI546
|
||||
#set_property -dict {LOC M43 } [get_ports {qsfp1_mgt_refclk_1_n}] ;# MGTREFCLK1N_135 from SI546
|
||||
set_property -dict {LOC H30 IOSTANDARD LVCMOS18} [get_ports {qsfp1_refclk_oe_b}]
|
||||
set_property -dict {LOC G33 IOSTANDARD LVCMOS18} [get_ports {qsfp1_refclk_fs}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI570)
|
||||
create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports {qsfp1_mgt_refclk_0_p}]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI546, fs = 0)
|
||||
#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports {qsfp1_mgt_refclk_1_p}]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (from SI546, fs = 1)
|
||||
#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports {qsfp1_mgt_refclk_1_p}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp1_refclk_oe_b qsfp1_refclk_fs}]
|
||||
set_output_delay 0 [get_ports {qsfp1_refclk_oe_b qsfp1_refclk_fs}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL11} [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL10} [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN6 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN5 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN11} [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN10} [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR11} [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR10} [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU11} [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU10} [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW6 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW5 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW11} [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW10} [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC BA6 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA5 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA11} [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA10} [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB9 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB8 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC11} [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC10} [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AL15} [get_ports {pcie_refclk_0_p}] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AL14} [get_ports {pcie_refclk_0_n}] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK13} [get_ports {pcie_refclk_2_p}] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK12} [get_ports {pcie_refclk_2_n}] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AR15} [get_ports {pcie_refclk_1_p}] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AR14} [get_ports {pcie_refclk_1_n}] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP13} [get_ports {pcie_refclk_3_p}] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP12} [get_ports {pcie_refclk_3_n}] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC BH26 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {pcie_reset_n}]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports {pcie_refclk_0_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports {pcie_refclk_1_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports {pcie_refclk_2_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports {pcie_refclk_3_p}]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
#set_property -dict {LOC BF46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
#set_property -dict {LOC BG43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
#set_property -dict {LOC BK45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
#set_property -dict {LOC BF42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
#set_property -dict {LOC BL45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
#set_property -dict {LOC BF43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
#set_property -dict {LOC BG42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
#set_property -dict {LOC BL43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
#set_property -dict {LOC BK43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
#set_property -dict {LOC BM42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
#set_property -dict {LOC BG45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
#set_property -dict {LOC BD41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
#set_property -dict {LOC BL42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
#set_property -dict {LOC BE44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
#set_property -dict {LOC BE43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
#set_property -dict {LOC BL46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
#set_property -dict {LOC BH44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
#set_property -dict {LOC BH45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
#set_property -dict {LOC BM47 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
#set_property -dict {LOC BF41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
#set_property -dict {LOC BE41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
#set_property -dict {LOC BH46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t}]
|
||||
#set_property -dict {LOC BJ46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c}]
|
||||
#set_property -dict {LOC BH42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}]
|
||||
#set_property -dict {LOC BK46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}]
|
||||
#set_property -dict {LOC BH41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
#set_property -dict {LOC BG44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}]
|
||||
#set_property -dict {LOC BF45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
#set_property -dict {LOC BG33 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
#set_property -dict {LOC BN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
#set_property -dict {LOC BP32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
#set_property -dict {LOC BL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
#set_property -dict {LOC BM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
#set_property -dict {LOC BP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
#set_property -dict {LOC BP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
#set_property -dict {LOC BP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
#set_property -dict {LOC BN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
#set_property -dict {LOC BJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
#set_property -dict {LOC BH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
#set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
#set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
#set_property -dict {LOC BH29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
#set_property -dict {LOC BH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
#set_property -dict {LOC BF31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
#set_property -dict {LOC BG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
#set_property -dict {LOC BK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
#set_property -dict {LOC BL31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
#set_property -dict {LOC BK33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
#set_property -dict {LOC BL33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
#set_property -dict {LOC BL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
#set_property -dict {LOC BM33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
#set_property -dict {LOC BN34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
#set_property -dict {LOC BP34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
#set_property -dict {LOC BH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
#set_property -dict {LOC BH35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
#set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
#set_property -dict {LOC BJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
#set_property -dict {LOC BJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
#set_property -dict {LOC BG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
#set_property -dict {LOC BG35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
#set_property -dict {LOC BM52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
#set_property -dict {LOC BL53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
#set_property -dict {LOC BL52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
#set_property -dict {LOC BL51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
#set_property -dict {LOC BN50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
#set_property -dict {LOC BN51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
#set_property -dict {LOC BN49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
#set_property -dict {LOC BM48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
#set_property -dict {LOC BE50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
#set_property -dict {LOC BE49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
#set_property -dict {LOC BE51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
#set_property -dict {LOC BD51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
#set_property -dict {LOC BF52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
#set_property -dict {LOC BF51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
#set_property -dict {LOC BG50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
#set_property -dict {LOC BF50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
#set_property -dict {LOC BH50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
#set_property -dict {LOC BJ51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
#set_property -dict {LOC BH51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
#set_property -dict {LOC BH49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
#set_property -dict {LOC BK50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
#set_property -dict {LOC BK51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
#set_property -dict {LOC BJ49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
#set_property -dict {LOC BJ48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
#set_property -dict {LOC BN44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
#set_property -dict {LOC BN45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
#set_property -dict {LOC BM44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
#set_property -dict {LOC BM45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
#set_property -dict {LOC BP43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
#set_property -dict {LOC BP44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
#set_property -dict {LOC BN47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
#set_property -dict {LOC BP47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
#set_property -dict {LOC BG54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
#set_property -dict {LOC BG53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
#set_property -dict {LOC BE53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
#set_property -dict {LOC BE54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
#set_property -dict {LOC BH52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
#set_property -dict {LOC BG52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
#set_property -dict {LOC BK54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
#set_property -dict {LOC BK53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
#set_property -dict {LOC BN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
#set_property -dict {LOC BN30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
#set_property -dict {LOC BM28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
#set_property -dict {LOC BM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
#set_property -dict {LOC BJ29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
#set_property -dict {LOC BK30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
#set_property -dict {LOC BG29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
#set_property -dict {LOC BG30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
#set_property -dict {LOC BL35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
#set_property -dict {LOC BM35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
#set_property -dict {LOC BM34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
#set_property -dict {LOC BN35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
#set_property -dict {LOC BK34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
#set_property -dict {LOC BK35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
#set_property -dict {LOC BH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
#set_property -dict {LOC BJ32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
#set_property -dict {LOC BM49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
#set_property -dict {LOC BM50 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
#set_property -dict {LOC BP48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
#set_property -dict {LOC BP49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
#set_property -dict {LOC BF47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
#set_property -dict {LOC BF48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
#set_property -dict {LOC BG48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
#set_property -dict {LOC BG49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
#set_property -dict {LOC BH47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
#set_property -dict {LOC BJ47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
#set_property -dict {LOC BK48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
#set_property -dict {LOC BK49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
#set_property -dict {LOC BN46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
#set_property -dict {LOC BP46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
#set_property -dict {LOC BN42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
#set_property -dict {LOC BP42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
#set_property -dict {LOC BH54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
#set_property -dict {LOC BJ54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
#set_property -dict {LOC BJ52 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
#set_property -dict {LOC BJ53 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
#set_property -dict {LOC BF7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
#set_property -dict {LOC BK1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
#set_property -dict {LOC BF6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
#set_property -dict {LOC BF5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
#set_property -dict {LOC BE3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
#set_property -dict {LOC BE6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
#set_property -dict {LOC BE5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
#set_property -dict {LOC BG7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
#set_property -dict {LOC BJ1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
#set_property -dict {LOC BG2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
#set_property -dict {LOC BJ8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
#set_property -dict {LOC BE4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
#set_property -dict {LOC BL2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
#set_property -dict {LOC BK5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
#set_property -dict {LOC BK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
#set_property -dict {LOC BJ4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
#set_property -dict {LOC BF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
#set_property -dict {LOC BG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
#set_property -dict {LOC BK4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
#set_property -dict {LOC BF3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
#set_property -dict {LOC BF2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
#set_property -dict {LOC BJ3 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t}]
|
||||
#set_property -dict {LOC BJ2 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c}]
|
||||
#set_property -dict {LOC BE1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
#set_property -dict {LOC BL3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
#set_property -dict {LOC BG3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
#set_property -dict {LOC BH2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
#set_property -dict {LOC BH1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
#set_property -dict {LOC BH12 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
#set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
#set_property -dict {LOC A10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
#set_property -dict {LOC A9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
#set_property -dict {LOC A8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
#set_property -dict {LOC B12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
#set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
#set_property -dict {LOC C12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
#set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
#set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
#set_property -dict {LOC D11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
#set_property -dict {LOC E12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
#set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
#set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
#set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
#set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
#set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
#set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
#set_property -dict {LOC G13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
#set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
#set_property -dict {LOC J11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
#set_property -dict {LOC J12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
#set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
#set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
#set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
#set_property -dict {LOC B15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
#set_property -dict {LOC E14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
#set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
#set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
#set_property -dict {LOC BM3 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
#set_property -dict {LOC BM4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
#set_property -dict {LOC BM5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
#set_property -dict {LOC BL6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
#set_property -dict {LOC BN4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
#set_property -dict {LOC BN5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
#set_property -dict {LOC BN6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
#set_property -dict {LOC BN7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
#set_property -dict {LOC BJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
#set_property -dict {LOC BK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
#set_property -dict {LOC BK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
#set_property -dict {LOC BL10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
#set_property -dict {LOC BM9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
#set_property -dict {LOC BN9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
#set_property -dict {LOC BN10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
#set_property -dict {LOC BM10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
#set_property -dict {LOC BM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
#set_property -dict {LOC BM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
#set_property -dict {LOC BL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
#set_property -dict {LOC BM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
#set_property -dict {LOC BN12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
#set_property -dict {LOC BM12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
#set_property -dict {LOC BP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
#set_property -dict {LOC BP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
#set_property -dict {LOC BJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
#set_property -dict {LOC BJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
#set_property -dict {LOC BH15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
#set_property -dict {LOC BH14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
#set_property -dict {LOC BK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
#set_property -dict {LOC BK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
#set_property -dict {LOC BL12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
#set_property -dict {LOC BL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
#set_property -dict {LOC BE9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
#set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
#set_property -dict {LOC BF10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
#set_property -dict {LOC BE11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
#set_property -dict {LOC BG13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
#set_property -dict {LOC BG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
#set_property -dict {LOC BG9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
#set_property -dict {LOC BG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
#set_property -dict {LOC B13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
#set_property -dict {LOC A13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
#set_property -dict {LOC C10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
#set_property -dict {LOC C9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
#set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
#set_property -dict {LOC D9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
#set_property -dict {LOC H10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
#set_property -dict {LOC G10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
#set_property -dict {LOC H15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
#set_property -dict {LOC G15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
#set_property -dict {LOC K14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
#set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
#set_property -dict {LOC D14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
#set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
#set_property -dict {LOC D12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
#set_property -dict {LOC BL7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
#set_property -dict {LOC BM7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
#set_property -dict {LOC BP7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
#set_property -dict {LOC BP6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
#set_property -dict {LOC BL8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
#set_property -dict {LOC BM8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
#set_property -dict {LOC BP9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
#set_property -dict {LOC BP8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
#set_property -dict {LOC BN15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
#set_property -dict {LOC BN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
#set_property -dict {LOC BP12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
#set_property -dict {LOC BP11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
#set_property -dict {LOC BJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
#set_property -dict {LOC BK13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
#set_property -dict {LOC BJ11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
#set_property -dict {LOC BK11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
#set_property -dict {LOC BF12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
#set_property -dict {LOC BF11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
#set_property -dict {LOC BH10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
#set_property -dict {LOC BH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
222
src/eth/example/Alveo/fpga/fpga_au45n.xdc
Normal file
222
src/eth/example/Alveo/fpga/fpga_au45n.xdc
Normal file
@@ -0,0 +1,222 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Xilinx Alveo U45N/SN1022 board
|
||||
# part: xcu26-vsva1365-2LV-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 72.9 [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
# limit with auxiliary PCIe power input connected
|
||||
set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 300 MHz
|
||||
#set_property -dict {LOC AK23 IOSTANDARD LVDS} [get_ports clk_300mhz_p]
|
||||
#set_property -dict {LOC AL23 IOSTANDARD LVDS} [get_ports clk_300mhz_n]
|
||||
#create_clock -period 10 -name clk_300mhz [get_ports clk_300mhz_p]
|
||||
|
||||
# 300 MHz
|
||||
#set_property -dict {LOC AN27 IOSTANDARD LVDS} [get_ports clk_ddr4_c0_p]
|
||||
#set_property -dict {LOC AN28 IOSTANDARD LVDS} [get_ports clk_ddr4_c0_n]
|
||||
#create_clock -period 10 -name clk_ddr4_c0 [get_ports clk_ddr4_c0_p]
|
||||
|
||||
# 300 MHz
|
||||
#set_property -dict {LOC H34 IOSTANDARD LVDS} [get_ports clk_ddr4_c1_p]
|
||||
#set_property -dict {LOC H35 IOSTANDARD LVDS} [get_ports clk_ddr4_c1_n]
|
||||
#create_clock -period 10 -name clk_ddr4_c1 [get_ports clk_ddr4_c1_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AH24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {card_heart_bit}]
|
||||
set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {card_status_led}]
|
||||
set_property -dict {LOC AM23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_act[0]}]
|
||||
set_property -dict {LOC AM22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_g[0]}]
|
||||
set_property -dict {LOC AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_y[0]}]
|
||||
set_property -dict {LOC AJ25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_act[1]}]
|
||||
set_property -dict {LOC AH25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_g[1]}]
|
||||
set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_y[1]}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
|
||||
set_output_delay 0 [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
|
||||
|
||||
# UART (DMB-2 FT4232H channel CDBUS)
|
||||
set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# DMB-2 U4.39 RXD CDBUS1
|
||||
set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] ;# DMB-2 U4.38 TXD CDBUS0
|
||||
|
||||
set_false_path -to [get_ports {uart_txd}]
|
||||
set_output_delay 0 [get_ports {uart_txd}]
|
||||
set_false_path -from [get_ports {uart_rxd}]
|
||||
set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# BMC
|
||||
#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {suc_gpio[0]}]
|
||||
#set_property -dict {LOC AL18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {suc_gpio[1]}]
|
||||
#set_property -dict {LOC AK21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {suc_uart_txd}]
|
||||
#set_property -dict {LOC AJ21 IOSTANDARD LVCMOS18} [get_ports {suc_uart_rxd}]
|
||||
|
||||
#set_false_path -to [get_ports {suc_uart_txd}]
|
||||
#set_output_delay 0 [get_ports {suc_uart_txd}]
|
||||
#set_false_path -from [get_ports {suc_gpio[*] suc_uart_rxd}]
|
||||
#set_input_delay 0 [get_ports {suc_gpio[*] suc_uart_rxd}]
|
||||
|
||||
# SI5394 (SI5394J-A-GM)
|
||||
# IN0: 20 MHz TCXO
|
||||
# OUT1: 161.1328125 MHz to QSFP GTM and GTY
|
||||
# OUT2: 100 MHz to ...
|
||||
# OUT3: 300 MHz to ...
|
||||
#set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {si5394_rst_b}]
|
||||
#set_property -dict {LOC AH19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_int_b}]
|
||||
#set_property -dict {LOC AJ19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_lol_b}]
|
||||
#set_property -dict {LOC AJ20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_los_b}]
|
||||
|
||||
#set_false_path -to [get_ports {si5394_rst_b}]
|
||||
#set_output_delay 0 [get_ports {si5394_rst_b}]
|
||||
#set_false_path -from [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
#set_input_delay 0 [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
#set_property -dict {LOC A13} [get_ports {qsfp0_rx_p[0]}] ;# MGTMRXP0_234 GTM_DUAL_X0Y1 CH0
|
||||
#set_property -dict {LOC A12} [get_ports {qsfp0_rx_n[0]}] ;# MGTMRXN0_234 GTM_DUAL_X0Y1 CH0
|
||||
#set_property -dict {LOC C15} [get_ports {qsfp0_tx_p[0]}] ;# MGTMTXP0_234 GTM_DUAL_X0Y1 CH0
|
||||
#set_property -dict {LOC C14} [get_ports {qsfp0_tx_n[0]}] ;# MGTMTXN0_234 GTM_DUAL_X0Y1 CH0
|
||||
#set_property -dict {LOC A16} [get_ports {qsfp0_rx_p[1]}] ;# MGTMRXP1_234 GTM_DUAL_X0Y1 CH1
|
||||
#set_property -dict {LOC A15} [get_ports {qsfp0_rx_n[1]}] ;# MGTMRXN1_234 GTM_DUAL_X0Y1 CH1
|
||||
#set_property -dict {LOC C18} [get_ports {qsfp0_tx_p[1]}] ;# MGTMTXP1_234 GTM_DUAL_X0Y1 CH1
|
||||
#set_property -dict {LOC C17} [get_ports {qsfp0_tx_n[1]}] ;# MGTMTXN1_234 GTM_DUAL_X0Y1 CH1
|
||||
#set_property -dict {LOC A7 } [get_ports {qsfp0_rx_p[2]}] ;# MGTMRXP0_233 GTM_DUAL_X0Y0 CH0
|
||||
#set_property -dict {LOC A6 } [get_ports {qsfp0_rx_n[2]}] ;# MGTMRXN0_233 GTM_DUAL_X0Y0 CH0
|
||||
#set_property -dict {LOC C9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTMTXP0_233 GTM_DUAL_X0Y0 CH0
|
||||
#set_property -dict {LOC C8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTMTXN0_233 GTM_DUAL_X0Y0 CH0
|
||||
#set_property -dict {LOC A10} [get_ports {qsfp0_rx_p[3]}] ;# MGTMRXP1_233 GTM_DUAL_X0Y0 CH1
|
||||
#set_property -dict {LOC A9 } [get_ports {qsfp0_rx_n[3]}] ;# MGTMRXN1_233 GTM_DUAL_X0Y0 CH1
|
||||
#set_property -dict {LOC C12} [get_ports {qsfp0_tx_p[3]}] ;# MGTMTXP1_233 GTM_DUAL_X0Y0 CH1
|
||||
#set_property -dict {LOC C11} [get_ports {qsfp0_tx_n[3]}] ;# MGTMTXN1_233 GTM_DUAL_X0Y0 CH1
|
||||
#set_property -dict {LOC G10} [get_ports {qsfp0_mgt_refclk_0_p}] ;# MGTREFCLK0P_234 from SI5394 OUT1 via U16
|
||||
#set_property -dict {LOC G9 } [get_ports {qsfp0_mgt_refclk_0_n}] ;# MGTREFCLK0N_234 from SI5394 OUT1 via U16
|
||||
#set_property -dict {LOC J10} [get_ports {qsfp0_mgt_refclk_1_p}] ;# MGTREFCLK1P_233 from SI5394 OUT1 via U16
|
||||
#set_property -dict {LOC J9 } [get_ports {qsfp0_mgt_refclk_1_n}] ;# MGTREFCLK1N_233 from SI5394 OUT1 via U16
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (SI5394 OUT1 via U16)
|
||||
#create_clock -period 6.206 -name qsfp0_mgt_refclk_0 [get_ports {qsfp0_mgt_refclk_0_p}]
|
||||
#create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports {qsfp0_mgt_refclk_1_p}]
|
||||
|
||||
set_property -dict {LOC K4} [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC K3} [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J7} [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J6} [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J2} [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J1} [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC H5} [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC H4} [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G2} [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G1} [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G7} [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G6} [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E2} [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E1} [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F5} [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F4} [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC P9} [get_ports {qsfp1_mgt_refclk_p}] ;# MGTREFCLK0P_231 from SI5394 OUT1 via U16
|
||||
set_property -dict {LOC P8} [get_ports {qsfp1_mgt_refclk_n}] ;# MGTREFCLK0N_231 from SI5394 OUT1 via U16
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (SI5394 OUT1 via U16)
|
||||
create_clock -period 6.206 -name qsfp1_mgt_refclk [get_ports {qsfp1_mgt_refclk_p}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AF4 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AF3 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AD8 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AD7 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AE6 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AE5 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AG6 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AG5 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AK4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AK3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AH4 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AH3 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AJ6 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AJ5 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AL6 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AL5 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AN6 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AN5 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AP3 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AP8 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU5 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AR6 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AR5 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT8 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT7 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AR10} [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AR9 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU10} [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU9 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT12} [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT11} [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU14} [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU13} [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR14} [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR13} [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT16} [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT15} [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR18} [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR17} [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU18} [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU17} [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT20} [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT19} [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU22} [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU21} [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR22} [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR21} [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AF8 } [get_ports {pcie_refclk_0_p}] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AF7 } [get_ports {pcie_refclk_0_n}] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AE10} [get_ports {pcie_refclk_2_p}] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AE9 } [get_ports {pcie_refclk_2_n}] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AL10} [get_ports {pcie_refclk_1_p}] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AL9 } [get_ports {pcie_refclk_1_n}] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AK8 } [get_ports {pcie_refclk_3_p}] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AK7 } [get_ports {pcie_refclk_3_n}] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AK18 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {pcie_reset_n}]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports {pcie_refclk_0_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports {pcie_refclk_1_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports {pcie_refclk_2_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports {pcie_refclk_3_p}]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
212
src/eth/example/Alveo/fpga/fpga_au50.xdc
Normal file
212
src/eth/example/Alveo/fpga/fpga_au50.xdc
Normal file
@@ -0,0 +1,212 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Xilinx Alveo U50 board
|
||||
# part: xcu50-fsvh2104-2-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
set_operating_conditions -design_power_budget 63
|
||||
|
||||
# System clocks
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC G17 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
#set_property -dict {LOC G16 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC BB18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
#set_property -dict {LOC BC18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC E18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_act]
|
||||
set_property -dict {LOC E16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_stat_g]
|
||||
set_property -dict {LOC F17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_stat_y]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_led_act qsfp_led_stat_g qsfp_led_stat_y}]
|
||||
set_output_delay 0 [get_ports {qsfp_led_act qsfp_led_stat_g qsfp_led_stat_y}]
|
||||
|
||||
# UART (DMB-1 FT4232H)
|
||||
set_property -dict {LOC BE26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}] ;# DMB-1 U9.39 CDBUS1 RXD
|
||||
set_property -dict {LOC BF26 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}] ;# DMB-1 U9.38 CDBUS0 TXD
|
||||
set_property -dict {LOC A17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}] ;# DMB-1 U9.52 DDBUS1 RXD
|
||||
set_property -dict {LOC B15 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}] ;# DMB-1 U9.48 DDBUS0 TXD
|
||||
set_property -dict {LOC A19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}] ;# DMB-1 U18.39 CDBUS1 RXD
|
||||
set_property -dict {LOC A18 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}] ;# DMB-1 U18.38 CDBUS0 TXD
|
||||
|
||||
set_false_path -to [get_ports {uart_txd[*]}]
|
||||
set_output_delay 0 [get_ports {uart_txd[*]}]
|
||||
set_false_path -from [get_ports {uart_rxd[*]}]
|
||||
set_input_delay 0 [get_ports {uart_rxd[*]}]
|
||||
|
||||
# BMC
|
||||
#set_property -dict {LOC C16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}]
|
||||
#set_property -dict {LOC C17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}]
|
||||
#set_property -dict {LOC BB25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}]
|
||||
#set_property -dict {LOC BB26 IOSTANDARD LVCMOS18} [get_ports {msp_uart_rxd}]
|
||||
|
||||
#set_false_path -to [get_ports {msp_uart_txd}]
|
||||
#set_output_delay 0 [get_ports {msp_uart_txd}]
|
||||
#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
|
||||
# HBM overtemp
|
||||
set_property -dict {LOC J18 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip]
|
||||
|
||||
set_false_path -to [get_ports {hbm_cattrip}]
|
||||
set_output_delay 0 [get_ports {hbm_cattrip}]
|
||||
|
||||
# SI5394 (SI5394B-A10605-GM)
|
||||
# I2C address 0x68
|
||||
# IN0: 161.1328125 MHz from qsfp_recclk
|
||||
# OUT0: 161.1328125 MHz to qsfp_mgt_refclk_0
|
||||
# OUT2: 322.265625 MHz to qsfp_mgt_refclk_1
|
||||
# OUT3: 100 MHz to clk_100mhz_0, clk_100mhz_1, pcie_refclk_2, pcie_refclk_3
|
||||
#set_property -dict {LOC F20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {si5394_rst_b}]
|
||||
#set_property -dict {LOC H18 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_int_b}]
|
||||
#set_property -dict {LOC G19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_lol_b}]
|
||||
#set_property -dict {LOC H19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_los_b}]
|
||||
#set_property -dict {LOC J16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports {si5394_sda}]
|
||||
#set_property -dict {LOC L19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports {si5394_scl}]
|
||||
|
||||
#set_false_path -to [get_ports {si5394_rst_b}]
|
||||
#set_output_delay 0 [get_ports {si5394_rst_b}]
|
||||
#set_false_path -from [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
#set_input_delay 0 [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
|
||||
#set_false_path -to [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
#set_output_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
#set_false_path -from [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC J45 } [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J46 } [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D42 } [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC D43 } [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G45 } [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G46 } [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C40 } [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC C41 } [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F43 } [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F44 } [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B42 } [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC B43 } [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E45 } [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E46 } [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A40 } [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC A41 } [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC N36 } [get_ports {qsfp_mgt_refclk_0_p}] ;# MGTREFCLK0P_131 from SI5394 OUT0
|
||||
set_property -dict {LOC N37 } [get_ports {qsfp_mgt_refclk_0_n}] ;# MGTREFCLK0N_131 from SI5394 OUT0
|
||||
#set_property -dict {LOC M38 } [get_ports {qsfp_mgt_refclk_1_p}] ;# MGTREFCLK1P_131 from SI5394 OUT2
|
||||
#set_property -dict {LOC M39 } [get_ports {qsfp_mgt_refclk_1_n}] ;# MGTREFCLK1N_131 from SI5394 OUT2
|
||||
#set_property -dict {LOC F19 IOSTANDARD LVDS} [get_ports {qsfp_recclk_p}] ;# to SI5394 IN0
|
||||
#set_property -dict {LOC F18 IOSTANDARD LVDS} [get_ports {qsfp_recclk_n}] ;# to SI5394 IN0
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (SI5394 OUT0)
|
||||
create_clock -period 6.206 -name qsfp_mgt_refclk_0 [get_ports {qsfp_mgt_refclk_0_p}]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (SI5394 OUT2)
|
||||
#create_clock -period 3.103 -name qsfp_mgt_refclk_1 [get_ports {qsfp_mgt_refclk_1_p}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC Y5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC Y4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AA7 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AA6 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AK4 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AK3 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AB5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AB4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AC7 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AC6 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AD5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AD4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AF5 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AF4 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AE7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AE6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AH5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AH4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AG7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AG6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AJ7 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AJ6 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AL7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AL6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AM9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AM8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AN7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AN6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AP9 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AP8 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BD4 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BD3 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR7 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR6 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BE6 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BE5 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT9 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT8 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AB9 } [get_ports {pcie_refclk_0_p}] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AB8 } [get_ports {pcie_refclk_0_n}] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AA11} [get_ports {pcie_refclk_2_p}] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AA10} [get_ports {pcie_refclk_2_n}] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AF9 } [get_ports {pcie_refclk_1_p}] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AF8 } [get_ports {pcie_refclk_1_n}] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AE11} [get_ports {pcie_refclk_3_p}] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AE10} [get_ports {pcie_refclk_3_n}] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AW27 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {pcie_reset_n}]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports {pcie_refclk_0_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports {pcie_refclk_1_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports {pcie_refclk_2_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports {pcie_refclk_3_p}]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
253
src/eth/example/Alveo/fpga/fpga_au55.xdc
Normal file
253
src/eth/example/Alveo/fpga/fpga_au55.xdc
Normal file
@@ -0,0 +1,253 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Xilinx Alveo U55C/Alveo U55N/Varium C1100 board
|
||||
# U55C part: xcu55c-fsvh2892-2L-e
|
||||
# U55N/C1100 part: xcu55n-fsvh2892-2L-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
#set_operating_conditions -design_power_budget 63
|
||||
|
||||
# System clocks
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC BK10 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
#set_property -dict {LOC BL10 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC BK43 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
#set_property -dict {LOC BK44 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC F24 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p]
|
||||
#set_property -dict {LOC F23 IOSTANDARD LVDS} [get_ports clk_100mhz_2_n]
|
||||
#create_clock -period 10 -name clk_100mhz_2 [get_ports clk_100mhz_2_p]
|
||||
|
||||
# Reset button
|
||||
set_property -dict {LOC BG45 IOSTANDARD LVCMOS18} [get_ports reset]
|
||||
|
||||
set_false_path -from [get_ports {reset}]
|
||||
set_input_delay 0 [get_ports {reset}]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC BL13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_act[0]}]
|
||||
set_property -dict {LOC BK11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_g[0]}]
|
||||
set_property -dict {LOC BJ11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_y[0]}]
|
||||
set_property -dict {LOC BK14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_act[1]}]
|
||||
set_property -dict {LOC BK15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_g[1]}]
|
||||
set_property -dict {LOC BL12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_y[1]}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
|
||||
set_output_delay 0 [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
|
||||
|
||||
# UART (U35 FT4232H/DMB-1 FT4232H)
|
||||
set_property -dict {LOC BJ41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}] ;# U35.39 CDBUS1 RXD / DMB-1 U9.39 CDBUS1 RXD
|
||||
set_property -dict {LOC BK41 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}] ;# U35.38 CDBUS0 TXD / DMB-1 U9.38 CDBUS0 TXD
|
||||
set_property -dict {LOC BN47 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}] ;# U35.52 DDBUS1 RXD / DMB-1 U9.52 DDBUS1 RXD
|
||||
set_property -dict {LOC BP47 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}] ;# U35.48 DDBUS0 TXD / DMB-1 U9.48 DDBUS0 TXD
|
||||
set_property -dict {LOC BL45 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}] ;# DMB-1 U18.39 CDBUS1 RXD
|
||||
set_property -dict {LOC BL46 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}] ;# DMB-1 U18.38 CDBUS0 TXD
|
||||
|
||||
set_false_path -to [get_ports {uart_txd[*]}]
|
||||
set_output_delay 0 [get_ports {uart_txd[*]}]
|
||||
set_false_path -from [get_ports {uart_rxd[*]}]
|
||||
set_input_delay 0 [get_ports {uart_rxd[*]}]
|
||||
|
||||
# BMC
|
||||
#set_property -dict {LOC BE46 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}]
|
||||
#set_property -dict {LOC BH46 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}]
|
||||
#set_property -dict {LOC BF45 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}]
|
||||
#set_property -dict {LOC BF46 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}]
|
||||
#set_property -dict {LOC BH42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}]
|
||||
#set_property -dict {LOC BJ42 IOSTANDARD LVCMOS18} [get_ports {msp_uart_rxd}]
|
||||
|
||||
#set_false_path -to [get_ports {msp_uart_txd}]
|
||||
#set_output_delay 0 [get_ports {msp_uart_txd}]
|
||||
#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
|
||||
# HBM overtemp
|
||||
set_property -dict {LOC BE45 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip]
|
||||
|
||||
set_false_path -to [get_ports {hbm_cattrip}]
|
||||
set_output_delay 0 [get_ports {hbm_cattrip}]
|
||||
|
||||
# SI5394 (SI5394B-A10605-GM)
|
||||
# I2C address 0x68
|
||||
# IN0: 161.1328125 MHz from qsfp_recclk
|
||||
# OUT0: 161.1328125 MHz to qsfp0_mgt_refclk
|
||||
# OUT1: 161.1328125 MHz to qsfp1_mgt_refclk
|
||||
# OUT3: 100 MHz to clk_100mhz_0, clk_100mhz_1, pcie_refclk_2, pcie_refclk_3
|
||||
#set_property -dict {LOC BM8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {si5394_rst_b}]
|
||||
#set_property -dict {LOC BM9 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_int_b}]
|
||||
#set_property -dict {LOC BN10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_lol_b}]
|
||||
#set_property -dict {LOC BM10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_los_b}]
|
||||
#set_property -dict {LOC BN14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports {si5394_sda}]
|
||||
#set_property -dict {LOC BM14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports {si5394_scl}]
|
||||
|
||||
#set_false_path -to [get_ports {si5394_rst_b}]
|
||||
#set_output_delay 0 [get_ports {si5394_rst_b}]
|
||||
#set_false_path -from [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
#set_input_delay 0 [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
|
||||
#set_false_path -to [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
#set_output_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
#set_false_path -from [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC AD51} [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AD52} [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AD46} [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AD47} [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC53} [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC54} [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC44} [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC45} [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC49} [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC50} [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB46} [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB47} [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB51} [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB52} [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA48} [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA49} [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AD42} [get_ports {qsfp0_mgt_refclk_p}] ;# MGTREFCLK0P_130 from SI5394 OUT0
|
||||
set_property -dict {LOC AD43} [get_ports {qsfp0_mgt_refclk_n}] ;# MGTREFCLK0N_130 from SI5394 OUT0
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (SI5394 OUT0)
|
||||
create_clock -period 6.206 -name qsfp0_mgt_refclk [get_ports {qsfp0_mgt_refclk_p}]
|
||||
|
||||
set_property -dict {LOC AA53} [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA54} [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA44} [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA45} [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC Y51 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC Y52 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC Y46 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC Y47 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W53 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W54 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W48 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W49 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC V51 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC V52 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W44 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W45 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB42} [get_ports {qsfp1_mgt_refclk_p}] ;# MGTREFCLK0P_131 from SI5394 OUT1
|
||||
set_property -dict {LOC AB43} [get_ports {qsfp1_mgt_refclk_n}] ;# MGTREFCLK0N_131 from SI5394 OUT1
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (SI5394 OUT1)
|
||||
create_clock -period 6.206 -name qsfp1_mgt_refclk [get_ports {qsfp1_mgt_refclk_p}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL11} [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL10} [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN6 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN5 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN11} [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN10} [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR11} [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR10} [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU11} [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU10} [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW6 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW5 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW11} [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW10} [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC BA6 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA5 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA11} [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA10} [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB9 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB8 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC11} [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC10} [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AL15} [get_ports {pcie_refclk_0_p}] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AL14} [get_ports {pcie_refclk_0_n}] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK13} [get_ports {pcie_refclk_2_p}] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK12} [get_ports {pcie_refclk_2_n}] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AR15} [get_ports {pcie_refclk_1_p}] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AR14} [get_ports {pcie_refclk_1_n}] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP13} [get_ports {pcie_refclk_3_p}] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP12} [get_ports {pcie_refclk_3_n}] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC BF41 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {pcie_reset_n}]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports {pcie_refclk_0_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports {pcie_refclk_1_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports {pcie_refclk_2_p}]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports {pcie_refclk_3_p}]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
|
||||
|
||||
# set_property PACKAGE_PIN BN42 [get_ports "TESTCLK_OUT"] ;# Bank 65 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_RS0_65
|
||||
# set_property IOSTANDARD LVCMOS18 [get_ports "TESTCLK_OUT"] ;# Bank 65 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_RS0_65
|
||||
# set_property PACKAGE_PIN BJ33 [get_ports "PPS_IN_FPGA"] ;# Bank 64 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_64
|
||||
# set_property IOSTANDARD LVCMOS18 [get_ports "PPS_IN_FPGA"] ;# Bank 64 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_64
|
||||
# set_property PACKAGE_PIN BH32 [get_ports "PPS_OUT_FPGA"] ;# Bank 64 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_64
|
||||
# set_property IOSTANDARD LVCMOS18 [get_ports "PPS_OUT_FPGA"] ;# Bank 64 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_64
|
||||
168
src/eth/example/Alveo/fpga/fpga_x3522.xdc
Normal file
168
src/eth/example/Alveo/fpga/fpga_x3522.xdc
Normal file
@@ -0,0 +1,168 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Xilinx Alveo U45N/SN1022 board
|
||||
# part: xcux35-vsva1365-3-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 72.9 [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
set_operating_conditions -design_power_budget 60
|
||||
|
||||
# System clocks
|
||||
# 300 MHz
|
||||
#set_property -dict {LOC AK23 IOSTANDARD LVDS} [get_ports clk_300mhz_p]
|
||||
#set_property -dict {LOC AL23 IOSTANDARD LVDS} [get_ports clk_300mhz_n]
|
||||
#create_clock -period 10 -name clk_300mhz [get_ports clk_300mhz_p]
|
||||
|
||||
# 300 MHz
|
||||
#set_property -dict {LOC AN27 IOSTANDARD LVDS} [get_ports clk_ddr4_p]
|
||||
#set_property -dict {LOC AN28 IOSTANDARD LVDS} [get_ports clk_ddr4_n]
|
||||
#create_clock -period 10 -name clk_ddr4 [get_ports clk_ddr4_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AM23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_r[0]}]
|
||||
set_property -dict {LOC AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_g[0]}]
|
||||
set_property -dict {LOC AM22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_b[0]}]
|
||||
set_property -dict {LOC AN22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_r[1]}]
|
||||
set_property -dict {LOC AN25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_g[1]}]
|
||||
set_property -dict {LOC AP25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_b[1]}]
|
||||
set_property -dict {LOC AH24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_r[2]}]
|
||||
set_property -dict {LOC AK24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_g[2]}]
|
||||
set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_b[2]}]
|
||||
set_property -dict {LOC AJ25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_r[3]}]
|
||||
set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_g[3]}]
|
||||
set_property -dict {LOC AH25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {dsfp_led_b[3]}]
|
||||
|
||||
set_false_path -to [get_ports {dsfp_led_r[*] dsfp_led_g[*] dsfp_led_b[*]}]
|
||||
set_output_delay 0 [get_ports {dsfp_led_r[*] dsfp_led_g[*] dsfp_led_b[*]}]
|
||||
|
||||
# PPS in/out
|
||||
#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18} [get_ports {pps_in}]
|
||||
#set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 8} [get_ports {pps_out}]
|
||||
|
||||
#set_false_path -from [get_ports {pps_in}]
|
||||
#set_input_delay 0 [get_ports {pps_in}]
|
||||
#set_false_path -to [get_ports {pps_out}]
|
||||
#set_output_delay 0 [get_ports {pps_out}]
|
||||
|
||||
# UART (DMB-2 FT4232H channel CDBUS)
|
||||
set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# DMB-2 U4.39 RXD CDBUS1
|
||||
set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] ;# DMB-2 U4.38 TXD CDBUS0
|
||||
|
||||
set_false_path -to [get_ports {uart_txd}]
|
||||
set_output_delay 0 [get_ports {uart_txd}]
|
||||
set_false_path -from [get_ports {uart_rxd}]
|
||||
set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# BMC
|
||||
#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {suc_gpio[0]}]
|
||||
#set_property -dict {LOC AL18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {suc_gpio[1]}]
|
||||
#set_property -dict {LOC AK21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {suc_uart_txd}]
|
||||
#set_property -dict {LOC AJ21 IOSTANDARD LVCMOS18} [get_ports {suc_uart_rxd}]
|
||||
|
||||
#set_false_path -to [get_ports {suc_uart_txd}]
|
||||
#set_output_delay 0 [get_ports {suc_uart_txd}]
|
||||
#set_false_path -from [get_ports {suc_gpio[*] suc_uart_rxd}]
|
||||
#set_input_delay 0 [get_ports {suc_gpio[*] suc_uart_rxd}]
|
||||
|
||||
# SI5394 (SI5394J-A-GM)
|
||||
# IN0: 20 MHz TCXO
|
||||
# OUT1: 161.1328125 MHz to DSFP GTY
|
||||
# OUT2: 100 MHz to ...
|
||||
# OUT3: 300 MHz to ...
|
||||
#set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {si5394_rst_b}]
|
||||
#set_property -dict {LOC AH19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_int_b}]
|
||||
#set_property -dict {LOC AJ19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_lol_b}]
|
||||
#set_property -dict {LOC AJ20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {si5394_los_b}]
|
||||
|
||||
#set_false_path -to [get_ports {si5394_rst_b}]
|
||||
#set_output_delay 0 [get_ports {si5394_rst_b}]
|
||||
#set_false_path -from [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
#set_input_delay 0 [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
|
||||
# DSFP Interfaces
|
||||
set_property -dict {LOC K4} [get_ports {dsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC K3} [get_ports {dsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J7} [get_ports {dsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J6} [get_ports {dsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J2} [get_ports {dsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC J1} [get_ports {dsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC H5} [get_ports {dsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC H4} [get_ports {dsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
|
||||
set_property -dict {LOC G2} [get_ports {dsfp0_rx_p[0]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G1} [get_ports {dsfp0_rx_n[0]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G7} [get_ports {dsfp0_tx_p[0]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC G6} [get_ports {dsfp0_tx_n[0]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E2} [get_ports {dsfp0_rx_p[1]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC E1} [get_ports {dsfp0_rx_n[1]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F5} [get_ports {dsfp0_tx_p[1]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC F4} [get_ports {dsfp0_tx_n[1]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
|
||||
set_property -dict {LOC P9} [get_ports {dsfp_mgt_refclk_p}] ;# MGTREFCLK0P_231 from SI5394 OUT1 via U16
|
||||
set_property -dict {LOC P8} [get_ports {dsfp_mgt_refclk_n}] ;# MGTREFCLK0N_231 from SI5394 OUT1 via U16
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (SI5394 OUT1 via U16)
|
||||
create_clock -period 6.206 -name dsfp_mgt_refclk [get_ports {dsfp_mgt_refclk_p}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AP8 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU5 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AR6 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AR5 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT8 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT7 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AR10} [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AR9 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU10} [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU9 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT12} [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AT11} [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU14} [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU13} [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR14} [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR13} [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT16} [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT15} [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR18} [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR17} [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU18} [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU17} [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT20} [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AT19} [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU22} [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AU21} [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR22} [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AR21} [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AL10} [get_ports {pcie_refclk_p}] ;# MGTREFCLK0P_225
|
||||
#set_property -dict {LOC AL9 } [get_ports {pcie_refclk_n}] ;# MGTREFCLK0N_225
|
||||
#set_property -dict {LOC AK8 } [get_ports {pcie_refclk_p}] ;# MGTREFCLK1P_225
|
||||
#set_property -dict {LOC AK7 } [get_ports {pcie_refclk_n}] ;# MGTREFCLK1N_225
|
||||
#set_property -dict {LOC AK18 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {pcie_reset_n}]
|
||||
#set_property -dict {LOC AM20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {pcie_pwrbrkn_n}]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports {pcie_refclk_p}]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n pcie_pwrbrkn_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n pcie_pwrbrkn_n}]
|
||||
1
src/eth/example/Alveo/fpga/lib/taxi
Symbolic link
1
src/eth/example/Alveo/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../../../
|
||||
280
src/eth/example/Alveo/fpga/rtl/fpga_au200.sv
Normal file
280
src/eth/example/Alveo/fpga/rtl/fpga_au200.sv
Normal file
@@ -0,0 +1,280 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Reset: Push button, active low
|
||||
*/
|
||||
input wire logic reset,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic [3:0] sw,
|
||||
output wire logic [2:0] led,
|
||||
|
||||
/*
|
||||
* I2C for board management
|
||||
*/
|
||||
inout wire logic i2c_scl,
|
||||
inout wire logic i2c_sda,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic uart_txd,
|
||||
input wire logic uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp0_tx_p,
|
||||
output wire logic [3:0] qsfp0_tx_n,
|
||||
input wire logic [3:0] qsfp0_rx_p,
|
||||
input wire logic [3:0] qsfp0_rx_n,
|
||||
input wire logic qsfp0_mgt_refclk_0_p,
|
||||
input wire logic qsfp0_mgt_refclk_0_n,
|
||||
// input wire logic qsfp0_mgt_refclk_1_p,
|
||||
// input wire logic qsfp0_mgt_refclk_1_n,
|
||||
output wire logic qsfp0_modsell,
|
||||
output wire logic qsfp0_resetl,
|
||||
input wire logic qsfp0_modprsl,
|
||||
input wire logic qsfp0_intl,
|
||||
output wire logic qsfp0_lpmode,
|
||||
// output wire logic qsfp0_refclk_reset,
|
||||
// output wire logic [1:0] qsfp0_fs,
|
||||
|
||||
output wire logic [3:0] qsfp1_tx_p,
|
||||
output wire logic [3:0] qsfp1_tx_n,
|
||||
input wire logic [3:0] qsfp1_rx_p,
|
||||
input wire logic [3:0] qsfp1_rx_n,
|
||||
input wire logic qsfp1_mgt_refclk_0_p,
|
||||
input wire logic qsfp1_mgt_refclk_0_n,
|
||||
// input wire logic qsfp1_mgt_refclk_1_p,
|
||||
// input wire logic qsfp1_mgt_refclk_1_n,
|
||||
output wire logic qsfp1_modsell,
|
||||
output wire logic qsfp1_resetl,
|
||||
input wire logic qsfp1_modprsl,
|
||||
input wire logic qsfp1_intl,
|
||||
output wire logic qsfp1_lpmode
|
||||
// output wire logic qsfp1_refclk_reset,
|
||||
// output wire logic [1:0] qsfp1_fs
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_156mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 156.25 MHz input
|
||||
.CLKIN1_PERIOD(6.4),
|
||||
.REF_JITTER1(0.010),
|
||||
// 156.25 MHz input / 1 = 156.25 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(1),
|
||||
// 156.25 MHz PFD * 8 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(8),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 156.25 MHz input
|
||||
.CLKIN1(clk_156mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire [3:0] sw_int;
|
||||
|
||||
taxi_debounce_switch #(
|
||||
.WIDTH(4),
|
||||
.N(4),
|
||||
.RATE(156000)
|
||||
)
|
||||
debounce_switch_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
.in({sw}),
|
||||
.out({sw_int})
|
||||
);
|
||||
|
||||
// SI570 I2C
|
||||
wire i2c_scl_i;
|
||||
wire i2c_scl_o = 1'b1;
|
||||
wire i2c_scl_t = 1'b1;
|
||||
wire i2c_sda_i;
|
||||
wire i2c_sda_o = 1'b1;
|
||||
wire i2c_sda_t = 1'b1;
|
||||
|
||||
assign i2c_scl_i = i2c_scl;
|
||||
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
|
||||
assign i2c_sda_i = i2c_sda;
|
||||
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
|
||||
|
||||
wire qsfp0_mgt_refclk_0;
|
||||
wire qsfp1_mgt_refclk_0;
|
||||
|
||||
assign clk_156mhz_ref_int = qsfp0_mgt_refclk_0;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(3),
|
||||
.UART_CNT(1),
|
||||
.PORT_CNT(2),
|
||||
.GTY_QUAD_CNT(2),
|
||||
.GTY_CNT(2*4),
|
||||
.GTY_CLK_CNT(2)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw(sw_int),
|
||||
.led(led),
|
||||
.port_led_act(),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
|
||||
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
|
||||
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
|
||||
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
|
||||
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_0_p, qsfp0_mgt_refclk_0_p}),
|
||||
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_0_n, qsfp0_mgt_refclk_0_n}),
|
||||
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk_0, qsfp0_mgt_refclk_0}),
|
||||
|
||||
.eth_port_modsell({qsfp1_modsell, qsfp0_modsell}),
|
||||
.eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),
|
||||
.eth_port_modprsl({qsfp1_modprsl, qsfp0_modprsl}),
|
||||
.eth_port_intl({qsfp1_intl, qsfp0_intl}),
|
||||
.eth_port_lpmode({qsfp1_lpmode, qsfp0_lpmode})
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
243
src/eth/example/Alveo/fpga/rtl/fpga_au280.sv
Normal file
243
src/eth/example/Alveo/fpga/rtl/fpga_au280.sv
Normal file
@@ -0,0 +1,243 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Reset: Push button, active low
|
||||
*/
|
||||
input wire logic reset,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic hbm_cattrip,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic uart_txd,
|
||||
input wire logic uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp0_tx_p,
|
||||
output wire logic [3:0] qsfp0_tx_n,
|
||||
input wire logic [3:0] qsfp0_rx_p,
|
||||
input wire logic [3:0] qsfp0_rx_n,
|
||||
input wire logic qsfp0_mgt_refclk_0_p,
|
||||
input wire logic qsfp0_mgt_refclk_0_n,
|
||||
// input wire logic qsfp0_mgt_refclk_1_p,
|
||||
// input wire logic qsfp0_mgt_refclk_1_n,
|
||||
output wire logic qsfp0_refclk_oe_b,
|
||||
output wire logic qsfp0_refclk_fs,
|
||||
|
||||
output wire logic [3:0] qsfp1_tx_p,
|
||||
output wire logic [3:0] qsfp1_tx_n,
|
||||
input wire logic [3:0] qsfp1_rx_p,
|
||||
input wire logic [3:0] qsfp1_rx_n,
|
||||
input wire logic qsfp1_mgt_refclk_0_p,
|
||||
input wire logic qsfp1_mgt_refclk_0_n,
|
||||
// input wire logic qsfp1_mgt_refclk_1_p,
|
||||
// input wire logic qsfp1_mgt_refclk_1_n,
|
||||
output wire logic qsfp1_refclk_oe_b,
|
||||
output wire logic qsfp1_refclk_fs
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_156mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = ~reset;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 156.25 MHz input
|
||||
.CLKIN1_PERIOD(6.4),
|
||||
.REF_JITTER1(0.010),
|
||||
// 156.25 MHz input / 1 = 156.25 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(1),
|
||||
// 156.25 MHz PFD * 8 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(8),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 156.25 MHz input
|
||||
.CLKIN1(clk_156mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign hbm_cattrip = 1'b0;
|
||||
|
||||
assign qsfp0_refclk_oe_b = 1'b0;
|
||||
assign qsfp0_refclk_fs = 1'b1;
|
||||
assign qsfp1_refclk_oe_b = 1'b0;
|
||||
assign qsfp1_refclk_fs = 1'b1;
|
||||
|
||||
wire qsfp0_mgt_refclk_0;
|
||||
wire qsfp1_mgt_refclk_0;
|
||||
|
||||
assign clk_156mhz_ref_int = qsfp0_mgt_refclk_0;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(3),
|
||||
.UART_CNT(1),
|
||||
.PORT_CNT(2),
|
||||
.GTY_QUAD_CNT(2),
|
||||
.GTY_CNT(2*4),
|
||||
.GTY_CLK_CNT(2)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led(),
|
||||
.port_led_act(),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
|
||||
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
|
||||
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
|
||||
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
|
||||
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_0_p, qsfp0_mgt_refclk_0_p}),
|
||||
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_0_n, qsfp0_mgt_refclk_0_n}),
|
||||
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk_0, qsfp0_mgt_refclk_0}),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
229
src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv
Normal file
229
src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv
Normal file
@@ -0,0 +1,229 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter QSFP_CNT = 2,
|
||||
parameter UART_CNT = 1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic card_heart_bit,
|
||||
output wire logic card_status_led,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_act,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_g,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_y,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic [UART_CNT-1:0] uart_txd,
|
||||
input wire logic [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
// output wire logic [3:0] qsfp0_tx_p,
|
||||
// output wire logic [3:0] qsfp0_tx_n,
|
||||
// input wire logic [3:0] qsfp0_rx_p,
|
||||
// input wire logic [3:0] qsfp0_rx_n,
|
||||
// input wire logic qsfp0_mgt_refclk_0_p,
|
||||
// input wire logic qsfp0_mgt_refclk_0_n,
|
||||
// input wire logic qsfp0_mgt_refclk_1_p,
|
||||
// input wire logic qsfp0_mgt_refclk_1_n,
|
||||
|
||||
output wire logic [3:0] qsfp1_tx_p,
|
||||
output wire logic [3:0] qsfp1_tx_n,
|
||||
input wire logic [3:0] qsfp1_rx_p,
|
||||
input wire logic [3:0] qsfp1_rx_n,
|
||||
input wire logic qsfp1_mgt_refclk_p,
|
||||
input wire logic qsfp1_mgt_refclk_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_161mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 161.13 MHz input
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.REF_JITTER1(0.010),
|
||||
// 161.13 MHz input / 11 = 14.65 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(11),
|
||||
// 14.65 MHz PFD * 64 = 937.5 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 937.5 MHz / 7.5 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 161.13 MHz input
|
||||
.CLKIN1(clk_161mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
wire qsfp1_mgt_refclk;
|
||||
|
||||
assign clk_161mhz_ref_int = qsfp1_mgt_refclk;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(2),
|
||||
.UART_CNT(UART_CNT),
|
||||
.PORT_CNT(QSFP_CNT),
|
||||
.GTY_QUAD_CNT(1),
|
||||
.GTY_CNT(1*4),
|
||||
.GTY_CLK_CNT(1)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led({card_heart_bit, card_status_led}),
|
||||
.port_led_act(qsfp_led_act),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(qsfp_led_stat_g),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(qsfp_led_stat_y),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p(qsfp1_tx_p),
|
||||
.eth_gty_tx_n(qsfp1_tx_n),
|
||||
.eth_gty_rx_p(qsfp1_rx_p),
|
||||
.eth_gty_rx_n(qsfp1_rx_n),
|
||||
.eth_gty_mgt_refclk_p(qsfp1_mgt_refclk_p),
|
||||
.eth_gty_mgt_refclk_n(qsfp1_mgt_refclk_n),
|
||||
.eth_gty_mgt_refclk_out(qsfp1_mgt_refclk),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
224
src/eth/example/Alveo/fpga/rtl/fpga_au50.sv
Normal file
224
src/eth/example/Alveo/fpga/rtl/fpga_au50.sv
Normal file
@@ -0,0 +1,224 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter QSFP_CNT = 1,
|
||||
parameter UART_CNT = 3
|
||||
)
|
||||
(
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_act,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_g,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_y,
|
||||
output wire logic hbm_cattrip,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic [UART_CNT-1:0] uart_txd,
|
||||
input wire logic [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp_tx_p,
|
||||
output wire logic [3:0] qsfp_tx_n,
|
||||
input wire logic [3:0] qsfp_rx_p,
|
||||
input wire logic [3:0] qsfp_rx_n,
|
||||
input wire logic qsfp_mgt_refclk_0_p,
|
||||
input wire logic qsfp_mgt_refclk_0_n
|
||||
// input wire logic qsfp_mgt_refclk_1_p,
|
||||
// input wire logic qsfp_mgt_refclk_1_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_161mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 161.13 MHz input
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.REF_JITTER1(0.010),
|
||||
// 161.13 MHz input / 11 = 14.65 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(11),
|
||||
// 14.65 MHz PFD * 64 = 937.5 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 937.5 MHz / 7.5 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 161.13 MHz input
|
||||
.CLKIN1(clk_161mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign hbm_cattrip = 1'b0;
|
||||
|
||||
wire qsfp_mgt_refclk_0;
|
||||
|
||||
assign clk_161mhz_ref_int = qsfp_mgt_refclk_0;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(3),
|
||||
.UART_CNT(UART_CNT),
|
||||
.PORT_CNT(QSFP_CNT),
|
||||
.GTY_QUAD_CNT(QSFP_CNT),
|
||||
.GTY_CNT(QSFP_CNT*4),
|
||||
.GTY_CLK_CNT(QSFP_CNT)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led(),
|
||||
.port_led_act(qsfp_led_act),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(qsfp_led_stat_g),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(qsfp_led_stat_y),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p(qsfp_tx_p),
|
||||
.eth_gty_tx_n(qsfp_tx_n),
|
||||
.eth_gty_rx_p(qsfp_rx_p),
|
||||
.eth_gty_rx_n(qsfp_rx_n),
|
||||
.eth_gty_mgt_refclk_p(qsfp_mgt_refclk_0_p),
|
||||
.eth_gty_mgt_refclk_n(qsfp_mgt_refclk_0_n),
|
||||
.eth_gty_mgt_refclk_out(qsfp_mgt_refclk_0),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
235
src/eth/example/Alveo/fpga/rtl/fpga_au55.sv
Normal file
235
src/eth/example/Alveo/fpga/rtl/fpga_au55.sv
Normal file
@@ -0,0 +1,235 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter QSFP_CNT = 2,
|
||||
parameter UART_CNT = 3
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Reset: Push button, active low
|
||||
*/
|
||||
input wire logic reset,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_act,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_g,
|
||||
output wire logic [QSFP_CNT-1:0] qsfp_led_stat_y,
|
||||
output wire logic hbm_cattrip,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic [UART_CNT-1:0] uart_txd,
|
||||
input wire logic [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp0_tx_p,
|
||||
output wire logic [3:0] qsfp0_tx_n,
|
||||
input wire logic [3:0] qsfp0_rx_p,
|
||||
input wire logic [3:0] qsfp0_rx_n,
|
||||
input wire logic qsfp0_mgt_refclk_p,
|
||||
input wire logic qsfp0_mgt_refclk_n,
|
||||
|
||||
output wire logic [3:0] qsfp1_tx_p,
|
||||
output wire logic [3:0] qsfp1_tx_n,
|
||||
input wire logic [3:0] qsfp1_rx_p,
|
||||
input wire logic [3:0] qsfp1_rx_n,
|
||||
input wire logic qsfp1_mgt_refclk_p,
|
||||
input wire logic qsfp1_mgt_refclk_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_161mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 161.13 MHz input
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.REF_JITTER1(0.010),
|
||||
// 161.13 MHz input / 11 = 14.65 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(11),
|
||||
// 14.65 MHz PFD * 64 = 937.5 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 937.5 MHz / 7.5 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 161.13 MHz input
|
||||
.CLKIN1(clk_161mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign hbm_cattrip = 1'b0;
|
||||
|
||||
wire qsfp0_mgt_refclk;
|
||||
wire qsfp1_mgt_refclk;
|
||||
|
||||
assign clk_161mhz_ref_int = qsfp0_mgt_refclk;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(3),
|
||||
.UART_CNT(UART_CNT),
|
||||
.PORT_CNT(QSFP_CNT),
|
||||
.GTY_QUAD_CNT(QSFP_CNT),
|
||||
.GTY_CNT(QSFP_CNT*4),
|
||||
.GTY_CLK_CNT(QSFP_CNT)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led(),
|
||||
.port_led_act(qsfp_led_act),
|
||||
.port_led_stat_r(),
|
||||
.port_led_stat_g(qsfp_led_stat_g),
|
||||
.port_led_stat_b(),
|
||||
.port_led_stat_y(qsfp_led_stat_y),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
|
||||
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
|
||||
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
|
||||
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
|
||||
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_p, qsfp0_mgt_refclk_p}),
|
||||
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_n, qsfp0_mgt_refclk_n}),
|
||||
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk, qsfp0_mgt_refclk}),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
561
src/eth/example/Alveo/fpga/rtl/fpga_core.sv
Normal file
561
src/eth/example/Alveo/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,561 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter SW_CNT = 4,
|
||||
parameter LED_CNT = 3,
|
||||
parameter UART_CNT = 1,
|
||||
parameter PORT_CNT = 2,
|
||||
parameter PORT_LED_CNT = PORT_CNT,
|
||||
parameter GTY_QUAD_CNT = PORT_CNT,
|
||||
parameter GTY_CNT = GTY_QUAD_CNT*4,
|
||||
parameter GTY_CLK_CNT = GTY_QUAD_CNT
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire clk_125mhz,
|
||||
input wire rst_125mhz,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire [SW_CNT-1:0] sw,
|
||||
output wire [LED_CNT-1:0] led,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_act,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_stat_r,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_stat_g,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_stat_b,
|
||||
output wire [PORT_LED_CNT-1:0] port_led_stat_y,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire [UART_CNT-1:0] uart_txd,
|
||||
input wire [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
output wire logic [GTY_CNT-1:0] eth_gty_tx_p,
|
||||
output wire logic [GTY_CNT-1:0] eth_gty_tx_n,
|
||||
input wire logic [GTY_CNT-1:0] eth_gty_rx_p,
|
||||
input wire logic [GTY_CNT-1:0] eth_gty_rx_n,
|
||||
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p,
|
||||
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n,
|
||||
output wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out,
|
||||
|
||||
output wire logic [PORT_CNT-1:0] eth_port_modsell,
|
||||
output wire logic [PORT_CNT-1:0] eth_port_resetl,
|
||||
input wire logic [PORT_CNT-1:0] eth_port_modprsl,
|
||||
input wire logic [PORT_CNT-1:0] eth_port_intl,
|
||||
output wire logic [PORT_CNT-1:0] eth_port_lpmode
|
||||
);
|
||||
|
||||
// XFCP
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
|
||||
|
||||
taxi_xfcp_if_uart #(
|
||||
.TX_FIFO_DEPTH(512),
|
||||
.RX_FIFO_DEPTH(512)
|
||||
)
|
||||
xfcp_if_uart_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.uart_rxd(uart_rxd[0]),
|
||||
.uart_txd(uart_txd[0]),
|
||||
|
||||
/*
|
||||
* XFCP downstream interface
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_ds),
|
||||
.xfcp_dsp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/3000000))
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
|
||||
|
||||
taxi_xfcp_switch #(
|
||||
.XFCP_ID_STR("Alveo"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR("Taxi example"),
|
||||
.PORTS($size(xfcp_sw_us))
|
||||
)
|
||||
xfcp_sw_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_ds),
|
||||
.xfcp_usp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* XFCP downstream ports
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_sw_ds),
|
||||
.xfcp_dsp_us(xfcp_sw_us)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
|
||||
|
||||
taxi_xfcp_mod_stats #(
|
||||
.XFCP_ID_STR("Statistics"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR(""),
|
||||
.STAT_COUNT_W(64),
|
||||
.STAT_PIPELINE(2)
|
||||
)
|
||||
xfcp_stats_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_sw_ds[0]),
|
||||
.xfcp_usp_us(xfcp_sw_us[0]),
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
.s_axis_stat(axis_stat)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[GTY_QUAD_CNT]();
|
||||
|
||||
taxi_axis_arb_mux #(
|
||||
.S_COUNT($size(axis_eth_stat)),
|
||||
.UPDATE_TID(1'b0),
|
||||
.ARB_ROUND_ROBIN(1'b1),
|
||||
.ARB_LSB_HIGH_PRIO(1'b0)
|
||||
)
|
||||
stat_mux_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* AXI4-Stream inputs (sink)
|
||||
*/
|
||||
.s_axis(axis_eth_stat),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(axis_stat)
|
||||
);
|
||||
|
||||
// Additional UARTs
|
||||
for (genvar n = 1; n < UART_CNT; n = n + 1) begin : uart_ch
|
||||
|
||||
taxi_axis_if #(.DATA_W(8)) axis_uart();
|
||||
|
||||
taxi_uart
|
||||
uart_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis_tx(axis_uart),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis_rx(axis_uart),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.rxd(uart_rxd[n]),
|
||||
.txd(uart_txd[n]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_busy(),
|
||||
.rx_busy(),
|
||||
.rx_overrun_error(),
|
||||
.rx_frame_error(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/115200))
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
// Ethernet
|
||||
assign eth_port_modsell = '1;
|
||||
assign eth_port_resetl = '1;
|
||||
assign eth_port_lpmode = '0;
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_tx_clk;
|
||||
wire [GTY_CNT-1:0] eth_gty_tx_rst;
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_clk;
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_rst;
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_status;
|
||||
|
||||
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
|
||||
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
|
||||
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
|
||||
|
||||
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
|
||||
|
||||
wire eth_gty_mgt_refclk_int;
|
||||
|
||||
if (SIM) begin
|
||||
|
||||
assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n];
|
||||
assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n];
|
||||
assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int;
|
||||
|
||||
end else begin
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst (
|
||||
.I (eth_gty_mgt_refclk_p[n]),
|
||||
.IB (eth_gty_mgt_refclk_n[n]),
|
||||
.CEB (1'b0),
|
||||
.O (eth_gty_mgt_refclk[n]),
|
||||
.ODIV2 (eth_gty_mgt_refclk_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
|
||||
.CE (ð_gty_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (eth_gty_mgt_refclk_int),
|
||||
.O (eth_gty_mgt_refclk_bufg[n])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
assign eth_gty_mgt_refclk_out[n] = eth_gty_mgt_refclk_bufg[n];
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_sync_reset_inst (
|
||||
.clk(eth_gty_mgt_refclk_bufg[n]),
|
||||
.rst(rst_125mhz),
|
||||
.out(eth_gty_rst[n])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"};
|
||||
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"};
|
||||
|
||||
for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
|
||||
|
||||
localparam CLK = n;
|
||||
localparam CNT = 4;
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(CNT),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(n*CNT*(16+16)),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP1 : STAT_PREFIX_STR_QSFP2)
|
||||
)
|
||||
mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(eth_gty_rst[CLK]),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
|
||||
.xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]),
|
||||
.xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]),
|
||||
.xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]),
|
||||
.xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
|
||||
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]),
|
||||
.m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('{CNT{'0}}),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('{CNT{'0}}),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('{CNT{'0}}),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('{CNT{'0}}),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('{CNT{'0}}),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk_125mhz),
|
||||
.stat_rst(rst_125mhz),
|
||||
.m_axis_stat(axis_eth_stat[n]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(eth_gty_rx_status[n*CNT +: CNT]),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(),
|
||||
.stat_rx_err_bad_block(),
|
||||
.stat_rx_err_framing(),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop('0),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
|
||||
.cfg_tx_ifg('{CNT{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
for (genvar n = 0; n < GTY_CNT; n = n + 1) begin : gty_ch
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(16384),
|
||||
.RAM_PIPELINE(2),
|
||||
.FRAME_FIFO(1),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(1),
|
||||
.DROP_BAD_FRAME(1),
|
||||
.DROP_WHEN_FULL(1)
|
||||
)
|
||||
ch_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(eth_gty_rx_clk[n]),
|
||||
.s_rst(eth_gty_rx_rst[n]),
|
||||
.s_axis(eth_gty_axis_rx[n]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(eth_gty_tx_clk[n]),
|
||||
.m_rst(eth_gty_tx_rst[n]),
|
||||
.m_axis(eth_gty_axis_tx[n]),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
222
src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv
Normal file
222
src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv
Normal file
@@ -0,0 +1,222 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter PORT_CNT = 4,
|
||||
parameter UART_CNT = 1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [PORT_CNT-1:0] dsfp_led_r,
|
||||
output wire logic [PORT_CNT-1:0] dsfp_led_g,
|
||||
output wire logic [PORT_CNT-1:0] dsfp_led_b,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire logic [UART_CNT-1:0] uart_txd,
|
||||
input wire logic [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [1:0] dsfp0_tx_p,
|
||||
output wire logic [1:0] dsfp0_tx_n,
|
||||
input wire logic [1:0] dsfp0_rx_p,
|
||||
input wire logic [1:0] dsfp0_rx_n,
|
||||
output wire logic [1:0] dsfp1_tx_p,
|
||||
output wire logic [1:0] dsfp1_tx_n,
|
||||
input wire logic [1:0] dsfp1_rx_p,
|
||||
input wire logic [1:0] dsfp1_rx_n,
|
||||
input wire logic dsfp_mgt_refclk_p,
|
||||
input wire logic dsfp_mgt_refclk_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_161mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 161.13 MHz input
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.REF_JITTER1(0.010),
|
||||
// 161.13 MHz input / 11 = 14.65 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(11),
|
||||
// 14.65 MHz PFD * 64 = 937.5 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 937.5 MHz / 7.5 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 161.13 MHz input
|
||||
.CLKIN1(clk_161mhz_ref_int),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
wire dsfp_mgt_refclk;
|
||||
|
||||
assign clk_161mhz_ref_int = dsfp_mgt_refclk;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SW_CNT(4),
|
||||
.LED_CNT(2),
|
||||
.UART_CNT(UART_CNT),
|
||||
.PORT_CNT(PORT_CNT),
|
||||
.GTY_QUAD_CNT(1),
|
||||
.GTY_CNT(1*4),
|
||||
.GTY_CLK_CNT(1)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw('0),
|
||||
.led(),
|
||||
.port_led_act(),
|
||||
.port_led_stat_r(dsfp_led_r),
|
||||
.port_led_stat_g(dsfp_led_g),
|
||||
.port_led_stat_b(dsfp_led_b),
|
||||
.port_led_stat_y(),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.eth_gty_tx_p({dsfp1_tx_p, dsfp0_tx_p}),
|
||||
.eth_gty_tx_n({dsfp1_tx_n, dsfp0_tx_n}),
|
||||
.eth_gty_rx_p({dsfp1_rx_p, dsfp0_rx_p}),
|
||||
.eth_gty_rx_n({dsfp1_rx_n, dsfp0_rx_n}),
|
||||
.eth_gty_mgt_refclk_p(dsfp_mgt_refclk_p),
|
||||
.eth_gty_mgt_refclk_n(dsfp_mgt_refclk_n),
|
||||
.eth_gty_mgt_refclk_out(dsfp_mgt_refclk),
|
||||
|
||||
.eth_port_modsell(),
|
||||
.eth_port_resetl(),
|
||||
.eth_port_modprsl('0),
|
||||
.eth_port_intl('0),
|
||||
.eth_port_lpmode()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
67
src/eth/example/Alveo/fpga/tb/fpga_core/Makefile
Normal file
67
src/eth/example/Alveo/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,67 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"virtexuplus\""
|
||||
export PARAM_SW_CNT := 4
|
||||
export PARAM_LED_CNT := 3
|
||||
export PARAM_UART_CNT := 1
|
||||
export PARAM_PORT_CNT := 2
|
||||
export PARAM_PORT_LED_CNT := $(PARAM_PORT_CNT)
|
||||
export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT)
|
||||
export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) )))
|
||||
export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT)
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
src/eth/example/Alveo/fpga/tb/fpga_core/baser.py
Symbolic link
1
src/eth/example/Alveo/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/src/eth/tb/baser.py
|
||||
221
src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
Normal file
221
src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,221 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer, Combine
|
||||
|
||||
from cocotbext.eth import XgmiiFrame
|
||||
from cocotbext.uart import UartSource, UartSink
|
||||
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
|
||||
|
||||
self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
|
||||
self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)
|
||||
|
||||
self.qsfp_sources = []
|
||||
self.qsfp_sinks = []
|
||||
|
||||
for inst in dut.gty_quad:
|
||||
for ch in inst.mac_inst.ch:
|
||||
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
|
||||
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())
|
||||
|
||||
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
|
||||
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))
|
||||
|
||||
dut.sw.setimmediatevalue(0)
|
||||
dut.eth_port_modprsl.setimmediatevalue(0)
|
||||
dut.eth_port_intl.setimmediatevalue(0)
|
||||
|
||||
cocotb.start_soon(self._run_refclk())
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst_125mhz.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 0
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
async def _run_refclk(self):
|
||||
t = Timer(3.2, 'ns')
|
||||
val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1
|
||||
while True:
|
||||
self.dut.eth_gty_mgt_refclk_p.value = val
|
||||
await t
|
||||
self.dut.eth_gty_mgt_refclk_p.value = 0
|
||||
await t
|
||||
|
||||
|
||||
async def mac_test(tb, source, sink):
|
||||
tb.log.info("Test MAC")
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 32
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("MAC test done")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tests = []
|
||||
|
||||
for k in range(len(tb.qsfp_sources)):
|
||||
tb.log.info("Start QSFP %d MAC loopback test", k)
|
||||
|
||||
tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
|
||||
|
||||
await Combine(*tests)
|
||||
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
|
||||
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
|
||||
os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = "1'b1"
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"virtexuplus\""
|
||||
parameters['SW_CNT'] = 4
|
||||
parameters['LED_CNT'] = 3
|
||||
parameters['UART_CNT'] = 1
|
||||
parameters['PORT_CNT'] = 2
|
||||
parameters['PORT_LED_CNT'] = parameters['PORT_CNT']
|
||||
parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT']
|
||||
parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4
|
||||
parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT']
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
35
src/eth/example/Arty/fpga/README.md
Normal file
35
src/eth/example/Arty/fpga/README.md
Normal file
@@ -0,0 +1,35 @@
|
||||
# Taxi Example Design for Arty A7
|
||||
|
||||
## Introduction
|
||||
|
||||
This example design targets the Digilent Arty A7 FPGA board.
|
||||
|
||||
The design places a looped-back MAC on the BASE-T port, as well as XFCP on the USB UART for monitoring and control.
|
||||
|
||||
* USB UART
|
||||
* XFCP (3 Mbaud)
|
||||
* RJ-45 Ethernet port with TI DP83848J PHY
|
||||
* Looped-back MAC via MII
|
||||
|
||||
## Board details
|
||||
|
||||
* FPGA: XC7A35TICSG324-1L
|
||||
* USB UART: FTDI FT2232H
|
||||
* PHY: TI DP83848J via MII
|
||||
|
||||
## Licensing
|
||||
|
||||
* Toolchain
|
||||
* Vivado Standard (enterprise license not required)
|
||||
* IP
|
||||
* No licensed vendor IP or 3rd party IP
|
||||
|
||||
## How to build
|
||||
|
||||
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
|
||||
|
||||
## How to test
|
||||
|
||||
Run `make program` to program the board with Vivado.
|
||||
|
||||
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
|
||||
153
src/eth/example/Arty/fpga/common/vivado.mk
Normal file
153
src/eth/example/Arty/fpga/common/vivado.mk
Normal file
@@ -0,0 +1,153 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016-2025 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - list of source files
|
||||
# INC_FILES - list of include files
|
||||
# XDC_FILES - list of timing constraint files
|
||||
# XCI_FILES - list of IP XCI files
|
||||
# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
|
||||
# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
|
||||
#
|
||||
# Note: both SYN_FILES and INC_FILES support file list files. File list
|
||||
# files are files with a .f extension that contain a list of additional
|
||||
# files to include, one path relative to the .f file location per line.
|
||||
# The .f files are processed recursively, and then the complete file list
|
||||
# is de-duplicated, with later files in the list taking precedence.
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: fpga vivado tmpclean clean distclean
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include $(CONFIG)
|
||||
|
||||
FPGA_TOP ?= fpga
|
||||
PROJECT ?= $(FPGA_TOP)
|
||||
XDC_FILES ?= $(PROJECT).xdc
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
|
||||
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything (fpga)
|
||||
# fpga: build FPGA config
|
||||
# vivado: open project in Vivado
|
||||
# tmpclean: remove intermediate files
|
||||
# clean: remove output files and project files
|
||||
# distclean: remove archived output files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(PROJECT).bit
|
||||
|
||||
vivado: $(PROJECT).xpr
|
||||
vivado $(PROJECT).xpr
|
||||
|
||||
tmpclean::
|
||||
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean:: tmpclean
|
||||
-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
|
||||
|
||||
distclean:: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
|
||||
# create fresh project if Makefile or IP files have changed
|
||||
create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
|
||||
echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
|
||||
echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
|
||||
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
|
||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
# source config TCL scripts if any source file has changed
|
||||
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
||||
echo "open_project -quiet $(PROJECT).xpr" > $@
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
$(PROJECT).xpr: create_project.tcl update_config.tcl
|
||||
vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
|
||||
|
||||
# synthesis run
|
||||
$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
|
||||
echo "open_project $(PROJECT).xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
|
||||
echo "open_project $(PROJECT).xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "open_run impl_1" >> run_impl.tcl
|
||||
echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
|
||||
echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# output files (including potentially bit, bin, ltx, and xsa)
|
||||
$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
|
||||
echo "open_project $(PROJECT).xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
|
||||
echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
|
||||
echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
|
||||
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
|
||||
147
src/eth/example/Arty/fpga/fpga.xdc
Normal file
147
src/eth/example/Arty/fpga/fpga.xdc
Normal file
@@ -0,0 +1,147 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Digilent Arty board
|
||||
# part: xc7a35t-csg324-1
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
|
||||
# 100 MHz clock
|
||||
set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports clk]
|
||||
create_clock -period 10.000 -name clk [get_ports clk]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC G6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_r]
|
||||
set_property -dict {LOC F6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_g]
|
||||
set_property -dict {LOC E1 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_b]
|
||||
set_property -dict {LOC G3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_r]
|
||||
set_property -dict {LOC J4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_g]
|
||||
set_property -dict {LOC G4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_b]
|
||||
set_property -dict {LOC J3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_r]
|
||||
set_property -dict {LOC J2 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_g]
|
||||
set_property -dict {LOC H4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_b]
|
||||
set_property -dict {LOC K1 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_r]
|
||||
set_property -dict {LOC H6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_g]
|
||||
set_property -dict {LOC K2 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_b]
|
||||
set_property -dict {LOC H5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led4]
|
||||
set_property -dict {LOC J5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led5]
|
||||
set_property -dict {LOC T9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led6]
|
||||
set_property -dict {LOC T10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led7]
|
||||
|
||||
set_false_path -to [get_ports {led0_r led0_g led0_b led1_r led1_g led1_b led2_r led2_g led2_b led3_r led3_g led3_b led4 led5 led6 led7}]
|
||||
set_output_delay 0 [get_ports {led0_r led0_g led0_b led1_r led1_g led1_b led2_r led2_g led2_b led3_r led3_g led3_b led4 led5 led6 led7}]
|
||||
|
||||
# Reset button
|
||||
# Note: IC8.43 BDBUS4 DTR drives FPGA pin C2 (reset_n) via JP2
|
||||
set_property -dict {LOC C2 IOSTANDARD LVCMOS33} [get_ports reset_n]
|
||||
|
||||
set_false_path -from [get_ports {reset_n}]
|
||||
set_input_delay 0 [get_ports {reset_n}]
|
||||
|
||||
# Push buttons
|
||||
set_property -dict {LOC D9 IOSTANDARD LVCMOS33} [get_ports {btn[0]}]
|
||||
set_property -dict {LOC C9 IOSTANDARD LVCMOS33} [get_ports {btn[1]}]
|
||||
set_property -dict {LOC B9 IOSTANDARD LVCMOS33} [get_ports {btn[2]}]
|
||||
set_property -dict {LOC B8 IOSTANDARD LVCMOS33} [get_ports {btn[3]}]
|
||||
|
||||
set_false_path -from [get_ports {btn[*]}]
|
||||
set_input_delay 0 [get_ports {btn[*]}]
|
||||
|
||||
# Toggle switches
|
||||
set_property -dict {LOC A8 IOSTANDARD LVCMOS33} [get_ports {sw[0]}]
|
||||
set_property -dict {LOC C11 IOSTANDARD LVCMOS33} [get_ports {sw[1]}]
|
||||
set_property -dict {LOC C10 IOSTANDARD LVCMOS33} [get_ports {sw[2]}]
|
||||
set_property -dict {LOC A10 IOSTANDARD LVCMOS33} [get_ports {sw[3]}]
|
||||
|
||||
set_false_path -from [get_ports {sw[*]}]
|
||||
set_input_delay 0 [get_ports {sw[*]}]
|
||||
|
||||
# GPIO
|
||||
# PMOD JA
|
||||
#set_property -dict {LOC G13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja1}] ;# PMOD JA pin 1
|
||||
#set_property -dict {LOC B11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja2}] ;# PMOD JA pin 2
|
||||
#set_property -dict {LOC A11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja3}] ;# PMOD JA pin 3
|
||||
#set_property -dict {LOC D12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja4}] ;# PMOD JA pin 4
|
||||
#set_property -dict {LOC D13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja7}] ;# PMOD JA pin 7
|
||||
#set_property -dict {LOC B18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja8}] ;# PMOD JA pin 8
|
||||
#set_property -dict {LOC A18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja9}] ;# PMOD JA pin 9
|
||||
#set_property -dict {LOC K16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja10}] ;# PMOD JA pin 10
|
||||
# PMOD JB
|
||||
#set_property -dict {LOC E15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb1}] ;# PMOD JB pin 1
|
||||
#set_property -dict {LOC E16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb2}] ;# PMOD JB pin 2
|
||||
#set_property -dict {LOC D15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb3}] ;# PMOD JB pin 3
|
||||
#set_property -dict {LOC C15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb4}] ;# PMOD JB pin 4
|
||||
#set_property -dict {LOC J17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb7}] ;# PMOD JB pin 7
|
||||
#set_property -dict {LOC J18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb8}] ;# PMOD JB pin 8
|
||||
#set_property -dict {LOC K15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb9}] ;# PMOD JB pin 9
|
||||
#set_property -dict {LOC J15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb10}] ;# PMOD JB pin 10
|
||||
# PMOD JC
|
||||
#set_property -dict {LOC U12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc1}] ;# PMOD JC pin 1
|
||||
#set_property -dict {LOC V12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc2}] ;# PMOD JC pin 2
|
||||
#set_property -dict {LOC V10 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc3}] ;# PMOD JC pin 3
|
||||
#set_property -dict {LOC V11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc4}] ;# PMOD JC pin 4
|
||||
#set_property -dict {LOC U14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc7}] ;# PMOD JC pin 7
|
||||
#set_property -dict {LOC V14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc8}] ;# PMOD JC pin 8
|
||||
#set_property -dict {LOC T13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc9}] ;# PMOD JC pin 9
|
||||
#set_property -dict {LOC U13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc10}] ;# PMOD JC pin 10
|
||||
# PMOD JD
|
||||
#set_property -dict {LOC D4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd1}] ;# PMOD JD pin 1
|
||||
#set_property -dict {LOC D3 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd2}] ;# PMOD JD pin 2
|
||||
#set_property -dict {LOC F4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd3}] ;# PMOD JD pin 3
|
||||
#set_property -dict {LOC F3 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd4}] ;# PMOD JD pin 4
|
||||
#set_property -dict {LOC E2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd7}] ;# PMOD JD pin 7
|
||||
#set_property -dict {LOC D2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd8}] ;# PMOD JD pin 8
|
||||
#set_property -dict {LOC H2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd9}] ;# PMOD JD pin 9
|
||||
#set_property -dict {LOC G2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd10}] ;# PMOD JD pin 10
|
||||
|
||||
# UART (IC8 FT2232H BDBUS)
|
||||
# Note: IC8.43 BDBUS4 DTR drives FPGA pin C2 (reset_n) via JP2
|
||||
set_property -dict {LOC D10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports uart_txd] ;# IC8.39 BDBUS1 RXD
|
||||
set_property -dict {LOC A9 IOSTANDARD LVCMOS33} [get_ports uart_rxd] ;# IC8.38 BDBUS0 TXD
|
||||
|
||||
set_false_path -to [get_ports {uart_txd}]
|
||||
set_output_delay 0 [get_ports {uart_txd}]
|
||||
set_false_path -from [get_ports {uart_rxd}]
|
||||
set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# Ethernet MII PHY
|
||||
set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
|
||||
set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
|
||||
set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
|
||||
set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
|
||||
set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
|
||||
set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
|
||||
set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
|
||||
set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
|
||||
set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
|
||||
set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
|
||||
set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
|
||||
set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
|
||||
set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col]
|
||||
set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs]
|
||||
set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
|
||||
set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
|
||||
#set_property -dict {LOC K13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdio]
|
||||
#set_property -dict {LOC F16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
|
||||
|
||||
create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk]
|
||||
create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
|
||||
|
||||
set_false_path -to [get_ports {phy_ref_clk phy_reset_n}]
|
||||
set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}]
|
||||
|
||||
#set_false_path -to [get_ports {phy_mdio phy_mdc}]
|
||||
#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
|
||||
#set_false_path -from [get_ports {phy_mdio}]
|
||||
#set_input_delay 0 [get_ports {phy_mdio}]
|
||||
84
src/eth/example/Arty/fpga/fpga/Makefile
Normal file
84
src/eth/example/Arty/fpga/fpga/Makefile
Normal file
@@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7a35t-csg324-1
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = artix7
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_mii_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql128-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
1
src/eth/example/Arty/fpga/lib/taxi
Symbolic link
1
src/eth/example/Arty/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../../../
|
||||
290
src/eth/example/Arty/fpga/rtl/fpga.sv
Normal file
290
src/eth/example/Arty/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,290 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "artix7"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 100MHz
|
||||
* Reset: Push button, active low
|
||||
*/
|
||||
input wire logic clk,
|
||||
input wire logic reset_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic [3:0] sw,
|
||||
input wire logic [3:0] btn,
|
||||
output wire logic led0_r,
|
||||
output wire logic led0_g,
|
||||
output wire logic led0_b,
|
||||
output wire logic led1_r,
|
||||
output wire logic led1_g,
|
||||
output wire logic led1_b,
|
||||
output wire logic led2_r,
|
||||
output wire logic led2_g,
|
||||
output wire logic led2_b,
|
||||
output wire logic led3_r,
|
||||
output wire logic led3_g,
|
||||
output wire logic led3_b,
|
||||
output wire logic led4,
|
||||
output wire logic led5,
|
||||
output wire logic led6,
|
||||
output wire logic led7,
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
|
||||
/*
|
||||
* Ethernet: 100BASE-T MII
|
||||
*/
|
||||
output wire logic phy_ref_clk,
|
||||
input wire logic phy_rx_clk,
|
||||
input wire logic [3:0] phy_rxd,
|
||||
input wire logic phy_rx_dv,
|
||||
input wire logic phy_rx_er,
|
||||
input wire logic phy_tx_clk,
|
||||
output wire logic [3:0] phy_txd,
|
||||
output wire logic phy_tx_en,
|
||||
input wire logic phy_col,
|
||||
input wire logic phy_crs,
|
||||
output wire logic phy_reset_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_ibufg;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_mmcm_out;
|
||||
wire clk_int;
|
||||
wire rst_int;
|
||||
|
||||
wire mmcm_rst = ~reset_n;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFG
|
||||
clk_ibufg_inst(
|
||||
.I(clk),
|
||||
.O(clk_ibufg)
|
||||
);
|
||||
|
||||
wire clk_25mhz_mmcm_out;
|
||||
wire clk_25mhz_int;
|
||||
|
||||
// MMCM instance
|
||||
MMCME2_BASE #(
|
||||
// 100 MHz input
|
||||
.CLKIN1_PERIOD(10.0),
|
||||
.REF_JITTER1(0.010),
|
||||
// 100 MHz input / 1 = 100 MHz PFD (range 10 MHz to 550 MHz)
|
||||
.DIVCLK_DIVIDE(1),
|
||||
// 100 MHz PFD * 10 = 1000 MHz VCO (range 600 MHz to 1200 MHz)
|
||||
.CLKFBOUT_MULT_F(10),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz VCO / 8 = 128 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(8),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// 1250 MHz VCO / 40 = 25 MHz, 0 degrees
|
||||
.CLKOUT1_DIVIDE(40),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 100 MHz input
|
||||
.CLKIN1(clk_ibufg),
|
||||
// direct clkfb feedback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// 25 MHz, 0 degrees
|
||||
.CLKOUT1(clk_25mhz_mmcm_out),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_bufg_inst (
|
||||
.I(clk_mmcm_out),
|
||||
.O(clk_int)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_25mhz_bufg_inst (
|
||||
.I(clk_25mhz_mmcm_out),
|
||||
.O(clk_25mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_inst (
|
||||
.clk(clk_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire [3:0] btn_int;
|
||||
wire [3:0] sw_int;
|
||||
|
||||
taxi_debounce_switch #(
|
||||
.WIDTH(8),
|
||||
.N(4),
|
||||
.RATE(125000)
|
||||
)
|
||||
debounce_switch_inst (
|
||||
.clk(clk_int),
|
||||
.rst(rst_int),
|
||||
.in({btn,
|
||||
sw}),
|
||||
.out({btn_int,
|
||||
sw_int})
|
||||
);
|
||||
|
||||
wire uart_rxd_int;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(1),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(clk_int),
|
||||
.in({uart_rxd}),
|
||||
.out({uart_rxd_int})
|
||||
);
|
||||
|
||||
assign phy_ref_clk = clk_25mhz_int;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk(clk_int),
|
||||
.rst(rst_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.btn(btn_int),
|
||||
.sw(sw_int),
|
||||
.led0_r(led0_r),
|
||||
.led0_g(led0_g),
|
||||
.led0_b(led0_b),
|
||||
.led1_r(led1_r),
|
||||
.led1_g(led1_g),
|
||||
.led1_b(led1_b),
|
||||
.led2_r(led2_r),
|
||||
.led2_g(led2_g),
|
||||
.led2_b(led2_b),
|
||||
.led3_r(led3_r),
|
||||
.led3_g(led3_g),
|
||||
.led3_b(led3_b),
|
||||
.led4(led4),
|
||||
.led5(led5),
|
||||
.led6(led6),
|
||||
.led7(led7),
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd_int),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* Ethernet: 100BASE-T MII
|
||||
*/
|
||||
.phy_rx_clk(phy_rx_clk),
|
||||
.phy_rxd(phy_rxd),
|
||||
.phy_rx_dv(phy_rx_dv),
|
||||
.phy_rx_er(phy_rx_er),
|
||||
.phy_tx_clk(phy_tx_clk),
|
||||
.phy_txd(phy_txd),
|
||||
.phy_tx_en(phy_tx_en),
|
||||
.phy_col(phy_col),
|
||||
.phy_crs(phy_crs),
|
||||
.phy_reset_n(phy_reset_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
241
src/eth/example/Arty/fpga/rtl/fpga_core.sv
Normal file
241
src/eth/example/Arty/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,241 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "artix7"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic [3:0] btn,
|
||||
input wire logic [3:0] sw,
|
||||
output wire logic led0_r,
|
||||
output wire logic led0_g,
|
||||
output wire logic led0_b,
|
||||
output wire logic led1_r,
|
||||
output wire logic led1_g,
|
||||
output wire logic led1_b,
|
||||
output wire logic led2_r,
|
||||
output wire logic led2_g,
|
||||
output wire logic led2_b,
|
||||
output wire logic led3_r,
|
||||
output wire logic led3_g,
|
||||
output wire logic led3_b,
|
||||
output wire logic led4,
|
||||
output wire logic led5,
|
||||
output wire logic led6,
|
||||
output wire logic led7,
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
|
||||
/*
|
||||
* Ethernet: 100BASE-T MII
|
||||
*/
|
||||
input wire logic phy_rx_clk,
|
||||
input wire logic [3:0] phy_rxd,
|
||||
input wire logic phy_rx_dv,
|
||||
input wire logic phy_rx_er,
|
||||
input wire logic phy_tx_clk,
|
||||
output wire logic [3:0] phy_txd,
|
||||
output wire logic phy_tx_en,
|
||||
input wire logic phy_col,
|
||||
input wire logic phy_crs,
|
||||
output wire logic phy_reset_n
|
||||
);
|
||||
|
||||
assign {led7, led6, led5, led4, led3_g, led2_g, led1_g, led0_g} = {sw, btn};
|
||||
assign phy_reset_n = !rst;
|
||||
|
||||
// XFCP
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
|
||||
|
||||
taxi_xfcp_if_uart #(
|
||||
.TX_FIFO_DEPTH(512),
|
||||
.RX_FIFO_DEPTH(512)
|
||||
)
|
||||
xfcp_if_uart_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.uart_rxd(uart_rxd),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* XFCP downstream interface
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_ds),
|
||||
.xfcp_dsp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/3000000))
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
|
||||
|
||||
taxi_xfcp_switch #(
|
||||
.XFCP_ID_STR("Arty A7"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR("Taxi example"),
|
||||
.PORTS($size(xfcp_sw_us))
|
||||
)
|
||||
xfcp_sw_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_ds),
|
||||
.xfcp_usp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* XFCP downstream ports
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_sw_ds),
|
||||
.xfcp_dsp_us(xfcp_sw_us)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_mac_stat();
|
||||
|
||||
taxi_xfcp_mod_stats #(
|
||||
.XFCP_ID_STR("Statistics"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR(""),
|
||||
.STAT_COUNT_W(64),
|
||||
.STAT_PIPELINE(2)
|
||||
)
|
||||
xfcp_stats_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_sw_ds[0]),
|
||||
.xfcp_usp_us(xfcp_sw_us[0]),
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
.s_axis_stat(axis_mac_stat)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
|
||||
|
||||
taxi_eth_mac_mii_fifo #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(0),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR("MII0"),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.rst(rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_eth),
|
||||
.m_axis_tx_cpl(axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_eth),
|
||||
|
||||
/*
|
||||
* MII interface
|
||||
*/
|
||||
.mii_rx_clk(phy_rx_clk),
|
||||
.mii_rxd(phy_rxd),
|
||||
.mii_rx_dv(phy_rx_dv),
|
||||
.mii_rx_er(phy_rx_er),
|
||||
.mii_tx_clk(phy_tx_clk),
|
||||
.mii_txd(phy_txd),
|
||||
.mii_tx_en(phy_tx_en),
|
||||
.mii_tx_er(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_mac_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(16'd9218),
|
||||
.cfg_tx_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_max_pkt_len(16'd9218),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
58
src/eth/example/Arty/fpga/tb/fpga_core/Makefile
Normal file
58
src/eth/example/Arty/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_mii_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"artix7\""
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
180
src/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
Normal file
180
src/eth/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,180 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Combine
|
||||
|
||||
from cocotbext.eth import GmiiFrame, MiiPhy
|
||||
from cocotbext.uart import UartSource, UartSink
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut, speed=100e6):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
|
||||
|
||||
self.mii_phy = MiiPhy(dut.phy_txd, None, dut.phy_tx_en, dut.phy_tx_clk,
|
||||
dut.phy_rxd, dut.phy_rx_er, dut.phy_rx_dv, dut.phy_rx_clk, speed=speed)
|
||||
|
||||
self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
|
||||
self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)
|
||||
|
||||
dut.phy_crs.setimmediatevalue(0)
|
||||
dut.phy_col.setimmediatevalue(0)
|
||||
|
||||
dut.btn.setimmediatevalue(0)
|
||||
dut.sw.setimmediatevalue(0)
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 0
|
||||
|
||||
|
||||
async def mac_test(tb, phy):
|
||||
tb.log.info("Test MAC")
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await phy.rx.send(GmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await phy.tx.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 32
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await phy.rx.send(GmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await phy.tx.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
tb.log.info("MAC test done")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Start MAC loopback test")
|
||||
|
||||
mac_test_cr = cocotb.start_soon(mac_test(tb, tb.mii_phy))
|
||||
|
||||
await Combine(mac_test_cr)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_mii_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
|
||||
os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = "1'b1"
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"artix7\""
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
35
src/eth/example/HTG940/fpga/README.md
Normal file
35
src/eth/example/HTG940/fpga/README.md
Normal file
@@ -0,0 +1,35 @@
|
||||
# Taxi Example Design for HTG-940
|
||||
|
||||
## Introduction
|
||||
|
||||
This example design targets the HiTech Global HTG-940 FPGA board.
|
||||
|
||||
The design places a looped-back MAC on the BASE-T port, as well as XFCP on the USB UART for monitoring and control.
|
||||
|
||||
* USB UART
|
||||
* XFCP (921600 baud)
|
||||
* RJ-45 Ethernet ports with TI DP83867IRPAP PHY
|
||||
* Looped-back MAC via RGMII
|
||||
|
||||
## Board details
|
||||
|
||||
* FPGA: xcvu9p-flgb2104-2-e
|
||||
* USB UART: Silicon Labs CP2103
|
||||
* 1000BASE-T PHY: TI DP83867IRPAP via RGMII
|
||||
|
||||
## Licensing
|
||||
|
||||
* Toolchain
|
||||
* Vivado Enterprise (requires license)
|
||||
* IP
|
||||
* No licensed vendor IP or 3rd party IP
|
||||
|
||||
## How to build
|
||||
|
||||
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
|
||||
|
||||
## How to test
|
||||
|
||||
Run `make program` to program the board with Vivado.
|
||||
|
||||
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
|
||||
153
src/eth/example/HTG940/fpga/common/vivado.mk
Normal file
153
src/eth/example/HTG940/fpga/common/vivado.mk
Normal file
@@ -0,0 +1,153 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016-2025 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - list of source files
|
||||
# INC_FILES - list of include files
|
||||
# XDC_FILES - list of timing constraint files
|
||||
# XCI_FILES - list of IP XCI files
|
||||
# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
|
||||
# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
|
||||
#
|
||||
# Note: both SYN_FILES and INC_FILES support file list files. File list
|
||||
# files are files with a .f extension that contain a list of additional
|
||||
# files to include, one path relative to the .f file location per line.
|
||||
# The .f files are processed recursively, and then the complete file list
|
||||
# is de-duplicated, with later files in the list taking precedence.
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: fpga vivado tmpclean clean distclean
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include $(CONFIG)
|
||||
|
||||
FPGA_TOP ?= fpga
|
||||
PROJECT ?= $(FPGA_TOP)
|
||||
XDC_FILES ?= $(PROJECT).xdc
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
|
||||
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything (fpga)
|
||||
# fpga: build FPGA config
|
||||
# vivado: open project in Vivado
|
||||
# tmpclean: remove intermediate files
|
||||
# clean: remove output files and project files
|
||||
# distclean: remove archived output files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(PROJECT).bit
|
||||
|
||||
vivado: $(PROJECT).xpr
|
||||
vivado $(PROJECT).xpr
|
||||
|
||||
tmpclean::
|
||||
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean:: tmpclean
|
||||
-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
|
||||
|
||||
distclean:: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
|
||||
# create fresh project if Makefile or IP files have changed
|
||||
create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
|
||||
echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
|
||||
echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
|
||||
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
|
||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
# source config TCL scripts if any source file has changed
|
||||
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
||||
echo "open_project -quiet $(PROJECT).xpr" > $@
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
$(PROJECT).xpr: create_project.tcl update_config.tcl
|
||||
vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
|
||||
|
||||
# synthesis run
|
||||
$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
|
||||
echo "open_project $(PROJECT).xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
|
||||
echo "open_project $(PROJECT).xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "open_run impl_1" >> run_impl.tcl
|
||||
echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
|
||||
echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# output files (including potentially bit, bin, ltx, and xsa)
|
||||
$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
|
||||
echo "open_project $(PROJECT).xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
|
||||
echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
|
||||
echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
|
||||
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
|
||||
15
src/eth/example/HTG940/fpga/eth_rgmii.xdc
Normal file
15
src/eth/example/HTG940/fpga/eth_rgmii.xdc
Normal file
@@ -0,0 +1,15 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# Ethernet constraints
|
||||
|
||||
# IDELAY from PHY chip (RGMII)
|
||||
set_property DELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_bit[*].idelay_inst}]
|
||||
|
||||
# MMCM phase (RGMII)
|
||||
set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
|
||||
122
src/eth/example/HTG940/fpga/fpga.xdc
Normal file
122
src/eth/example/HTG940/fpga/fpga.xdc
Normal file
@@ -0,0 +1,122 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the HiTech Global HTG-9200 board
|
||||
# part: xcvu9p-flgb2104-2-e
|
||||
# part: xcvu13p-fhgb2104-2-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
# System clocks
|
||||
# DDR4 clocks from U37 (200 MHz)
|
||||
#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_p]
|
||||
#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_n]
|
||||
#create_clock -period 5.000 -name sys_clk_ddr4_a [get_ports sys_clk_ddr4_a_p]
|
||||
|
||||
# refclk from U39 (156.25 MHz)
|
||||
set_property -dict {LOC AW28 IOSTANDARD LVDS} [get_ports ref_clk_p]
|
||||
set_property -dict {LOC AY28 IOSTANDARD LVDS} [get_ports ref_clk_n]
|
||||
create_clock -period 6.400 -name ref_clk [get_ports ref_clk_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AP28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
|
||||
set_property -dict {LOC AN28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
|
||||
set_property -dict {LOC AP26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
|
||||
set_property -dict {LOC AP25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
|
||||
set_property -dict {LOC AR28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}]
|
||||
set_property -dict {LOC AR27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}]
|
||||
set_property -dict {LOC AT28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}]
|
||||
set_property -dict {LOC AR25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}]
|
||||
|
||||
set_false_path -to [get_ports {led[*]}]
|
||||
set_output_delay 0 [get_ports {led[*]}]
|
||||
|
||||
# Push buttons
|
||||
set_property -dict {LOC AJ34 IOSTANDARD LVCMOS12} [get_ports {btn[0]}]
|
||||
set_property -dict {LOC AK32 IOSTANDARD LVCMOS12} [get_ports {btn[1]}]
|
||||
|
||||
set_false_path -from [get_ports {btn[*]}]
|
||||
set_input_delay 0 [get_ports {btn[*]}]
|
||||
|
||||
# DIP switches
|
||||
set_property -dict {LOC BF33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
|
||||
set_property -dict {LOC AK27 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
|
||||
set_property -dict {LOC AR32 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
|
||||
set_property -dict {LOC AR31 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
|
||||
set_property -dict {LOC AT32 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
|
||||
set_property -dict {LOC AW30 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
|
||||
set_property -dict {LOC BC32 IOSTANDARD LVCMOS12} [get_ports {sw[6]}]
|
||||
set_property -dict {LOC BC33 IOSTANDARD LVCMOS12} [get_ports {sw[7]}]
|
||||
|
||||
set_false_path -from [get_ports {sw[*]}]
|
||||
set_input_delay 0 [get_ports {sw[*]}]
|
||||
|
||||
# UART (U53 CP2103)
|
||||
set_property -dict {LOC R15 IOSTANDARD LVCMOS18} [get_ports {uart_txd}] ;# U53.25 TXD_O
|
||||
set_property -dict {LOC P15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rxd}] ;# U53.24 RXD_I
|
||||
set_property -dict {LOC L15 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U53.23 RTS_O_B
|
||||
set_property -dict {LOC D14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U53.22 CTS_I_B
|
||||
set_property -dict {LOC P16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_rst_n}] ;# U53.9 RST_B
|
||||
|
||||
set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n}]
|
||||
set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n}]
|
||||
set_false_path -from [get_ports {uart_txd uart_rts}]
|
||||
set_input_delay 0 [get_ports {uart_txd uart_rts}]
|
||||
|
||||
# I2C
|
||||
set_property -dict {LOC AV28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl]
|
||||
set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda]
|
||||
set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n]
|
||||
|
||||
set_false_path -to [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}]
|
||||
set_output_delay 0 [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}]
|
||||
set_false_path -from [get_ports {i2c_main_sda i2c_main_scl}]
|
||||
set_input_delay 0 [get_ports {i2c_main_sda i2c_main_scl}]
|
||||
|
||||
# Gigabit Ethernet RGMII PHY
|
||||
set_property -dict {LOC G20 IOSTANDARD LVCMOS18} [get_ports {phy_rx_clk}] ;# from U2.43 // MAYBE
|
||||
set_property -dict {LOC A20 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# from U2.44
|
||||
set_property -dict {LOC D21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# from U2.45
|
||||
set_property -dict {LOC E21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# from U2.46
|
||||
set_property -dict {LOC C21 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# from U2.47
|
||||
set_property -dict {LOC B21 IOSTANDARD LVCMOS18} [get_ports {phy_rx_ctl}] ;# from U2.53
|
||||
set_property -dict {LOC B20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_clk}] ;# from U2.40
|
||||
set_property -dict {LOC D20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# from U2.38
|
||||
set_property -dict {LOC A19 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# from U2.37
|
||||
set_property -dict {LOC B19 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# from U2.36
|
||||
set_property -dict {LOC E20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# from U2.35
|
||||
set_property -dict {LOC G21 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_ctl}] ;# from U2.52
|
||||
#set_property -dict {LOC G19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdio}] ;# from U2.21
|
||||
#set_property -dict {LOC A18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdc}] ;# from U2.20
|
||||
|
||||
create_clock -period 8.000 -name {phy_rx_clk} [get_ports {phy_rx_clk}]
|
||||
|
||||
#set_false_path -to [get_ports {phy_mdio phy_mdc}]
|
||||
#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
|
||||
#set_false_path -from [get_ports {phy_mdio}]
|
||||
#set_input_delay 0 [get_ports {phy_mdio}]
|
||||
|
||||
# QSPI flash
|
||||
#set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}]
|
||||
#set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}]
|
||||
#set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[2]}]
|
||||
#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}]
|
||||
#set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}]
|
||||
|
||||
#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_false_path -from [get_ports {qspi_1_dq}]
|
||||
#set_input_delay 0 [get_ports {qspi_1_dq}]
|
||||
92
src/eth/example/HTG940/fpga/fpga_vu13p/Makefile
Normal file
92
src/eth/example/HTG940/fpga/fpga_vu13p/Makefile
Normal file
@@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu13p-fhgb2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += ../eth_rgmii.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
#IP_TCL_FILES += ../ip/eth_xcvr_gt.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT)_primary.mcs\" \"$(PROJECT)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)_primary.prm\" \"$(PROJECT)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
92
src/eth/example/HTG940/fpga/fpga_vu9p/Makefile
Normal file
92
src/eth/example/HTG940/fpga/fpga_vu9p/Makefile
Normal file
@@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu9p-flgb2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += ../eth_rgmii.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
#IP_TCL_FILES += ../ip/eth_xcvr_gt.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(PROJECT)_secondary.prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT)_primary.mcs\" \"$(PROJECT)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)_primary.prm\" \"$(PROJECT)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
1
src/eth/example/HTG940/fpga/lib/taxi
Symbolic link
1
src/eth/example/HTG940/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../../../
|
||||
373
src/eth/example/HTG940/fpga/rtl/fpga.sv
Normal file
373
src/eth/example/HTG940/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,373 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "zynquplus",
|
||||
// Use 90 degree clock for RGMII transmit
|
||||
parameter logic USE_CLK90 = 1'b0
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 156.25 MHz LVDS
|
||||
*/
|
||||
input wire logic ref_clk_p,
|
||||
input wire logic ref_clk_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic [1:0] btn,
|
||||
input wire logic [7:0] sw,
|
||||
output wire logic [7:0] led,
|
||||
|
||||
/*
|
||||
* I2C for board management
|
||||
*/
|
||||
inout wire logic i2c_main_scl,
|
||||
inout wire logic i2c_main_sda,
|
||||
output wire logic i2c_main_rst_n,
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
output wire logic uart_rxd,
|
||||
input wire logic uart_txd,
|
||||
input wire logic uart_rts,
|
||||
output wire logic uart_cts,
|
||||
output wire logic uart_rst_n,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T RGMII
|
||||
*/
|
||||
input wire logic phy_rx_clk,
|
||||
input wire logic [3:0] phy_rxd,
|
||||
input wire logic phy_rx_ctl,
|
||||
output wire logic phy_tx_clk,
|
||||
output wire logic [3:0] phy_txd,
|
||||
output wire logic phy_tx_ctl
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire ref_clk_ibufg;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk90_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire clk90_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
// Internal 312.5 MHz clock
|
||||
wire clk_312mhz_mmcm_out;
|
||||
wire clk_312mhz_int;
|
||||
wire rst_312mhz_int;
|
||||
|
||||
wire mmcm_rst = ~btn[0];
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFGDS #(
|
||||
.DIFF_TERM("FALSE"),
|
||||
.IBUF_LOW_PWR("FALSE")
|
||||
)
|
||||
ref_clk_ibufg_inst (
|
||||
.O (ref_clk_ibufg),
|
||||
.I (ref_clk_p),
|
||||
.IB (ref_clk_n)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 156.25 MHz input
|
||||
.CLKIN1_PERIOD(6.4),
|
||||
.REF_JITTER1(0.010),
|
||||
// 156.25 MHz input / 1 = 156.25 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(1),
|
||||
// 156.25 MHz PFD * 8 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(8),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 90 degrees
|
||||
.CLKOUT1_DIVIDE(10),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(90),
|
||||
// 1250 MHz / 4 = 312.5 MHz, 0 degrees
|
||||
.CLKOUT2_DIVIDE(4),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 156.25 MHz input
|
||||
.CLKIN1(ref_clk_ibufg),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// 125 MHz, 90 degrees
|
||||
.CLKOUT1(clk90_125mhz_mmcm_out),
|
||||
.CLKOUT1B(),
|
||||
// 312.5 MHz, 0 degrees
|
||||
.CLKOUT2(clk_312mhz_mmcm_out),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk90_125mhz_bufg_inst (
|
||||
.I(clk90_125mhz_mmcm_out),
|
||||
.O(clk90_125mhz_int)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_312mhz_bufg_inst (
|
||||
.I(clk_312mhz_mmcm_out),
|
||||
.O(clk_312mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_312mhz_inst (
|
||||
.clk(clk_312mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_312mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire btn_int;
|
||||
wire [7:0] sw_int;
|
||||
|
||||
taxi_debounce_switch #(
|
||||
.WIDTH(9),
|
||||
.N(4),
|
||||
.RATE(125000)
|
||||
)
|
||||
debounce_switch_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
.in({btn[1],
|
||||
~sw}),
|
||||
.out({btn_int,
|
||||
sw_int})
|
||||
);
|
||||
|
||||
wire uart_txd_int;
|
||||
wire uart_rts_int;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(2),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.in({uart_txd, uart_rts}),
|
||||
.out({uart_txd_int, uart_rts_int})
|
||||
);
|
||||
|
||||
wire i2c_scl_i;
|
||||
wire i2c_scl_o;
|
||||
wire i2c_scl_t;
|
||||
wire i2c_sda_i;
|
||||
wire i2c_sda_o;
|
||||
wire i2c_sda_t;
|
||||
|
||||
assign i2c_scl_i = i2c_main_scl;
|
||||
assign i2c_main_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
|
||||
assign i2c_sda_i = i2c_main_sda;
|
||||
assign i2c_main_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
|
||||
assign i2c_main_rst_n = 1'b1;
|
||||
|
||||
// IODELAY elements for RGMII interface to PHY
|
||||
wire [3:0] phy_rxd_int;
|
||||
wire phy_rx_ctl_int;
|
||||
|
||||
IDELAYCTRL #(
|
||||
.SIM_DEVICE("ULTRASCALE")
|
||||
)
|
||||
idelayctrl_inst (
|
||||
.REFCLK(clk_312mhz_int),
|
||||
.RST(rst_312mhz_int),
|
||||
.RDY()
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit
|
||||
|
||||
IDELAYE3 #(
|
||||
.DELAY_SRC("IDATAIN"),
|
||||
.CASCADE("NONE"),
|
||||
.DELAY_TYPE("FIXED"),
|
||||
.DELAY_VALUE(0),
|
||||
.REFCLK_FREQUENCY(312.5),
|
||||
.DELAY_FORMAT("TIME"),
|
||||
.UPDATE_MODE("SYNC"),
|
||||
.SIM_DEVICE("ULTRASCALE_PLUS")
|
||||
)
|
||||
idelay_inst (
|
||||
.CASC_IN(1'b0),
|
||||
.CASC_RETURN(1'b0),
|
||||
.CASC_OUT(),
|
||||
.IDATAIN(phy_rxd[n]),
|
||||
.DATAIN(1'b0),
|
||||
.DATAOUT(phy_rxd_int[n]),
|
||||
.CLK(1'b0),
|
||||
.EN_VTC(1'b1),
|
||||
.CE(1'b0),
|
||||
.INC(1'b0),
|
||||
.LOAD(1'b0),
|
||||
.RST(1'b0),
|
||||
.CNTVALUEIN(9'd0),
|
||||
.CNTVALUEOUT()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
IDELAYE3 #(
|
||||
.DELAY_SRC("IDATAIN"),
|
||||
.CASCADE("NONE"),
|
||||
.DELAY_TYPE("FIXED"),
|
||||
.DELAY_VALUE(0),
|
||||
.REFCLK_FREQUENCY(312.5),
|
||||
.DELAY_FORMAT("TIME"),
|
||||
.UPDATE_MODE("SYNC"),
|
||||
.SIM_DEVICE("ULTRASCALE_PLUS")
|
||||
)
|
||||
phy_rx_ctl_idelay (
|
||||
.CASC_IN(1'b0),
|
||||
.CASC_RETURN(1'b0),
|
||||
.CASC_OUT(),
|
||||
.IDATAIN(phy_rx_ctl),
|
||||
.DATAIN(1'b0),
|
||||
.DATAOUT(phy_rx_ctl_int),
|
||||
.CLK(1'b0),
|
||||
.EN_VTC(1'b1),
|
||||
.CE(1'b0),
|
||||
.INC(1'b0),
|
||||
.LOAD(1'b0),
|
||||
.RST(1'b0),
|
||||
.CNTVALUEIN(9'd0),
|
||||
.CNTVALUEOUT()
|
||||
);
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.USE_CLK90(USE_CLK90)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk(clk_125mhz_int),
|
||||
.clk90(clk90_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.btn(btn_int),
|
||||
.sw(sw_int),
|
||||
.led(led),
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd),
|
||||
.uart_txd(uart_txd_int),
|
||||
.uart_rts(uart_rts_int),
|
||||
.uart_cts(uart_cts),
|
||||
.uart_rst_n(uart_rst_n),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T RGMII
|
||||
*/
|
||||
.phy_rgmii_rx_clk(phy_rx_clk),
|
||||
.phy_rgmii_rxd(phy_rxd),
|
||||
.phy_rgmii_rx_ctl(phy_rx_ctl),
|
||||
.phy_rgmii_tx_clk(phy_tx_clk),
|
||||
.phy_rgmii_txd(phy_txd),
|
||||
.phy_rgmii_tx_ctl(phy_tx_ctl)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
233
src/eth/example/HTG940/fpga/rtl/fpga_core.sv
Normal file
233
src/eth/example/HTG940/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,233 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "zynquplus",
|
||||
// Use 90 degree clock for RGMII transmit
|
||||
parameter logic USE_CLK90 = 1'b1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk,
|
||||
input wire logic clk90,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic btn,
|
||||
input wire logic [7:0] sw,
|
||||
output wire logic [7:0] led,
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
output wire logic uart_rxd,
|
||||
input wire logic uart_txd,
|
||||
input wire logic uart_rts,
|
||||
output wire logic uart_cts,
|
||||
output wire logic uart_rst_n,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T RGMII
|
||||
*/
|
||||
input wire logic phy_rgmii_rx_clk,
|
||||
input wire logic [3:0] phy_rgmii_rxd,
|
||||
input wire logic phy_rgmii_rx_ctl,
|
||||
output wire logic phy_rgmii_tx_clk,
|
||||
output wire logic [3:0] phy_rgmii_txd,
|
||||
output wire logic phy_rgmii_tx_ctl
|
||||
);
|
||||
|
||||
assign led = sw;
|
||||
|
||||
// XFCP
|
||||
assign uart_cts = 1'b1;
|
||||
assign uart_rst_n = 1'b1;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
|
||||
|
||||
taxi_xfcp_if_uart #(
|
||||
.TX_FIFO_DEPTH(512),
|
||||
.RX_FIFO_DEPTH(512)
|
||||
)
|
||||
xfcp_if_uart_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.uart_rxd(uart_txd),
|
||||
.uart_txd(uart_rxd),
|
||||
|
||||
/*
|
||||
* XFCP downstream interface
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_ds),
|
||||
.xfcp_dsp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/921600))
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
|
||||
|
||||
taxi_xfcp_switch #(
|
||||
.XFCP_ID_STR("HTG940"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR("Taxi example"),
|
||||
.PORTS($size(xfcp_sw_us))
|
||||
)
|
||||
xfcp_sw_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_ds),
|
||||
.xfcp_usp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* XFCP downstream ports
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_sw_ds),
|
||||
.xfcp_dsp_us(xfcp_sw_us)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_mac_stat();
|
||||
|
||||
taxi_xfcp_mod_stats #(
|
||||
.XFCP_ID_STR("Statistics"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR(""),
|
||||
.STAT_COUNT_W(64),
|
||||
.STAT_PIPELINE(2)
|
||||
)
|
||||
xfcp_stats_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_sw_ds[0]),
|
||||
.xfcp_usp_us(xfcp_sw_us[0]),
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
.s_axis_stat(axis_mac_stat)
|
||||
);
|
||||
|
||||
// BASE-T PHY
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
|
||||
|
||||
taxi_eth_mac_1g_rgmii_fifo #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.USE_CLK90(USE_CLK90),
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(0),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR("RGMII0"),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.gtx_clk(clk),
|
||||
.gtx_clk90(clk90),
|
||||
.gtx_rst(rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_eth),
|
||||
.m_axis_tx_cpl(axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_eth),
|
||||
|
||||
/*
|
||||
* RGMII interface
|
||||
*/
|
||||
.rgmii_rx_clk(phy_rgmii_rx_clk),
|
||||
.rgmii_rxd(phy_rgmii_rxd),
|
||||
.rgmii_rx_ctl(phy_rgmii_rx_ctl),
|
||||
.rgmii_tx_clk(phy_rgmii_tx_clk),
|
||||
.rgmii_txd(phy_rgmii_txd),
|
||||
.rgmii_tx_ctl(phy_rgmii_tx_ctl),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_mac_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
.link_speed(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(16'd9218),
|
||||
.cfg_tx_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_max_pkt_len(16'd9218),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
58
src/eth/example/HTG940/fpga/tb/fpga_core/Makefile
Normal file
58
src/eth/example/HTG940/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"virtexuplus\""
|
||||
export PARAM_USE_CLK90 := "1'b1"
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
186
src/eth/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py
Normal file
186
src/eth/example/HTG940/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,186 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer, Combine
|
||||
|
||||
from cocotbext.eth import GmiiFrame, RgmiiPhy
|
||||
from cocotbext.uart import UartSource, UartSink
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut, speed=1000e6):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
self.baset_phy = RgmiiPhy(dut.phy_rgmii_txd, dut.phy_rgmii_tx_ctl, dut.phy_rgmii_tx_clk,
|
||||
dut.phy_rgmii_rxd, dut.phy_rgmii_rx_ctl, dut.phy_rgmii_rx_clk, speed=speed)
|
||||
|
||||
self.uart_source = UartSource(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
|
||||
self.uart_sink = UartSink(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
|
||||
|
||||
cocotb.start_soon(self._run_clk())
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 0
|
||||
|
||||
async def _run_clk(self):
|
||||
t = Timer(2, 'ns')
|
||||
while True:
|
||||
self.dut.clk.value = 1
|
||||
await t
|
||||
self.dut.clk90.value = 1
|
||||
await t
|
||||
self.dut.clk.value = 0
|
||||
await t
|
||||
self.dut.clk90.value = 0
|
||||
await t
|
||||
|
||||
|
||||
async def mac_test(tb, source, sink):
|
||||
tb.log.info("Test MAC")
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(GmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 32
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(GmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
tb.log.info("MAC test done")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Start BASE-T MAC loopback test")
|
||||
|
||||
phy_test_cr = cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx))
|
||||
|
||||
await Combine(phy_test_cr)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = "1'b1"
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"virtexuplus\""
|
||||
parameters['USE_CLK90'] = "1'b1"
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
52
src/eth/example/KC705/fpga/README.md
Normal file
52
src/eth/example/KC705/fpga/README.md
Normal file
@@ -0,0 +1,52 @@
|
||||
# Taxi Example Design for KC705
|
||||
|
||||
## Introduction
|
||||
|
||||
This example design targets the Xilinx KC705 FPGA board.
|
||||
|
||||
The design places looped-back MACs on both the BASE-T port and the SFP+ cage, as well as XFCP on the USB UART for monitoring and control.
|
||||
|
||||
* USB UART
|
||||
* XFCP (921600 baud)
|
||||
* RJ-45 Ethernet port with Marvell 88E1111 PHY
|
||||
* Looped-back MAC via GMII
|
||||
* Looped-back MAC via RGMII
|
||||
* Looped-back MAC via SGMII via Xilinx PCS/PMA core and GTX transceiver
|
||||
* SFP+ cage
|
||||
* Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTX transceiver
|
||||
|
||||
## Board details
|
||||
|
||||
* FPGA: XC7K325T-2FFG900C
|
||||
* USB UART: Silicon Labs CP2103
|
||||
* 1000BASE-T PHY: Marvell 88E1111 via GMII, RGMII, or SGMII
|
||||
* 1000BASE-X PHY: Xilinx PCS/PMA core via GTX transceiver
|
||||
|
||||
## Licensing
|
||||
|
||||
* Toolchain
|
||||
* Vivado Enterprise (requires license)
|
||||
* IP
|
||||
* No licensed vendor IP or 3rd party IP
|
||||
|
||||
## How to build
|
||||
|
||||
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
|
||||
|
||||
## Board configuration
|
||||
|
||||
Several jumpers must be configured to configure the PHY chip for the appropriate mode.
|
||||
|
||||
| Mode | J29 | J30 | J64 |
|
||||
| -------- | ---- | ---- | ---- |
|
||||
| GMII/MII | 1-2 | 1-2 | open |
|
||||
| RGMII | 1-2 | open | 1-2 |
|
||||
| SGMII | 2-3 | 2-3 | open |
|
||||
|
||||
Also, note that version 1.0 of the KC705 has the SFP+ TX and RX connections polarity-inverted. Version 1.1 has this fixed. This setting is controlled via a top-level parameter setting that is configurable via config.tcl, so ensure to use a design matching the board revision.
|
||||
|
||||
## How to test
|
||||
|
||||
Run `make program` to program the board with Vivado.
|
||||
|
||||
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
|
||||
153
src/eth/example/KC705/fpga/common/vivado.mk
Normal file
153
src/eth/example/KC705/fpga/common/vivado.mk
Normal file
@@ -0,0 +1,153 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016-2025 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - list of source files
|
||||
# INC_FILES - list of include files
|
||||
# XDC_FILES - list of timing constraint files
|
||||
# XCI_FILES - list of IP XCI files
|
||||
# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
|
||||
# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
|
||||
#
|
||||
# Note: both SYN_FILES and INC_FILES support file list files. File list
|
||||
# files are files with a .f extension that contain a list of additional
|
||||
# files to include, one path relative to the .f file location per line.
|
||||
# The .f files are processed recursively, and then the complete file list
|
||||
# is de-duplicated, with later files in the list taking precedence.
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: fpga vivado tmpclean clean distclean
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include $(CONFIG)
|
||||
|
||||
FPGA_TOP ?= fpga
|
||||
PROJECT ?= $(FPGA_TOP)
|
||||
XDC_FILES ?= $(PROJECT).xdc
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
|
||||
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything (fpga)
|
||||
# fpga: build FPGA config
|
||||
# vivado: open project in Vivado
|
||||
# tmpclean: remove intermediate files
|
||||
# clean: remove output files and project files
|
||||
# distclean: remove archived output files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(PROJECT).bit
|
||||
|
||||
vivado: $(PROJECT).xpr
|
||||
vivado $(PROJECT).xpr
|
||||
|
||||
tmpclean::
|
||||
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean:: tmpclean
|
||||
-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
|
||||
|
||||
distclean:: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
|
||||
# create fresh project if Makefile or IP files have changed
|
||||
create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
|
||||
echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
|
||||
echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
|
||||
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
|
||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
# source config TCL scripts if any source file has changed
|
||||
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
||||
echo "open_project -quiet $(PROJECT).xpr" > $@
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
$(PROJECT).xpr: create_project.tcl update_config.tcl
|
||||
vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
|
||||
|
||||
# synthesis run
|
||||
$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
|
||||
echo "open_project $(PROJECT).xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
|
||||
echo "open_project $(PROJECT).xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "open_run impl_1" >> run_impl.tcl
|
||||
echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
|
||||
echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# output files (including potentially bit, bin, ltx, and xsa)
|
||||
$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
|
||||
echo "open_project $(PROJECT).xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
|
||||
echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
|
||||
echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
|
||||
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
|
||||
12
src/eth/example/KC705/fpga/eth_gmii.xdc
Normal file
12
src/eth/example/KC705/fpga/eth_gmii.xdc
Normal file
@@ -0,0 +1,12 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# Ethernet constraints
|
||||
|
||||
# BUFGMUX outputs (GMII)
|
||||
set_clock_groups -physically_exclusive -group clk_mmcm_out -group phy_tx_clk
|
||||
15
src/eth/example/KC705/fpga/eth_rgmii.xdc
Normal file
15
src/eth/example/KC705/fpga/eth_rgmii.xdc
Normal file
@@ -0,0 +1,15 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# Ethernet constraints
|
||||
|
||||
# IDELAY from PHY chip (RGMII)
|
||||
set_property IDELAY_VALUE 0 [get_cells {phy_if.phy_rx_ctl_idelay phy_if.phy_rxd_idelay_bit[*].idelay_inst}]
|
||||
|
||||
# MMCM phase (RGMII)
|
||||
set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
|
||||
198
src/eth/example/KC705/fpga/fpga.xdc
Normal file
198
src/eth/example/KC705/fpga/fpga.xdc
Normal file
@@ -0,0 +1,198 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Xilinx KC705 board
|
||||
# part: xc7k325tffg900-2
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 2.5 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
|
||||
# System clocks
|
||||
# 200 MHz system clock
|
||||
set_property -dict {LOC AD12 IOSTANDARD LVDS} [get_ports clk_200mhz_p] ;# from SiT9102 U6.4
|
||||
set_property -dict {LOC AD11 IOSTANDARD LVDS} [get_ports clk_200mhz_n] ;# from SiT9102 U6.5
|
||||
create_clock -period 5.000 -name clk_200mhz [get_ports clk_200mhz_p]
|
||||
|
||||
# Si570 user clock (156.25 MHz default)
|
||||
#set_property -dict {LOC K28 IOSTANDARD LVDS_25} [get_ports clk_user_p] ;# from Si570 U45.4
|
||||
#set_property -dict {LOC K29 IOSTANDARD LVDS_25} [get_ports clk_user_n] ;# from Si570 U45.5
|
||||
#create_clock -period 6.400 -name clk_user [get_ports clk_user_p]
|
||||
|
||||
# User SMA clock
|
||||
#set_property -dict {LOC L25 IOSTANDARD LVDS_25} [get_ports clk_user_sma_p] ;# from J11
|
||||
#set_property -dict {LOC K25 IOSTANDARD LVDS_25} [get_ports clk_user_sma_n] ;# from J12
|
||||
#create_clock -period 10.000 -name clk_user_sma [get_ports clk_user_sma_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AB8 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# to DS4
|
||||
set_property -dict {LOC AA8 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# to DS1
|
||||
set_property -dict {LOC AC9 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# to DS10
|
||||
set_property -dict {LOC AB9 IOSTANDARD LVCMOS15 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# to DS2
|
||||
set_property -dict {LOC AE26 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[4]}] ;# to DS3
|
||||
set_property -dict {LOC G19 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[5]}] ;# to DS25
|
||||
set_property -dict {LOC E18 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[6]}] ;# to DS26
|
||||
set_property -dict {LOC F16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[7]}] ;# to DS27
|
||||
|
||||
set_false_path -to [get_ports {led[*]}]
|
||||
set_output_delay 0 [get_ports {led[*]}]
|
||||
|
||||
# Reset button
|
||||
set_property -dict {LOC AB7 IOSTANDARD LVCMOS15} [get_ports reset] ;# from SW7
|
||||
|
||||
set_false_path -from [get_ports {reset}]
|
||||
set_input_delay 0 [get_ports {reset}]
|
||||
|
||||
# Push buttons
|
||||
set_property -dict {LOC AA12 IOSTANDARD LVCMOS15} [get_ports btnu] ;# from SW2
|
||||
set_property -dict {LOC AC6 IOSTANDARD LVCMOS15} [get_ports btnl] ;# from SW6
|
||||
set_property -dict {LOC AB12 IOSTANDARD LVCMOS15} [get_ports btnd] ;# from SW4
|
||||
set_property -dict {LOC AG5 IOSTANDARD LVCMOS15} [get_ports btnr] ;# from SW3
|
||||
set_property -dict {LOC G12 IOSTANDARD LVCMOS25} [get_ports btnc] ;# from SW5
|
||||
|
||||
set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
|
||||
set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
|
||||
|
||||
# DIP switches
|
||||
set_property -dict {LOC Y29 IOSTANDARD LVCMOS25} [get_ports {sw[0]}] ;# from SW4.4
|
||||
set_property -dict {LOC W29 IOSTANDARD LVCMOS25} [get_ports {sw[1]}] ;# from SW4.3
|
||||
set_property -dict {LOC AA28 IOSTANDARD LVCMOS25} [get_ports {sw[2]}] ;# from SW4.2
|
||||
set_property -dict {LOC Y28 IOSTANDARD LVCMOS25} [get_ports {sw[3]}] ;# from SW4.1
|
||||
|
||||
set_false_path -from [get_ports {sw[*]}]
|
||||
set_input_delay 0 [get_ports {sw[*]}]
|
||||
|
||||
# UART (U12 CP2103)
|
||||
set_property -dict {LOC K24 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U12.24 RXD_I
|
||||
set_property -dict {LOC M19 IOSTANDARD LVCMOS25} [get_ports {uart_rxd}] ;# U12.25 TXD_O
|
||||
set_property -dict {LOC L27 IOSTANDARD LVCMOS25} [get_ports {uart_rts}] ;# U12.23 RTS_O_B
|
||||
set_property -dict {LOC K23 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U12.22 CTS_I_B
|
||||
|
||||
set_false_path -to [get_ports {uart_txd uart_cts}]
|
||||
set_output_delay 0 [get_ports {uart_txd uart_cts}]
|
||||
set_false_path -from [get_ports {uart_rxd uart_rts}]
|
||||
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
|
||||
|
||||
# I2C interface
|
||||
#set_property -dict {LOC K21 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
|
||||
#set_property -dict {LOC L21 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
|
||||
|
||||
#set_false_path -to [get_ports {i2c_sda i2c_scl}]
|
||||
#set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||
#set_false_path -from [get_ports {i2c_sda i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||
|
||||
# Gigabit Ethernet GMII PHY
|
||||
set_property -dict {LOC U27 IOSTANDARD LVCMOS25} [get_ports phy_rx_clk] ;# from U37.C1 RXCLK
|
||||
set_property -dict {LOC U30 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[0]}] ;# from U37.B2 RXD0
|
||||
set_property -dict {LOC U25 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[1]}] ;# from U37.D3 RXD1
|
||||
set_property -dict {LOC T25 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[2]}] ;# from U37.C3 RXD2
|
||||
set_property -dict {LOC U28 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[3]}] ;# from U37.B3 RXD3
|
||||
set_property -dict {LOC R19 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[4]}] ;# from U37.C4 RXD4
|
||||
set_property -dict {LOC T27 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[5]}] ;# from U37.A1 RXD5
|
||||
set_property -dict {LOC T26 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[6]}] ;# from U37.A2 RXD6
|
||||
set_property -dict {LOC T28 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[7]}] ;# from U37.C5 RXD7
|
||||
set_property -dict {LOC R28 IOSTANDARD LVCMOS25} [get_ports phy_rx_dv] ;# from U37.B1 RXCTL_RXDV
|
||||
set_property -dict {LOC V26 IOSTANDARD LVCMOS25} [get_ports phy_rx_er] ;# from U37.D4 RXER
|
||||
set_property -dict {LOC K30 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports phy_gtx_clk] ;# from U37.E2 TXC_GTXCLK
|
||||
set_property -dict {LOC M28 IOSTANDARD LVCMOS25} [get_ports phy_tx_clk] ;# from U37.D1 TXCLK
|
||||
set_property -dict {LOC N27 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[0]}] ;# from U37.F1 TXD0
|
||||
set_property -dict {LOC N25 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[1]}] ;# from U37.G2 TXD1
|
||||
set_property -dict {LOC M29 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[2]}] ;# from U37.G3 TXD2
|
||||
set_property -dict {LOC L28 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[3]}] ;# from U37.H1 TXD3
|
||||
set_property -dict {LOC J26 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[4]}] ;# from U37.H2 TXD4
|
||||
set_property -dict {LOC K26 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[5]}] ;# from U37.H3 TXD5
|
||||
set_property -dict {LOC L30 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[6]}] ;# from U37.J1 TXD6
|
||||
set_property -dict {LOC J28 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[7]}] ;# from U37.J2 TXD7
|
||||
set_property -dict {LOC M27 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports phy_tx_en] ;# from U37.E1 TXCTL_TXEN
|
||||
set_property -dict {LOC N29 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports phy_tx_er] ;# from U37.F2 TXER
|
||||
set_property -dict {LOC L20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] ;# from U37.K3 RESET_B
|
||||
set_property -dict {LOC N30 IOSTANDARD LVCMOS25} [get_ports phy_int_n] ;# from U37.L1 INT_B
|
||||
#set_property -dict {LOC J21 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdio] ;# from U37.M1 MDIO
|
||||
#set_property -dict {LOC R23 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdc] ;# from U37.L3 MDC
|
||||
|
||||
create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
|
||||
create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
|
||||
|
||||
set_false_path -to [get_ports {phy_reset_n}]
|
||||
set_output_delay 0 [get_ports {phy_reset_n}]
|
||||
set_false_path -from [get_ports {phy_int_n}]
|
||||
set_input_delay 0 [get_ports {phy_int_n}]
|
||||
|
||||
#set_false_path -to [get_ports {phy_mdio phy_mdc}]
|
||||
#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
|
||||
#set_false_path -from [get_ports {phy_mdio}]
|
||||
#set_input_delay 0 [get_ports {phy_mdio}]
|
||||
|
||||
# GTX for Ethernet
|
||||
set_property -dict {LOC G4 } [get_ports sfp_rx_p] ;# MGTXRXP2_117 GTXE2_CHANNEL_X0Y10 / GTXE2_COMMON_X0Y2 from P5.13
|
||||
set_property -dict {LOC G3 } [get_ports sfp_rx_n] ;# MGTXRXN2_117 GTXE2_CHANNEL_X0Y10 / GTXE2_COMMON_X0Y2 from P5.12
|
||||
set_property -dict {LOC H2 } [get_ports sfp_tx_p] ;# MGTXTXP2_117 GTXE2_CHANNEL_X0Y10 / GTXE2_COMMON_X0Y2 from P5.18
|
||||
set_property -dict {LOC H1 } [get_ports sfp_tx_n] ;# MGTXTXN2_117 GTXE2_CHANNEL_X0Y10 / GTXE2_COMMON_X0Y2 from P5.19
|
||||
set_property -dict {LOC H6 } [get_ports phy_sgmii_rx_p] ;# MGTXRXP1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A7 SOUT_P
|
||||
set_property -dict {LOC H5 } [get_ports phy_sgmii_rx_n] ;# MGTXRXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A8 SOUT_N
|
||||
set_property -dict {LOC J4 } [get_ports phy_sgmii_tx_p] ;# MGTXTXP1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A3 SIN_P
|
||||
set_property -dict {LOC J3 } [get_ports phy_sgmii_tx_n] ;# MGTXTXN1_117 GTXE2_CHANNEL_X0Y9 / GTXE2_COMMON_X0Y2 from U37.A4 SIN_N
|
||||
set_property -dict {LOC G8 } [get_ports sgmii_clk_p] ;# MGTREFCLK0P_117 from U2.7
|
||||
set_property -dict {LOC G7 } [get_ports sgmii_clk_n] ;# MGTREFCLK0N_117 from U2.6
|
||||
#set_property -dict {LOC L8 } [get_ports sfp_clk_p] ;# MGTREFCLK0P_116 from Si5324 U70.28 CKOUT1_P
|
||||
#set_property -dict {LOC L7 } [get_ports sfp_clk_n] ;# MGTREFCLK0N_116 from Si5324 U70.29 CKOUT1_N
|
||||
#set_property -dict {LOC W27 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to Si5324 U70.16 CKIN1_P
|
||||
#set_property -dict {LOC W28 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to Si5324 U70.17 CKIN1_N
|
||||
|
||||
set_property -dict {LOC Y20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}]
|
||||
|
||||
create_clock -period 8.000 -name sgmii_clk [get_ports sgmii_clk_p]
|
||||
#create_clock -period 6.400 -name sgmii_clk [get_ports sfp_clk_p]
|
||||
|
||||
set_false_path -to [get_ports {sfp_tx_disable_b}]
|
||||
set_output_delay 0 [get_ports {sfp_tx_disable_b}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC M6 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_225 GTXE3_CHANNEL_X0Y7 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC M5 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_225 GTXE3_CHANNEL_X0Y7 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC L4 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_225 GTXE3_CHANNEL_X0Y7 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC L3 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_225 GTXE3_CHANNEL_X0Y7 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC P6 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_225 GTXE3_CHANNEL_X0Y6 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC P5 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_225 GTXE3_CHANNEL_X0Y6 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC M2 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_225 GTXE3_CHANNEL_X0Y6 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC M1 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_225 GTXE3_CHANNEL_X0Y6 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC R4 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_225 GTXE3_CHANNEL_X0Y5 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC R3 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_225 GTXE3_CHANNEL_X0Y5 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC N4 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_225 GTXE3_CHANNEL_X0Y5 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC N3 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_225 GTXE3_CHANNEL_X0Y5 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC T6 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_225 GTXE3_CHANNEL_X0Y4 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC T5 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_225 GTXE3_CHANNEL_X0Y4 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC P2 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_225 GTXE3_CHANNEL_X0Y4 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC P1 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_225 GTXE3_CHANNEL_X0Y4 / GTXE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC V6 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_224 GTXE3_CHANNEL_X0Y3 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC V5 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_224 GTXE3_CHANNEL_X0Y3 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC T2 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_224 GTXE3_CHANNEL_X0Y3 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC T1 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_224 GTXE3_CHANNEL_X0Y3 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC W4 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_224 GTXE3_CHANNEL_X0Y2 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC W3 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_224 GTXE3_CHANNEL_X0Y2 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC U4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_224 GTXE3_CHANNEL_X0Y2 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC U3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_224 GTXE3_CHANNEL_X0Y2 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC Y6 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_224 GTXE3_CHANNEL_X0Y1 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC Y5 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_224 GTXE3_CHANNEL_X0Y1 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC V2 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_224 GTXE3_CHANNEL_X0Y1 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC V1 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_224 GTXE3_CHANNEL_X0Y1 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_224 GTXE3_CHANNEL_X0Y0 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_224 GTXE3_CHANNEL_X0Y0 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC Y2 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_224 GTXE3_CHANNEL_X0Y0 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC Y1 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_224 GTXE3_CHANNEL_X0Y0 / GTXE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC U8 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225
|
||||
#set_property -dict {LOC U7 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225
|
||||
#set_property -dict {LOC G25 IOSTANDARD LVCMOS25 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
56
src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile
Normal file
56
src/eth/example/KC705/fpga/fpga_gmii_1g/Makefile
Normal file
@@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7k325tffg900-2
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintex7
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += ../eth_gmii.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
|
||||
IP_TCL_FILES += ../ip/basex_pcs_pma_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
26
src/eth/example/KC705/fpga/fpga_gmii_1g/config.tcl
Normal file
26
src/eth/example/KC705/fpga/fpga_gmii_1g/config.tcl
Normal file
@@ -0,0 +1,26 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# Type of PHY on RJ-45 10/100/1000BASE-T port (GMII, RGMII, or SGMII)
|
||||
dict set params BASET_PHY_TYPE "GMII"
|
||||
|
||||
# Invert polarity for SFP+ cage
|
||||
# KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped
|
||||
dict set params SFP_INVERT "1"
|
||||
# KC705 rev 1.1: diff pairs to SFP+ are correct
|
||||
#dict set params SFP_INVERT "0"
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
57
src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile
Normal file
57
src/eth/example/KC705/fpga/fpga_rgmii_1g/Makefile
Normal file
@@ -0,0 +1,57 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7k325tffg900-2
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintex7
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += ../eth_rgmii.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
|
||||
IP_TCL_FILES += ../ip/basex_pcs_pma_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
26
src/eth/example/KC705/fpga/fpga_rgmii_1g/config.tcl
Normal file
26
src/eth/example/KC705/fpga/fpga_rgmii_1g/config.tcl
Normal file
@@ -0,0 +1,26 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# Type of PHY on RJ-45 10/100/1000BASE-T port (GMII, RGMII, or SGMII)
|
||||
dict set params BASET_PHY_TYPE "RGMII"
|
||||
|
||||
# Invert polarity for SFP+ cage
|
||||
# KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped
|
||||
dict set params SFP_INVERT "1"
|
||||
# KC705 rev 1.1: diff pairs to SFP+ are correct
|
||||
#dict set params SFP_INVERT "0"
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
@@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# Generate bit file with different IODELAY settings without rebuilding the full project
|
||||
|
||||
open_project fpga.xpr
|
||||
open_run impl_1
|
||||
|
||||
# IDELAY from PHY chip (RGMII)
|
||||
set_property IDELAY_VALUE 0 [get_cells {phy_if.phy_rx_ctl_idelay phy_if.phy_rxd_idelay_bit[*].idelay_inst}]
|
||||
|
||||
# MMCM phase (RGMII)
|
||||
set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
|
||||
|
||||
write_bitstream -force fpga.bit
|
||||
exit
|
||||
54
src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile
Normal file
54
src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile
Normal file
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7k325tffg900-2
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintex7
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
|
||||
IP_TCL_FILES += ../ip/basex_pcs_pma_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
26
src/eth/example/KC705/fpga/fpga_sgmii_1g/config.tcl
Normal file
26
src/eth/example/KC705/fpga/fpga_sgmii_1g/config.tcl
Normal file
@@ -0,0 +1,26 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# Type of PHY on RJ-45 10/100/1000BASE-T port (GMII, RGMII, or SGMII)
|
||||
dict set params BASET_PHY_TYPE "SGMII"
|
||||
|
||||
# Invert polarity for SFP+ cage
|
||||
# KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped
|
||||
dict set params SFP_INVERT "1"
|
||||
# KC705 rev 1.1: diff pairs to SFP+ are correct
|
||||
#dict set params SFP_INVERT "0"
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
18
src/eth/example/KC705/fpga/ip/basex_pcs_pma_0.tcl
Normal file
18
src/eth/example/KC705/fpga/ip/basex_pcs_pma_0.tcl
Normal file
@@ -0,0 +1,18 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.Standard {1000BASEX} \
|
||||
CONFIG.Physical_Interface {Transceiver} \
|
||||
CONFIG.Management_Interface {false} \
|
||||
CONFIG.Auto_Negotiation {false} \
|
||||
CONFIG.TransceiverControl {true} \
|
||||
CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design} \
|
||||
] [get_ips basex_pcs_pma_0]
|
||||
16
src/eth/example/KC705/fpga/ip/sgmii_pcs_pma_0.tcl
Normal file
16
src/eth/example/KC705/fpga/ip/sgmii_pcs_pma_0.tcl
Normal file
@@ -0,0 +1,16 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name sgmii_pcs_pma_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.Standard {SGMII} \
|
||||
CONFIG.Physical_Interface {Transceiver} \
|
||||
CONFIG.Management_Interface {false} \
|
||||
CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
|
||||
] [get_ips sgmii_pcs_pma_0]
|
||||
1
src/eth/example/KC705/fpga/lib/taxi
Symbolic link
1
src/eth/example/KC705/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../../../
|
||||
711
src/eth/example/KC705/fpga/rtl/fpga.sv
Normal file
711
src/eth/example/KC705/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,711 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "kintex7",
|
||||
// Use 90 degree clock for RGMII transmit
|
||||
parameter logic USE_CLK90 = 1'b1,
|
||||
// BASE-T PHY type (GMII, RGMII, SGMII)
|
||||
parameter BASET_PHY_TYPE = "GMII",
|
||||
// Invert SFP data pins
|
||||
parameter logic SFP_INVERT = 1'b1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 200MHz
|
||||
* Reset: Push button, active high
|
||||
*/
|
||||
input wire logic clk_200mhz_p,
|
||||
input wire logic clk_200mhz_n,
|
||||
input wire logic reset,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic btnu,
|
||||
input wire logic btnl,
|
||||
input wire logic btnd,
|
||||
input wire logic btnr,
|
||||
input wire logic btnc,
|
||||
input wire logic [3:0] sw,
|
||||
output wire logic [7:0] led,
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
input wire logic uart_rts,
|
||||
output wire logic uart_cts,
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
input wire logic sfp_rx_p,
|
||||
input wire logic sfp_rx_n,
|
||||
output wire logic sfp_tx_p,
|
||||
output wire logic sfp_tx_n,
|
||||
input wire logic phy_sgmii_rx_p,
|
||||
input wire logic phy_sgmii_rx_n,
|
||||
output wire logic phy_sgmii_tx_p,
|
||||
output wire logic phy_sgmii_tx_n,
|
||||
input wire logic sgmii_clk_p,
|
||||
input wire logic sgmii_clk_n,
|
||||
|
||||
output wire logic sfp_tx_disable_b,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T GMII, RGMII, or SGMII
|
||||
*/
|
||||
input wire logic phy_rx_clk,
|
||||
input wire logic [7:0] phy_rxd,
|
||||
input wire logic phy_rx_dv,
|
||||
input wire logic phy_rx_er,
|
||||
output wire logic phy_gtx_clk,
|
||||
input wire logic phy_tx_clk,
|
||||
output wire logic [7:0] phy_txd,
|
||||
output wire logic phy_tx_en,
|
||||
output wire logic phy_tx_er,
|
||||
output wire logic phy_reset_n,
|
||||
input wire logic phy_int_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_200mhz_ibufg;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_mmcm_out;
|
||||
wire clk_int;
|
||||
wire clk90_mmcm_out;
|
||||
wire clk90_int;
|
||||
wire rst_int;
|
||||
|
||||
wire clk_200mhz_mmcm_out;
|
||||
wire clk_200mhz_int;
|
||||
|
||||
wire mmcm_rst = reset;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFGDS
|
||||
clk_200mhz_ibufgds_inst(
|
||||
.I(clk_200mhz_p),
|
||||
.IB(clk_200mhz_n),
|
||||
.O(clk_200mhz_ibufg)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
MMCME2_BASE #(
|
||||
// 200 MHz input
|
||||
.CLKIN1_PERIOD(5.0),
|
||||
.REF_JITTER1(0.010),
|
||||
// 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(1),
|
||||
// 200 MHz PFD * 5 = 1000 MHz VCO (range 600 MHz to 1440 MHz)
|
||||
.CLKFBOUT_MULT_F(5),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1000 MHz VCO / 8 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(8),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// 1000 MHz VCO / 8 = 125 MHz, 90 degrees
|
||||
.CLKOUT1_DIVIDE(8),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(90),
|
||||
// 1000 MHz VCO / 5 = 200 MHz, 0 degrees
|
||||
.CLKOUT2_DIVIDE(5),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 200 MHz input
|
||||
.CLKIN1(clk_200mhz_ibufg),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// 125 MHz, 90 degrees
|
||||
.CLKOUT1(clk90_mmcm_out),
|
||||
.CLKOUT1B(),
|
||||
// 200 MHz, 0 degrees
|
||||
.CLKOUT2(clk_200mhz_mmcm_out),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_bufg_inst (
|
||||
.I(clk_mmcm_out),
|
||||
.O(clk_int)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk90_bufg_inst (
|
||||
.I(clk90_mmcm_out),
|
||||
.O(clk90_int)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_200mhz_bufg_inst (
|
||||
.I(clk_200mhz_mmcm_out),
|
||||
.O(clk_200mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_inst (
|
||||
.clk(clk_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire btnu_int;
|
||||
wire btnl_int;
|
||||
wire btnd_int;
|
||||
wire btnr_int;
|
||||
wire btnc_int;
|
||||
wire [3:0] sw_int;
|
||||
|
||||
taxi_debounce_switch #(
|
||||
.WIDTH(9),
|
||||
.N(4),
|
||||
.RATE(125000)
|
||||
)
|
||||
debounce_switch_inst (
|
||||
.clk(clk_int),
|
||||
.rst(rst_int),
|
||||
.in({btnu,
|
||||
btnl,
|
||||
btnd,
|
||||
btnr,
|
||||
btnc,
|
||||
sw}),
|
||||
.out({btnu_int,
|
||||
btnl_int,
|
||||
btnd_int,
|
||||
btnr_int,
|
||||
btnc_int,
|
||||
sw_int})
|
||||
);
|
||||
|
||||
wire uart_rxd_int;
|
||||
wire uart_rts_int;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(2),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(clk_int),
|
||||
.in({uart_rxd, uart_rts}),
|
||||
.out({uart_rxd_int, uart_rts_int})
|
||||
);
|
||||
|
||||
wire [7:0] led_int;
|
||||
|
||||
// SGMII interface to PHY
|
||||
wire phy_sgmii_clk_int;
|
||||
wire phy_sgmii_rst_int;
|
||||
wire phy_sgmii_clk_en_int;
|
||||
wire [7:0] phy_sgmii_txd_int;
|
||||
wire phy_sgmii_tx_en_int;
|
||||
wire phy_sgmii_tx_er_int;
|
||||
wire [7:0] phy_sgmii_rxd_int;
|
||||
wire phy_sgmii_rx_dv_int;
|
||||
wire phy_sgmii_rx_er_int;
|
||||
|
||||
wire sgmii_gtrefclk;
|
||||
wire sgmii_gtrefclk_bufg;
|
||||
wire sgmii_txuserclk;
|
||||
wire sgmii_txuserclk2;
|
||||
wire sgmii_rxuserclk;
|
||||
wire sgmii_rxuserclk2;
|
||||
wire sgmii_pma_reset;
|
||||
wire sgmii_mmcm_locked;
|
||||
|
||||
wire phy_sgmii_resetdone;
|
||||
|
||||
assign phy_sgmii_clk_int = sgmii_txuserclk2;
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_sgmii_inst (
|
||||
.clk(phy_sgmii_clk_int),
|
||||
.rst(rst_int || !phy_sgmii_resetdone),
|
||||
.out(phy_sgmii_rst_int)
|
||||
);
|
||||
|
||||
wire [15:0] sgmii_status_vect;
|
||||
|
||||
wire sgmii_status_link_status = sgmii_status_vect[0];
|
||||
wire sgmii_status_link_synchronization = sgmii_status_vect[1];
|
||||
wire sgmii_status_rudi_c = sgmii_status_vect[2];
|
||||
wire sgmii_status_rudi_i = sgmii_status_vect[3];
|
||||
wire sgmii_status_rudi_invalid = sgmii_status_vect[4];
|
||||
wire sgmii_status_rxdisperr = sgmii_status_vect[5];
|
||||
wire sgmii_status_rxnotintable = sgmii_status_vect[6];
|
||||
wire sgmii_status_phy_link_status = sgmii_status_vect[7];
|
||||
wire [1:0] sgmii_status_remote_fault_encdg = sgmii_status_vect[9:8];
|
||||
wire [1:0] sgmii_status_speed = sgmii_status_vect[11:10];
|
||||
wire sgmii_status_duplex = sgmii_status_vect[12];
|
||||
wire sgmii_status_remote_fault = sgmii_status_vect[13];
|
||||
wire [1:0] sgmii_status_pause = sgmii_status_vect[15:14];
|
||||
|
||||
wire [4:0] sgmii_config_vect;
|
||||
|
||||
assign sgmii_config_vect[4] = 1'b1; // autonegotiation enable
|
||||
assign sgmii_config_vect[3] = 1'b0; // isolate
|
||||
assign sgmii_config_vect[2] = 1'b0; // power down
|
||||
assign sgmii_config_vect[1] = 1'b0; // loopback enable
|
||||
assign sgmii_config_vect[0] = 1'b0; // unidirectional enable
|
||||
|
||||
wire [15:0] sgmii_an_config_vect;
|
||||
|
||||
assign sgmii_an_config_vect[15] = 1'b1; // SGMII link status
|
||||
assign sgmii_an_config_vect[14] = 1'b1; // SGMII Acknowledge
|
||||
assign sgmii_an_config_vect[13:12] = 2'b01; // full duplex
|
||||
assign sgmii_an_config_vect[11:10] = 2'b10; // SGMII speed
|
||||
assign sgmii_an_config_vect[9] = 1'b0; // reserved
|
||||
assign sgmii_an_config_vect[8:7] = 2'b00; // pause frames - SGMII reserved
|
||||
assign sgmii_an_config_vect[6] = 1'b0; // reserved
|
||||
assign sgmii_an_config_vect[5] = 1'b0; // full duplex - SGMII reserved
|
||||
assign sgmii_an_config_vect[4:1] = 4'b0000; // reserved
|
||||
assign sgmii_an_config_vect[0] = 1'b1; // SGMII
|
||||
|
||||
sgmii_pcs_pma_0
|
||||
sgmii_pcspma (
|
||||
// Transceiver Interface
|
||||
.gtrefclk_p (sgmii_clk_p),
|
||||
.gtrefclk_n (sgmii_clk_n),
|
||||
.gtrefclk_out (sgmii_gtrefclk),
|
||||
.gtrefclk_bufg_out (sgmii_gtrefclk_bufg),
|
||||
.txp (phy_sgmii_tx_p),
|
||||
.txn (phy_sgmii_tx_n),
|
||||
.rxp (phy_sgmii_rx_p),
|
||||
.rxn (phy_sgmii_rx_n),
|
||||
.resetdone (phy_sgmii_resetdone),
|
||||
.userclk_out (sgmii_txuserclk),
|
||||
.userclk2_out (sgmii_txuserclk2),
|
||||
.rxuserclk_out (sgmii_rxuserclk),
|
||||
.rxuserclk2_out (sgmii_rxuserclk2),
|
||||
.independent_clock_bufg(clk_int),
|
||||
.pma_reset_out (sgmii_pma_reset),
|
||||
.mmcm_locked_out (sgmii_mmcm_locked),
|
||||
.gt0_qplloutclk_out (),
|
||||
.gt0_qplloutrefclk_out (),
|
||||
// GMII Interface
|
||||
.sgmii_clk_r (),
|
||||
.sgmii_clk_f (),
|
||||
.sgmii_clk_en (phy_sgmii_clk_en_int),
|
||||
.gmii_txd (phy_sgmii_txd_int),
|
||||
.gmii_tx_en (phy_sgmii_tx_en_int),
|
||||
.gmii_tx_er (phy_sgmii_tx_er_int),
|
||||
.gmii_rxd (phy_sgmii_rxd_int),
|
||||
.gmii_rx_dv (phy_sgmii_rx_dv_int),
|
||||
.gmii_rx_er (phy_sgmii_rx_er_int),
|
||||
.gmii_isolate (),
|
||||
// Management: Alternative to MDIO Interface
|
||||
.configuration_vector (sgmii_config_vect),
|
||||
.an_interrupt (),
|
||||
.an_adv_config_vector (sgmii_an_config_vect),
|
||||
.an_restart_config (1'b0),
|
||||
// Speed Control
|
||||
.speed_is_10_100 (sgmii_status_speed != 2'b10),
|
||||
.speed_is_100 (sgmii_status_speed == 2'b01),
|
||||
// General IO's
|
||||
.status_vector (sgmii_status_vect),
|
||||
.reset (rst_int),
|
||||
.signal_detect (1'b1)
|
||||
);
|
||||
|
||||
// 1000BASE-X SFP
|
||||
wire sfp_gmii_clk_int;
|
||||
wire sfp_gmii_rst_int;
|
||||
wire sfp_gmii_clk_en_int;
|
||||
wire [7:0] sfp_gmii_txd_int;
|
||||
wire sfp_gmii_tx_en_int;
|
||||
wire sfp_gmii_tx_er_int;
|
||||
wire [7:0] sfp_gmii_rxd_int;
|
||||
wire sfp_gmii_rx_dv_int;
|
||||
wire sfp_gmii_rx_er_int;
|
||||
|
||||
wire sfp_gmii_txuserclk2 = sgmii_txuserclk2;
|
||||
wire sfp_gmii_resetdone;
|
||||
|
||||
assign sfp_gmii_clk_int = sfp_gmii_txuserclk2;
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_sfp_inst (
|
||||
.clk(sfp_gmii_clk_int),
|
||||
.rst(rst_int || !sfp_gmii_resetdone),
|
||||
.out(sfp_gmii_rst_int)
|
||||
);
|
||||
|
||||
wire [15:0] sfp_status_vect;
|
||||
|
||||
wire sfp_status_link_status = sfp_status_vect[0];
|
||||
wire sfp_status_link_synchronization = sfp_status_vect[1];
|
||||
wire sfp_status_rudi_c = sfp_status_vect[2];
|
||||
wire sfp_status_rudi_i = sfp_status_vect[3];
|
||||
wire sfp_status_rudi_invalid = sfp_status_vect[4];
|
||||
wire sfp_status_rxdisperr = sfp_status_vect[5];
|
||||
wire sfp_status_rxnotintable = sfp_status_vect[6];
|
||||
wire sfp_status_phy_link_status = sfp_status_vect[7];
|
||||
wire [1:0] sfp_status_remote_fault_encdg = sfp_status_vect[9:8];
|
||||
wire [1:0] sfp_status_speed = sfp_status_vect[11:10];
|
||||
wire sfp_status_duplex = sfp_status_vect[12];
|
||||
wire sfp_status_remote_fault = sfp_status_vect[13];
|
||||
wire [1:0] sfp_status_pause = sfp_status_vect[15:14];
|
||||
|
||||
wire [4:0] sfp_config_vect;
|
||||
|
||||
assign sfp_config_vect[4] = 1'b0; // autonegotiation enable
|
||||
assign sfp_config_vect[3] = 1'b0; // isolate
|
||||
assign sfp_config_vect[2] = 1'b0; // power down
|
||||
assign sfp_config_vect[1] = 1'b0; // loopback enable
|
||||
assign sfp_config_vect[0] = 1'b0; // unidirectional enable
|
||||
|
||||
basex_pcs_pma_0
|
||||
sfp_pcspma (
|
||||
// Transceiver Interface
|
||||
.gtrefclk(sgmii_gtrefclk),
|
||||
.gtrefclk_bufg(sgmii_gtrefclk_bufg),
|
||||
.txp(sfp_tx_p),
|
||||
.txn(sfp_tx_n),
|
||||
.rxp(sfp_rx_p),
|
||||
.rxn(sfp_rx_n),
|
||||
.independent_clock_bufg(clk_int),
|
||||
.txoutclk(),
|
||||
.rxoutclk(),
|
||||
.resetdone(sfp_gmii_resetdone),
|
||||
.cplllock(),
|
||||
.mmcm_reset(),
|
||||
.userclk(sgmii_txuserclk),
|
||||
.userclk2(sgmii_txuserclk2),
|
||||
.pma_reset(sgmii_pma_reset),
|
||||
.mmcm_locked(sgmii_mmcm_locked),
|
||||
.rxuserclk(sgmii_rxuserclk),
|
||||
.rxuserclk2(sgmii_rxuserclk2),
|
||||
// GMII Interface
|
||||
.gmii_txd(sfp_gmii_txd_int),
|
||||
.gmii_tx_en(sfp_gmii_tx_en_int),
|
||||
.gmii_tx_er(sfp_gmii_tx_er_int),
|
||||
.gmii_rxd(sfp_gmii_rxd_int),
|
||||
.gmii_rx_dv(sfp_gmii_rx_dv_int),
|
||||
.gmii_rx_er(sfp_gmii_rx_er_int),
|
||||
.gmii_isolate(),
|
||||
// Management: Alternative to MDIO Interface
|
||||
.configuration_vector(sfp_config_vect),
|
||||
// General IO's
|
||||
.status_vector(sfp_status_vect),
|
||||
.reset(rst_int),
|
||||
.signal_detect(1'b1),
|
||||
|
||||
.gt0_qplloutclk_in(1'b0),
|
||||
.gt0_qplloutrefclk_in(1'b0),
|
||||
.gt0_rxchariscomma_out(),
|
||||
.gt0_rxcharisk_out(),
|
||||
.gt0_rxbyteisaligned_out(),
|
||||
.gt0_rxbyterealign_out(),
|
||||
.gt0_rxcommadet_out(),
|
||||
.gt0_txpolarity_in(SFP_INVERT),
|
||||
.gt0_txdiffctrl_in(4'b1000),
|
||||
.gt0_txpostcursor_in(5'b00000),
|
||||
.gt0_txprecursor_in(5'b00000),
|
||||
.gt0_rxpolarity_in(SFP_INVERT),
|
||||
.gt0_txinhibit_in(1'b0),
|
||||
.gt0_txprbssel_in(3'b000),
|
||||
.gt0_txprbsforceerr_in(1'b0),
|
||||
.gt0_rxprbscntreset_in(1'b0),
|
||||
.gt0_rxprbserr_out(),
|
||||
.gt0_rxprbssel_in(3'b000),
|
||||
.gt0_loopback_in(3'b000),
|
||||
.gt0_txresetdone_out(),
|
||||
.gt0_rxresetdone_out(),
|
||||
.gt0_rxdisperr_out(),
|
||||
.gt0_txbufstatus_out(),
|
||||
.gt0_rxnotintable_out(),
|
||||
.gt0_eyescanreset_in(1'b0),
|
||||
.gt0_eyescandataerror_out(),
|
||||
.gt0_eyescantrigger_in(1'b0),
|
||||
.gt0_rxcdrhold_in(1'b0),
|
||||
.gt0_rxpmareset_in(1'b0),
|
||||
.gt0_txpmareset_in(1'b0),
|
||||
.gt0_rxpcsreset_in(1'b0),
|
||||
.gt0_txpcsreset_in(1'b0),
|
||||
.gt0_rxbufreset_in(1'b0),
|
||||
.gt0_rxbufstatus_out(),
|
||||
.gt0_rxdfelpmreset_in(1'b0),
|
||||
.gt0_rxdfeagcovrden_in(1'b0),
|
||||
.gt0_rxlpmen_in(1'b1),
|
||||
.gt0_rxmonitorout_out(),
|
||||
.gt0_rxmonitorsel_in(2'b00),
|
||||
.gt0_drpaddr_in(9'd0),
|
||||
.gt0_drpclk_in(1'b0),
|
||||
.gt0_drpdi_in(9'd0),
|
||||
.gt0_drpdo_out(),
|
||||
.gt0_drpen_in(1'b0),
|
||||
.gt0_drprdy_out(),
|
||||
.gt0_drpwe_in(1'b0),
|
||||
.gt0_dmonitorout_out()
|
||||
);
|
||||
|
||||
assign sfp_gmii_clk_en_int = 1'b1;
|
||||
|
||||
// SGMII interface debug:
|
||||
// SW4:1 (sw[3]) off for payload byte, on for status vector
|
||||
// SW4:2 (sw[2]) off for BASE-T port (SGMII), on for SFP
|
||||
// SW4:4 (sw[0]) off for LSB of status vector, on for MSB
|
||||
wire [15:0] sel_sv = sw[2] ? sfp_status_vect : sgmii_status_vect;
|
||||
assign led = sw[3] ? (sw[0] ? sel_sv[15:8] : sel_sv[7:0]) : led_int;
|
||||
|
||||
wire phy_rgmii_rx_clk_int;
|
||||
wire [3:0] phy_rgmii_rxd_int;
|
||||
wire phy_rgmii_rx_ctl_int;
|
||||
wire phy_rgmii_tx_clk_int;
|
||||
wire [3:0] phy_rgmii_txd_int;
|
||||
wire phy_rgmii_tx_ctl_int;
|
||||
|
||||
wire phy_gmii_rx_clk_int;
|
||||
wire [7:0] phy_gmii_rxd_int;
|
||||
wire phy_gmii_rx_dv_int;
|
||||
wire phy_gmii_rx_er_int;
|
||||
wire phy_gmii_gtx_clk_int;
|
||||
wire phy_gmii_tx_clk_int;
|
||||
wire [7:0] phy_gmii_txd_int;
|
||||
wire phy_gmii_tx_en_int;
|
||||
wire phy_gmii_tx_er_int;
|
||||
|
||||
if (BASET_PHY_TYPE == "RGMII") begin : phy_if
|
||||
|
||||
assign phy_rgmii_rx_clk_int = phy_rx_clk;
|
||||
|
||||
// IODELAY elements for RGMII interface to PHY
|
||||
IDELAYCTRL
|
||||
idelayctrl_inst (
|
||||
.REFCLK(clk_200mhz_int),
|
||||
.RST(rst_int),
|
||||
.RDY()
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit
|
||||
|
||||
IDELAYE2 #(
|
||||
.IDELAY_TYPE("FIXED")
|
||||
)
|
||||
idelay_inst (
|
||||
.IDATAIN(phy_rxd[n]),
|
||||
.DATAOUT(phy_rgmii_rxd_int[n]),
|
||||
.DATAIN(1'b0),
|
||||
.C(1'b0),
|
||||
.CE(1'b0),
|
||||
.INC(1'b0),
|
||||
.CINVCTRL(1'b0),
|
||||
.CNTVALUEIN(5'd0),
|
||||
.CNTVALUEOUT(),
|
||||
.LD(1'b0),
|
||||
.LDPIPEEN(1'b0),
|
||||
.REGRST(1'b0)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
IDELAYE2 #(
|
||||
.IDELAY_TYPE("FIXED")
|
||||
)
|
||||
phy_rx_ctl_idelay (
|
||||
.IDATAIN(phy_rx_dv),
|
||||
.DATAOUT(phy_rgmii_rx_ctl_int),
|
||||
.DATAIN(1'b0),
|
||||
.C(1'b0),
|
||||
.CE(1'b0),
|
||||
.INC(1'b0),
|
||||
.CINVCTRL(1'b0),
|
||||
.CNTVALUEIN(5'd0),
|
||||
.CNTVALUEOUT(),
|
||||
.LD(1'b0),
|
||||
.LDPIPEEN(1'b0),
|
||||
.REGRST(1'b0)
|
||||
);
|
||||
|
||||
assign phy_gtx_clk = phy_rgmii_tx_clk_int;
|
||||
assign phy_txd[3:0] = phy_rgmii_txd_int;
|
||||
assign phy_tx_en = phy_rgmii_tx_ctl_int;
|
||||
|
||||
assign phy_txd[7:4] = '0;
|
||||
assign phy_tx_er = 1'b0;
|
||||
|
||||
assign phy_gmii_rx_clk_int = 1'b0;
|
||||
assign phy_gmii_rxd_int = '0;
|
||||
assign phy_gmii_rx_dv_int = 1'b0;
|
||||
assign phy_gmii_rx_er_int = 1'b0;
|
||||
assign phy_gmii_tx_clk_int = 1'b0;
|
||||
|
||||
end else begin : phy_if
|
||||
|
||||
assign phy_rgmii_rx_clk_int = 1'b0;
|
||||
assign phy_rgmii_rxd_int = '0;
|
||||
assign phy_rgmii_rx_ctl_int = 1'b0;
|
||||
|
||||
assign phy_gmii_rx_clk_int = phy_rx_clk;
|
||||
assign phy_gmii_rxd_int = phy_rxd;
|
||||
assign phy_gmii_rx_dv_int = phy_rx_dv;
|
||||
assign phy_gmii_rx_er_int = phy_rx_er;
|
||||
|
||||
assign phy_gtx_clk = phy_gmii_gtx_clk_int;
|
||||
assign phy_gmii_tx_clk_int = phy_tx_clk;
|
||||
assign phy_txd = phy_gmii_txd_int;
|
||||
assign phy_tx_en = phy_gmii_tx_en_int;
|
||||
assign phy_tx_er = phy_gmii_tx_er_int;
|
||||
|
||||
end
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.USE_CLK90(USE_CLK90),
|
||||
.BASET_PHY_TYPE(BASET_PHY_TYPE),
|
||||
.SFP_INVERT(SFP_INVERT)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk(clk_int),
|
||||
.clk90(clk90_int),
|
||||
.rst(rst_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.btnu(btnu_int),
|
||||
.btnl(btnl_int),
|
||||
.btnd(btnd_int),
|
||||
.btnr(btnr_int),
|
||||
.btnc(btnc_int),
|
||||
.sw(sw_int),
|
||||
.led(led_int),
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd_int),
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rts(uart_rts_int),
|
||||
.uart_cts(uart_cts),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-X SFP
|
||||
*/
|
||||
.sfp_gmii_clk(sfp_gmii_clk_int),
|
||||
.sfp_gmii_rst(sfp_gmii_rst_int),
|
||||
.sfp_gmii_clk_en(sfp_gmii_clk_en_int),
|
||||
.sfp_gmii_rxd(sfp_gmii_rxd_int),
|
||||
.sfp_gmii_rx_dv(sfp_gmii_rx_dv_int),
|
||||
.sfp_gmii_rx_er(sfp_gmii_rx_er_int),
|
||||
.sfp_gmii_txd(sfp_gmii_txd_int),
|
||||
.sfp_gmii_tx_en(sfp_gmii_tx_en_int),
|
||||
.sfp_gmii_tx_er(sfp_gmii_tx_er_int),
|
||||
.sfp_tx_disable_b(sfp_tx_disable_b),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T GMII/RGMII/SGMII
|
||||
*/
|
||||
.phy_sgmii_clk(phy_sgmii_clk_int),
|
||||
.phy_sgmii_rst(phy_sgmii_rst_int),
|
||||
.phy_sgmii_clk_en(phy_sgmii_clk_en_int),
|
||||
.phy_sgmii_rxd(phy_sgmii_rxd_int),
|
||||
.phy_sgmii_rx_dv(phy_sgmii_rx_dv_int),
|
||||
.phy_sgmii_rx_er(phy_sgmii_rx_er_int),
|
||||
.phy_sgmii_txd(phy_sgmii_txd_int),
|
||||
.phy_sgmii_tx_en(phy_sgmii_tx_en_int),
|
||||
.phy_sgmii_tx_er(phy_sgmii_tx_er_int),
|
||||
.phy_rgmii_rx_clk(phy_rgmii_rx_clk_int),
|
||||
.phy_rgmii_rxd(phy_rgmii_rxd_int),
|
||||
.phy_rgmii_rx_ctl(phy_rgmii_rx_ctl_int),
|
||||
.phy_rgmii_tx_clk(phy_rgmii_tx_clk_int),
|
||||
.phy_rgmii_txd(phy_rgmii_txd_int),
|
||||
.phy_rgmii_tx_ctl(phy_rgmii_tx_ctl_int),
|
||||
.phy_gmii_rx_clk(phy_gmii_rx_clk_int),
|
||||
.phy_gmii_rxd(phy_gmii_rxd_int),
|
||||
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
|
||||
.phy_gmii_rx_er(phy_gmii_rx_er_int),
|
||||
.phy_gmii_gtx_clk(phy_gmii_gtx_clk_int),
|
||||
.phy_gmii_tx_clk(phy_gmii_tx_clk_int),
|
||||
.phy_gmii_txd(phy_gmii_txd_int),
|
||||
.phy_gmii_tx_en(phy_gmii_tx_en_int),
|
||||
.phy_gmii_tx_er(phy_gmii_tx_er_int),
|
||||
.phy_reset_n(phy_reset_n),
|
||||
.phy_int_n(phy_int_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
581
src/eth/example/KC705/fpga/rtl/fpga_core.sv
Normal file
581
src/eth/example/KC705/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,581 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "kintex7",
|
||||
// Use 90 degree clock for RGMII transmit
|
||||
parameter logic USE_CLK90 = 1'b1,
|
||||
// BASE-T PHY type (GMII, RGMII, SGMII)
|
||||
parameter BASET_PHY_TYPE = "GMII",
|
||||
// Invert SFP data pins
|
||||
parameter logic SFP_INVERT = 1'b1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk,
|
||||
input wire logic clk90,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic btnu,
|
||||
input wire logic btnl,
|
||||
input wire logic btnd,
|
||||
input wire logic btnr,
|
||||
input wire logic btnc,
|
||||
input wire logic [7:0] sw,
|
||||
output wire logic [7:0] led,
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
input wire logic uart_rts,
|
||||
output wire logic uart_cts,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-X SFP
|
||||
*/
|
||||
input wire logic sfp_gmii_clk,
|
||||
input wire logic sfp_gmii_rst,
|
||||
input wire logic sfp_gmii_clk_en,
|
||||
input wire logic [7:0] sfp_gmii_rxd,
|
||||
input wire logic sfp_gmii_rx_dv,
|
||||
input wire logic sfp_gmii_rx_er,
|
||||
output wire logic [7:0] sfp_gmii_txd,
|
||||
output wire logic sfp_gmii_tx_en,
|
||||
output wire logic sfp_gmii_tx_er,
|
||||
output wire logic sfp_tx_disable_b,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T
|
||||
*/
|
||||
input wire logic phy_sgmii_clk,
|
||||
input wire logic phy_sgmii_rst,
|
||||
input wire logic phy_sgmii_clk_en,
|
||||
input wire logic [7:0] phy_sgmii_rxd,
|
||||
input wire logic phy_sgmii_rx_dv,
|
||||
input wire logic phy_sgmii_rx_er,
|
||||
output wire logic [7:0] phy_sgmii_txd,
|
||||
output wire logic phy_sgmii_tx_en,
|
||||
output wire logic phy_sgmii_tx_er,
|
||||
input wire logic phy_rgmii_rx_clk,
|
||||
input wire logic [3:0] phy_rgmii_rxd,
|
||||
input wire logic phy_rgmii_rx_ctl,
|
||||
output wire logic phy_rgmii_tx_clk,
|
||||
output wire logic [3:0] phy_rgmii_txd,
|
||||
output wire logic phy_rgmii_tx_ctl,
|
||||
input wire logic phy_gmii_rx_clk,
|
||||
input wire logic [7:0] phy_gmii_rxd,
|
||||
input wire logic phy_gmii_rx_dv,
|
||||
input wire logic phy_gmii_rx_er,
|
||||
output wire logic phy_gmii_gtx_clk,
|
||||
input wire logic phy_gmii_tx_clk,
|
||||
output wire logic [7:0] phy_gmii_txd,
|
||||
output wire logic phy_gmii_tx_en,
|
||||
output wire logic phy_gmii_tx_er,
|
||||
output wire logic phy_reset_n,
|
||||
input wire logic phy_int_n
|
||||
);
|
||||
|
||||
assign led = sw;
|
||||
|
||||
// XFCP
|
||||
assign uart_cts = 1'b0;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
|
||||
|
||||
taxi_xfcp_if_uart #(
|
||||
.TX_FIFO_DEPTH(512),
|
||||
.RX_FIFO_DEPTH(512)
|
||||
)
|
||||
xfcp_if_uart_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.uart_rxd(uart_rxd),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* XFCP downstream interface
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_ds),
|
||||
.xfcp_dsp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/921600))
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
|
||||
|
||||
taxi_xfcp_switch #(
|
||||
.XFCP_ID_STR("KC705"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR("Taxi example"),
|
||||
.PORTS($size(xfcp_sw_us))
|
||||
)
|
||||
xfcp_sw_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_ds),
|
||||
.xfcp_usp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* XFCP downstream ports
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_sw_ds),
|
||||
.xfcp_dsp_us(xfcp_sw_us)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
|
||||
|
||||
taxi_xfcp_mod_stats #(
|
||||
.XFCP_ID_STR("Statistics"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR(""),
|
||||
.STAT_COUNT_W(64),
|
||||
.STAT_PIPELINE(2)
|
||||
)
|
||||
xfcp_stats_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_sw_ds[0]),
|
||||
.xfcp_usp_us(xfcp_sw_us[0]),
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
.s_axis_stat(axis_stat)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[2]();
|
||||
|
||||
taxi_axis_arb_mux #(
|
||||
.S_COUNT($size(axis_eth_stat)),
|
||||
.UPDATE_TID(1'b0),
|
||||
.ARB_ROUND_ROBIN(1'b1),
|
||||
.ARB_LSB_HIGH_PRIO(1'b0)
|
||||
)
|
||||
stat_mux_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream inputs (sink)
|
||||
*/
|
||||
.s_axis(axis_eth_stat),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(axis_stat)
|
||||
);
|
||||
|
||||
// BASE-T PHY
|
||||
assign phy_reset_n = !rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
|
||||
|
||||
if (BASET_PHY_TYPE == "GMII") begin : baset_mac_gmii
|
||||
|
||||
taxi_eth_mac_1g_gmii_fifo #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(0),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR("GMII0"),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.gtx_clk(clk),
|
||||
.gtx_rst(rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_eth),
|
||||
.m_axis_tx_cpl(axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rx_clk(phy_gmii_rx_clk),
|
||||
.gmii_rxd(phy_gmii_rxd),
|
||||
.gmii_rx_dv(phy_gmii_rx_dv),
|
||||
.gmii_rx_er(phy_gmii_rx_er),
|
||||
.gmii_tx_clk(phy_gmii_gtx_clk),
|
||||
.mii_tx_clk(phy_gmii_tx_clk),
|
||||
.gmii_txd(phy_gmii_txd),
|
||||
.gmii_tx_en(phy_gmii_tx_en),
|
||||
.gmii_tx_er(phy_gmii_tx_er),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_eth_stat[0]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
.link_speed(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(16'd9218),
|
||||
.cfg_tx_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_max_pkt_len(16'd9218),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
assign phy_sgmii_txd = '0;
|
||||
assign phy_sgmii_tx_en = 1'b0;
|
||||
assign phy_sgmii_tx_er = 1'b0;
|
||||
|
||||
assign phy_rgmii_tx_clk = 1'b0;
|
||||
assign phy_rgmii_txd = '0;
|
||||
assign phy_rgmii_tx_ctl = 1'b0;
|
||||
|
||||
end else if (BASET_PHY_TYPE == "RGMII") begin : baset_mac_rgmii
|
||||
|
||||
taxi_eth_mac_1g_rgmii_fifo #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.USE_CLK90(USE_CLK90),
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(0),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR("RGMII0"),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.gtx_clk(clk),
|
||||
.gtx_clk90(clk90),
|
||||
.gtx_rst(rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_eth),
|
||||
.m_axis_tx_cpl(axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_eth),
|
||||
|
||||
/*
|
||||
* RGMII interface
|
||||
*/
|
||||
.rgmii_rx_clk(phy_rgmii_rx_clk),
|
||||
.rgmii_rxd(phy_rgmii_rxd),
|
||||
.rgmii_rx_ctl(phy_rgmii_rx_ctl),
|
||||
.rgmii_tx_clk(phy_rgmii_tx_clk),
|
||||
.rgmii_txd(phy_rgmii_txd),
|
||||
.rgmii_tx_ctl(phy_rgmii_tx_ctl),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_eth_stat[0]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
.link_speed(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(16'd9218),
|
||||
.cfg_tx_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_max_pkt_len(16'd9218),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
assign phy_gmii_gtx_clk = 1'b0;
|
||||
assign phy_gmii_txd = '0;
|
||||
assign phy_gmii_tx_en = 1'b0;
|
||||
assign phy_gmii_tx_er = 1'b0;
|
||||
|
||||
assign phy_sgmii_txd = '0;
|
||||
assign phy_sgmii_tx_en = 1'b0;
|
||||
assign phy_sgmii_tx_er = 1'b0;
|
||||
|
||||
end else if (BASET_PHY_TYPE == "SGMII") begin : baset_mac_sgmii
|
||||
|
||||
taxi_eth_mac_1g_fifo #(
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(0),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR("SGMII0"),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.rx_clk(phy_sgmii_clk),
|
||||
.rx_rst(phy_sgmii_rst),
|
||||
.tx_clk(phy_sgmii_clk),
|
||||
.tx_rst(phy_sgmii_rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_eth),
|
||||
.m_axis_tx_cpl(axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rxd(phy_sgmii_rxd),
|
||||
.gmii_rx_dv(phy_sgmii_rx_dv),
|
||||
.gmii_rx_er(phy_sgmii_rx_er),
|
||||
.gmii_txd(phy_sgmii_txd),
|
||||
.gmii_tx_en(phy_sgmii_tx_en),
|
||||
.gmii_tx_er(phy_sgmii_tx_er),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.rx_clk_enable(phy_sgmii_clk_en),
|
||||
.tx_clk_enable(phy_sgmii_clk_en),
|
||||
.rx_mii_select(1'b0),
|
||||
.tx_mii_select(1'b0),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_eth_stat[0]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(16'd9218),
|
||||
.cfg_tx_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_max_pkt_len(16'd9218),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
assign phy_gmii_gtx_clk = 1'b0;
|
||||
assign phy_gmii_txd = '0;
|
||||
assign phy_gmii_tx_en = 1'b0;
|
||||
assign phy_gmii_tx_er = 1'b0;
|
||||
|
||||
assign phy_rgmii_tx_clk = 1'b0;
|
||||
assign phy_rgmii_txd = '0;
|
||||
assign phy_rgmii_tx_ctl = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
// SFP+
|
||||
assign sfp_tx_disable_b = 1'b1;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl();
|
||||
|
||||
taxi_eth_mac_1g_fifo #(
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(16+16),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR("SFP"),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.rx_clk(sfp_gmii_clk),
|
||||
.rx_rst(sfp_gmii_rst),
|
||||
.tx_clk(sfp_gmii_clk),
|
||||
.tx_rst(sfp_gmii_rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_sfp_eth),
|
||||
.m_axis_tx_cpl(axis_sfp_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_sfp_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rxd(sfp_gmii_rxd),
|
||||
.gmii_rx_dv(sfp_gmii_rx_dv),
|
||||
.gmii_rx_er(sfp_gmii_rx_er),
|
||||
.gmii_txd(sfp_gmii_txd),
|
||||
.gmii_tx_en(sfp_gmii_tx_en),
|
||||
.gmii_tx_er(sfp_gmii_tx_er),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.rx_clk_enable(sfp_gmii_clk_en),
|
||||
.tx_clk_enable(sfp_gmii_clk_en),
|
||||
.rx_mii_select(1'b0),
|
||||
.tx_mii_select(1'b0),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_eth_stat[1]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(16'd9218),
|
||||
.cfg_tx_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_max_pkt_len(16'd9218),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
63
src/eth/example/KC705/fpga/tb/fpga_core/Makefile
Normal file
63
src/eth/example/KC705/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"kintex7\""
|
||||
export PARAM_USE_CLK90 := "1'b1"
|
||||
export PARAM_BASET_PHY_TYPE := "\"GMII\""
|
||||
export PARAM_SFP_INVERT := "1'b1"
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
237
src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py
Normal file
237
src/eth/example/KC705/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,237 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
|
||||
import pytest
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer, Combine
|
||||
|
||||
from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink, GmiiPhy, RgmiiPhy
|
||||
from cocotbext.uart import UartSource, UartSink
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut, speed=1000e6):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.phy_sgmii_clk, 8, units="ns").start())
|
||||
|
||||
if hasattr(dut, "baset_mac_gmii"):
|
||||
self.baset_phy = GmiiPhy(dut.phy_gmii_txd, dut.phy_gmii_tx_er, dut.phy_gmii_tx_en, dut.phy_gmii_tx_clk, dut.phy_gmii_gtx_clk,
|
||||
dut.phy_gmii_rxd, dut.phy_gmii_rx_er, dut.phy_gmii_rx_dv, dut.phy_gmii_rx_clk, speed=speed)
|
||||
elif hasattr(dut, "baset_mac_rgmii"):
|
||||
self.baset_phy = RgmiiPhy(dut.phy_rgmii_txd, dut.phy_rgmii_tx_ctl, dut.phy_rgmii_tx_clk,
|
||||
dut.phy_rgmii_rxd, dut.phy_rgmii_rx_ctl, dut.phy_rgmii_rx_clk, speed=speed)
|
||||
elif hasattr(dut, "baset_mac_sgmii"):
|
||||
self.sgmii_source = GmiiSource(dut.phy_sgmii_rxd, dut.phy_sgmii_rx_er, dut.phy_sgmii_rx_dv,
|
||||
dut.phy_sgmii_clk, dut.phy_sgmii_rst, dut.phy_sgmii_clk_en)
|
||||
self.sgmii_sink = GmiiSink(dut.phy_sgmii_txd, dut.phy_sgmii_tx_er, dut.phy_sgmii_tx_en,
|
||||
dut.phy_sgmii_clk, dut.phy_sgmii_rst, dut.phy_sgmii_clk_en)
|
||||
|
||||
cocotb.start_soon(Clock(dut.sfp_gmii_clk, 8, units="ns").start())
|
||||
|
||||
self.sfp_source = GmiiSource(dut.sfp_gmii_rxd, dut.sfp_gmii_rx_er, dut.sfp_gmii_rx_dv,
|
||||
dut.sfp_gmii_clk, dut.sfp_gmii_rst, dut.sfp_gmii_clk_en)
|
||||
self.sfp_sink = GmiiSink(dut.sfp_gmii_txd, dut.sfp_gmii_tx_er, dut.sfp_gmii_tx_en,
|
||||
dut.sfp_gmii_clk, dut.sfp_gmii_rst, dut.sfp_gmii_clk_en)
|
||||
|
||||
self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
|
||||
self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
|
||||
|
||||
dut.phy_sgmii_clk_en.setimmediatevalue(1)
|
||||
dut.sfp_gmii_clk_en.setimmediatevalue(1)
|
||||
|
||||
dut.btnu.setimmediatevalue(0)
|
||||
dut.btnl.setimmediatevalue(0)
|
||||
dut.btnd.setimmediatevalue(0)
|
||||
dut.btnr.setimmediatevalue(0)
|
||||
dut.btnc.setimmediatevalue(0)
|
||||
dut.sw.setimmediatevalue(0)
|
||||
dut.uart_rts.setimmediatevalue(0)
|
||||
|
||||
cocotb.start_soon(self._run_clk())
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
self.dut.phy_sgmii_rst.setimmediatevalue(0)
|
||||
self.dut.sfp_gmii_rst.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 1
|
||||
self.dut.phy_sgmii_rst.value = 1
|
||||
self.dut.sfp_gmii_rst.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 0
|
||||
self.dut.phy_sgmii_rst.value = 0
|
||||
self.dut.sfp_gmii_rst.value = 0
|
||||
|
||||
async def _run_clk(self):
|
||||
t = Timer(2, 'ns')
|
||||
while True:
|
||||
self.dut.clk.value = 1
|
||||
await t
|
||||
self.dut.clk90.value = 1
|
||||
await t
|
||||
self.dut.clk.value = 0
|
||||
await t
|
||||
self.dut.clk90.value = 0
|
||||
await t
|
||||
|
||||
|
||||
async def mac_test(tb, source, sink):
|
||||
tb.log.info("Test MAC")
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(GmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 32
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(GmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
tb.log.info("MAC test done")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Start BASE-T MAC loopback test")
|
||||
|
||||
if hasattr(dut, "baset_mac_gmii"):
|
||||
baset_test_cr = cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx))
|
||||
elif hasattr(dut, "baset_mac_rgmii"):
|
||||
baset_test_cr = cocotb.start_soon(mac_test(tb, tb.baset_phy.rx, tb.baset_phy.tx))
|
||||
elif hasattr(dut, "baset_mac_sgmii"):
|
||||
baset_test_cr = cocotb.start_soon(mac_test(tb, tb.sgmii_source, tb.sgmii_sink))
|
||||
|
||||
tb.log.info("Start SFP MAC loopback test")
|
||||
|
||||
sfp_test_cr = cocotb.start_soon(mac_test(tb, tb.sfp_source, tb.sfp_sink))
|
||||
|
||||
await Combine(baset_test_cr, sfp_test_cr)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("phy_type", ["GMII", "RGMII", "SGMII"])
|
||||
def test_fpga_core(request, phy_type):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_gmii_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_rgmii_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
|
||||
os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = "1'b1"
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"artix7\""
|
||||
parameters['USE_CLK90'] = "1'b1"
|
||||
parameters['BASET_PHY_TYPE'] = f"\"{phy_type}\""
|
||||
parameters['SFP_INVERT'] = "1'b1"
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
40
src/eth/example/KCU105/fpga/README.md
Normal file
40
src/eth/example/KCU105/fpga/README.md
Normal file
@@ -0,0 +1,40 @@
|
||||
# Taxi Example Design for KCU105
|
||||
|
||||
## Introduction
|
||||
|
||||
This example design targets the Xilinx KCU105 FPGA board.
|
||||
|
||||
The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as XFCP on the USB UART for monitoring and control.
|
||||
|
||||
* USB UART
|
||||
* XFCP (921600 baud)
|
||||
* RJ-45 Ethernet port with Marvell 88E1111 PHY
|
||||
* Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
|
||||
* SFP+ cages
|
||||
* Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTH transceiver
|
||||
* Looped-back 10GBASE-R MAC via GTH transceiver
|
||||
|
||||
## Board details
|
||||
|
||||
* FPGA: xcku040-ffva1156-2-e
|
||||
* USB UART: Silicon Labs CP2105 SCI
|
||||
* 1000BASE-T PHY: Marvell 88E1111 via SGMII
|
||||
* 1000BASE-X PHY: Xilinx PCS/PMA core via GTH transceiver
|
||||
* 10GBASE-R PHY: Soft PCS with GTH transceiver
|
||||
|
||||
## Licensing
|
||||
|
||||
* Toolchain
|
||||
* Vivado Enterprise (requires license)
|
||||
* IP
|
||||
* No licensed vendor IP or 3rd party IP
|
||||
|
||||
## How to build
|
||||
|
||||
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
|
||||
|
||||
## How to test
|
||||
|
||||
Run `make program` to program the board with Vivado.
|
||||
|
||||
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
|
||||
153
src/eth/example/KCU105/fpga/common/vivado.mk
Normal file
153
src/eth/example/KCU105/fpga/common/vivado.mk
Normal file
@@ -0,0 +1,153 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016-2025 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - list of source files
|
||||
# INC_FILES - list of include files
|
||||
# XDC_FILES - list of timing constraint files
|
||||
# XCI_FILES - list of IP XCI files
|
||||
# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
|
||||
# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
|
||||
#
|
||||
# Note: both SYN_FILES and INC_FILES support file list files. File list
|
||||
# files are files with a .f extension that contain a list of additional
|
||||
# files to include, one path relative to the .f file location per line.
|
||||
# The .f files are processed recursively, and then the complete file list
|
||||
# is de-duplicated, with later files in the list taking precedence.
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: fpga vivado tmpclean clean distclean
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include $(CONFIG)
|
||||
|
||||
FPGA_TOP ?= fpga
|
||||
PROJECT ?= $(FPGA_TOP)
|
||||
XDC_FILES ?= $(PROJECT).xdc
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
|
||||
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything (fpga)
|
||||
# fpga: build FPGA config
|
||||
# vivado: open project in Vivado
|
||||
# tmpclean: remove intermediate files
|
||||
# clean: remove output files and project files
|
||||
# distclean: remove archived output files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(PROJECT).bit
|
||||
|
||||
vivado: $(PROJECT).xpr
|
||||
vivado $(PROJECT).xpr
|
||||
|
||||
tmpclean::
|
||||
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean:: tmpclean
|
||||
-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
|
||||
|
||||
distclean:: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
|
||||
# create fresh project if Makefile or IP files have changed
|
||||
create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
|
||||
echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
|
||||
echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
|
||||
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
|
||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
# source config TCL scripts if any source file has changed
|
||||
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
||||
echo "open_project -quiet $(PROJECT).xpr" > $@
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
$(PROJECT).xpr: create_project.tcl update_config.tcl
|
||||
vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
|
||||
|
||||
# synthesis run
|
||||
$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
|
||||
echo "open_project $(PROJECT).xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
|
||||
echo "open_project $(PROJECT).xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "open_run impl_1" >> run_impl.tcl
|
||||
echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
|
||||
echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# output files (including potentially bit, bin, ltx, and xsa)
|
||||
$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
|
||||
echo "open_project $(PROJECT).xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
|
||||
echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
|
||||
echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
|
||||
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
|
||||
618
src/eth/example/KCU105/fpga/fpga.xdc
Normal file
618
src/eth/example/KCU105/fpga/fpga.xdc
Normal file
@@ -0,0 +1,618 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the Xilinx KCU105 board
|
||||
# part: xcku040-ffva1156-2-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
# System clocks
|
||||
# 300 MHz system clock
|
||||
#set_property -dict {LOC AK17 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p] ;# from U122 Si5335
|
||||
#set_property -dict {LOC AK16 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n] ;# from U122 Si5335
|
||||
#create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
|
||||
|
||||
# 125 MHz system clock
|
||||
set_property -dict {LOC G10 IOSTANDARD LVDS} [get_ports clk_125mhz_p] ;# from U122 Si5335
|
||||
set_property -dict {LOC F10 IOSTANDARD LVDS} [get_ports clk_125mhz_n] ;# from U122 Si5335
|
||||
create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
|
||||
|
||||
# Si570 user clock (156.25 MHz default)
|
||||
#set_property -dict {LOC M25 IOSTANDARD LVDS_25} [get_ports clk_user_p] ;# from U122 Si5335
|
||||
#set_property -dict {LOC M26 IOSTANDARD LVDS_25} [get_ports clk_user_n] ;# from U122 Si5335
|
||||
#create_clock -period 6.400 -name clk_user [get_ports clk_user_p]
|
||||
|
||||
# 90 MHz
|
||||
#set_property -dict {LOC K20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] ;# from U122 Si5335
|
||||
#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
|
||||
|
||||
# User SMA clock J34/J35
|
||||
#set_property -dict {LOC D23 IOSTANDARD LVDS} [get_ports clk_user_sma_p] ;# J34
|
||||
#set_property -dict {LOC C23 IOSTANDARD LVDS} [get_ports clk_user_sma_n] ;# J35
|
||||
#create_clock -period 10.000 -name clk_user_sma [get_ports clk_user_sma_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AP8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# to DS7
|
||||
set_property -dict {LOC H23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# to DS6
|
||||
set_property -dict {LOC P20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}] ;# to DS8
|
||||
set_property -dict {LOC P21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}] ;# to DS9
|
||||
set_property -dict {LOC N22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}] ;# to DS10
|
||||
set_property -dict {LOC M22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}] ;# to DS33
|
||||
set_property -dict {LOC R23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}] ;# to DS32
|
||||
set_property -dict {LOC P23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}] ;# to DS31
|
||||
|
||||
set_false_path -to [get_ports {led[*]}]
|
||||
set_output_delay 0 [get_ports {led[*]}]
|
||||
|
||||
# Reset button
|
||||
set_property -dict {LOC AN8 IOSTANDARD LVCMOS18} [get_ports reset] ;# from SW5
|
||||
|
||||
set_false_path -from [get_ports {reset}]
|
||||
set_input_delay 0 [get_ports {reset}]
|
||||
|
||||
# Push buttons
|
||||
set_property -dict {LOC AD10 IOSTANDARD LVCMOS18} [get_ports btnu] ;# from SW10
|
||||
set_property -dict {LOC AF9 IOSTANDARD LVCMOS18} [get_ports btnl] ;# from SW6
|
||||
set_property -dict {LOC AF8 IOSTANDARD LVCMOS18} [get_ports btnd] ;# from SW8
|
||||
set_property -dict {LOC AE8 IOSTANDARD LVCMOS18} [get_ports btnr] ;# from SW9
|
||||
set_property -dict {LOC AE10 IOSTANDARD LVCMOS18} [get_ports btnc] ;# from SW7
|
||||
|
||||
set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
|
||||
set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
|
||||
|
||||
# DIP switches
|
||||
set_property -dict {LOC AN16 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] ;# from SW12.4
|
||||
set_property -dict {LOC AN19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] ;# from SW12.3
|
||||
set_property -dict {LOC AP18 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] ;# from SW12.2
|
||||
set_property -dict {LOC AN14 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] ;# from SW12.1
|
||||
|
||||
set_false_path -from [get_ports {sw[*]}]
|
||||
set_input_delay 0 [get_ports {sw[*]}]
|
||||
|
||||
# PMOD0
|
||||
#set_property -dict {LOC AK25 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] ;# J52.1
|
||||
#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] ;# J52.3
|
||||
#set_property -dict {LOC AH18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] ;# J52.5
|
||||
#set_property -dict {LOC AM19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] ;# J52.7
|
||||
#set_property -dict {LOC AE26 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] ;# J52.2
|
||||
#set_property -dict {LOC AF25 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] ;# J52.4
|
||||
#set_property -dict {LOC AE21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] ;# J52.6
|
||||
#set_property -dict {LOC AM17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] ;# J52.8
|
||||
|
||||
#set_false_path -to [get_ports {pmod0[*]}]
|
||||
#set_output_delay 0 [get_ports {pmod0[*]}]
|
||||
|
||||
# PMOD1
|
||||
#set_property -dict {LOC AL14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J53.1
|
||||
#set_property -dict {LOC AM14 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J53.3
|
||||
#set_property -dict {LOC AP16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J53.5
|
||||
#set_property -dict {LOC AP15 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J53.7
|
||||
#set_property -dict {LOC AM16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J53.2
|
||||
#set_property -dict {LOC AM15 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J53.4
|
||||
#set_property -dict {LOC AN18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J53.6
|
||||
#set_property -dict {LOC AN17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J53.8
|
||||
|
||||
#set_false_path -to [get_ports {pmod1[*]}]
|
||||
#set_output_delay 0 [get_ports {pmod1[*]}]
|
||||
|
||||
# UART (U34 CP2105 SCI)
|
||||
set_property -dict {LOC K26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.20 RXD_SCI_I
|
||||
set_property -dict {LOC G25 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.21 TXD_SCI_O
|
||||
set_property -dict {LOC L23 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U34.19 RTS_SCI_O
|
||||
set_property -dict {LOC K27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U34.18 CTS_SCI_I
|
||||
|
||||
set_false_path -to [get_ports {uart_txd uart_cts}]
|
||||
set_output_delay 0 [get_ports {uart_txd uart_cts}]
|
||||
set_false_path -from [get_ports {uart_rxd uart_rts}]
|
||||
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
|
||||
|
||||
# I2C interface
|
||||
#set_property -dict {LOC J24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
|
||||
#set_property -dict {LOC J25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
|
||||
|
||||
#set_false_path -to [get_ports {i2c_sda i2c_scl}]
|
||||
#set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||
#set_false_path -from [get_ports {i2c_sda i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||
|
||||
# Gigabit Ethernet SGMII PHY
|
||||
set_property -dict {LOC P24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_p]
|
||||
set_property -dict {LOC P25 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_n]
|
||||
set_property -dict {LOC N24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_p]
|
||||
set_property -dict {LOC M24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_n]
|
||||
set_property -dict {LOC P26 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_p]
|
||||
set_property -dict {LOC N26 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_n]
|
||||
set_property -dict {LOC J23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n]
|
||||
set_property -dict {LOC K25 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
|
||||
#set_property -dict {LOC H26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio]
|
||||
#set_property -dict {LOC L25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc]
|
||||
|
||||
# 625 MHz ref clock from SGMII PHY
|
||||
#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
|
||||
|
||||
set_false_path -to [get_ports {phy_reset_n}]
|
||||
set_output_delay 0 [get_ports {phy_reset_n}]
|
||||
set_false_path -from [get_ports {phy_int_n}]
|
||||
set_input_delay 0 [get_ports {phy_int_n}]
|
||||
|
||||
#set_false_path -to [get_ports {phy_mdio phy_mdc}]
|
||||
#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
|
||||
#set_false_path -from [get_ports {phy_mdio}]
|
||||
#set_input_delay 0 [get_ports {phy_mdio}]
|
||||
|
||||
# SFP+ interface
|
||||
set_property -dict {LOC T2 } [get_ports {sfp_rx_p[0]}] ;# MGTYRXP2_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
set_property -dict {LOC T1 } [get_ports {sfp_rx_n[0]}] ;# MGTYRXN2_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
set_property -dict {LOC U4 } [get_ports {sfp_tx_p[0]}] ;# MGTYTXP2_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
set_property -dict {LOC U3 } [get_ports {sfp_tx_n[0]}] ;# MGTYTXN2_226 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
set_property -dict {LOC V2 } [get_ports {sfp_rx_p[1]}] ;# MGTYRXP1_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
set_property -dict {LOC V1 } [get_ports {sfp_rx_n[1]}] ;# MGTYRXN1_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
set_property -dict {LOC W4 } [get_ports {sfp_tx_p[1]}] ;# MGTYTXP1_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
set_property -dict {LOC W3 } [get_ports {sfp_tx_n[1]}] ;# MGTYTXN1_226 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
set_property -dict {LOC P6 } [get_ports sfp_mgt_refclk_0_p] ;# MGTREFCLK0P_227 from U32 Si570 via U104 Si53340
|
||||
set_property -dict {LOC P5 } [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK0N_227 from U32 Si570 via U104 Si53340
|
||||
#set_property -dict {LOC M6 } [get_ports sfp_mgt_refclk_1_p] ;# MGTREFCLK1P_227 from U57 Si5328B
|
||||
#set_property -dict {LOC M5 } [get_ports sfp_mgt_refclk_1_n] ;# MGTREFCLK1N_227 from U57 Si5328B
|
||||
#set_property -dict {LOC AG11 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to U57 CKIN1 SI5328
|
||||
#set_property -dict {LOC AH11 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U57 CKIN1 SI5328
|
||||
|
||||
set_property -dict {LOC AL8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[0]}]
|
||||
set_property -dict {LOC D28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[1]}]
|
||||
|
||||
# 156.25 MHz MGT reference clock
|
||||
create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p]
|
||||
#create_clock -period 6.400 -name sfp_mgt_refclk_1 [get_ports sfp_mgt_refclk_1_p]
|
||||
|
||||
set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b}]
|
||||
set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AC4 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AC3 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AE4 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AE3 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AG4 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AG3 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AH6 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AH5 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AN4 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AN3 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AB6 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225
|
||||
#set_property -dict {LOC AB5 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225
|
||||
#set_property -dict {LOC K22 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# FMC interface
|
||||
# FMC HPC J22
|
||||
#set_property -dict {LOC H11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[0]"] ;# J22.G9 LA00_P_CC
|
||||
#set_property -dict {LOC G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[0]"] ;# J22.G10 LA00_N_CC
|
||||
#set_property -dict {LOC G9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[1]"] ;# J22.D8 LA01_P_CC
|
||||
#set_property -dict {LOC F9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[1]"] ;# J22.D9 LA01_N_CC
|
||||
#set_property -dict {LOC K10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[2]"] ;# J22.H7 LA02_P
|
||||
#set_property -dict {LOC J10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[2]"] ;# J22.H8 LA02_N
|
||||
#set_property -dict {LOC A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[3]"] ;# J22.G12 LA03_P
|
||||
#set_property -dict {LOC A12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[3]"] ;# J22.G13 LA03_N
|
||||
#set_property -dict {LOC L12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[4]"] ;# J22.H10 LA04_P
|
||||
#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[4]"] ;# J22.H11 LA04_N
|
||||
#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[5]"] ;# J22.D11 LA05_P
|
||||
#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[5]"] ;# J22.D12 LA05_N
|
||||
#set_property -dict {LOC D13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[6]"] ;# J22.C10 LA06_P
|
||||
#set_property -dict {LOC C13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[6]"] ;# J22.C11 LA06_N
|
||||
#set_property -dict {LOC F8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[7]"] ;# J22.H13 LA07_P
|
||||
#set_property -dict {LOC E8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[7]"] ;# J22.H14 LA07_N
|
||||
#set_property -dict {LOC J8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[8]"] ;# J22.G12 LA08_P
|
||||
#set_property -dict {LOC H8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[8]"] ;# J22.G13 LA08_N
|
||||
#set_property -dict {LOC J9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[9]"] ;# J22.D14 LA09_P
|
||||
#set_property -dict {LOC H9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[9]"] ;# J22.D15 LA09_N
|
||||
#set_property -dict {LOC L8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[10]"] ;# J22.C14 LA10_P
|
||||
#set_property -dict {LOC K8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[10]"] ;# J22.C15 LA10_N
|
||||
#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[11]"] ;# J22.H16 LA11_P
|
||||
#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[11]"] ;# J22.H17 LA11_N
|
||||
#set_property -dict {LOC E10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[12]"] ;# J22.G15 LA12_P
|
||||
#set_property -dict {LOC D10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[12]"] ;# J22.G16 LA12_N
|
||||
#set_property -dict {LOC D9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[13]"] ;# J22.D17 LA13_P
|
||||
#set_property -dict {LOC C9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[13]"] ;# J22.D18 LA13_N
|
||||
#set_property -dict {LOC B10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[14]"] ;# J22.C18 LA14_P
|
||||
#set_property -dict {LOC A10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[14]"] ;# J22.C19 LA14_N
|
||||
#set_property -dict {LOC D8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[15]"] ;# J22.H19 LA15_P
|
||||
#set_property -dict {LOC C8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[15]"] ;# J22.H20 LA15_N
|
||||
#set_property -dict {LOC B9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[16]"] ;# J22.G18 LA16_P
|
||||
#set_property -dict {LOC A9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[16]"] ;# J22.G19 LA16_N
|
||||
#set_property -dict {LOC D24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[17]"] ;# J22.D20 LA17_P_CC
|
||||
#set_property -dict {LOC C24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[17]"] ;# J22.D21 LA17_N_CC
|
||||
#set_property -dict {LOC E22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[18]"] ;# J22.C22 LA18_P_CC
|
||||
#set_property -dict {LOC E23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[18]"] ;# J22.C23 LA18_N_CC
|
||||
#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[19]"] ;# J22.H22 LA19_P
|
||||
#set_property -dict {LOC C22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[19]"] ;# J22.H23 LA19_N
|
||||
#set_property -dict {LOC B24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[20]"] ;# J22.G21 LA20_P
|
||||
#set_property -dict {LOC A24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[20]"] ;# J22.G22 LA20_N
|
||||
#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[21]"] ;# J22.H25 LA21_P
|
||||
#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[21]"] ;# J22.H26 LA21_N
|
||||
#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[22]"] ;# J22.G24 LA22_P
|
||||
#set_property -dict {LOC F25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[22]"] ;# J22.G25 LA22_N
|
||||
#set_property -dict {LOC G22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[23]"] ;# J22.D23 LA23_P
|
||||
#set_property -dict {LOC F22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[23]"] ;# J22.D24 LA23_N
|
||||
#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[24]"] ;# J22.H28 LA24_P
|
||||
#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[24]"] ;# J22.H29 LA24_N
|
||||
#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[25]"] ;# J22.G27 LA25_P
|
||||
#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[25]"] ;# J22.G28 LA25_N
|
||||
#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[26]"] ;# J22.D26 LA26_P
|
||||
#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[26]"] ;# J22.D27 LA26_N
|
||||
#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[27]"] ;# J22.C26 LA27_P
|
||||
#set_property -dict {LOC G21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[27]"] ;# J22.C27 LA27_N
|
||||
#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[28]"] ;# J22.H31 LA28_P
|
||||
#set_property -dict {LOC B22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[28]"] ;# J22.H32 LA28_N
|
||||
#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[29]"] ;# J22.G30 LA29_P
|
||||
#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[29]"] ;# J22.G31 LA29_N
|
||||
#set_property -dict {LOC C26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[30]"] ;# J22.H34 LA30_P
|
||||
#set_property -dict {LOC B26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[30]"] ;# J22.H35 LA30_N
|
||||
#set_property -dict {LOC B25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[31]"] ;# J22.G33 LA31_P
|
||||
#set_property -dict {LOC A25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[31]"] ;# J22.G34 LA31_N
|
||||
#set_property -dict {LOC E26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[32]"] ;# J22.H37 LA32_P
|
||||
#set_property -dict {LOC D26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[32]"] ;# J22.H38 LA32_N
|
||||
#set_property -dict {LOC A27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_p[33]"] ;# J22.G36 LA33_P
|
||||
#set_property -dict {LOC A28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_la_n[33]"] ;# J22.G37 LA33_N
|
||||
|
||||
#set_property -dict {LOC G17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[0]"] ;# J22.F4 HA00_P_CC
|
||||
#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[0]"] ;# J22.F5 HA00_N_CC
|
||||
#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[1]"] ;# J22.E2 HA01_P_CC
|
||||
#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[1]"] ;# J22.E3 HA01_N_CC
|
||||
#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[2]"] ;# J22.K7 HA02_P
|
||||
#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[2]"] ;# J22.K8 HA02_N
|
||||
#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[3]"] ;# J22.J6 HA03_P
|
||||
#set_property -dict {LOC G14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[3]"] ;# J22.J7 HA03_N
|
||||
#set_property -dict {LOC G19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[4]"] ;# J22.F7 HA04_P
|
||||
#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[4]"] ;# J22.F8 HA04_N
|
||||
#set_property -dict {LOC J15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[5]"] ;# J22.E6 HA05_P
|
||||
#set_property -dict {LOC J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[5]"] ;# J22.E7 HA05_N
|
||||
#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[6]"] ;# J22.K10 HA06_P
|
||||
#set_property -dict {LOC K15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[6]"] ;# J22.K11 HA06_N
|
||||
#set_property -dict {LOC L19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[7]"] ;# J22.J9 HA07_P
|
||||
#set_property -dict {LOC L18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[7]"] ;# J22.J10 HA07_N
|
||||
#set_property -dict {LOC K18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[8]"] ;# J22.F10 HA08_P
|
||||
#set_property -dict {LOC K17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[8]"] ;# J22.F11 HA08_N
|
||||
#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[9]"] ;# J22.E9 HA09_P
|
||||
#set_property -dict {LOC F17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[9]"] ;# J22.E10 HA09_N
|
||||
#set_property -dict {LOC H17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[10]"] ;# J22.K13 HA10_P
|
||||
#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[10]"] ;# J22.K14 HA10_N
|
||||
#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[11]"] ;# J22.J12 HA11_P
|
||||
#set_property -dict {LOC J18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[11]"] ;# J22.J13 HA11_N
|
||||
#set_property -dict {LOC K16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[12]"] ;# J22.F13 HA12_P
|
||||
#set_property -dict {LOC J16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[12]"] ;# J22.F14 HA12_N
|
||||
#set_property -dict {LOC B14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[13]"] ;# J22.E12 HA13_P
|
||||
#set_property -dict {LOC A14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[13]"] ;# J22.E13 HA13_N
|
||||
#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[14]"] ;# J22.J15 HA14_P
|
||||
#set_property -dict {LOC F14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[14]"] ;# J22.J16 HA14_N
|
||||
#set_property -dict {LOC D14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[15]"] ;# J22.F14 HA15_P
|
||||
#set_property -dict {LOC C14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[15]"] ;# J22.F16 HA15_N
|
||||
#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[16]"] ;# J22.E15 HA16_P
|
||||
#set_property -dict {LOC A18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[16]"] ;# J22.E16 HA16_N
|
||||
#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[17]"] ;# J22.K16 HA17_P_CC
|
||||
#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[17]"] ;# J22.K17 HA17_N_CC
|
||||
#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[18]"] ;# J22.J18 HA18_P_CC
|
||||
#set_property -dict {LOC B16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[18]"] ;# J22.J19 HA18_N_CC
|
||||
#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[19]"] ;# J22.F19 HA19_P
|
||||
#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[19]"] ;# J22.F20 HA19_N
|
||||
#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[20]"] ;# J22.E18 HA20_P
|
||||
#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[20]"] ;# J22.E19 HA20_N
|
||||
#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[21]"] ;# J22.K19 HA21_P
|
||||
#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[21]"] ;# J22.K20 HA21_N
|
||||
#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[22]"] ;# J22.J21 HA22_P
|
||||
#set_property -dict {LOC C17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[22]"] ;# J22.J22 HA22_N
|
||||
#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_p[23]"] ;# J22.K22 HA23_P
|
||||
#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_ha_n[23]"] ;# J22.K23 HA23_N
|
||||
|
||||
#set_property -dict {LOC H12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_clk0_m2c_p"] ;# J22.H4 CLK0_M2C_P
|
||||
#set_property -dict {LOC G12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_clk0_m2c_n"] ;# J22.H5 CLK0_M2C_N
|
||||
#set_property -dict {LOC E25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_clk1_m2c_p"] ;# J22.G2 CLK1_M2C_P
|
||||
#set_property -dict {LOC D25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc_clk1_m2c_n"] ;# J22.G3 CLK1_M2C_N
|
||||
|
||||
#set_property -dict {LOC L27 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc_pg_m2c}] ;# J22.F1 PG_M2C
|
||||
#set_property -dict {LOC H24 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L
|
||||
|
||||
#set_property -dict {LOC F6} [get_ports {fmc_hpc_dp_c2m_p[0]}] ;# MGTHTXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.C2 DP0_C2M_P
|
||||
#set_property -dict {LOC F5} [get_ports {fmc_hpc_dp_c2m_n[0]}] ;# MGTHTXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.C3 DP0_C2M_N
|
||||
#set_property -dict {LOC E4} [get_ports {fmc_hpc_dp_m2c_p[0]}] ;# MGTHRXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.C6 DP0_M2C_P
|
||||
#set_property -dict {LOC E3} [get_ports {fmc_hpc_dp_m2c_n[0]}] ;# MGTHRXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.C7 DP0_M2C_N
|
||||
#set_property -dict {LOC D6} [get_ports {fmc_hpc_dp_c2m_p[1]}] ;# MGTHTXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.A22 DP1_C2M_P
|
||||
#set_property -dict {LOC D5} [get_ports {fmc_hpc_dp_c2m_n[1]}] ;# MGTHTXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.A23 DP1_C2M_N
|
||||
#set_property -dict {LOC D2} [get_ports {fmc_hpc_dp_m2c_p[1]}] ;# MGTHRXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.A2 DP1_M2C_P
|
||||
#set_property -dict {LOC D1} [get_ports {fmc_hpc_dp_m2c_n[1]}] ;# MGTHRXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.A3 DP1_M2C_N
|
||||
#set_property -dict {LOC C4} [get_ports {fmc_hpc_dp_c2m_p[2]}] ;# MGTHTXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J22.A26 DP2_C2M_P
|
||||
#set_property -dict {LOC C3} [get_ports {fmc_hpc_dp_c2m_n[2]}] ;# MGTHTXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J22.A27 DP2_C2M_N
|
||||
#set_property -dict {LOC B2} [get_ports {fmc_hpc_dp_m2c_p[2]}] ;# MGTHRXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J22.A6 DP2_M2C_P
|
||||
#set_property -dict {LOC B1} [get_ports {fmc_hpc_dp_m2c_n[2]}] ;# MGTHRXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J22.A7 DP2_M2C_N
|
||||
#set_property -dict {LOC B6} [get_ports {fmc_hpc_dp_c2m_p[3]}] ;# MGTHTXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4 from J22.A30 DP3_C2M_P
|
||||
#set_property -dict {LOC B5} [get_ports {fmc_hpc_dp_c2m_n[3]}] ;# MGTHTXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4 from J22.A31 DP3_C2M_N
|
||||
#set_property -dict {LOC A4} [get_ports {fmc_hpc_dp_m2c_p[3]}] ;# MGTHRXP3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4 from J22.A10 DP3_M2C_P
|
||||
#set_property -dict {LOC A3} [get_ports {fmc_hpc_dp_m2c_n[3]}] ;# MGTHRXN3_228 GTHE3_CHANNEL_X0Y19 / GTHE3_COMMON_X0Y4 from J22.A11 DP3_M2C_N
|
||||
#set_property -dict {LOC K6 } [get_ports fmc_hpc_mgt_refclk_0_p] ;# MGTREFCLK0P_228 from J22.D4 GBTCLK0_M2C_P
|
||||
#set_property -dict {LOC K5 } [get_ports fmc_hpc_mgt_refclk_0_n] ;# MGTREFCLK0N_228 from J22.D5 GBTCLK0_M2C_N
|
||||
#set_property -dict {LOC H6 } [get_ports fmc_hpc_mgt_refclk_1_p] ;# MGTREFCLK1P_228 from J22.B20 GBTCLK1_M2C_P
|
||||
#set_property -dict {LOC H5 } [get_ports fmc_hpc_mgt_refclk_1_n] ;# MGTREFCLK1N_228 from J22.B21 GBTCLK1_M2C_N
|
||||
|
||||
#set_property -dict {LOC N4} [get_ports {fmc_hpc_dp_c2m_p[4]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A34 DP4_C2M_P
|
||||
#set_property -dict {LOC N3} [get_ports {fmc_hpc_dp_c2m_n[4]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A35 DP4_C2M_N
|
||||
#set_property -dict {LOC M2} [get_ports {fmc_hpc_dp_m2c_p[4]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A14 DP4_M2C_P
|
||||
#set_property -dict {LOC M1} [get_ports {fmc_hpc_dp_m2c_n[4]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J22.A15 DP4_M2C_N
|
||||
#set_property -dict {LOC L4} [get_ports {fmc_hpc_dp_c2m_p[5]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A38 DP5_C2M_P
|
||||
#set_property -dict {LOC L3} [get_ports {fmc_hpc_dp_c2m_n[5]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A39 DP5_C2M_N
|
||||
#set_property -dict {LOC K2} [get_ports {fmc_hpc_dp_m2c_p[5]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A18 DP5_M2C_P
|
||||
#set_property -dict {LOC K1} [get_ports {fmc_hpc_dp_m2c_n[5]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J22.A19 DP5_M2C_N
|
||||
#set_property -dict {LOC J4} [get_ports {fmc_hpc_dp_c2m_p[6]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B36 DP6_C2M_P
|
||||
#set_property -dict {LOC J3} [get_ports {fmc_hpc_dp_c2m_n[6]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B37 DP6_C2M_N
|
||||
#set_property -dict {LOC H2} [get_ports {fmc_hpc_dp_m2c_p[6]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B16 DP6_M2C_P
|
||||
#set_property -dict {LOC H1} [get_ports {fmc_hpc_dp_m2c_n[6]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J22.B17 DP6_M2C_N
|
||||
#set_property -dict {LOC G4} [get_ports {fmc_hpc_dp_c2m_p[7]}] ;# MGTHTXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B32 DP7_C2M_P
|
||||
#set_property -dict {LOC G3} [get_ports {fmc_hpc_dp_c2m_n[7]}] ;# MGTHTXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B33 DP7_C2M_N
|
||||
#set_property -dict {LOC F2} [get_ports {fmc_hpc_dp_m2c_p[7]}] ;# MGTHRXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B12 DP7_M2C_P
|
||||
#set_property -dict {LOC F1} [get_ports {fmc_hpc_dp_m2c_n[7]}] ;# MGTHRXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J22.B13 DP7_M2C_N
|
||||
|
||||
# reference clock
|
||||
#create_clock -period 6.400 -name fmc_hpc_mgt_refclk_0 [get_ports fmc_hpc_mgt_refclk_0_p]
|
||||
#create_clock -period 6.400 -name fmc_hpc_mgt_refclk_1 [get_ports fmc_hpc_mgt_refclk_1_p]
|
||||
|
||||
# FMC LPC J2
|
||||
#set_property -dict {LOC W23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[0]"] ;# J2.G9 LA00_P_CC
|
||||
#set_property -dict {LOC W24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[0]"] ;# J2.G10 LA00_N_CC
|
||||
#set_property -dict {LOC W25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[1]"] ;# J2.D8 LA01_P_CC
|
||||
#set_property -dict {LOC Y25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[1]"] ;# J2.D9 LA01_N_CC
|
||||
#set_property -dict {LOC AA22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[2]"] ;# J2.H7 LA02_P
|
||||
#set_property -dict {LOC AB22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[2]"] ;# J2.H8 LA02_N
|
||||
#set_property -dict {LOC W28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[3]"] ;# J2.G12 LA03_P
|
||||
#set_property -dict {LOC Y28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[3]"] ;# J2.G13 LA03_N
|
||||
#set_property -dict {LOC U26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[4]"] ;# J2.H10 LA04_P
|
||||
#set_property -dict {LOC U27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[4]"] ;# J2.H11 LA04_N
|
||||
#set_property -dict {LOC V27 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[5]"] ;# J2.D11 LA05_P
|
||||
#set_property -dict {LOC V28 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[5]"] ;# J2.D12 LA05_N
|
||||
#set_property -dict {LOC V29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[6]"] ;# J2.C10 LA06_P
|
||||
#set_property -dict {LOC W29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[6]"] ;# J2.C11 LA06_N
|
||||
#set_property -dict {LOC V22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[7]"] ;# J2.H13 LA07_P
|
||||
#set_property -dict {LOC V23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[7]"] ;# J2.H14 LA07_N
|
||||
#set_property -dict {LOC U24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[8]"] ;# J2.G12 LA08_P
|
||||
#set_property -dict {LOC U25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[8]"] ;# J2.G13 LA08_N
|
||||
#set_property -dict {LOC V26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[9]"] ;# J2.D14 LA09_P
|
||||
#set_property -dict {LOC W26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[9]"] ;# J2.D15 LA09_N
|
||||
#set_property -dict {LOC T22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[10]"] ;# J2.C14 LA10_P
|
||||
#set_property -dict {LOC T23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[10]"] ;# J2.C15 LA10_N
|
||||
#set_property -dict {LOC V21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[11]"] ;# J2.H16 LA11_P
|
||||
#set_property -dict {LOC W21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[11]"] ;# J2.H17 LA11_N
|
||||
#set_property -dict {LOC AC22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[12]"] ;# J2.G15 LA12_P
|
||||
#set_property -dict {LOC AC23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[12]"] ;# J2.G16 LA12_N
|
||||
#set_property -dict {LOC AA20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[13]"] ;# J2.D17 LA13_P
|
||||
#set_property -dict {LOC AB20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[13]"] ;# J2.D18 LA13_N
|
||||
#set_property -dict {LOC U21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[14]"] ;# J2.C18 LA14_P
|
||||
#set_property -dict {LOC U22 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[14]"] ;# J2.C19 LA14_N
|
||||
#set_property -dict {LOC AB25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[15]"] ;# J2.H19 LA15_P
|
||||
#set_property -dict {LOC AB26 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[15]"] ;# J2.H20 LA15_N
|
||||
#set_property -dict {LOC AB21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[16]"] ;# J2.G18 LA16_P
|
||||
#set_property -dict {LOC AC21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[16]"] ;# J2.G19 LA16_N
|
||||
#set_property -dict {LOC AA32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[17]"] ;# J2.D20 LA17_P_CC
|
||||
#set_property -dict {LOC AB32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[17]"] ;# J2.D21 LA17_N_CC
|
||||
#set_property -dict {LOC AB30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[18]"] ;# J2.C22 LA18_P_CC
|
||||
#set_property -dict {LOC AB31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[18]"] ;# J2.C23 LA18_N_CC
|
||||
#set_property -dict {LOC AA29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[19]"] ;# J2.H22 LA19_P
|
||||
#set_property -dict {LOC AB29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[19]"] ;# J2.H23 LA19_N
|
||||
#set_property -dict {LOC AA34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[20]"] ;# J2.G21 LA20_P
|
||||
#set_property -dict {LOC AB34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[20]"] ;# J2.G22 LA20_N
|
||||
#set_property -dict {LOC AC33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[21]"] ;# J2.H25 LA21_P
|
||||
#set_property -dict {LOC AD33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[21]"] ;# J2.H26 LA21_N
|
||||
#set_property -dict {LOC AC34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[22]"] ;# J2.G24 LA22_P
|
||||
#set_property -dict {LOC AD34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[22]"] ;# J2.G25 LA22_N
|
||||
#set_property -dict {LOC AD30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[23]"] ;# J2.D23 LA23_P
|
||||
#set_property -dict {LOC AD31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[23]"] ;# J2.D24 LA23_N
|
||||
#set_property -dict {LOC AE32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[24]"] ;# J2.H28 LA24_P
|
||||
#set_property -dict {LOC AF32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[24]"] ;# J2.H29 LA24_N
|
||||
#set_property -dict {LOC AE33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[25]"] ;# J2.G27 LA25_P
|
||||
#set_property -dict {LOC AF34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[25]"] ;# J2.G28 LA25_N
|
||||
#set_property -dict {LOC AF33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[26]"] ;# J2.D26 LA26_P
|
||||
#set_property -dict {LOC AG34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[26]"] ;# J2.D27 LA26_N
|
||||
#set_property -dict {LOC AG31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[27]"] ;# J2.C26 LA27_P
|
||||
#set_property -dict {LOC AG32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[27]"] ;# J2.C27 LA27_N
|
||||
#set_property -dict {LOC V31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[28]"] ;# J2.H31 LA28_P
|
||||
#set_property -dict {LOC W31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[28]"] ;# J2.H32 LA28_N
|
||||
#set_property -dict {LOC U34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[29]"] ;# J2.G30 LA29_P
|
||||
#set_property -dict {LOC V34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[29]"] ;# J2.G31 LA29_N
|
||||
#set_property -dict {LOC Y31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[30]"] ;# J2.H34 LA30_P
|
||||
#set_property -dict {LOC Y32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[30]"] ;# J2.H35 LA30_N
|
||||
#set_property -dict {LOC V33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[31]"] ;# J2.G33 LA31_P
|
||||
#set_property -dict {LOC W34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[31]"] ;# J2.G34 LA31_N
|
||||
#set_property -dict {LOC W30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[32]"] ;# J2.H37 LA32_P
|
||||
#set_property -dict {LOC Y30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[32]"] ;# J2.H38 LA32_N
|
||||
#set_property -dict {LOC W33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_p[33]"] ;# J2.G36 LA33_P
|
||||
#set_property -dict {LOC Y33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_la_n[33]"] ;# J2.G37 LA33_N
|
||||
|
||||
#set_property -dict {LOC AA24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_clk0_m2c_p"] ;# J2.H4 CLK0_M2C_P
|
||||
#set_property -dict {LOC AA25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_clk0_m2c_n"] ;# J2.H5 CLK0_M2C_N
|
||||
#set_property -dict {LOC AC31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_clk1_m2c_p"] ;# J2.G2 CLK1_M2C_P
|
||||
#set_property -dict {LOC AC32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_lpc_clk1_m2c_n"] ;# J2.G3 CLK1_M2C_N
|
||||
|
||||
#set_property -dict {LOC J26 IOSTANDARD LVCMOS18} [get_ports {fmc_lpc_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L
|
||||
|
||||
#set_property -dict {LOC AA4 } [get_ports {fmc_lpc_dp_c2m_p[0]}] ;# MGTHTXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C2 DP0_C2M_P
|
||||
#set_property -dict {LOC AA3 } [get_ports {fmc_lpc_dp_c2m_n[0]}] ;# MGTHTXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C3 DP0_C2M_N
|
||||
#set_property -dict {LOC Y2 } [get_ports {fmc_lpc_dp_m2c_p[0]}] ;# MGTHRXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C6 DP0_M2C_P
|
||||
#set_property -dict {LOC Y1 } [get_ports {fmc_lpc_dp_m2c_n[0]}] ;# MGTHRXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C7 DP0_M2C_N
|
||||
#set_property -dict {LOC T6 } [get_ports fmc_lpc_mgt_refclk_p] ;# MGTREFCLK1P_226 from J2.D4 GBTCLK0_M2C_P
|
||||
#set_property -dict {LOC T5 } [get_ports fmc_lpc_mgt_refclk_n] ;# MGTREFCLK1N_226 from J2.D5 GBTCLK0_M2C_N
|
||||
|
||||
# reference clock
|
||||
#create_clock -period 6.400 -name fmc_lpc_mgt_refclk [get_ports fmc_lpc_mgt_refclk_p]
|
||||
|
||||
# DDR4 C1
|
||||
# 4x MT40A256M16GE-075E
|
||||
#set_property -dict {LOC AE17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
#set_property -dict {LOC AH17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
#set_property -dict {LOC AE18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
#set_property -dict {LOC AJ15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
#set_property -dict {LOC AG16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
#set_property -dict {LOC AL17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
#set_property -dict {LOC AK18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
#set_property -dict {LOC AG17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
#set_property -dict {LOC AF18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
#set_property -dict {LOC AH19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
#set_property -dict {LOC AF15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
#set_property -dict {LOC AD19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
#set_property -dict {LOC AJ14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
#set_property -dict {LOC AG19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
#set_property -dict {LOC AD16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
#set_property -dict {LOC AG14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
#set_property -dict {LOC AF14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
#set_property -dict {LOC AF17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
#set_property -dict {LOC AL15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
#set_property -dict {LOC AG15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
#set_property -dict {LOC AE16 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
|
||||
#set_property -dict {LOC AE15 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
|
||||
#set_property -dict {LOC AD15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
#set_property -dict {LOC AL19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
#set_property -dict {LOC AH14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
#set_property -dict {LOC AJ18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
#set_property -dict {LOC AD18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
#set_property -dict {LOC AL18 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
#set_property -dict {LOC AJ16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}]
|
||||
#set_property -dict {LOC AH16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}]
|
||||
|
||||
#set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0
|
||||
#set_property -dict {LOC AG20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1
|
||||
#set_property -dict {LOC AF22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2
|
||||
#set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3
|
||||
#set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4
|
||||
#set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5
|
||||
#set_property -dict {LOC AG22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6
|
||||
#set_property -dict {LOC AE20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7
|
||||
#set_property -dict {LOC AJ24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0
|
||||
#set_property -dict {LOC AG24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1
|
||||
#set_property -dict {LOC AJ23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2
|
||||
#set_property -dict {LOC AF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3
|
||||
#set_property -dict {LOC AH23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4
|
||||
#set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5
|
||||
#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6
|
||||
#set_property -dict {LOC AG25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7
|
||||
#set_property -dict {LOC AG21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T
|
||||
#set_property -dict {LOC AH21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C
|
||||
#set_property -dict {LOC AH24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T
|
||||
#set_property -dict {LOC AJ25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C
|
||||
#set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0
|
||||
#set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1
|
||||
#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2
|
||||
#set_property -dict {LOC AK23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3
|
||||
#set_property -dict {LOC AK22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4
|
||||
#set_property -dict {LOC AL24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5
|
||||
#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6
|
||||
#set_property -dict {LOC AL23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7
|
||||
#set_property -dict {LOC AM24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0
|
||||
#set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1
|
||||
#set_property -dict {LOC AN24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2
|
||||
#set_property -dict {LOC AP23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3
|
||||
#set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4
|
||||
#set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5
|
||||
#set_property -dict {LOC AP24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6
|
||||
#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7
|
||||
#set_property -dict {LOC AJ20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T
|
||||
#set_property -dict {LOC AK20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C
|
||||
#set_property -dict {LOC AP20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T
|
||||
#set_property -dict {LOC AP21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C
|
||||
#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC AM21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC AH28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0
|
||||
#set_property -dict {LOC AK26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1
|
||||
#set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2
|
||||
#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3
|
||||
#set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4
|
||||
#set_property -dict {LOC AH27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5
|
||||
#set_property -dict {LOC AK27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6
|
||||
#set_property -dict {LOC AM26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7
|
||||
#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0
|
||||
#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1
|
||||
#set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2
|
||||
#set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3
|
||||
#set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4
|
||||
#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5
|
||||
#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6
|
||||
#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7
|
||||
#set_property -dict {LOC AL27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T
|
||||
#set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C
|
||||
#set_property -dict {LOC AN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T
|
||||
#set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C
|
||||
#set_property -dict {LOC AH26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC AN26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC AH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0
|
||||
#set_property -dict {LOC AH32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1
|
||||
#set_property -dict {LOC AJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2
|
||||
#set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3
|
||||
#set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4
|
||||
#set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5
|
||||
#set_property -dict {LOC AH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6
|
||||
#set_property -dict {LOC AK32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7
|
||||
#set_property -dict {LOC AN33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0
|
||||
#set_property -dict {LOC AP33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1
|
||||
#set_property -dict {LOC AM34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2
|
||||
#set_property -dict {LOC AP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3
|
||||
#set_property -dict {LOC AM32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4
|
||||
#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5
|
||||
#set_property -dict {LOC AL34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6
|
||||
#set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7
|
||||
#set_property -dict {LOC AH33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T
|
||||
#set_property -dict {LOC AJ33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C
|
||||
#set_property -dict {LOC AN34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T
|
||||
#set_property -dict {LOC AP34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C
|
||||
#set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC AL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B
|
||||
|
||||
# QSPI flash
|
||||
#set_property -dict {LOC M20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}]
|
||||
#set_property -dict {LOC L20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}]
|
||||
#set_property -dict {LOC R21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}]
|
||||
#set_property -dict {LOC R22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}]
|
||||
#set_property -dict {LOC G26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}]
|
||||
|
||||
#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_false_path -from [get_ports {qspi_1_dq}]
|
||||
#set_input_delay 0 [get_ports {qspi_1_dq}]
|
||||
55
src/eth/example/KCU105/fpga/fpga_10g/Makefile
Normal file
55
src/eth/example/KCU105/fpga/fpga_10g/Makefile
Normal file
@@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku040-ffva1156-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexu
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
|
||||
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
21
src/eth/example/KCU105/fpga/fpga_10g/config.tcl
Normal file
21
src/eth/example/KCU105/fpga/fpga_10g/config.tcl
Normal file
@@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# SFP+ rate
|
||||
# 0 for 1G, 1 for 10G
|
||||
dict set params SFP_RATE "1"
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
55
src/eth/example/KCU105/fpga/fpga_1g/Makefile
Normal file
55
src/eth/example/KCU105/fpga/fpga_1g/Makefile
Normal file
@@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku040-ffva1156-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexu
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
|
||||
IP_TCL_FILES += ../ip/basex_pcs_pma_0.tcl
|
||||
IP_TCL_FILES += ../ip/basex_pcs_pma_1.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
21
src/eth/example/KCU105/fpga/fpga_1g/config.tcl
Normal file
21
src/eth/example/KCU105/fpga/fpga_1g/config.tcl
Normal file
@@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# SFP+ rate
|
||||
# 0 for 1G, 1 for 10G
|
||||
dict set params SFP_RATE "0"
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
21
src/eth/example/KCU105/fpga/ip/basex_pcs_pma_0.tcl
Normal file
21
src/eth/example/KCU105/fpga/ip/basex_pcs_pma_0.tcl
Normal file
@@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.Standard {1000BASEX} \
|
||||
CONFIG.Physical_Interface {Transceiver} \
|
||||
CONFIG.Management_Interface {false} \
|
||||
CONFIG.Auto_Negotiation {false} \
|
||||
CONFIG.TransceiverControl {false} \
|
||||
CONFIG.RefClkRate {156.25} \
|
||||
CONFIG.DrpClkRate {62.5} \
|
||||
CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
|
||||
CONFIG.GT_Location {X0Y10} \
|
||||
] [get_ips basex_pcs_pma_0]
|
||||
21
src/eth/example/KCU105/fpga/ip/basex_pcs_pma_1.tcl
Normal file
21
src/eth/example/KCU105/fpga/ip/basex_pcs_pma_1.tcl
Normal file
@@ -0,0 +1,21 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_1
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.Standard {1000BASEX} \
|
||||
CONFIG.Physical_Interface {Transceiver} \
|
||||
CONFIG.Management_Interface {false} \
|
||||
CONFIG.Auto_Negotiation {false} \
|
||||
CONFIG.TransceiverControl {false} \
|
||||
CONFIG.RefClkRate {156.25} \
|
||||
CONFIG.DrpClkRate {62.5} \
|
||||
CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design} \
|
||||
CONFIG.GT_Location {X0Y9} \
|
||||
] [get_ips basex_pcs_pma_1]
|
||||
17
src/eth/example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl
Normal file
17
src/eth/example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl
Normal file
@@ -0,0 +1,17 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name sgmii_pcs_pma_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.Standard {SGMII} \
|
||||
CONFIG.Physical_Interface {LVDS} \
|
||||
CONFIG.Management_Interface {false} \
|
||||
CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
|
||||
CONFIG.LvdsRefClk {625} \
|
||||
] [get_ips sgmii_pcs_pma_0]
|
||||
1
src/eth/example/KCU105/fpga/lib/taxi
Symbolic link
1
src/eth/example/KCU105/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../../../
|
||||
626
src/eth/example/KCU105/fpga/rtl/fpga.sv
Normal file
626
src/eth/example/KCU105/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,626 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "kintexu",
|
||||
// SFP rate selection (0 for 1G, 1 for 10G)
|
||||
parameter logic SFP_RATE = 1'b1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz LVDS
|
||||
* Reset: Push button, active high
|
||||
*/
|
||||
input wire logic clk_125mhz_p,
|
||||
input wire logic clk_125mhz_n,
|
||||
input wire logic reset,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic btnu,
|
||||
input wire logic btnl,
|
||||
input wire logic btnd,
|
||||
input wire logic btnr,
|
||||
input wire logic btnc,
|
||||
input wire logic [3:0] sw,
|
||||
output wire logic [7:0] led,
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
input wire logic uart_rts,
|
||||
output wire logic uart_cts,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T SGMII
|
||||
*/
|
||||
input wire logic phy_sgmii_rx_p,
|
||||
input wire logic phy_sgmii_rx_n,
|
||||
output wire logic phy_sgmii_tx_p,
|
||||
output wire logic phy_sgmii_tx_n,
|
||||
input wire logic phy_sgmii_clk_p,
|
||||
input wire logic phy_sgmii_clk_n,
|
||||
output wire logic phy_reset_n,
|
||||
input wire logic phy_int_n,
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
input wire logic [1:0] sfp_rx_p,
|
||||
input wire logic [1:0] sfp_rx_n,
|
||||
output wire logic [1:0] sfp_tx_p,
|
||||
output wire logic [1:0] sfp_tx_n,
|
||||
input wire logic sfp_mgt_refclk_0_p,
|
||||
input wire logic sfp_mgt_refclk_0_n,
|
||||
|
||||
output wire logic [1:0] sfp_tx_disable_b
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_125mhz_ibufg;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
// Internal 62.5 MHz clock
|
||||
wire clk_62mhz_mmcm_out;
|
||||
wire clk_62mhz_int;
|
||||
|
||||
wire mmcm_rst = reset;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFGDS #(
|
||||
.DIFF_TERM("FALSE"),
|
||||
.IBUF_LOW_PWR("FALSE")
|
||||
)
|
||||
clk_125mhz_ibufg_inst (
|
||||
.O (clk_125mhz_ibufg),
|
||||
.I (clk_125mhz_p),
|
||||
.IB (clk_125mhz_n)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
MMCME3_BASE #(
|
||||
// 125 MHz input
|
||||
.CLKIN1_PERIOD(8.0),
|
||||
.REF_JITTER1(0.010),
|
||||
// 125 MHz input / 1 = 125 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(1),
|
||||
// 125 MHz PFD * 10 = 1250 MHz VCO (range 600 MHz to 1440 MHz)
|
||||
.CLKFBOUT_MULT_F(10),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// 1250 MHz / 20 = 62.5 MHz, 0 degrees
|
||||
.CLKOUT1_DIVIDE(20),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 125 MHz input
|
||||
.CLKIN1(clk_125mhz_ibufg),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// 62.5 MHz, 0 degrees
|
||||
.CLKOUT1(clk_62mhz_mmcm_out),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_62mhz_bufg_inst (
|
||||
.I(clk_62mhz_mmcm_out),
|
||||
.O(clk_62mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire btnu_int;
|
||||
wire btnl_int;
|
||||
wire btnd_int;
|
||||
wire btnr_int;
|
||||
wire btnc_int;
|
||||
wire [3:0] sw_int;
|
||||
|
||||
taxi_debounce_switch #(
|
||||
.WIDTH(9),
|
||||
.N(4),
|
||||
.RATE(125000)
|
||||
)
|
||||
debounce_switch_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
.in({btnu,
|
||||
btnl,
|
||||
btnd,
|
||||
btnr,
|
||||
btnc,
|
||||
sw}),
|
||||
.out({btnu_int,
|
||||
btnl_int,
|
||||
btnd_int,
|
||||
btnr_int,
|
||||
btnc_int,
|
||||
sw_int})
|
||||
);
|
||||
|
||||
wire uart_rxd_int;
|
||||
wire uart_rts_int;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(2),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.in({uart_rxd, uart_rts}),
|
||||
.out({uart_rxd_int, uart_rts_int})
|
||||
);
|
||||
|
||||
wire [7:0] led_int;
|
||||
|
||||
// SGMII interface to PHY
|
||||
wire phy_gmii_clk_int;
|
||||
wire phy_gmii_rst_int;
|
||||
wire phy_gmii_clk_en_int;
|
||||
wire [7:0] phy_gmii_txd_int;
|
||||
wire phy_gmii_tx_en_int;
|
||||
wire phy_gmii_tx_er_int;
|
||||
wire [7:0] phy_gmii_rxd_int;
|
||||
wire phy_gmii_rx_dv_int;
|
||||
wire phy_gmii_rx_er_int;
|
||||
|
||||
wire [15:0] sgmii_status_vect;
|
||||
|
||||
wire sgmii_status_link_status = sgmii_status_vect[0];
|
||||
wire sgmii_status_link_synchronization = sgmii_status_vect[1];
|
||||
wire sgmii_status_rudi_c = sgmii_status_vect[2];
|
||||
wire sgmii_status_rudi_i = sgmii_status_vect[3];
|
||||
wire sgmii_status_rudi_invalid = sgmii_status_vect[4];
|
||||
wire sgmii_status_rxdisperr = sgmii_status_vect[5];
|
||||
wire sgmii_status_rxnotintable = sgmii_status_vect[6];
|
||||
wire sgmii_status_phy_link_status = sgmii_status_vect[7];
|
||||
wire [1:0] sgmii_status_remote_fault_encdg = sgmii_status_vect[9:8];
|
||||
wire [1:0] sgmii_status_speed = sgmii_status_vect[11:10];
|
||||
wire sgmii_status_duplex = sgmii_status_vect[12];
|
||||
wire sgmii_status_remote_fault = sgmii_status_vect[13];
|
||||
wire [1:0] sgmii_status_pause = sgmii_status_vect[15:14];
|
||||
|
||||
wire [4:0] sgmii_config_vect;
|
||||
|
||||
assign sgmii_config_vect[4] = 1'b1; // autonegotiation enable
|
||||
assign sgmii_config_vect[3] = 1'b0; // isolate
|
||||
assign sgmii_config_vect[2] = 1'b0; // power down
|
||||
assign sgmii_config_vect[1] = 1'b0; // loopback enable
|
||||
assign sgmii_config_vect[0] = 1'b0; // unidirectional enable
|
||||
|
||||
wire [15:0] sgmii_an_config_vect;
|
||||
|
||||
assign sgmii_an_config_vect[15] = 1'b1; // SGMII link status
|
||||
assign sgmii_an_config_vect[14] = 1'b1; // SGMII Acknowledge
|
||||
assign sgmii_an_config_vect[13:12] = 2'b01; // full duplex
|
||||
assign sgmii_an_config_vect[11:10] = 2'b10; // SGMII speed
|
||||
assign sgmii_an_config_vect[9] = 1'b0; // reserved
|
||||
assign sgmii_an_config_vect[8:7] = 2'b00; // pause frames - SGMII reserved
|
||||
assign sgmii_an_config_vect[6] = 1'b0; // reserved
|
||||
assign sgmii_an_config_vect[5] = 1'b0; // full duplex - SGMII reserved
|
||||
assign sgmii_an_config_vect[4:1] = 4'b0000; // reserved
|
||||
assign sgmii_an_config_vect[0] = 1'b1; // SGMII
|
||||
|
||||
sgmii_pcs_pma_0
|
||||
eth_pcspma (
|
||||
// SGMII
|
||||
.txp (phy_sgmii_tx_p),
|
||||
.txn (phy_sgmii_tx_n),
|
||||
.rxp (phy_sgmii_rx_p),
|
||||
.rxn (phy_sgmii_rx_n),
|
||||
|
||||
// Ref clock from PHY
|
||||
.refclk625_p (phy_sgmii_clk_p),
|
||||
.refclk625_n (phy_sgmii_clk_n),
|
||||
|
||||
// async reset
|
||||
.reset (rst_125mhz_int),
|
||||
|
||||
// clock and reset outputs
|
||||
.clk125_out (phy_gmii_clk_int),
|
||||
.clk625_out (),
|
||||
.clk312_out (),
|
||||
.rst_125_out (phy_gmii_rst_int),
|
||||
.idelay_rdy_out (),
|
||||
.mmcm_locked_out (),
|
||||
|
||||
// MAC clocking
|
||||
.sgmii_clk_r (),
|
||||
.sgmii_clk_f (),
|
||||
.sgmii_clk_en (phy_gmii_clk_en_int),
|
||||
|
||||
// Speed control
|
||||
.speed_is_10_100 (sgmii_status_speed != 2'b10),
|
||||
.speed_is_100 (sgmii_status_speed == 2'b01),
|
||||
|
||||
// Internal GMII
|
||||
.gmii_txd (phy_gmii_txd_int),
|
||||
.gmii_tx_en (phy_gmii_tx_en_int),
|
||||
.gmii_tx_er (phy_gmii_tx_er_int),
|
||||
.gmii_rxd (phy_gmii_rxd_int),
|
||||
.gmii_rx_dv (phy_gmii_rx_dv_int),
|
||||
.gmii_rx_er (phy_gmii_rx_er_int),
|
||||
.gmii_isolate (),
|
||||
|
||||
// Configuration
|
||||
.configuration_vector (sgmii_config_vect),
|
||||
|
||||
.an_interrupt (),
|
||||
.an_adv_config_vector (sgmii_an_config_vect),
|
||||
.an_restart_config (1'b0),
|
||||
|
||||
// Status
|
||||
.status_vector (sgmii_status_vect),
|
||||
.signal_detect (1'b1)
|
||||
);
|
||||
|
||||
// SFP+
|
||||
wire [1:0] sfp_tx_p_int;
|
||||
wire [1:0] sfp_tx_n_int;
|
||||
|
||||
wire sfp0_gmii_clk_int;
|
||||
wire sfp0_gmii_rst_int;
|
||||
wire sfp0_gmii_clk_en_int = 1'b1;
|
||||
wire [7:0] sfp0_gmii_txd_int;
|
||||
wire sfp0_gmii_tx_en_int;
|
||||
wire sfp0_gmii_tx_er_int;
|
||||
wire [7:0] sfp0_gmii_rxd_int;
|
||||
wire sfp0_gmii_rx_dv_int;
|
||||
wire sfp0_gmii_rx_er_int;
|
||||
|
||||
wire [15:0] sfp0_status_vect;
|
||||
|
||||
wire sfp1_gmii_clk_int;
|
||||
wire sfp1_gmii_rst_int;
|
||||
wire sfp1_gmii_clk_en_int = 1'b1;
|
||||
wire [7:0] sfp1_gmii_txd_int;
|
||||
wire sfp1_gmii_tx_en_int;
|
||||
wire sfp1_gmii_tx_er_int;
|
||||
wire [7:0] sfp1_gmii_rxd_int;
|
||||
wire sfp1_gmii_rx_dv_int;
|
||||
wire sfp1_gmii_rx_er_int;
|
||||
|
||||
wire [15:0] sfp1_status_vect;
|
||||
|
||||
if (SFP_RATE == 0) begin : sfp_phy
|
||||
// 1000BASE-X
|
||||
|
||||
wire sfp0_gmii_gtrefclk;
|
||||
wire sfp0_gmii_txuserclk;
|
||||
wire sfp0_gmii_txuserclk2;
|
||||
wire sfp0_gmii_rxuserclk;
|
||||
wire sfp0_gmii_rxuserclk2;
|
||||
wire sfp0_gmii_resetdone;
|
||||
wire sfp0_gmii_pmareset;
|
||||
wire sfp0_gmii_mmcm_locked;
|
||||
|
||||
assign sfp0_gmii_clk_int = sfp0_gmii_txuserclk2;
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_sfp0_inst (
|
||||
.clk(sfp0_gmii_clk_int),
|
||||
.rst(rst_125mhz_int || !sfp0_gmii_resetdone),
|
||||
.out(sfp0_gmii_rst_int)
|
||||
);
|
||||
|
||||
wire sfp0_status_link_status = sfp0_status_vect[0];
|
||||
wire sfp0_status_link_synchronization = sfp0_status_vect[1];
|
||||
wire sfp0_status_rudi_c = sfp0_status_vect[2];
|
||||
wire sfp0_status_rudi_i = sfp0_status_vect[3];
|
||||
wire sfp0_status_rudi_invalid = sfp0_status_vect[4];
|
||||
wire sfp0_status_rxdisperr = sfp0_status_vect[5];
|
||||
wire sfp0_status_rxnotintable = sfp0_status_vect[6];
|
||||
wire sfp0_status_phy_link_status = sfp0_status_vect[7];
|
||||
wire [1:0] sfp0_status_remote_fault_encdg = sfp0_status_vect[9:8];
|
||||
wire [1:0] sfp0_status_speed = sfp0_status_vect[11:10];
|
||||
wire sfp0_status_duplex = sfp0_status_vect[12];
|
||||
wire sfp0_status_remote_fault = sfp0_status_vect[13];
|
||||
wire [1:0] sfp0_status_pause = sfp0_status_vect[15:14];
|
||||
|
||||
wire [4:0] sfp0_config_vect;
|
||||
|
||||
assign sfp0_config_vect[4] = 1'b0; // autonegotiation enable
|
||||
assign sfp0_config_vect[3] = 1'b0; // isolate
|
||||
assign sfp0_config_vect[2] = 1'b0; // power down
|
||||
assign sfp0_config_vect[1] = 1'b0; // loopback enable
|
||||
assign sfp0_config_vect[0] = 1'b0; // unidirectional enable
|
||||
|
||||
basex_pcs_pma_0
|
||||
sfp0_pcspma (
|
||||
.gtrefclk_p(sfp_mgt_refclk_0_p),
|
||||
.gtrefclk_n(sfp_mgt_refclk_0_n),
|
||||
.gtrefclk_out(sfp0_gmii_gtrefclk),
|
||||
.txn(sfp_tx_n[0]),
|
||||
.txp(sfp_tx_p[0]),
|
||||
.rxn(sfp_rx_n[0]),
|
||||
.rxp(sfp_rx_p[0]),
|
||||
.independent_clock_bufg(clk_62mhz_int),
|
||||
.userclk_out(sfp0_gmii_txuserclk),
|
||||
.userclk2_out(sfp0_gmii_txuserclk2),
|
||||
.rxuserclk_out(sfp0_gmii_rxuserclk),
|
||||
.rxuserclk2_out(sfp0_gmii_rxuserclk2),
|
||||
.gtpowergood(),
|
||||
.resetdone(sfp0_gmii_resetdone),
|
||||
.pma_reset_out(sfp0_gmii_pmareset),
|
||||
.mmcm_locked_out(sfp0_gmii_mmcm_locked),
|
||||
.gmii_txd(sfp0_gmii_txd_int),
|
||||
.gmii_tx_en(sfp0_gmii_tx_en_int),
|
||||
.gmii_tx_er(sfp0_gmii_tx_er_int),
|
||||
.gmii_rxd(sfp0_gmii_rxd_int),
|
||||
.gmii_rx_dv(sfp0_gmii_rx_dv_int),
|
||||
.gmii_rx_er(sfp0_gmii_rx_er_int),
|
||||
.gmii_isolate(),
|
||||
.configuration_vector(sfp0_config_vect),
|
||||
.status_vector(sfp0_status_vect),
|
||||
.reset(rst_125mhz_int),
|
||||
.signal_detect(1'b1)
|
||||
);
|
||||
|
||||
wire sfp1_gmii_txuserclk2 = sfp0_gmii_txuserclk2;
|
||||
wire sfp1_gmii_resetdone;
|
||||
|
||||
assign sfp1_gmii_clk_int = sfp1_gmii_txuserclk2;
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_sfp1_inst (
|
||||
.clk(sfp1_gmii_clk_int),
|
||||
.rst(rst_125mhz_int || !sfp1_gmii_resetdone),
|
||||
.out(sfp1_gmii_rst_int)
|
||||
);
|
||||
|
||||
wire sfp1_status_link_status = sfp1_status_vect[0];
|
||||
wire sfp1_status_link_synchronization = sfp1_status_vect[1];
|
||||
wire sfp1_status_rudi_c = sfp1_status_vect[2];
|
||||
wire sfp1_status_rudi_i = sfp1_status_vect[3];
|
||||
wire sfp1_status_rudi_invalid = sfp1_status_vect[4];
|
||||
wire sfp1_status_rxdisperr = sfp1_status_vect[5];
|
||||
wire sfp1_status_rxnotintable = sfp1_status_vect[6];
|
||||
wire sfp1_status_phy_link_status = sfp1_status_vect[7];
|
||||
wire [1:0] sfp1_status_remote_fault_encdg = sfp1_status_vect[9:8];
|
||||
wire [1:0] sfp1_status_speed = sfp1_status_vect[11:10];
|
||||
wire sfp1_status_duplex = sfp1_status_vect[12];
|
||||
wire sfp1_status_remote_fault = sfp1_status_vect[13];
|
||||
wire [1:0] sfp1_status_pause = sfp1_status_vect[15:14];
|
||||
|
||||
wire [4:0] sfp1_config_vect;
|
||||
|
||||
assign sfp1_config_vect[4] = 1'b0; // autonegotiation enable
|
||||
assign sfp1_config_vect[3] = 1'b0; // isolate
|
||||
assign sfp1_config_vect[2] = 1'b0; // power down
|
||||
assign sfp1_config_vect[1] = 1'b0; // loopback enable
|
||||
assign sfp1_config_vect[0] = 1'b0; // unidirectional enable
|
||||
|
||||
basex_pcs_pma_1
|
||||
sfp1_pcspma (
|
||||
.gtrefclk(sfp0_gmii_gtrefclk),
|
||||
.txn(sfp_tx_n[1]),
|
||||
.txp(sfp_tx_p[1]),
|
||||
.rxn(sfp_rx_n[1]),
|
||||
.rxp(sfp_rx_p[1]),
|
||||
.independent_clock_bufg(clk_62mhz_int),
|
||||
.txoutclk(),
|
||||
.gtpowergood(),
|
||||
.rxoutclk(),
|
||||
.resetdone(sfp1_gmii_resetdone),
|
||||
.cplllock(),
|
||||
.mmcm_reset(),
|
||||
.userclk(sfp0_gmii_txuserclk),
|
||||
.userclk2(sfp0_gmii_txuserclk2),
|
||||
.pma_reset(sfp0_gmii_pmareset),
|
||||
.mmcm_locked(sfp0_gmii_mmcm_locked),
|
||||
.rxuserclk(sfp0_gmii_txuserclk),
|
||||
.rxuserclk2(sfp0_gmii_txuserclk2),
|
||||
.gmii_txd(sfp1_gmii_txd_int),
|
||||
.gmii_tx_en(sfp1_gmii_tx_en_int),
|
||||
.gmii_tx_er(sfp1_gmii_tx_er_int),
|
||||
.gmii_rxd(sfp1_gmii_rxd_int),
|
||||
.gmii_rx_dv(sfp1_gmii_rx_dv_int),
|
||||
.gmii_rx_er(sfp1_gmii_rx_er_int),
|
||||
.gmii_isolate(),
|
||||
.configuration_vector(sfp1_config_vect),
|
||||
.status_vector(sfp1_status_vect),
|
||||
.reset(rst_125mhz_int),
|
||||
.signal_detect(1'b1)
|
||||
);
|
||||
|
||||
end else begin
|
||||
// 10GBASE-R
|
||||
|
||||
assign sfp_tx_p = sfp_tx_p_int;
|
||||
assign sfp_tx_n = sfp_tx_n_int;
|
||||
|
||||
end
|
||||
|
||||
// SGMII interface debug:
|
||||
// SW12:1 (sw[3]) off for payload byte, on for status vector
|
||||
// SW12:2 (sw[2]) off for BASE-T port (SGMII), on for SFP
|
||||
// SW12:3 (sw[1]) off for SFP0, on for SFP1
|
||||
// SW12:4 (sw[0]) off for LSB of status vector, on for MSB
|
||||
wire [15:0] sel_sv = sw[2] ? (sw[1] ? sfp1_status_vect : sfp0_status_vect) : sgmii_status_vect;
|
||||
assign led = sw[3] ? (sw[0] ? sel_sv[15:8] : sel_sv[7:0]) : led_int;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.SFP_RATE(SFP_RATE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.btnu(btnu_int),
|
||||
.btnl(btnl_int),
|
||||
.btnd(btnd_int),
|
||||
.btnr(btnr_int),
|
||||
.btnc(btnc_int),
|
||||
.sw(sw_int),
|
||||
.led(led_int),
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd_int),
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rts(uart_rts_int),
|
||||
.uart_cts(uart_cts),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T SGMII
|
||||
*/
|
||||
.phy_gmii_clk(phy_gmii_clk_int),
|
||||
.phy_gmii_rst(phy_gmii_rst_int),
|
||||
.phy_gmii_clk_en(phy_gmii_clk_en_int),
|
||||
.phy_gmii_rxd(phy_gmii_rxd_int),
|
||||
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
|
||||
.phy_gmii_rx_er(phy_gmii_rx_er_int),
|
||||
.phy_gmii_txd(phy_gmii_txd_int),
|
||||
.phy_gmii_tx_en(phy_gmii_tx_en_int),
|
||||
.phy_gmii_tx_er(phy_gmii_tx_er_int),
|
||||
.phy_reset_n(phy_reset_n),
|
||||
.phy_int_n(phy_int_n),
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
.sfp_rx_p(sfp_rx_p),
|
||||
.sfp_rx_n(sfp_rx_n),
|
||||
.sfp_tx_p(sfp_tx_p_int),
|
||||
.sfp_tx_n(sfp_tx_n_int),
|
||||
.sfp_mgt_refclk_0_p(sfp_mgt_refclk_0_p),
|
||||
.sfp_mgt_refclk_0_n(sfp_mgt_refclk_0_n),
|
||||
|
||||
.sfp0_gmii_clk(sfp0_gmii_clk_int),
|
||||
.sfp0_gmii_rst(sfp0_gmii_rst_int),
|
||||
.sfp0_gmii_clk_en(sfp0_gmii_clk_en_int),
|
||||
.sfp0_gmii_rxd(sfp0_gmii_rxd_int),
|
||||
.sfp0_gmii_rx_dv(sfp0_gmii_rx_dv_int),
|
||||
.sfp0_gmii_rx_er(sfp0_gmii_rx_er_int),
|
||||
.sfp0_gmii_txd(sfp0_gmii_txd_int),
|
||||
.sfp0_gmii_tx_en(sfp0_gmii_tx_en_int),
|
||||
.sfp0_gmii_tx_er(sfp0_gmii_tx_er_int),
|
||||
|
||||
.sfp1_gmii_clk(sfp1_gmii_clk_int),
|
||||
.sfp1_gmii_rst(sfp1_gmii_rst_int),
|
||||
.sfp1_gmii_clk_en(sfp1_gmii_clk_en_int),
|
||||
.sfp1_gmii_rxd(sfp1_gmii_rxd_int),
|
||||
.sfp1_gmii_rx_dv(sfp1_gmii_rx_dv_int),
|
||||
.sfp1_gmii_rx_er(sfp1_gmii_rx_er_int),
|
||||
.sfp1_gmii_txd(sfp1_gmii_txd_int),
|
||||
.sfp1_gmii_tx_en(sfp1_gmii_tx_en_int),
|
||||
.sfp1_gmii_tx_er(sfp1_gmii_tx_er_int),
|
||||
|
||||
.sfp_tx_disable_b(sfp_tx_disable_b)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
798
src/eth/example/KCU105/fpga/rtl/fpga_core.sv
Normal file
798
src/eth/example/KCU105/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,798 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "kintexu",
|
||||
// SFP rate selection (0 for 1G, 1 for 10G)
|
||||
parameter logic SFP_RATE = 1'b1
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic btnu,
|
||||
input wire logic btnl,
|
||||
input wire logic btnd,
|
||||
input wire logic btnr,
|
||||
input wire logic btnc,
|
||||
input wire logic [7:0] sw,
|
||||
output wire logic [7:0] led,
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
input wire logic uart_rts,
|
||||
output wire logic uart_cts,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T
|
||||
*/
|
||||
input wire logic phy_gmii_clk,
|
||||
input wire logic phy_gmii_rst,
|
||||
input wire logic phy_gmii_clk_en,
|
||||
input wire logic [7:0] phy_gmii_rxd,
|
||||
input wire logic phy_gmii_rx_dv,
|
||||
input wire logic phy_gmii_rx_er,
|
||||
output wire logic [7:0] phy_gmii_txd,
|
||||
output wire logic phy_gmii_tx_en,
|
||||
output wire logic phy_gmii_tx_er,
|
||||
output wire logic phy_reset_n,
|
||||
input wire logic phy_int_n,
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
input wire logic [1:0] sfp_rx_p,
|
||||
input wire logic [1:0] sfp_rx_n,
|
||||
output wire logic [1:0] sfp_tx_p,
|
||||
output wire logic [1:0] sfp_tx_n,
|
||||
input wire logic sfp_mgt_refclk_0_p,
|
||||
input wire logic sfp_mgt_refclk_0_n,
|
||||
|
||||
input wire logic sfp0_gmii_clk,
|
||||
input wire logic sfp0_gmii_rst,
|
||||
input wire logic sfp0_gmii_clk_en,
|
||||
input wire logic [7:0] sfp0_gmii_rxd,
|
||||
input wire logic sfp0_gmii_rx_dv,
|
||||
input wire logic sfp0_gmii_rx_er,
|
||||
output wire logic [7:0] sfp0_gmii_txd,
|
||||
output wire logic sfp0_gmii_tx_en,
|
||||
output wire logic sfp0_gmii_tx_er,
|
||||
|
||||
input wire logic sfp1_gmii_clk,
|
||||
input wire logic sfp1_gmii_rst,
|
||||
input wire logic sfp1_gmii_clk_en,
|
||||
input wire logic [7:0] sfp1_gmii_rxd,
|
||||
input wire logic sfp1_gmii_rx_dv,
|
||||
input wire logic sfp1_gmii_rx_er,
|
||||
output wire logic [7:0] sfp1_gmii_txd,
|
||||
output wire logic sfp1_gmii_tx_en,
|
||||
output wire logic sfp1_gmii_tx_er,
|
||||
|
||||
output wire logic [1:0] sfp_tx_disable_b
|
||||
);
|
||||
|
||||
assign led = sw;
|
||||
|
||||
// XFCP
|
||||
assign uart_cts = 1'b0;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
|
||||
|
||||
taxi_xfcp_if_uart #(
|
||||
.TX_FIFO_DEPTH(512),
|
||||
.RX_FIFO_DEPTH(512)
|
||||
)
|
||||
xfcp_if_uart_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.uart_rxd(uart_rxd),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* XFCP downstream interface
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_ds),
|
||||
.xfcp_dsp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/921600))
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
|
||||
|
||||
taxi_xfcp_switch #(
|
||||
.XFCP_ID_STR("KCU105"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR("Taxi example"),
|
||||
.PORTS($size(xfcp_sw_us))
|
||||
)
|
||||
xfcp_sw_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_ds),
|
||||
.xfcp_usp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* XFCP downstream ports
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_sw_ds),
|
||||
.xfcp_dsp_us(xfcp_sw_us)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
|
||||
|
||||
taxi_xfcp_mod_stats #(
|
||||
.XFCP_ID_STR("Statistics"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR(""),
|
||||
.STAT_COUNT_W(64),
|
||||
.STAT_PIPELINE(2)
|
||||
)
|
||||
xfcp_stats_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_sw_ds[0]),
|
||||
.xfcp_usp_us(xfcp_sw_us[0]),
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
.s_axis_stat(axis_stat)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[SFP_RATE ? 2 : 3]();
|
||||
|
||||
taxi_axis_arb_mux #(
|
||||
.S_COUNT($size(axis_eth_stat)),
|
||||
.UPDATE_TID(1'b0),
|
||||
.ARB_ROUND_ROBIN(1'b1),
|
||||
.ARB_LSB_HIGH_PRIO(1'b0)
|
||||
)
|
||||
stat_mux_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream inputs (sink)
|
||||
*/
|
||||
.s_axis(axis_eth_stat),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(axis_stat)
|
||||
);
|
||||
|
||||
// BASE-T PHY
|
||||
assign phy_reset_n = !rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
|
||||
|
||||
taxi_eth_mac_1g_fifo #(
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(0),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR("SGMII0"),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
eth_mac_inst (
|
||||
.rx_clk(phy_gmii_clk),
|
||||
.rx_rst(phy_gmii_rst),
|
||||
.tx_clk(phy_gmii_clk),
|
||||
.tx_rst(phy_gmii_rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_eth),
|
||||
.m_axis_tx_cpl(axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rxd(phy_gmii_rxd),
|
||||
.gmii_rx_dv(phy_gmii_rx_dv),
|
||||
.gmii_rx_er(phy_gmii_rx_er),
|
||||
.gmii_txd(phy_gmii_txd),
|
||||
.gmii_tx_en(phy_gmii_tx_en),
|
||||
.gmii_tx_er(phy_gmii_tx_er),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.rx_clk_enable(phy_gmii_clk_en),
|
||||
.tx_clk_enable(phy_gmii_clk_en),
|
||||
.rx_mii_select(1'b0),
|
||||
.tx_mii_select(1'b0),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_eth_stat[0]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(16'd9218),
|
||||
.cfg_tx_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_max_pkt_len(16'd9218),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
// SFP+
|
||||
assign sfp_tx_disable_b = '1;
|
||||
|
||||
if (SFP_RATE == 0) begin : sfp_mac
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp0_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp0_tx_cpl();
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp1_eth();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp1_tx_cpl();
|
||||
|
||||
taxi_eth_mac_1g_fifo #(
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE((16+16)+(16+16)*0),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR("SFP0"),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
sfp0_eth_mac_inst (
|
||||
.rx_clk(sfp0_gmii_clk),
|
||||
.rx_rst(sfp0_gmii_rst),
|
||||
.tx_clk(sfp0_gmii_clk),
|
||||
.tx_rst(sfp0_gmii_rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_sfp0_eth),
|
||||
.m_axis_tx_cpl(axis_sfp0_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_sfp0_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rxd(sfp0_gmii_rxd),
|
||||
.gmii_rx_dv(sfp0_gmii_rx_dv),
|
||||
.gmii_rx_er(sfp0_gmii_rx_er),
|
||||
.gmii_txd(sfp0_gmii_txd),
|
||||
.gmii_tx_en(sfp0_gmii_tx_en),
|
||||
.gmii_tx_er(sfp0_gmii_tx_er),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.rx_clk_enable(sfp0_gmii_clk_en),
|
||||
.tx_clk_enable(sfp0_gmii_clk_en),
|
||||
.rx_mii_select(1'b0),
|
||||
.tx_mii_select(1'b0),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_eth_stat[1]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(16'd9218),
|
||||
.cfg_tx_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_max_pkt_len(16'd9218),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
taxi_eth_mac_1g_fifo #(
|
||||
.PADDING_EN(1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE((16+16)+(16+16)*1),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR("SFP1"),
|
||||
.TX_FIFO_DEPTH(16384),
|
||||
.TX_FRAME_FIFO(1),
|
||||
.RX_FIFO_DEPTH(16384),
|
||||
.RX_FRAME_FIFO(1)
|
||||
)
|
||||
sfp1_eth_mac_inst (
|
||||
.rx_clk(sfp1_gmii_clk),
|
||||
.rx_rst(sfp1_gmii_rst),
|
||||
.tx_clk(sfp1_gmii_clk),
|
||||
.tx_rst(sfp1_gmii_rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_sfp1_eth),
|
||||
.m_axis_tx_cpl(axis_sfp1_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_sfp1_eth),
|
||||
|
||||
/*
|
||||
* GMII interface
|
||||
*/
|
||||
.gmii_rxd(sfp1_gmii_rxd),
|
||||
.gmii_rx_dv(sfp1_gmii_rx_dv),
|
||||
.gmii_rx_er(sfp1_gmii_rx_er),
|
||||
.gmii_txd(sfp1_gmii_txd),
|
||||
.gmii_tx_en(sfp1_gmii_tx_en),
|
||||
.gmii_tx_er(sfp1_gmii_tx_er),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.rx_clk_enable(sfp1_gmii_clk_en),
|
||||
.tx_clk_enable(sfp1_gmii_clk_en),
|
||||
.rx_mii_select(1'b0),
|
||||
.tx_mii_select(1'b0),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_eth_stat[2]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(),
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(16'd9218),
|
||||
.cfg_tx_ifg(8'd12),
|
||||
.cfg_tx_enable(1'b1),
|
||||
.cfg_rx_max_pkt_len(16'd9218),
|
||||
.cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
end else begin : sfp_mac
|
||||
|
||||
wire [1:0] sfp_tx_clk;
|
||||
wire [1:0] sfp_tx_rst;
|
||||
wire [1:0] sfp_rx_clk;
|
||||
wire [1:0] sfp_rx_rst;
|
||||
|
||||
wire [1:0] sfp_rx_status;
|
||||
|
||||
wire sfp_gtpowergood;
|
||||
|
||||
wire sfp_mgt_refclk_0;
|
||||
wire sfp_mgt_refclk_0_int;
|
||||
wire sfp_mgt_refclk_0_bufg;
|
||||
|
||||
wire sfp_rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_tx[2]();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[2]();
|
||||
|
||||
if (SIM) begin
|
||||
|
||||
assign sfp_mgt_refclk_0 = sfp_mgt_refclk_0_p;
|
||||
assign sfp_mgt_refclk_0_int = sfp_mgt_refclk_0_p;
|
||||
assign sfp_mgt_refclk_0_bufg = sfp_mgt_refclk_0_int;
|
||||
|
||||
end else begin
|
||||
|
||||
IBUFDS_GTE3 ibufds_gte3_sfp_mgt_refclk_0_inst (
|
||||
.I (sfp_mgt_refclk_0_p),
|
||||
.IB (sfp_mgt_refclk_0_n),
|
||||
.CEB (1'b0),
|
||||
.O (sfp_mgt_refclk_0),
|
||||
.ODIV2 (sfp_mgt_refclk_0_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_sfp_mgt_refclk_0_inst (
|
||||
.CE (sfp_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (sfp_mgt_refclk_0_int),
|
||||
.O (sfp_mgt_refclk_0_bufg)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sfp_sync_reset_inst (
|
||||
.clk(sfp_mgt_refclk_0_bufg),
|
||||
.rst(rst),
|
||||
.out(sfp_rst)
|
||||
);
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(2),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTH"),
|
||||
|
||||
// PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(16+16),
|
||||
.STAT_UPDATE_PERIOD(1024)//,
|
||||
// disabled due to verilator bug
|
||||
// .STAT_STR_EN(1),
|
||||
// .STAT_PREFIX_STR('{"SFP0", "SFP1"})
|
||||
)
|
||||
sfp_mac_inst (
|
||||
.xcvr_ctrl_clk(clk),
|
||||
.xcvr_ctrl_rst(sfp_rst),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(sfp_gtpowergood),
|
||||
.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(sfp_tx_p),
|
||||
.xcvr_txn(sfp_tx_n),
|
||||
.xcvr_rxp(sfp_rx_p),
|
||||
.xcvr_rxn(sfp_rx_n),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(sfp_rx_clk),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(sfp_rx_rst),
|
||||
.tx_clk(sfp_tx_clk),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(sfp_tx_rst),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_sfp_tx),
|
||||
.m_axis_tx_cpl(axis_sfp_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_sfp_rx),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('{2{'0}}),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('{2{'0}}),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('{2{'0}}),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('{2{'0}}),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('{2{'0}}),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk),
|
||||
.stat_rst(rst),
|
||||
.m_axis_stat(axis_eth_stat[1]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(sfp_rx_status),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(),
|
||||
.stat_rx_err_bad_block(),
|
||||
.stat_rx_err_framing(),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop('0),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len('{2{16'd9218}}),
|
||||
.cfg_tx_ifg('{2{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_max_pkt_len('{2{16'd9218}}),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{2{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{2{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{2{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{2{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{2{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{2{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{2{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{2{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{2{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{2{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{2{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{2{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{2{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{2{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{2{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{2{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{2{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{2{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < 2; n = n + 1) begin : sfp_ch
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(16384),
|
||||
.RAM_PIPELINE(2),
|
||||
.FRAME_FIFO(1),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(1),
|
||||
.DROP_BAD_FRAME(1),
|
||||
.DROP_WHEN_FULL(1)
|
||||
)
|
||||
ch_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(sfp_rx_clk[n]),
|
||||
.s_rst(sfp_rx_rst[n]),
|
||||
.s_axis(axis_sfp_rx[n]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(sfp_tx_clk[n]),
|
||||
.m_rst(sfp_tx_rst[n]),
|
||||
.m_axis(axis_sfp_tx[n]),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user