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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
445
src/eth/example/XUPP3R/fpga/rtl/fpga_xusp3s.sv
Normal file
445
src/eth/example/XUPP3R/fpga/rtl/fpga_xusp3s.sv
Normal file
@@ -0,0 +1,445 @@
|
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
|
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexu"
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)
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(
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/*
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* Clock: 48MHz
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*/
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input wire logic clk_48mhz,
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input wire logic sys_rst_l,
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/*
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* GPIO
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*/
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output wire logic [3:0] led,
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|
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/*
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* UART: 3000000 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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/*
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* I2C and related signals
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*/
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inout wire logic eeprom_i2c_scl,
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inout wire logic eeprom_i2c_sda,
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output wire logic fpga_i2c_master_l,
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output wire logic qsfp_ctl_en,
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||||
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/*
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* Ethernet: QSFP28
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*/
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output wire logic [3:0] qsfp0_tx_p,
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output wire logic [3:0] qsfp0_tx_n,
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input wire logic [3:0] qsfp0_rx_p,
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input wire logic [3:0] qsfp0_rx_n,
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input wire logic qsfp0_mgt_refclk_b0_p,
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input wire logic qsfp0_mgt_refclk_b0_n,
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// input wire logic qsfp0_mgt_refclk_b1_p,
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// input wire logic qsfp0_mgt_refclk_b1_n,
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// input wire logic qsfp0_mgt_refclk_c0_p,
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// input wire logic qsfp0_mgt_refclk_c0_n,
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// input wire logic qsfp0_mgt_refclk_c1_p,
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// input wire logic qsfp0_mgt_refclk_c1_n,
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output wire logic qsfp0_resetl,
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input wire logic qsfp0_modprsl,
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input wire logic qsfp0_intl,
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output wire logic qsfp0_lpmode,
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inout wire logic qsfp0_i2c_scl,
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inout wire logic qsfp0_i2c_sda,
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output wire logic [3:0] qsfp1_tx_p,
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output wire logic [3:0] qsfp1_tx_n,
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input wire logic [3:0] qsfp1_rx_p,
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input wire logic [3:0] qsfp1_rx_n,
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input wire logic qsfp1_mgt_refclk_b0_p,
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input wire logic qsfp1_mgt_refclk_b0_n,
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// input wire logic qsfp1_mgt_refclk_b1_p,
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// input wire logic qsfp1_mgt_refclk_b1_n,
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// input wire logic qsfp1_mgt_refclk_c2_p,
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// input wire logic qsfp1_mgt_refclk_c2_n,
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// input wire logic qsfp1_mgt_refclk_c3_p,
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// input wire logic qsfp1_mgt_refclk_c3_n,
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output wire logic qsfp1_resetl,
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input wire logic qsfp1_modprsl,
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input wire logic qsfp1_intl,
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output wire logic qsfp1_lpmode,
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inout wire logic qsfp1_i2c_scl,
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inout wire logic qsfp1_i2c_sda,
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||||
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output wire logic [3:0] qsfp2_tx_p,
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output wire logic [3:0] qsfp2_tx_n,
|
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input wire logic [3:0] qsfp2_rx_p,
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input wire logic [3:0] qsfp2_rx_n,
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input wire logic qsfp2_mgt_refclk_b0_p,
|
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input wire logic qsfp2_mgt_refclk_b0_n,
|
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// input wire logic qsfp2_mgt_refclk_b2_p,
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// input wire logic qsfp2_mgt_refclk_b2_n,
|
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// input wire logic qsfp2_mgt_refclk_d0_p,
|
||||
// input wire logic qsfp2_mgt_refclk_d0_n,
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||||
// input wire logic qsfp2_mgt_refclk_d1_p,
|
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// input wire logic qsfp2_mgt_refclk_d1_n,
|
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output wire logic qsfp2_resetl,
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input wire logic qsfp2_modprsl,
|
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input wire logic qsfp2_intl,
|
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output wire logic qsfp2_lpmode,
|
||||
inout wire logic qsfp2_i2c_scl,
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||||
inout wire logic qsfp2_i2c_sda,
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output wire logic [3:0] qsfp3_tx_p,
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output wire logic [3:0] qsfp3_tx_n,
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input wire logic [3:0] qsfp3_rx_p,
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input wire logic [3:0] qsfp3_rx_n,
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input wire logic qsfp3_mgt_refclk_b0_p,
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input wire logic qsfp3_mgt_refclk_b0_n,
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// input wire logic qsfp3_mgt_refclk_b3_p,
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// input wire logic qsfp3_mgt_refclk_b3_n,
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||||
// input wire logic qsfp3_mgt_refclk_d2_p,
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// input wire logic qsfp3_mgt_refclk_d2_n,
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// input wire logic qsfp3_mgt_refclk_d3_p,
|
||||
// input wire logic qsfp3_mgt_refclk_d3_n,
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output wire logic qsfp3_resetl,
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input wire logic qsfp3_modprsl,
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input wire logic qsfp3_intl,
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output wire logic qsfp3_lpmode,
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inout wire logic qsfp3_i2c_scl,
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inout wire logic qsfp3_i2c_sda
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);
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// Clock and reset
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wire clk_125mhz_mmcm_out;
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// Internal 125 MHz clock
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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wire mmcm_rst = !sys_rst_l;
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wire mmcm_locked;
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wire mmcm_clkfb;
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// MMCM instance
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MMCME3_BASE #(
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// 48 MHz input
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.CLKIN1_PERIOD(20.833),
|
||||
.REF_JITTER1(0.010),
|
||||
// 48 MHz input / 3 = 16 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(3),
|
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// 16 MHz PFD * 62.5 = 1000 MHz VCO (range 600 MHz to 1440 MHz)
|
||||
.CLKFBOUT_MULT_F(62.5),
|
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.CLKFBOUT_PHASE(0),
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// 1000 MHz / 8 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
|
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.CLKOUT0_PHASE(0),
|
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// Not used
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
|
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
|
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.CLKOUT2_PHASE(0),
|
||||
// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
|
||||
.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
|
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.CLKOUT4_CASCADE("FALSE"),
|
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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|
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// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
|
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)
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clk_mmcm_inst (
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// 48 MHz input
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.CLKIN1(clk_48mhz),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// Not used
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.CLKOUT1(),
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.CLKOUT1B(),
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||||
// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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||||
.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
|
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);
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// GPIO
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assign qsfp_ctl_en = 1'b1;
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assign fpga_i2c_master_l = 1'b0;
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wire uart_rxd_int;
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wire eeprom_i2c_scl_i;
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wire eeprom_i2c_scl_o;
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wire eeprom_i2c_sda_i;
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wire eeprom_i2c_sda_o;
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wire qsfp0_modprsl_int;
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wire qsfp0_intl_int;
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wire qsfp0_i2c_scl_i;
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wire qsfp0_i2c_scl_o;
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wire qsfp0_i2c_sda_i;
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wire qsfp0_i2c_sda_o;
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wire qsfp1_modprsl_int;
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wire qsfp1_intl_int;
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wire qsfp1_i2c_scl_i;
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wire qsfp1_i2c_scl_o;
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wire qsfp1_i2c_sda_i;
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wire qsfp1_i2c_sda_o;
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wire qsfp2_modprsl_int;
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wire qsfp2_intl_int;
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wire qsfp2_i2c_scl_i;
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wire qsfp2_i2c_scl_o;
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wire qsfp2_i2c_sda_i;
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wire qsfp2_i2c_sda_o;
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wire qsfp3_modprsl_int;
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wire qsfp3_intl_int;
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wire qsfp3_i2c_scl_i;
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wire qsfp3_i2c_scl_o;
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wire qsfp3_i2c_sda_i;
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wire qsfp3_i2c_sda_o;
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|
||||
logic eeprom_i2c_scl_o_reg;
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logic eeprom_i2c_sda_o_reg;
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||||
|
||||
logic qsfp0_i2c_scl_o_reg;
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||||
logic qsfp0_i2c_sda_o_reg;
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||||
|
||||
logic qsfp1_i2c_scl_o_reg;
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||||
logic qsfp1_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp2_i2c_scl_o_reg;
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||||
logic qsfp2_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp3_i2c_scl_o_reg;
|
||||
logic qsfp3_i2c_sda_o_reg;
|
||||
|
||||
always_ff @(posedge clk_125mhz_int) begin
|
||||
eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
|
||||
eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
|
||||
|
||||
qsfp0_i2c_scl_o_reg <= qsfp0_i2c_scl_o;
|
||||
qsfp0_i2c_sda_o_reg <= qsfp0_i2c_sda_o;
|
||||
|
||||
qsfp1_i2c_scl_o_reg <= qsfp1_i2c_scl_o;
|
||||
qsfp1_i2c_sda_o_reg <= qsfp1_i2c_sda_o;
|
||||
|
||||
qsfp2_i2c_scl_o_reg <= qsfp2_i2c_scl_o;
|
||||
qsfp2_i2c_sda_o_reg <= qsfp2_i2c_sda_o;
|
||||
|
||||
qsfp3_i2c_scl_o_reg <= qsfp3_i2c_scl_o;
|
||||
qsfp3_i2c_sda_o_reg <= qsfp3_i2c_sda_o;
|
||||
end
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(19),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.in({uart_rxd, eeprom_i2c_scl, eeprom_i2c_sda,
|
||||
qsfp0_modprsl, qsfp0_intl, qsfp0_i2c_scl, qsfp0_i2c_sda,
|
||||
qsfp1_modprsl, qsfp1_intl, qsfp1_i2c_scl, qsfp1_i2c_sda,
|
||||
qsfp2_modprsl, qsfp2_intl, qsfp2_i2c_scl, qsfp2_i2c_sda,
|
||||
qsfp3_modprsl, qsfp3_intl, qsfp3_i2c_scl, qsfp3_i2c_sda}),
|
||||
.out({uart_rxd_int, eeprom_i2c_scl_i, eeprom_i2c_sda_i,
|
||||
qsfp0_modprsl_int, qsfp0_intl_int, qsfp0_i2c_scl_i, qsfp0_i2c_sda_i,
|
||||
qsfp1_modprsl_int, qsfp1_intl_int, qsfp1_i2c_scl_i, qsfp1_i2c_sda_i,
|
||||
qsfp2_modprsl_int, qsfp2_intl_int, qsfp2_i2c_scl_i, qsfp2_i2c_sda_i,
|
||||
qsfp3_modprsl_int, qsfp3_intl_int, qsfp3_i2c_scl_i, qsfp3_i2c_sda_i})
|
||||
);
|
||||
|
||||
assign eeprom_i2c_scl = eeprom_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign eeprom_i2c_sda = eeprom_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp0_i2c_scl = qsfp0_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp0_i2c_sda = qsfp0_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp1_i2c_scl = qsfp1_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp1_i2c_sda = qsfp1_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp2_i2c_scl = qsfp2_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp2_i2c_sda = qsfp2_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp3_i2c_scl = qsfp3_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp3_i2c_sda = qsfp3_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.led(led),
|
||||
|
||||
/*
|
||||
* UART: 3000000 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd_int),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
.eeprom_i2c_scl_i(eeprom_i2c_scl_i),
|
||||
.eeprom_i2c_scl_o(eeprom_i2c_scl_o),
|
||||
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
|
||||
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.qsfp0_tx_p(qsfp0_tx_p),
|
||||
.qsfp0_tx_n(qsfp0_tx_n),
|
||||
.qsfp0_rx_p(qsfp0_rx_p),
|
||||
.qsfp0_rx_n(qsfp0_rx_n),
|
||||
.qsfp0_mgt_refclk_b0_p(qsfp0_mgt_refclk_b0_p),
|
||||
.qsfp0_mgt_refclk_b0_n(qsfp0_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp0_modprsl(qsfp0_modprsl_int),
|
||||
.qsfp0_resetl(qsfp0_resetl),
|
||||
.qsfp0_intl(qsfp0_intl_int),
|
||||
.qsfp0_lpmode(qsfp0_lpmode),
|
||||
|
||||
.qsfp0_i2c_scl_i(qsfp0_i2c_scl_i),
|
||||
.qsfp0_i2c_scl_o(qsfp0_i2c_scl_o),
|
||||
.qsfp0_i2c_sda_i(qsfp0_i2c_sda_i),
|
||||
.qsfp0_i2c_sda_o(qsfp0_i2c_sda_o),
|
||||
|
||||
.qsfp1_tx_p(qsfp1_tx_p),
|
||||
.qsfp1_tx_n(qsfp1_tx_n),
|
||||
.qsfp1_rx_p(qsfp1_rx_p),
|
||||
.qsfp1_rx_n(qsfp1_rx_n),
|
||||
.qsfp1_mgt_refclk_b0_p(qsfp1_mgt_refclk_b0_p),
|
||||
.qsfp1_mgt_refclk_b0_n(qsfp1_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp1_modprsl(qsfp1_modprsl_int),
|
||||
.qsfp1_resetl(qsfp1_resetl),
|
||||
.qsfp1_intl(qsfp1_intl_int),
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
.qsfp1_i2c_scl_i(qsfp1_i2c_scl_i),
|
||||
.qsfp1_i2c_scl_o(qsfp1_i2c_scl_o),
|
||||
.qsfp1_i2c_sda_i(qsfp1_i2c_sda_i),
|
||||
.qsfp1_i2c_sda_o(qsfp1_i2c_sda_o),
|
||||
|
||||
.qsfp2_tx_p(qsfp2_tx_p),
|
||||
.qsfp2_tx_n(qsfp2_tx_n),
|
||||
.qsfp2_rx_p(qsfp2_rx_p),
|
||||
.qsfp2_rx_n(qsfp2_rx_n),
|
||||
.qsfp2_mgt_refclk_b0_p(qsfp2_mgt_refclk_b0_p),
|
||||
.qsfp2_mgt_refclk_b0_n(qsfp2_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp2_modprsl(qsfp2_modprsl_int),
|
||||
.qsfp2_resetl(qsfp2_resetl),
|
||||
.qsfp2_intl(qsfp2_intl_int),
|
||||
.qsfp2_lpmode(qsfp2_lpmode),
|
||||
|
||||
.qsfp2_i2c_scl_i(qsfp2_i2c_scl_i),
|
||||
.qsfp2_i2c_scl_o(qsfp2_i2c_scl_o),
|
||||
.qsfp2_i2c_sda_i(qsfp2_i2c_sda_i),
|
||||
.qsfp2_i2c_sda_o(qsfp2_i2c_sda_o),
|
||||
|
||||
.qsfp3_tx_p(qsfp3_tx_p),
|
||||
.qsfp3_tx_n(qsfp3_tx_n),
|
||||
.qsfp3_rx_p(qsfp3_rx_p),
|
||||
.qsfp3_rx_n(qsfp3_rx_n),
|
||||
.qsfp3_mgt_refclk_b0_p(qsfp3_mgt_refclk_b0_p),
|
||||
.qsfp3_mgt_refclk_b0_n(qsfp3_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp3_modprsl(qsfp3_modprsl_int),
|
||||
.qsfp3_resetl(qsfp3_resetl),
|
||||
.qsfp3_intl(qsfp3_intl_int),
|
||||
.qsfp3_lpmode(qsfp3_lpmode),
|
||||
|
||||
.qsfp3_i2c_scl_i(qsfp3_i2c_scl_i),
|
||||
.qsfp3_i2c_scl_o(qsfp3_i2c_scl_o),
|
||||
.qsfp3_i2c_sda_i(qsfp3_i2c_sda_i),
|
||||
.qsfp3_i2c_sda_o(qsfp3_i2c_sda_o)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user