Reorganize repository

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/tb/baser.py

@@ -0,0 +1,613 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+
+import cocotb
+from cocotb.queue import Queue, QueueFull
+from cocotb.triggers import RisingEdge, Timer, First, Event
+from cocotb.utils import get_sim_time
+
+from cocotbext.eth.constants import (EthPre, XgmiiCtrl, BaseRCtrl, BaseRO,
+    BaseRSync, BaseRBlockType, xgmii_ctrl_to_baser_mapping,
+    baser_ctrl_to_xgmii_mapping, block_type_term_lane_mapping)
+from cocotbext.eth import XgmiiFrame
+
+
+class BaseRSerdesSource():
+
+    def __init__(self, data, header, clock, enable=None, slip=None, scramble=True, reverse=False, *args, **kwargs):
+        self.log = logging.getLogger(f"cocotb.{data._path}")
+        self.data = data
+        self.header = header
+        self.clock = clock
+        self.enable = enable
+        self.slip = slip
+        self.scramble = scramble
+        self.reverse = reverse
+
+        self.log.info("BASE-R serdes source")
+        self.log.info("Copyright (c) 2021 Alex Forencich")
+        self.log.info("https://github.com/alexforencich/verilog-ethernet")
+
+        super().__init__(*args, **kwargs)
+
+        self.active = False
+        self.queue = Queue()
+        self.dequeue_event = Event()
+        self.current_frame = None
+        self.idle_event = Event()
+        self.idle_event.set()
+
+        self.enable_dic = True
+        self.ifg = 12
+        self.force_offset_start = False
+
+        self.bit_offset = 0
+
+        self.queue_occupancy_bytes = 0
+        self.queue_occupancy_frames = 0
+
+        self.queue_occupancy_limit_bytes = -1
+        self.queue_occupancy_limit_frames = -1
+
+        self.width = len(self.data)
+        self.byte_size = 8
+        self.byte_lanes = 8
+
+        assert self.width == self.byte_lanes * self.byte_size
+
+        self.log.info("BASE-R serdes source model configuration")
+        self.log.info("  Byte size: %d bits", self.byte_size)
+        self.log.info("  Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
+        self.log.info("  Enable scrambler: %s", self.scramble)
+        self.log.info("  Bit reverse: %s", self.reverse)
+
+        self.data.setimmediatevalue(0)
+        self.header.setimmediatevalue(0)
+
+        self._run_cr = cocotb.start_soon(self._run())
+
+    async def send(self, frame):
+        while self.full():
+            self.dequeue_event.clear()
+            await self.dequeue_event.wait()
+        frame = XgmiiFrame(frame)
+        await self.queue.put(frame)
+        self.idle_event.clear()
+        self.queue_occupancy_bytes += len(frame)
+        self.queue_occupancy_frames += 1
+
+    def send_nowait(self, frame):
+        if self.full():
+            raise QueueFull()
+        frame = XgmiiFrame(frame)
+        self.queue.put_nowait(frame)
+        self.idle_event.clear()
+        self.queue_occupancy_bytes += len(frame)
+        self.queue_occupancy_frames += 1
+
+    def count(self):
+        return self.queue.qsize()
+
+    def empty(self):
+        return self.queue.empty()
+
+    def full(self):
+        if self.queue_occupancy_limit_bytes > 0 and self.queue_occupancy_bytes > self.queue_occupancy_limit_bytes:
+            return True
+        elif self.queue_occupancy_limit_frames > 0 and self.queue_occupancy_frames > self.queue_occupancy_limit_frames:
+            return True
+        else:
+            return False
+
+    def idle(self):
+        return self.empty() and not self.active
+
+    def clear(self):
+        while not self.queue.empty():
+            frame = self.queue.get_nowait()
+            frame.sim_time_end = None
+            frame.handle_tx_complete()
+        self.dequeue_event.set()
+        self.idle_event.set()
+        self.queue_occupancy_bytes = 0
+        self.queue_occupancy_frames = 0
+
+    async def wait(self):
+        await self.idle_event.wait()
+
+    async def _run(self):
+        frame = None
+        frame_offset = 0
+        ifg_cnt = 0
+        deficit_idle_cnt = 0
+        scrambler_state = 0
+        last_d = 0
+        self.active = False
+
+        while True:
+            await RisingEdge(self.clock)
+
+            if self.enable is None or self.enable.value:
+                if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
+                    # in IFG
+                    ifg_cnt = ifg_cnt - self.byte_lanes
+                    if ifg_cnt < 0:
+                        if self.enable_dic:
+                            deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
+                        ifg_cnt = 0
+
+                elif frame is None:
+                    # idle
+                    if not self.queue.empty():
+                        # send frame
+                        frame = self.queue.get_nowait()
+                        self.dequeue_event.set()
+                        self.queue_occupancy_bytes -= len(frame)
+                        self.queue_occupancy_frames -= 1
+                        self.current_frame = frame
+                        frame.sim_time_start = get_sim_time()
+                        frame.sim_time_sfd = None
+                        frame.sim_time_end = None
+                        self.log.info("TX frame: %s", frame)
+                        frame.normalize()
+                        frame.start_lane = 0
+                        assert frame.data[0] == EthPre.PRE
+                        assert frame.ctrl[0] == 0
+                        frame.data[0] = XgmiiCtrl.START
+                        frame.ctrl[0] = 1
+                        frame.data.append(XgmiiCtrl.TERM)
+                        frame.ctrl.append(1)
+
+                        # offset start
+                        if self.enable_dic:
+                            min_ifg = 3 - deficit_idle_cnt
+                        else:
+                            min_ifg = 0
+
+                        if self.byte_lanes > 4 and (ifg_cnt > min_ifg or self.force_offset_start):
+                            ifg_cnt = ifg_cnt-4
+                            frame.start_lane = 4
+                            frame.data = bytearray([XgmiiCtrl.IDLE]*4)+frame.data
+                            frame.ctrl = [1]*4+frame.ctrl
+
+                        if self.enable_dic:
+                            deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
+                        ifg_cnt = 0
+                        self.active = True
+                        frame_offset = 0
+                    else:
+                        # clear counters
+                        deficit_idle_cnt = 0
+                        ifg_cnt = 0
+
+                if frame is not None:
+                    dl = bytearray()
+                    cl = []
+
+                    for k in range(self.byte_lanes):
+                        if frame is not None:
+                            d = frame.data[frame_offset]
+                            if frame.sim_time_sfd is None and d == EthPre.SFD:
+                                frame.sim_time_sfd = get_sim_time()
+                            dl.append(d)
+                            cl.append(frame.ctrl[frame_offset])
+                            frame_offset += 1
+
+                            if frame_offset >= len(frame.data):
+                                ifg_cnt = max(self.ifg - (self.byte_lanes-k), 0)
+                                frame.sim_time_end = get_sim_time()
+                                frame.handle_tx_complete()
+                                frame = None
+                                self.current_frame = None
+                        else:
+                            dl.append(XgmiiCtrl.IDLE)
+                            cl.append(1)
+
+                    # remap control characters
+                    ctrl = sum(xgmii_ctrl_to_baser_mapping.get(d, BaseRCtrl.ERROR) << i*7 for i, d in enumerate(dl))
+
+                    if not any(cl):
+                        # data
+                        header = BaseRSync.DATA
+                        data = int.from_bytes(dl, 'little')
+                    else:
+                        # control
+                        header = BaseRSync.CTRL
+                        if cl[0] and dl[0] == XgmiiCtrl.START and not any(cl[1:]):
+                            # start in lane 0
+                            data = BaseRBlockType.START_0
+                            for i in range(1, 8):
+                                data |= dl[i] << i*8
+                        elif cl[4] and dl[4] == XgmiiCtrl.START and not any(cl[5:]):
+                            # start in lane 4
+                            if cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
+                                # ordered set in lane 0
+                                data = BaseRBlockType.OS_START
+                                for i in range(1, 4):
+                                    data |= dl[i] << i*8
+                                if dl[0] == XgmiiCtrl.SIG_OS:
+                                    # signal ordered set
+                                    data |= BaseRO.SIG_OS << 32
+                            else:
+                                # other control
+                                data = BaseRBlockType.START_4 | (ctrl & 0xfffffff) << 8
+
+                            for i in range(5, 8):
+                                data |= dl[i] << i*8
+                        elif cl[0] and (dl[0] == XgmiiCtrl.SEQ_OS or dl[0] == XgmiiCtrl.SIG_OS) and not any(cl[1:4]):
+                            # ordered set in lane 0
+                            if cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
+                                # ordered set in lane 4
+                                data = BaseRBlockType.OS_04
+                                for i in range(5, 8):
+                                    data |= dl[i] << i*8
+                                if dl[4] == XgmiiCtrl.SIG_OS:
+                                    # signal ordered set
+                                    data |= BaseRO.SIG_OS << 36
+                            else:
+                                data = BaseRBlockType.OS_0 | (ctrl & 0xfffffff) << 40
+                            for i in range(1, 4):
+                                data |= dl[i] << i*8
+                            if dl[0] == XgmiiCtrl.SIG_OS:
+                                # signal ordered set
+                                data |= BaseRO.SIG_OS << 32
+                        elif cl[4] and (dl[4] == XgmiiCtrl.SEQ_OS or dl[4] == XgmiiCtrl.SIG_OS) and not any(cl[5:8]):
+                            # ordered set in lane 4
+                            data = BaseRBlockType.OS_4 | (ctrl & 0xfffffff) << 8
+                            for i in range(5, 8):
+                                data |= dl[i] << i*8
+                            if dl[4] == XgmiiCtrl.SIG_OS:
+                                # signal ordered set
+                                data |= BaseRO.SIG_OS << 36
+                        elif cl[0] and dl[0] == XgmiiCtrl.TERM:
+                            # terminate in lane 0
+                            data = BaseRBlockType.TERM_0 | (ctrl & 0xffffffffffff80) << 8
+                        elif cl[1] and dl[1] == XgmiiCtrl.TERM and not cl[0]:
+                            # terminate in lane 1
+                            data = BaseRBlockType.TERM_1 | (ctrl & 0xffffffffffc000) << 8 | dl[0] << 8
+                        elif cl[2] and dl[2] == XgmiiCtrl.TERM and not any(cl[0:2]):
+                            # terminate in lane 2
+                            data = BaseRBlockType.TERM_2 | (ctrl & 0xffffffffe00000) << 8
+                            for i in range(2):
+                                data |= dl[i] << ((i+1)*8)
+                        elif cl[3] and dl[3] == XgmiiCtrl.TERM and not any(cl[0:3]):
+                            # terminate in lane 3
+                            data = BaseRBlockType.TERM_3 | (ctrl & 0xfffffff0000000) << 8
+                            for i in range(3):
+                                data |= dl[i] << ((i+1)*8)
+                        elif cl[4] and dl[4] == XgmiiCtrl.TERM and not any(cl[0:4]):
+                            # terminate in lane 4
+                            data = BaseRBlockType.TERM_4 | (ctrl & 0xfffff800000000) << 8
+                            for i in range(4):
+                                data |= dl[i] << ((i+1)*8)
+                        elif cl[5] and dl[5] == XgmiiCtrl.TERM and not any(cl[0:5]):
+                            # terminate in lane 5
+                            data = BaseRBlockType.TERM_5 | (ctrl & 0xfffc0000000000) << 8
+                            for i in range(5):
+                                data |= dl[i] << ((i+1)*8)
+                        elif cl[6] and dl[6] == XgmiiCtrl.TERM and not any(cl[0:6]):
+                            # terminate in lane 6
+                            data = BaseRBlockType.TERM_6 | (ctrl & 0xfe000000000000) << 8
+                            for i in range(6):
+                                data |= dl[i] << ((i+1)*8)
+                        elif cl[7] and dl[7] == XgmiiCtrl.TERM and not any(cl[0:7]):
+                            # terminate in lane 7
+                            data = BaseRBlockType.TERM_7
+                            for i in range(7):
+                                data |= dl[i] << ((i+1)*8)
+                        else:
+                            # all control
+                            data = BaseRBlockType.CTRL | ctrl << 8
+                else:
+                    data = BaseRBlockType.CTRL
+                    header = BaseRSync.CTRL
+                    self.active = False
+                    self.idle_event.set()
+
+                if self.scramble:
+                    # 64b/66b scrambler
+                    b = 0
+                    for i in range(len(self.data)):
+                        if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)):
+                            scrambler_state = ((scrambler_state & 0x1ffffffffffffff) << 1) | 1
+                            b = b | (1 << i)
+                        else:
+                            scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1
+                    data = b
+
+                if self.slip is not None and self.slip.value:
+                    self.bit_offset += 1
+
+                self.bit_offset = max(0, self.bit_offset) % 66
+
+                if self.bit_offset != 0:
+                    d = data << 2 | header
+
+                    out_d = ((last_d | d << 66) >> 66-self.bit_offset) & 0x3ffffffffffffffff
+
+                    last_d = d
+
+                    data = out_d >> 2
+                    header = out_d & 3
+
+                if self.reverse:
+                    # bit reverse
+                    data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
+                    header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1)
+
+                self.data.value = data
+                self.header.value = header
+
+
+class BaseRSerdesSink:
+
+    def __init__(self, data, header, clock, enable=None, scramble=True, reverse=False, *args, **kwargs):
+        self.log = logging.getLogger(f"cocotb.{data._path}")
+        self.data = data
+        self.header = header
+        self.clock = clock
+        self.enable = enable
+        self.scramble = scramble
+        self.reverse = reverse
+
+        self.log.info("BASE-R serdes sink")
+        self.log.info("Copyright (c) 2021 Alex Forencich")
+        self.log.info("https://github.com/alexforencich/verilog-ethernet")
+
+        super().__init__(*args, **kwargs)
+
+        self.active = False
+        self.queue = Queue()
+        self.active_event = Event()
+
+        self.queue_occupancy_bytes = 0
+        self.queue_occupancy_frames = 0
+
+        self.width = len(self.data)
+        self.byte_size = 8
+        self.byte_lanes = 8
+
+        assert self.width == self.byte_lanes * self.byte_size
+
+        self.log.info("BASE-R serdes sink model configuration")
+        self.log.info("  Byte size: %d bits", self.byte_size)
+        self.log.info("  Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
+        self.log.info("  Enable scrambler: %s", self.scramble)
+        self.log.info("  Bit reverse: %s", self.reverse)
+
+        self._run_cr = cocotb.start_soon(self._run())
+
+    def _recv(self, frame, compact=True):
+        if self.queue.empty():
+            self.active_event.clear()
+        self.queue_occupancy_bytes -= len(frame)
+        self.queue_occupancy_frames -= 1
+        if compact:
+            frame.compact()
+        return frame
+
+    async def recv(self, compact=True):
+        frame = await self.queue.get()
+        return self._recv(frame, compact)
+
+    def recv_nowait(self, compact=True):
+        frame = self.queue.get_nowait()
+        return self._recv(frame, compact)
+
+    def count(self):
+        return self.queue.qsize()
+
+    def empty(self):
+        return self.queue.empty()
+
+    def idle(self):
+        return not self.active
+
+    def clear(self):
+        while not self.queue.empty():
+            self.queue.get_nowait()
+        self.active_event.clear()
+        self.queue_occupancy_bytes = 0
+        self.queue_occupancy_frames = 0
+
+    async def wait(self, timeout=0, timeout_unit=None):
+        if not self.empty():
+            return
+        if timeout:
+            await First(self.active_event.wait(), Timer(timeout, timeout_unit))
+        else:
+            await self.active_event.wait()
+
+    async def _run(self):
+        frame = None
+        scrambler_state = 0
+        self.active = False
+
+        while True:
+            await RisingEdge(self.clock)
+
+            if self.enable is None or self.enable.value:
+                data = self.data.value.integer
+                header = self.header.value.integer
+
+                if self.reverse:
+                    # bit reverse
+                    data = sum(1 << (63-i) for i in range(64) if (data >> i) & 1)
+                    header = sum(1 << (1-i) for i in range(2) if (header >> i) & 1)
+
+                if self.scramble:
+                    # 64b/66b descrambler
+                    b = 0
+                    for i in range(len(self.data)):
+                        if bool(scrambler_state & (1 << 38)) ^ bool(scrambler_state & (1 << 57)) ^ bool(data & (1 << i)):
+                            b = b | (1 << i)
+                        scrambler_state = (scrambler_state & 0x1ffffffffffffff) << 1 | bool(data & (1 << i))
+                    data = b
+
+                # 10GBASE-R decoding
+
+                # remap control characters
+                ctrl = bytearray(baser_ctrl_to_xgmii_mapping.get((data >> i*7+8) & 0x7f, XgmiiCtrl.ERROR) for i in range(8))
+
+                data = data.to_bytes(8, 'little')
+
+                dl = bytearray()
+                cl = []
+                if header == BaseRSync.DATA:
+                    # data
+                    dl = data
+                    cl = [0]*8
+                elif header == BaseRSync.CTRL:
+                    if data[0] == BaseRBlockType.CTRL:
+                        # C7 C6 C5 C4 C3 C2 C1 C0 BT
+                        dl = ctrl
+                        cl = [1]*8
+                    elif data[0] == BaseRBlockType.OS_4:
+                        # D7 D6 D5 O4 C3 C2 C1 C0 BT
+                        dl = ctrl[0:4]
+                        cl = [1]*4
+                        if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS:
+                            dl.append(XgmiiCtrl.SEQ_OS)
+                        elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS:
+                            dl.append(XgmiiCtrl.SIG_OS)
+                        else:
+                            dl.append(XgmiiCtrl.ERROR)
+                        cl.append(1)
+                        dl += data[5:]
+                        cl += [0]*3
+                    elif data[0] == BaseRBlockType.START_4:
+                        # D7 D6 D5    C3 C2 C1 C0 BT
+                        dl = ctrl[0:4]
+                        cl = [1]*4
+                        dl.append(XgmiiCtrl.START)
+                        cl.append(1)
+                        dl += data[5:]
+                        cl += [0]*3
+                    elif data[0] == BaseRBlockType.OS_START:
+                        # D7 D6 D5    O0 D3 D2 D1 BT
+                        if data[4] & 0xf == BaseRO.SEQ_OS:
+                            dl.append(XgmiiCtrl.SEQ_OS)
+                        elif data[4] & 0xf == BaseRO.SIG_OS:
+                            dl.append(XgmiiCtrl.SIG_OS)
+                        else:
+                            dl.append(XgmiiCtrl.ERROR)
+                        cl.append(1)
+                        dl += data[1:4]
+                        cl += [0]*3
+                        dl.append(XgmiiCtrl.START)
+                        cl.append(1)
+                        dl += data[5:]
+                        cl += [0]*3
+                    elif data[0] == BaseRBlockType.OS_04:
+                        # D7 D6 D5 O4 O0 D3 D2 D1 BT
+                        if data[4] & 0xf == BaseRO.SEQ_OS:
+                            dl.append(XgmiiCtrl.SEQ_OS)
+                        elif data[4] & 0xf == BaseRO.SIG_OS:
+                            dl.append(XgmiiCtrl.SIG_OS)
+                        else:
+                            dl.append(XgmiiCtrl.ERROR)
+                        cl.append(1)
+                        dl += data[1:4]
+                        cl += [0]*3
+                        if (data[4] >> 4) & 0xf == BaseRO.SEQ_OS:
+                            dl.append(XgmiiCtrl.SEQ_OS)
+                        elif (data[4] >> 4) & 0xf == BaseRO.SIG_OS:
+                            dl.append(XgmiiCtrl.SIG_OS)
+                        else:
+                            dl.append(XgmiiCtrl.ERROR)
+                        cl.append(1)
+                        dl += data[5:]
+                        cl += [0]*3
+                    elif data[0] == BaseRBlockType.START_0:
+                        # D7 D6 D5 D4 D3 D2 D1    BT
+                        dl.append(XgmiiCtrl.START)
+                        cl.append(1)
+                        dl += data[1:]
+                        cl += [0]*7
+                    elif data[0] == BaseRBlockType.OS_0:
+                        # C7 C6 C5 C4 O0 D3 D2 D1 BT
+                        if data[4] & 0xf == BaseRO.SEQ_OS:
+                            dl.append(XgmiiCtrl.SEQ_OS)
+                        elif data[4] & 0xf == BaseRO.SIG_OS:
+                            dl.append(XgmiiCtrl.SEQ_OS)
+                        else:
+                            dl.append(XgmiiCtrl.ERROR)
+                        cl.append(1)
+                        dl += data[1:4]
+                        cl += [0]*3
+                        dl += ctrl[4:]
+                        cl += [1]*4
+                    elif data[0] in {BaseRBlockType.TERM_0, BaseRBlockType.TERM_1,
+                            BaseRBlockType.TERM_2, BaseRBlockType.TERM_3, BaseRBlockType.TERM_4,
+                            BaseRBlockType.TERM_5, BaseRBlockType.TERM_6, BaseRBlockType.TERM_7}:
+                        # C7 C6 C5 C4 C3 C2 C1    BT
+                        # C7 C6 C5 C4 C3 C2    D0 BT
+                        # C7 C6 C5 C4 C3    D1 D0 BT
+                        # C7 C6 C5 C4    D2 D1 D0 BT
+                        # C7 C6 C5    D3 D2 D1 D0 BT
+                        # C7 C6    D4 D3 D2 D1 D0 BT
+                        # C7    D5 D4 D3 D2 D1 D0 BT
+                        #    D6 D5 D4 D3 D2 D1 D0 BT
+                        term_lane = block_type_term_lane_mapping[data[0]]
+                        dl += data[1:term_lane+1]
+                        cl += [0]*term_lane
+                        dl.append(XgmiiCtrl.TERM)
+                        cl.append(1)
+                        dl += ctrl[term_lane+1:]
+                        cl += [1]*(7-term_lane)
+                    else:
+                        # invalid block type
+                        self.log.warning("Invalid block type")
+                        dl = [XgmiiCtrl.ERROR]*8
+                        cl = [1]*8
+                else:
+                    # invalid sync header
+                    self.log.warning("Invalid sync header")
+                    dl = [XgmiiCtrl.ERROR]*8
+                    cl = [1]*8
+
+                for offset in range(self.byte_lanes):
+                    d_val = dl[offset]
+                    c_val = cl[offset]
+
+                    if frame is None:
+                        if c_val and d_val == XgmiiCtrl.START:
+                            # start
+                            frame = XgmiiFrame(bytearray([EthPre.PRE]), [0])
+                            frame.sim_time_start = get_sim_time()
+                            frame.start_lane = offset
+                    else:
+                        if c_val:
+                            # got a control character; terminate frame reception
+                            if d_val != XgmiiCtrl.TERM:
+                                # store control character if it's not a termination
+                                frame.data.append(d_val)
+                                frame.ctrl.append(c_val)
+
+                            frame.compact()
+                            frame.sim_time_end = get_sim_time()
+                            self.log.info("RX frame: %s", frame)
+
+                            self.queue_occupancy_bytes += len(frame)
+                            self.queue_occupancy_frames += 1
+
+                            self.queue.put_nowait(frame)
+                            self.active_event.set()
+
+                            frame = None
+                        else:
+                            if frame.sim_time_sfd is None and d_val == EthPre.SFD:
+                                frame.sim_time_sfd = get_sim_time()
+
+                            frame.data.append(d_val)
+                            frame.ctrl.append(c_val)

src/eth/tb/taxi_axis_baser_rx_64/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_baser_rx_64
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_HDR_W := 2
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_axis_baser_rx_64/baser.py

@@ -0,0 +1 @@
+../baser.py

src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py

@@ -0,0 +1,339 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSink
+
+try:
+    from baser import BaseRSerdesSource
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.source = BaseRSerdesSource(dut.encoded_rx_data, dut.encoded_rx_hdr, dut.clk, scramble=False)
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["stat_rx_byte"] = 0
+        self.stats["stat_rx_pkt_len"] = 0
+        self.stats["stat_rx_pkt_fragment"] = 0
+        self.stats["stat_rx_pkt_jabber"] = 0
+        self.stats["stat_rx_pkt_ucast"] = 0
+        self.stats["stat_rx_pkt_mcast"] = 0
+        self.stats["stat_rx_pkt_bcast"] = 0
+        self.stats["stat_rx_pkt_vlan"] = 0
+        self.stats["stat_rx_pkt_good"] = 0
+        self.stats["stat_rx_pkt_bad"] = 0
+        self.stats["stat_rx_err_oversize"] = 0
+        self.stats["stat_rx_err_bad_fcs"] = 0
+        self.stats["stat_rx_err_bad_block"] = 0
+        self.stats["stat_rx_err_framing"] = 0
+        self.stats["stat_rx_err_preamble"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.source.send(test_frame)
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        if tx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            tx_frame_sfd_ns -= 3.2
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - 6.4) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_rx_byte"] == total_bytes
+    assert tb.stats["stat_rx_pkt_len"] == total_bytes
+    assert tb.stats["stat_rx_pkt_fragment"] == 0
+    assert tb.stats["stat_rx_pkt_jabber"] == 0
+    assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_rx_pkt_mcast"] == 0
+    assert tb.stats["stat_rx_pkt_bcast"] == 0
+    assert tb.stats["stat_rx_pkt_vlan"] == 0
+    assert tb.stats["stat_rx_pkt_good"] == total_pkts
+    assert tb.stats["stat_rx_pkt_bad"] == 0
+    assert tb.stats["stat_rx_err_oversize"] == 0
+    assert tb.stats["stat_rx_err_bad_fcs"] == 0
+    assert tb.stats["stat_rx_err_bad_block"] == 0
+    assert tb.stats["stat_rx_err_framing"] == 0
+    assert tb.stats["stat_rx_err_preamble"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 1518
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for max_len in range(128-4-8, 128-4+9):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-8, max_len+9):
+
+            tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_rx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = XgmiiFrame.from_payload(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        frame_error = rx_frame.tuser[-1] & 1
+                        assert frame_error
+                    else:
+                        frame_error = rx_frame.tuser & 1
+                        assert rx_frame.tdata == test_data_2
+                        assert frame_error == 0
+                else:
+                    frame_error = rx_frame.tuser & 1
+                    assert rx_frame.tdata == test_data_1
+                    assert frame_error == 0
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["stat_rx_byte"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_len"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_fragment"] == 0
+        assert tb.stats["stat_rx_pkt_jabber"] == 0
+        assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_rx_pkt_mcast"] == 0
+        assert tb.stats["stat_rx_pkt_bcast"] == 0
+        assert tb.stats["stat_rx_pkt_vlan"] == 0
+        assert tb.stats["stat_rx_pkt_good"] == total_pkts-oversz_pkts
+        assert tb.stats["stat_rx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_rx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_rx_err_bad_fcs"] == 0
+        assert tb.stats["stat_rx_err_bad_block"] == 0
+        assert tb.stats["stat_rx_err_framing"] == 0
+        assert tb.stats["stat_rx_err_preamble"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", list(range(0, 13)))
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_oversize)
+    factory.add_option("ifg", list(range(0, 13)))
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_axis_baser_rx_64(request):
+    dut = "taxi_axis_baser_rx_64"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 64
+    parameters['HDR_W'] = 2
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv

@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream 10GBASE-R frame receiver testbench
+ */
+module test_taxi_axis_baser_rx_64 #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter HDR_W = 2,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic clk;
+logic rst;
+
+logic [DATA_W-1:0] encoded_rx_data;
+logic [HDR_W-1:0] encoded_rx_hdr;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx();
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+logic [1:0] rx_start_packet;
+logic [3:0] stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+
+taxi_axis_baser_rx_64 #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * 10GBASE-R encoded input
+     */
+    .encoded_rx_data(encoded_rx_data),
+    .encoded_rx_hdr(encoded_rx_hdr),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+
+    /*
+     * Status
+     */
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_axis_baser_tx_64/Makefile

@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_baser_tx_64
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_HDR_W := 2
+export PARAM_PADDING_EN := 1
+export PARAM_DIC_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
+export PARAM_TX_TAG_W := 16
+export PARAM_TX_CPL_CTRL_IN_TUSER := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_axis_baser_tx_64/baser.py

@@ -0,0 +1 @@
+../baser.py

src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py

@@ -0,0 +1,560 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+try:
+    from baser import BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
+        self.sink = BaseRSerdesSink(dut.encoded_tx_data, dut.encoded_tx_hdr, dut.clk, scramble=False)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.clk, dut.rst)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["stat_tx_byte"] = 0
+        self.stats["stat_tx_pkt_len"] = 0
+        self.stats["stat_tx_pkt_ucast"] = 0
+        self.stats["stat_tx_pkt_mcast"] = 0
+        self.stats["stat_tx_pkt_bcast"] = 0
+        self.stats["stat_tx_pkt_vlan"] = 0
+        self.stats["stat_tx_pkt_good"] = 0
+        self.stats["stat_tx_pkt_bad"] = 0
+        self.stats["stat_tx_err_oversize"] = 0
+        self.stats["stat_tx_err_user"] = 0
+        self.stats["stat_tx_err_underflow"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        await tb.source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        if rx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            rx_frame_sfd_ns -= 3.2
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.ctrl is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - 12.8) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] == total_bytes
+    assert tb.stats["stat_tx_pkt_len"] == total_bytes
+    assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == total_pkts
+    assert tb.stats["stat_tx_pkt_bad"] == 0
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_alignment(dut, payload_data=None, ifg=12):
+
+    enable_dic = int(dut.DIC_EN.value)
+
+    tb = TB(dut)
+
+    byte_width = tb.source.width // 8
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for length in range(60, 92):
+
+        for k in range(10):
+            await RisingEdge(dut.clk)
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            await tb.source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+            total_bytes += max(len(test_data), 60)+4
+            total_pkts += 1
+
+        for test_data in test_frames:
+            rx_frame = await tb.sink.recv()
+            tx_cpl = await tb.tx_cpl_sink.recv()
+
+            ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+            rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+            if rx_frame.start_lane == 4:
+                # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+                rx_frame_sfd_ns -= 3.2
+
+            tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+            tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+            tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - 12.8) < 0.01
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_width
+
+            if enable_dic:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.clk)
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] == total_bytes
+    assert tb.stats["stat_tx_pkt_len"] == total_bytes
+    assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == total_pkts
+    assert tb.stats["stat_tx_pkt_bad"] == 0
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_underrun(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.source.send(test_frame)
+
+    for k in range(16):
+        await RisingEdge(dut.clk)
+
+    tb.source.pause = True
+
+    for k in range(4):
+        await RisingEdge(dut.clk)
+
+    tb.source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 1
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_error(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 1
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 1518
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for max_len in range(128-4-8, 128-4+9):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-8, max_len+9):
+
+            tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_tx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = AxiStreamFrame(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        assert rx_frame.data[-1] == 0xFE
+                        assert rx_frame.ctrl[-1] == 1
+                    else:
+                        assert rx_frame.get_payload() == test_data_2
+                        assert rx_frame.check_fcs()
+                        assert rx_frame.ctrl is None
+                else:
+                    assert rx_frame.get_payload() == test_data_1
+                    assert rx_frame.check_fcs()
+                    assert rx_frame.ctrl is None
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["stat_tx_byte"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
+        assert tb.stats["stat_tx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_len"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
+        assert tb.stats["stat_tx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_tx_pkt_mcast"] == 0
+        assert tb.stats["stat_tx_pkt_bcast"] == 0
+        assert tb.stats["stat_tx_pkt_vlan"] == 0
+        assert tb.stats["stat_tx_pkt_good"] == total_pkts - oversz_pkts
+        assert tb.stats["stat_tx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_tx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_tx_err_user"] == 0
+        assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    for test in [
+                run_test_underrun,
+                run_test_error,
+                run_test_oversize
+            ]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("dic_en", [1, 0])
+def test_taxi_axis_baser_tx_64(request, dic_en):
+    dut = "taxi_axis_baser_tx_64"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 64
+    parameters['HDR_W'] = 2
+    parameters['PADDING_EN'] = 1
+    parameters['DIC_EN'] = dic_en
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+    parameters['TX_TAG_W'] = 16
+    parameters['TX_CPL_CTRL_IN_TUSER'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv

@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream 10GBASE-R frame transmitter testbench
+ */
+module test_taxi_axis_baser_tx_64 #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter HDR_W = 2,
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter TX_TAG_W = 16,
+    parameter logic TX_CPL_CTRL_IN_TUSER = 1'b0
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam USER_W = TX_CPL_CTRL_IN_TUSER ? 2 : 1;
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+
+logic [DATA_W-1:0] encoded_tx_data;
+logic [HDR_W-1:0] encoded_tx_hdr;
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+
+logic [1:0] tx_start_packet;
+logic [3:0] stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+
+taxi_axis_baser_tx_64 #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W),
+    .TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * 10GBASE-R encoded interface
+     */
+    .encoded_tx_data(encoded_tx_data),
+    .encoded_tx_hdr(encoded_tx_hdr),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_axis_gmii_rx/Makefile

@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_gmii_rx
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 8
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_W := 96
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.py

@@ -0,0 +1,361 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, GmiiSource, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSink
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        self._enable_generator = None
+        self._enable_cr = None
+
+        cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
+
+        self.source = GmiiSource(dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv,
+            dut.clk, dut.rst, dut.clk_enable, dut.mii_select)
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+
+        dut.clk_enable.setimmediatevalue(1)
+        dut.mii_select.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["rx_start_packet"] = 0
+        self.stats["stat_rx_byte"] = 0
+        self.stats["stat_rx_pkt_len"] = 0
+        self.stats["stat_rx_pkt_fragment"] = 0
+        self.stats["stat_rx_pkt_jabber"] = 0
+        self.stats["stat_rx_pkt_ucast"] = 0
+        self.stats["stat_rx_pkt_mcast"] = 0
+        self.stats["stat_rx_pkt_bcast"] = 0
+        self.stats["stat_rx_pkt_vlan"] = 0
+        self.stats["stat_rx_pkt_good"] = 0
+        self.stats["stat_rx_pkt_bad"] = 0
+        self.stats["stat_rx_err_oversize"] = 0
+        self.stats["stat_rx_err_bad_fcs"] = 0
+        self.stats["stat_rx_err_bad_block"] = 0
+        self.stats["stat_rx_err_framing"] = 0
+        self.stats["stat_rx_err_preamble"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+    def set_enable_generator(self, generator=None):
+        if self._enable_cr is not None:
+            self._enable_cr.kill()
+            self._enable_cr = None
+
+        self._enable_generator = generator
+
+        if self._enable_generator is not None:
+            self._enable_cr = cocotb.start_soon(self._run_enable())
+
+    def clear_enable_generator(self):
+        self.set_enable_generator(None)
+
+    async def _run_enable(self):
+        for val in self._enable_generator:
+            self.dut.clk_enable.value = val
+            await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.dut.mii_select.value = mii_sel
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    if enable_gen is not None:
+        tb.set_enable_generator(enable_gen())
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.source.send(test_frame)
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - (32 if enable_gen else 8)) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["rx_start_packet"] == total_pkts
+    assert tb.stats["stat_rx_byte"] == total_bytes
+    assert tb.stats["stat_rx_pkt_len"] == total_bytes
+    assert tb.stats["stat_rx_pkt_fragment"] == 0
+    assert tb.stats["stat_rx_pkt_jabber"] == 0
+    assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_rx_pkt_mcast"] == 0
+    assert tb.stats["stat_rx_pkt_bcast"] == 0
+    assert tb.stats["stat_rx_pkt_vlan"] == 0
+    assert tb.stats["stat_rx_pkt_good"] == total_pkts
+    assert tb.stats["stat_rx_pkt_bad"] == 0
+    assert tb.stats["stat_rx_err_oversize"] == 0
+    assert tb.stats["stat_rx_err_bad_fcs"] == 0
+    assert tb.stats["stat_rx_err_bad_block"] == 0
+    assert tb.stats["stat_rx_err_framing"] == 0
+    assert tb.stats["stat_rx_err_preamble"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.dut.mii_select.value = mii_sel
+    tb.dut.cfg_rx_max_pkt_len.value = 1518
+    tb.dut.cfg_rx_enable.value = 1
+
+    if enable_gen is not None:
+        tb.set_enable_generator(enable_gen())
+
+    await tb.reset()
+
+    for max_len in range(128-4-4, 128-4+5):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-4, max_len+5):
+
+            tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_rx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = GmiiFrame.from_payload(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        frame_error = rx_frame.tuser[-1] & 1
+                        assert frame_error
+                    else:
+                        frame_error = rx_frame.tuser & 1
+                        assert rx_frame.tdata == test_data_2
+                        assert frame_error == 0
+                else:
+                    frame_error = rx_frame.tuser & 1
+                    assert rx_frame.tdata == test_data_1
+                    assert frame_error == 0
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["rx_start_packet"] == total_pkts
+        assert tb.stats["stat_rx_byte"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_len"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_fragment"] == 0
+        assert tb.stats["stat_rx_pkt_jabber"] == 0
+        assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_rx_pkt_mcast"] == 0
+        assert tb.stats["stat_rx_pkt_bcast"] == 0
+        assert tb.stats["stat_rx_pkt_vlan"] == 0
+        assert tb.stats["stat_rx_pkt_good"] == total_pkts-oversz_pkts
+        assert tb.stats["stat_rx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_rx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_rx_err_bad_fcs"] == 0
+        assert tb.stats["stat_rx_err_bad_block"] == 0
+        assert tb.stats["stat_rx_err_framing"] == 0
+        assert tb.stats["stat_rx_err_preamble"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12, 0])
+    factory.add_option("enable_gen", [None, cycle_en])
+    factory.add_option("mii_sel", [False, True])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_oversize)
+    factory.add_option("ifg", [12, 0])
+    factory.add_option("enable_gen", [None, cycle_en])
+    factory.add_option("mii_sel", [False, True])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_axis_gmii_rx(request):
+    dut = "taxi_axis_gmii_rx"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 8
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_W'] = 96
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv

@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream GMII frame receiver testbench
+ */
+module test_taxi_axis_gmii_rx #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 8,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter PTP_TS_W = 96
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic clk;
+logic rst;
+
+logic [DATA_W-1:0] gmii_rxd;
+logic gmii_rx_dv;
+logic gmii_rx_er;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx();
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic clk_enable;
+logic mii_select;
+
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+logic rx_start_packet;
+logic stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+
+taxi_axis_gmii_rx #(
+    .DATA_W(DATA_W),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * GMII input
+     */
+    .gmii_rxd(gmii_rxd),
+    .gmii_rx_dv(gmii_rx_dv),
+    .gmii_rx_er(gmii_rx_er),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Control
+     */
+    .clk_enable(clk_enable),
+    .mii_select(mii_select),
+
+    /*
+     * Configuration
+     */
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+
+    /*
+     * Status
+     */
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_axis_gmii_tx/Makefile

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_gmii_tx
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 8
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_W := 96
+export PARAM_TX_TAG_W := 16
+export PARAM_TX_CPL_CTRL_IN_TUSER := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.py

@@ -0,0 +1,479 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiSink, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        self._enable_generator = None
+        self._enable_cr = None
+
+        cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
+
+        self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
+        self.sink = GmiiSink(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en,
+            dut.clk, dut.rst, dut.clk_enable, dut.mii_select)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.clk, dut.rst)
+
+        dut.clk_enable.setimmediatevalue(1)
+        dut.mii_select.setimmediatevalue(0)
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["tx_start_packet"] = 0
+        self.stats["stat_tx_byte"] = 0
+        self.stats["stat_tx_pkt_len"] = 0
+        self.stats["stat_tx_pkt_ucast"] = 0
+        self.stats["stat_tx_pkt_mcast"] = 0
+        self.stats["stat_tx_pkt_bcast"] = 0
+        self.stats["stat_tx_pkt_vlan"] = 0
+        self.stats["stat_tx_pkt_good"] = 0
+        self.stats["stat_tx_pkt_bad"] = 0
+        self.stats["stat_tx_err_oversize"] = 0
+        self.stats["stat_tx_err_user"] = 0
+        self.stats["stat_tx_err_underflow"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+    def set_enable_generator(self, generator=None):
+        if self._enable_cr is not None:
+            self._enable_cr.kill()
+            self._enable_cr = None
+
+        self._enable_generator = generator
+
+        if self._enable_generator is not None:
+            self._enable_cr = cocotb.start_soon(self._run_enable())
+
+    def clear_enable_generator(self):
+        self.set_enable_generator(None)
+
+    async def _run_enable(self):
+        for val in self._enable_generator:
+            self.dut.clk_enable.value = val
+            await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator(enable_gen())
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        await tb.source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - (32 if enable_gen else 8)) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["tx_start_packet"] == total_pkts
+    assert tb.stats["stat_tx_byte"] == total_bytes
+    assert tb.stats["stat_tx_pkt_len"] == total_bytes
+    assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == total_pkts
+    assert tb.stats["stat_tx_pkt_bad"] == 0
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_underrun(dut, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator(enable_gen())
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.source.send(test_frame)
+
+    for k in range(200 if mii_sel else 100):
+        while True:
+            await RisingEdge(dut.clk)
+            if dut.clk_enable.value.integer:
+                break
+
+    tb.source.pause = True
+
+    for k in range(10):
+        while True:
+            await RisingEdge(dut.clk)
+            if dut.clk_enable.value.integer:
+                break
+
+    tb.source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["tx_start_packet"] == 3
+    assert tb.stats["stat_tx_byte"] == 64*3
+    assert tb.stats["stat_tx_pkt_len"] == 64*3
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 1
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_error(dut, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator(enable_gen())
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["tx_start_packet"] == 3
+    assert tb.stats["stat_tx_byte"] == 64*3
+    assert tb.stats["stat_tx_pkt_len"] == 64*3
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 1
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 1518
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator(enable_gen())
+
+    await tb.reset()
+
+    for max_len in range(128-4-4, 128-4+5):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-4, max_len+5):
+
+            tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_tx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = AxiStreamFrame(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        assert rx_frame.error[-1] == 1
+                    else:
+                        assert rx_frame.get_payload() == test_data_2
+                        assert rx_frame.check_fcs()
+                        assert rx_frame.error is None
+                else:
+                    assert rx_frame.get_payload() == test_data_1
+                    assert rx_frame.check_fcs()
+                    assert rx_frame.error is None
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["tx_start_packet"] == total_pkts
+        assert tb.stats["stat_tx_byte"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_tx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_len"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_tx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_tx_pkt_mcast"] == 0
+        assert tb.stats["stat_tx_pkt_bcast"] == 0
+        assert tb.stats["stat_tx_pkt_vlan"] == 0
+        assert tb.stats["stat_tx_pkt_good"] == total_pkts - oversz_pkts
+        assert tb.stats["stat_tx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_tx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_tx_err_user"] == 0
+        assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.add_option("enable_gen", [None, cycle_en])
+    factory.add_option("mii_sel", [False, True])
+    factory.generate_tests()
+
+    for test in [
+                run_test_underrun,
+                run_test_error,
+                run_test_oversize,
+            ]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.add_option("enable_gen", [None, cycle_en])
+        factory.add_option("mii_sel", [False, True])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_axis_gmii_tx(request):
+    dut = "taxi_axis_gmii_tx"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 8
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_W'] = 96
+    parameters['TX_TAG_W'] = 16
+    parameters['TX_CPL_CTRL_IN_TUSER'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.sv

@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream GMII frame transmitter testbench
+ */
+module test_taxi_axis_gmii_tx #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 8,
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter PTP_TS_W = 96,
+    parameter TX_TAG_W = 16,
+    parameter logic TX_CPL_CTRL_IN_TUSER = 1'b0
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam USER_W = TX_CPL_CTRL_IN_TUSER ? 2 : 1;
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+
+logic [DATA_W-1:0] gmii_txd;
+logic gmii_tx_en;
+logic gmii_tx_er;
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic clk_enable;
+logic mii_select;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+
+logic tx_start_packet;
+logic stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+
+taxi_axis_gmii_tx #(
+    .DATA_W(DATA_W),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W),
+    .TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * GMII output
+     */
+    .gmii_txd(gmii_txd),
+    .gmii_tx_en(gmii_tx_en),
+    .gmii_tx_er(gmii_tx_er),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Control
+     */
+    .clk_enable(clk_enable),
+    .mii_select(mii_select),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_axis_xgmii_rx_32/Makefile

@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_xgmii_rx_32
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 32
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_W := 96
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.py

@@ -0,0 +1,325 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, XgmiiSource, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSink
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 3.2, units="ns").start())
+
+        self.source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.clk, dut.rst)
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["rx_start_packet"] = 0
+        self.stats["stat_rx_byte"] = 0
+        self.stats["stat_rx_pkt_len"] = 0
+        self.stats["stat_rx_pkt_fragment"] = 0
+        self.stats["stat_rx_pkt_jabber"] = 0
+        self.stats["stat_rx_pkt_ucast"] = 0
+        self.stats["stat_rx_pkt_mcast"] = 0
+        self.stats["stat_rx_pkt_bcast"] = 0
+        self.stats["stat_rx_pkt_vlan"] = 0
+        self.stats["stat_rx_pkt_good"] = 0
+        self.stats["stat_rx_pkt_bad"] = 0
+        self.stats["stat_rx_err_oversize"] = 0
+        self.stats["stat_rx_err_bad_fcs"] = 0
+        self.stats["stat_rx_err_bad_block"] = 0
+        self.stats["stat_rx_err_framing"] = 0
+        self.stats["stat_rx_err_preamble"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.source.send(test_frame)
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - 3.2) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["rx_start_packet"] == total_pkts
+    assert tb.stats["stat_rx_byte"] == total_bytes
+    assert tb.stats["stat_rx_pkt_len"] == total_bytes
+    assert tb.stats["stat_rx_pkt_fragment"] == 0
+    assert tb.stats["stat_rx_pkt_jabber"] == 0
+    assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_rx_pkt_mcast"] == 0
+    assert tb.stats["stat_rx_pkt_bcast"] == 0
+    assert tb.stats["stat_rx_pkt_vlan"] == 0
+    assert tb.stats["stat_rx_pkt_good"] == total_pkts
+    assert tb.stats["stat_rx_pkt_bad"] == 0
+    assert tb.stats["stat_rx_err_oversize"] == 0
+    assert tb.stats["stat_rx_err_bad_fcs"] == 0
+    assert tb.stats["stat_rx_err_bad_block"] == 0
+    assert tb.stats["stat_rx_err_framing"] == 0
+    assert tb.stats["stat_rx_err_preamble"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 1518
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for max_len in range(128-4-8, 128-4+9):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-8, max_len+9):
+
+            tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_rx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = XgmiiFrame.from_payload(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        frame_error = rx_frame.tuser[-1] & 1
+                        assert frame_error
+                    else:
+                        frame_error = rx_frame.tuser & 1
+                        assert rx_frame.tdata == test_data_2
+                        assert frame_error == 0
+                else:
+                    frame_error = rx_frame.tuser & 1
+                    assert rx_frame.tdata == test_data_1
+                    assert frame_error == 0
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["rx_start_packet"] == total_pkts
+        assert tb.stats["stat_rx_byte"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_len"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_fragment"] == 0
+        assert tb.stats["stat_rx_pkt_jabber"] == 0
+        assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_rx_pkt_mcast"] == 0
+        assert tb.stats["stat_rx_pkt_bcast"] == 0
+        assert tb.stats["stat_rx_pkt_vlan"] == 0
+        assert tb.stats["stat_rx_pkt_good"] == total_pkts-oversz_pkts
+        assert tb.stats["stat_rx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_rx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_rx_err_bad_fcs"] == 0
+        assert tb.stats["stat_rx_err_bad_block"] == 0
+        assert tb.stats["stat_rx_err_framing"] == 0
+        assert tb.stats["stat_rx_err_preamble"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", list(range(0, 13)))
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_oversize)
+    factory.add_option("ifg", list(range(0, 13)))
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_axis_xgmii_rx_32(request):
+    dut = "taxi_axis_xgmii_rx_32"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 32
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_W'] = 96
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv

@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream XGMII frame receiver testbench
+ */
+module test_taxi_axis_xgmii_rx_32 #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 32,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter PTP_TS_W = 96
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam CTRL_W = DATA_W/8;
+localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic clk;
+logic rst;
+
+logic [DATA_W-1:0] xgmii_rxd;
+logic [CTRL_W-1:0] xgmii_rxc;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx();
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+logic rx_start_packet;
+logic [2:0] stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+
+taxi_axis_xgmii_rx_32 #(
+    .DATA_W(DATA_W),
+    .CTRL_W(CTRL_W),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XGMII input
+     */
+    .xgmii_rxd(xgmii_rxd),
+    .xgmii_rxc(xgmii_rxc),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+
+    /*
+     * Status
+     */
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_axis_xgmii_rx_64/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_xgmii_rx_64
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py

@@ -0,0 +1,327 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, XgmiiSource, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSink
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.clk, dut.rst)
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["stat_rx_byte"] = 0
+        self.stats["stat_rx_pkt_len"] = 0
+        self.stats["stat_rx_pkt_fragment"] = 0
+        self.stats["stat_rx_pkt_jabber"] = 0
+        self.stats["stat_rx_pkt_ucast"] = 0
+        self.stats["stat_rx_pkt_mcast"] = 0
+        self.stats["stat_rx_pkt_bcast"] = 0
+        self.stats["stat_rx_pkt_vlan"] = 0
+        self.stats["stat_rx_pkt_good"] = 0
+        self.stats["stat_rx_pkt_bad"] = 0
+        self.stats["stat_rx_err_oversize"] = 0
+        self.stats["stat_rx_err_bad_fcs"] = 0
+        self.stats["stat_rx_err_bad_block"] = 0
+        self.stats["stat_rx_err_framing"] = 0
+        self.stats["stat_rx_err_preamble"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.source.send(test_frame)
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        if tx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            tx_frame_sfd_ns -= 3.2
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - 6.4) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_rx_byte"] == total_bytes
+    assert tb.stats["stat_rx_pkt_len"] == total_bytes
+    assert tb.stats["stat_rx_pkt_fragment"] == 0
+    assert tb.stats["stat_rx_pkt_jabber"] == 0
+    assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_rx_pkt_mcast"] == 0
+    assert tb.stats["stat_rx_pkt_bcast"] == 0
+    assert tb.stats["stat_rx_pkt_vlan"] == 0
+    assert tb.stats["stat_rx_pkt_good"] == total_pkts
+    assert tb.stats["stat_rx_pkt_bad"] == 0
+    assert tb.stats["stat_rx_err_oversize"] == 0
+    assert tb.stats["stat_rx_err_bad_fcs"] == 0
+    assert tb.stats["stat_rx_err_bad_block"] == 0
+    assert tb.stats["stat_rx_err_framing"] == 0
+    assert tb.stats["stat_rx_err_preamble"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 1518
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for max_len in range(128-4-8, 128-4+9):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-8, max_len+9):
+
+            tb.log.info("max len %d (with FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_rx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = XgmiiFrame.from_payload(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        frame_error = rx_frame.tuser[-1] & 1
+                        assert frame_error
+                    else:
+                        frame_error = rx_frame.tuser & 1
+                        assert rx_frame.tdata == test_data_2
+                        assert frame_error == 0
+                else:
+                    frame_error = rx_frame.tuser & 1
+                    assert rx_frame.tdata == test_data_1
+                    assert frame_error == 0
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["stat_rx_byte"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_len"] >= good_bytes+oversz_bytes_out
+        assert tb.stats["stat_rx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_rx_pkt_fragment"] == 0
+        assert tb.stats["stat_rx_pkt_jabber"] == 0
+        assert tb.stats["stat_rx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_rx_pkt_mcast"] == 0
+        assert tb.stats["stat_rx_pkt_bcast"] == 0
+        assert tb.stats["stat_rx_pkt_vlan"] == 0
+        assert tb.stats["stat_rx_pkt_good"] == total_pkts-oversz_pkts
+        assert tb.stats["stat_rx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_rx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_rx_err_bad_fcs"] == 0
+        assert tb.stats["stat_rx_err_bad_block"] == 0
+        assert tb.stats["stat_rx_err_framing"] == 0
+        assert tb.stats["stat_rx_err_preamble"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", list(range(0, 13)))
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_oversize)
+    factory.add_option("ifg", list(range(0, 13)))
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_axis_xgmii_rx_64(request):
+    dut = "taxi_axis_xgmii_rx_64"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv

@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream XGMII frame receiver testbench
+ */
+module test_taxi_axis_xgmii_rx_64 #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam CTRL_W = DATA_W/8;
+localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic clk;
+logic rst;
+
+logic [DATA_W-1:0] xgmii_rxd;
+logic [CTRL_W-1:0] xgmii_rxc;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx();
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+logic [1:0] rx_start_packet;
+logic [3:0] stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+
+taxi_axis_xgmii_rx_64 #(
+    .DATA_W(DATA_W),
+    .CTRL_W(CTRL_W),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XGMII input
+     */
+    .xgmii_rxd(xgmii_rxd),
+    .xgmii_rxc(xgmii_rxc),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+
+    /*
+     * Status
+     */
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_axis_xgmii_tx_32/Makefile

@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_xgmii_tx_32
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 32
+export PARAM_PADDING_EN := 1
+export PARAM_DIC_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_W := 96
+export PARAM_TX_TAG_W := 16
+export PARAM_TX_CPL_CTRL_IN_TUSER := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.py

@@ -0,0 +1,545 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiSink, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 3.2, units="ns").start())
+
+        self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
+        self.sink = XgmiiSink(dut.xgmii_txd, dut.xgmii_txc, dut.clk, dut.rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.clk, dut.rst)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["tx_start_packet"] = 0
+        self.stats["stat_tx_byte"] = 0
+        self.stats["stat_tx_pkt_len"] = 0
+        self.stats["stat_tx_pkt_ucast"] = 0
+        self.stats["stat_tx_pkt_mcast"] = 0
+        self.stats["stat_tx_pkt_bcast"] = 0
+        self.stats["stat_tx_pkt_vlan"] = 0
+        self.stats["stat_tx_pkt_good"] = 0
+        self.stats["stat_tx_pkt_bad"] = 0
+        self.stats["stat_tx_err_oversize"] = 0
+        self.stats["stat_tx_err_user"] = 0
+        self.stats["stat_tx_err_underflow"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        await tb.source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.ctrl is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - 3.2) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["tx_start_packet"] == total_pkts
+    assert tb.stats["stat_tx_byte"] == total_bytes
+    assert tb.stats["stat_tx_pkt_len"] == total_bytes
+    assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == total_pkts
+    assert tb.stats["stat_tx_pkt_bad"] == 0
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_alignment(dut, payload_data=None, ifg=12):
+
+    enable_dic = int(dut.DIC_EN.value)
+
+    tb = TB(dut)
+
+    byte_width = tb.source.width // 8
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for length in range(60, 92):
+
+        for k in range(10):
+            await RisingEdge(dut.clk)
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            await tb.source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+            total_bytes += max(len(test_data), 60)+4
+            total_pkts += 1
+
+        for test_data in test_frames:
+            rx_frame = await tb.sink.recv()
+            tx_cpl = await tb.tx_cpl_sink.recv()
+
+            ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+            rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+            tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+            tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+            tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - 3.2) < 0.01
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_width
+
+            if enable_dic:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.clk)
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["tx_start_packet"] == total_pkts
+    assert tb.stats["stat_tx_byte"] == total_bytes
+    assert tb.stats["stat_tx_pkt_len"] == total_bytes
+    assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == total_pkts
+    assert tb.stats["stat_tx_pkt_bad"] == 0
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_underrun(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.source.send(test_frame)
+
+    for k in range(32):
+        await RisingEdge(dut.clk)
+
+    tb.source.pause = True
+
+    for k in range(4):
+        await RisingEdge(dut.clk)
+
+    tb.source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["tx_start_packet"] == 3
+    assert tb.stats["stat_tx_byte"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 1
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_error(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["tx_start_packet"] == 3
+    assert tb.stats["stat_tx_byte"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 1
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 1518
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for max_len in range(128-4-8, 128-4+9):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-8, max_len+9):
+
+            tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_tx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = AxiStreamFrame(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        assert rx_frame.data[-1] == 0xFE
+                        assert rx_frame.ctrl[-1] == 1
+                    else:
+                        assert rx_frame.get_payload() == test_data_2
+                        assert rx_frame.check_fcs()
+                        assert rx_frame.ctrl is None
+                else:
+                    assert rx_frame.get_payload() == test_data_1
+                    assert rx_frame.check_fcs()
+                    assert rx_frame.ctrl is None
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["tx_start_packet"] == total_pkts
+        assert tb.stats["stat_tx_byte"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
+        assert tb.stats["stat_tx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_len"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
+        assert tb.stats["stat_tx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_tx_pkt_mcast"] == 0
+        assert tb.stats["stat_tx_pkt_bcast"] == 0
+        assert tb.stats["stat_tx_pkt_vlan"] == 0
+        assert tb.stats["stat_tx_pkt_good"] == total_pkts - oversz_pkts
+        assert tb.stats["stat_tx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_tx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_tx_err_user"] == 0
+        assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    for test in [
+                run_test_underrun,
+                run_test_error,
+                run_test_oversize
+            ]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("dic_en", [1, 0])
+def test_taxi_axis_xgmii_tx_32(request, dic_en):
+    dut = "taxi_axis_xgmii_tx_32"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 32
+    parameters['PADDING_EN'] = 1
+    parameters['DIC_EN'] = dic_en
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_W'] = 96
+    parameters['TX_TAG_W'] = 16
+    parameters['TX_CPL_CTRL_IN_TUSER'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.sv

@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream XGMII frame transmitter testbench
+ */
+module test_taxi_axis_xgmii_tx_32 #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 32,
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter PTP_TS_W = 96,
+    parameter TX_TAG_W = 16,
+    parameter logic TX_CPL_CTRL_IN_TUSER = 1'b0
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam CTRL_W = DATA_W/8;
+localparam USER_W = TX_CPL_CTRL_IN_TUSER ? 2 : 1;
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+
+logic [DATA_W-1:0] xgmii_txd;
+logic [CTRL_W-1:0] xgmii_txc;
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+
+logic tx_start_packet;
+logic [2:0] stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+
+taxi_axis_xgmii_tx_32 #(
+    .DATA_W(DATA_W),
+    .CTRL_W(CTRL_W),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W),
+    .TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * XGMII output
+     */
+    .xgmii_txd(xgmii_txd),
+    .xgmii_txc(xgmii_txc),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_axis_xgmii_tx_64/Makefile

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_axis_xgmii_tx_64
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_PADDING_EN := 1
+export PARAM_DIC_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
+export PARAM_TX_TAG_W := 16
+export PARAM_TX_CPL_CTRL_IN_TUSER := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.py

@@ -0,0 +1,548 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiSink, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
+        self.sink = XgmiiSink(dut.xgmii_txd, dut.xgmii_txc, dut.clk, dut.rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.clk, dut.rst)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+
+        self.stats = {}
+        self.stats["stat_tx_byte"] = 0
+        self.stats["stat_tx_pkt_len"] = 0
+        self.stats["stat_tx_pkt_ucast"] = 0
+        self.stats["stat_tx_pkt_mcast"] = 0
+        self.stats["stat_tx_pkt_bcast"] = 0
+        self.stats["stat_tx_pkt_vlan"] = 0
+        self.stats["stat_tx_pkt_good"] = 0
+        self.stats["stat_tx_pkt_bad"] = 0
+        self.stats["stat_tx_err_oversize"] = 0
+        self.stats["stat_tx_err_user"] = 0
+        self.stats["stat_tx_err_underflow"] = 0
+
+        cocotb.start_soon(self._run_stats_counters())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+        self.stats_reset()
+
+    def stats_reset(self):
+        for stat in self.stats:
+            self.stats[stat] = 0
+
+    async def _run_stats_counters(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+            for stat in self.stats:
+                self.stats[stat] += int(getattr(self.dut, stat).value)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for test_data in test_frames:
+        await tb.source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+        total_bytes += max(len(test_data), 60)+4
+        total_pkts += 1
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        if rx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            rx_frame_sfd_ns -= 3.2
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.ctrl is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - 6.4) < 0.01
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] == total_bytes
+    assert tb.stats["stat_tx_pkt_len"] == total_bytes
+    assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == total_pkts
+    assert tb.stats["stat_tx_pkt_bad"] == 0
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_alignment(dut, payload_data=None, ifg=12):
+
+    enable_dic = int(dut.DIC_EN.value)
+
+    tb = TB(dut)
+
+    byte_width = tb.source.width // 8
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    total_bytes = 0
+    total_pkts = 0
+
+    for length in range(60, 92):
+
+        for k in range(10):
+            await RisingEdge(dut.clk)
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            await tb.source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+            total_bytes += max(len(test_data), 60)+4
+            total_pkts += 1
+
+        for test_data in test_frames:
+            rx_frame = await tb.sink.recv()
+            tx_cpl = await tb.tx_cpl_sink.recv()
+
+            ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+            rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+            if rx_frame.start_lane == 4:
+                # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+                rx_frame_sfd_ns -= 3.2
+
+            tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+            tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+            tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - 6.4) < 0.01
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_width
+
+            if enable_dic:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.clk)
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] == total_bytes
+    assert tb.stats["stat_tx_pkt_len"] == total_bytes
+    assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == total_pkts
+    assert tb.stats["stat_tx_pkt_bad"] == 0
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_underrun(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.source.send(test_frame)
+
+    for k in range(16):
+        await RisingEdge(dut.clk)
+
+    tb.source.pause = True
+
+    for k in range(4):
+        await RisingEdge(dut.clk)
+
+    tb.source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 0
+    assert tb.stats["stat_tx_err_underflow"] == 1
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_error(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.sink.empty()
+
+    for stat, val in tb.stats.items():
+        tb.log.info("%s: %d", stat, val)
+
+    assert tb.stats["stat_tx_byte"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_len"] > 64*2 + 32
+    assert tb.stats["stat_tx_pkt_ucast"] == 3
+    assert tb.stats["stat_tx_pkt_mcast"] == 0
+    assert tb.stats["stat_tx_pkt_bcast"] == 0
+    assert tb.stats["stat_tx_pkt_vlan"] == 0
+    assert tb.stats["stat_tx_pkt_good"] == 2
+    assert tb.stats["stat_tx_pkt_bad"] == 1
+    assert tb.stats["stat_tx_err_oversize"] == 0
+    assert tb.stats["stat_tx_err_user"] == 1
+    assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_oversize(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.dut.cfg_tx_max_pkt_len.value = 1518
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for max_len in range(128-4-8, 128-4+9):
+
+        tb.stats_reset()
+
+        total_bytes = 0
+        total_pkts = 0
+        good_bytes = 0
+        oversz_pkts = 0
+        oversz_bytes_in = 0
+        oversz_bytes_out = 0
+
+        for test_pkt_len in range(max_len-8, max_len+9):
+
+            tb.log.info("max len %d (without FCS), test len %d (without FCS)", max_len, test_pkt_len)
+
+            tb.dut.cfg_tx_max_pkt_len.value = max_len+4
+
+            test_data_1 = bytes(x for x in range(60))
+            test_data_2 = bytes(x for x in range(test_pkt_len))
+
+            for k in range(3):
+                if k == 1:
+                    test_data = test_data_2
+                else:
+                    test_data = test_data_1
+                test_frame = AxiStreamFrame(test_data)
+                await tb.source.send(test_frame)
+                total_bytes += max(len(test_data), 60)+4
+                total_pkts += 1
+                if len(test_data) > max_len:
+                    oversz_pkts += 1
+                    oversz_bytes_in += len(test_data)+4
+                    oversz_bytes_out += max_len
+                else:
+                    good_bytes += len(test_data)+4
+
+            for k in range(3):
+                rx_frame = await tb.sink.recv()
+
+                if k == 1:
+                    if test_pkt_len > max_len:
+                        assert rx_frame.data[-1] == 0xFE
+                        assert rx_frame.ctrl[-1] == 1
+                    else:
+                        assert rx_frame.get_payload() == test_data_2
+                        assert rx_frame.check_fcs()
+                        assert rx_frame.ctrl is None
+                else:
+                    assert rx_frame.get_payload() == test_data_1
+                    assert rx_frame.check_fcs()
+                    assert rx_frame.ctrl is None
+
+        assert tb.sink.empty()
+
+        for stat, val in tb.stats.items():
+            tb.log.info("%s: %d", stat, val)
+
+        assert tb.stats["stat_tx_byte"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
+        assert tb.stats["stat_tx_byte"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_len"] >= good_bytes+oversz_bytes_out-8*oversz_pkts
+        assert tb.stats["stat_tx_pkt_len"] <= good_bytes+oversz_bytes_in
+        assert tb.stats["stat_tx_pkt_ucast"] == total_pkts
+        assert tb.stats["stat_tx_pkt_mcast"] == 0
+        assert tb.stats["stat_tx_pkt_bcast"] == 0
+        assert tb.stats["stat_tx_pkt_vlan"] == 0
+        assert tb.stats["stat_tx_pkt_good"] == total_pkts - oversz_pkts
+        assert tb.stats["stat_tx_pkt_bad"] == oversz_pkts
+        assert tb.stats["stat_tx_err_oversize"] == oversz_pkts
+        assert tb.stats["stat_tx_err_user"] == 0
+        assert tb.stats["stat_tx_err_underflow"] == 0
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    for test in [
+                run_test_underrun,
+                run_test_error,
+                run_test_oversize
+            ]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("enable_dic", [1, 0])
+def test_taxi_axis_xgmii_tx_64(request, enable_dic):
+    dut = "taxi_axis_xgmii_tx_64"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "lfsr", "rtl", "taxi_lfsr.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 64
+    parameters['PADDING_EN'] = 1
+    parameters['DIC_EN'] = enable_dic
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+    parameters['TX_TAG_W'] = 16
+    parameters['TX_CPL_CTRL_IN_TUSER'] = 1
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.sv

@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream XGMII frame transmitter testbench
+ */
+module test_taxi_axis_xgmii_tx_64 #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter TX_TAG_W = 16,
+    parameter logic TX_CPL_CTRL_IN_TUSER = 1'b0
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam CTRL_W = DATA_W/8;
+localparam USER_W = TX_CPL_CTRL_IN_TUSER ? 2 : 1;
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+
+logic [DATA_W-1:0] xgmii_txd;
+logic [CTRL_W-1:0] xgmii_txc;
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+
+logic [1:0] tx_start_packet;
+logic [3:0] stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+
+taxi_axis_xgmii_tx_64 #(
+    .DATA_W(DATA_W),
+    .CTRL_W(CTRL_W),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W),
+    .TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * XGMII output
+     */
+    .xgmii_txd(xgmii_txd),
+    .xgmii_txc(xgmii_txc),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_10g/Makefile

@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_10g
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_PADDING_EN := 1
+export PARAM_DIC_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
+export PARAM_TX_TAG_W := 16
+export PARAM_PFC_EN := 1
+export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py

@@ -0,0 +1,781 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import struct
+
+from scapy.layers.l2 import Ether
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        if len(dut.xgmii_txd) == 64:
+            self.clk_period = 6.4
+        else:
+            self.clk_period = 3.2
+
+        cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, self.clk_period, units="ns").start())
+
+        self.xgmii_source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.rx_clk, dut.rx_rst)
+        self.xgmii_sink = XgmiiSink(dut.xgmii_txd, dut.xgmii_txc, dut.tx_clk, dut.tx_rst)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.tx_clk, dut.tx_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.rx_clk, dut.rx_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
+        self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
+
+        dut.tx_lfc_req.setimmediatevalue(0)
+        dut.tx_lfc_resend.setimmediatevalue(0)
+        dut.rx_lfc_en.setimmediatevalue(0)
+        dut.rx_lfc_ack.setimmediatevalue(0)
+
+        dut.tx_pfc_req.setimmediatevalue(0)
+        dut.tx_pfc_resend.setimmediatevalue(0)
+        dut.rx_pfc_en.setimmediatevalue(0)
+        dut.rx_pfc_ack.setimmediatevalue(0)
+
+        dut.tx_lfc_pause_en.setimmediatevalue(0)
+        dut.tx_pause_req.setimmediatevalue(0)
+
+        dut.stat_rx_fifo_drop.setimmediatevalue(0)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_type.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_forward.setimmediatevalue(0)
+        dut.cfg_mcf_rx_enable.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_lfc_en.setimmediatevalue(0)
+        dut.cfg_tx_lfc_quanta.setimmediatevalue(0)
+        dut.cfg_tx_lfc_refresh.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_pfc_en.setimmediatevalue(0)
+        dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
+        dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
+        dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_lfc_en.setimmediatevalue(0)
+        dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_pfc_en.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rx_rst.setimmediatevalue(0)
+        self.dut.tx_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.rx_clk)
+        await RisingEdge(self.dut.rx_clk)
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.rx_clk)
+        await RisingEdge(self.dut.rx_clk)
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.rx_clk)
+        await RisingEdge(self.dut.rx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.xgmii_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        if tx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            tx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period) < 0.01
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+    for test_data in test_frames:
+        rx_frame = await tb.xgmii_sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        if rx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            rx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.ctrl is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < 0.01
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
+
+    dic_en = int(cocotb.top.DIC_EN.value)
+
+    tb = TB(dut)
+
+    byte_width = tb.axis_source.width // 8
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for length in range(60, 92):
+
+        for k in range(10):
+            await RisingEdge(dut.tx_clk)
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+        for test_data in test_frames:
+            rx_frame = await tb.xgmii_sink.recv()
+            tx_cpl = await tb.tx_cpl_sink.recv()
+
+            ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+            rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+            if rx_frame.start_lane == 4:
+                # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+                rx_frame_sfd_ns -= 3.2
+
+            tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+            tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+            tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < 0.01
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_width
+
+            if dic_en:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.tx_clk)
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_underrun(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.axis_source.send(test_frame)
+
+    for k in range(64*16 // tb.axis_source.width):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = True
+
+    for k in range(4):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.xgmii_sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_error(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.axis_source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.xgmii_sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_lfc(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    dut.tx_lfc_req.value = 0
+    dut.tx_lfc_resend.value = 0
+    dut.rx_lfc_en.value = 1
+    dut.rx_lfc_ack.value = 0
+
+    dut.tx_lfc_pause_en.value = 1
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_lfc_eth_type.value = 0x8808
+    dut.cfg_tx_lfc_opcode.value = 0x0001
+    dut.cfg_tx_lfc_en.value = 1
+    dut.cfg_tx_lfc_quanta.value = 0xFFFF
+    dut.cfg_tx_lfc_refresh.value = 0x7F00
+
+    dut.cfg_rx_lfc_opcode.value = 0x0001
+    dut.cfg_rx_lfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 512
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+        await tb.xgmii_source.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+            await tb.xgmii_source.send(test_frame)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while not dut.rx_lfc_req.value.integer:
+        await RisingEdge(dut.tx_clk)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_lfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.xgmii_sink.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_lfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_lfc_cnt == 4
+
+    assert tb.axis_sink.empty()
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_pfc(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    dut.tx_pfc_req.value = 0x00
+    dut.tx_pfc_resend.value = 0
+    dut.rx_pfc_en.value = 0xff
+    dut.rx_pfc_ack.value = 0x00
+
+    dut.tx_lfc_pause_en.value = 0
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_pfc_eth_type.value = 0x8808
+    dut.cfg_tx_pfc_opcode.value = 0x0101
+    dut.cfg_tx_pfc_en.value = 1
+    dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
+    dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
+
+    dut.cfg_rx_pfc_opcode.value = 0x0101
+    dut.cfg_rx_pfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 512
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+        await tb.xgmii_source.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+            await tb.xgmii_source.send(test_frame)
+
+    dut.rx_pfc_ack.value = 0xff
+
+    for i in range(8):
+        for k in range(200):
+            await RisingEdge(dut.tx_clk)
+
+        dut.tx_pfc_req.value = 0xff >> (7-i)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_pfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.xgmii_sink.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_pfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_pfc_cnt == 9
+
+    assert tb.axis_sink.empty()
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12, 0])
+        factory.generate_tests()
+
+    factory = TestFactory(run_test_tx_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    for test in [run_test_tx_underrun, run_test_tx_error]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.generate_tests()
+
+    if cocotb.top.PFC_EN.value:
+        for test in [run_test_lfc, run_test_pfc]:
+            factory = TestFactory(test)
+            factory.add_option("ifg", [12])
+            factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize(("dic_en", "pfc_en"), [(1, 1), (1, 0), (0, 0)])
+@pytest.mark.parametrize("data_w", [32, 64])
+def test_taxi_eth_mac_10g(request, data_w, dic_en, pfc_en):
+    dut = "taxi_eth_mac_10g"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['PADDING_EN'] = 1
+    parameters['DIC_EN'] = dic_en
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+    parameters['TX_TAG_W'] = 16
+    parameters['PFC_EN'] = pfc_en
+    parameters['PAUSE_EN'] = parameters['PFC_EN']
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.sv

@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 10G Ethernet MAC testbench
+ */
+module test_taxi_eth_mac_10g #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter TX_TAG_W = 16,
+    parameter logic PFC_EN = 1'b0,
+    parameter logic PAUSE_EN = PFC_EN,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam CTRL_W = (DATA_W/8);
+localparam TX_USER_W = 1;
+localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic [DATA_W-1:0] xgmii_rxd;
+logic [CTRL_W-1:0] xgmii_rxc;
+logic [DATA_W-1:0] xgmii_txd;
+logic [CTRL_W-1:0] xgmii_txc;
+
+logic [PTP_TS_W-1:0] tx_ptp_ts;
+logic [PTP_TS_W-1:0] rx_ptp_ts;
+
+logic tx_lfc_req;
+logic tx_lfc_resend;
+logic rx_lfc_en;
+logic rx_lfc_req;
+logic rx_lfc_ack;
+
+logic [7:0] tx_pfc_req;
+logic tx_pfc_resend;
+logic [7:0] rx_pfc_en;
+logic [7:0] rx_pfc_req;
+logic [7:0] rx_pfc_ack;
+
+logic tx_lfc_pause_en;
+logic tx_pause_req;
+logic tx_pause_ack;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic [1:0] tx_start_packet;
+logic [3:0] stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+logic [1:0] rx_start_packet;
+logic [3:0] stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+logic stat_rx_fifo_drop;
+logic stat_tx_mcf;
+logic stat_rx_mcf;
+logic stat_tx_lfc_pkt;
+logic stat_tx_lfc_xon;
+logic stat_tx_lfc_xoff;
+logic stat_tx_lfc_paused;
+logic stat_tx_pfc_pkt;
+logic [7:0] stat_tx_pfc_xon;
+logic [7:0] stat_tx_pfc_xoff;
+logic [7:0] stat_tx_pfc_paused;
+logic stat_rx_lfc_pkt;
+logic stat_rx_lfc_xon;
+logic stat_rx_lfc_xoff;
+logic stat_rx_lfc_paused;
+logic stat_rx_pfc_pkt;
+logic [7:0] stat_rx_pfc_xon;
+logic [7:0] stat_rx_pfc_xoff;
+logic [7:0] stat_rx_pfc_paused;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+logic [47:0] cfg_mcf_rx_eth_dst_mcast;
+logic cfg_mcf_rx_check_eth_dst_mcast;
+logic [47:0] cfg_mcf_rx_eth_dst_ucast;
+logic cfg_mcf_rx_check_eth_dst_ucast;
+logic [47:0] cfg_mcf_rx_eth_src;
+logic cfg_mcf_rx_check_eth_src;
+logic [15:0] cfg_mcf_rx_eth_type;
+logic [15:0] cfg_mcf_rx_opcode_lfc;
+logic cfg_mcf_rx_check_opcode_lfc;
+logic [15:0] cfg_mcf_rx_opcode_pfc;
+logic cfg_mcf_rx_check_opcode_pfc;
+logic cfg_mcf_rx_forward;
+logic cfg_mcf_rx_enable;
+logic [47:0] cfg_tx_lfc_eth_dst;
+logic [47:0] cfg_tx_lfc_eth_src;
+logic [15:0] cfg_tx_lfc_eth_type;
+logic [15:0] cfg_tx_lfc_opcode;
+logic cfg_tx_lfc_en;
+logic [15:0] cfg_tx_lfc_quanta;
+logic [15:0] cfg_tx_lfc_refresh;
+logic [47:0] cfg_tx_pfc_eth_dst;
+logic [47:0] cfg_tx_pfc_eth_src;
+logic [15:0] cfg_tx_pfc_eth_type;
+logic [15:0] cfg_tx_pfc_opcode;
+logic cfg_tx_pfc_en;
+logic [15:0] cfg_tx_pfc_quanta[8];
+logic [15:0] cfg_tx_pfc_refresh[8];
+logic [15:0] cfg_rx_lfc_opcode;
+logic cfg_rx_lfc_en;
+logic [15:0] cfg_rx_pfc_opcode;
+logic cfg_rx_pfc_en;
+
+taxi_eth_mac_10g #(
+    .DATA_W(DATA_W),
+    .CTRL_W(CTRL_W),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W),
+    .PFC_EN(PFC_EN),
+    .PAUSE_EN(PAUSE_EN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR)
+)
+uut (
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * XGMII interface
+     */
+    .xgmii_rxd(xgmii_rxd),
+    .xgmii_rxc(xgmii_rxc),
+    .xgmii_txd(xgmii_txd),
+    .xgmii_txc(xgmii_txc),
+
+    /*
+     * PTP
+     */
+    .tx_ptp_ts(tx_ptp_ts),
+    .rx_ptp_ts(rx_ptp_ts),
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req(tx_lfc_req),
+    .tx_lfc_resend(tx_lfc_resend),
+    .rx_lfc_en(rx_lfc_en),
+    .rx_lfc_req(rx_lfc_req),
+    .rx_lfc_ack(rx_lfc_ack),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req(tx_pfc_req),
+    .tx_pfc_resend(tx_pfc_resend),
+    .rx_pfc_en(rx_pfc_en),
+    .rx_pfc_req(rx_pfc_req),
+    .rx_pfc_ack(rx_pfc_ack),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en(tx_lfc_pause_en),
+    .tx_pause_req(tx_pause_req),
+    .tx_pause_ack(tx_pause_ack),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow),
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble),
+    .stat_rx_fifo_drop(stat_rx_fifo_drop),
+    .stat_tx_mcf(stat_tx_mcf),
+    .stat_rx_mcf(stat_rx_mcf),
+    .stat_tx_lfc_pkt(stat_tx_lfc_pkt),
+    .stat_tx_lfc_xon(stat_tx_lfc_xon),
+    .stat_tx_lfc_xoff(stat_tx_lfc_xoff),
+    .stat_tx_lfc_paused(stat_tx_lfc_paused),
+    .stat_tx_pfc_pkt(stat_tx_pfc_pkt),
+    .stat_tx_pfc_xon(stat_tx_pfc_xon),
+    .stat_tx_pfc_xoff(stat_tx_pfc_xoff),
+    .stat_tx_pfc_paused(stat_tx_pfc_paused),
+    .stat_rx_lfc_pkt(stat_rx_lfc_pkt),
+    .stat_rx_lfc_xon(stat_rx_lfc_xon),
+    .stat_rx_lfc_xoff(stat_rx_lfc_xoff),
+    .stat_rx_lfc_paused(stat_rx_lfc_paused),
+    .stat_rx_pfc_pkt(stat_rx_pfc_pkt),
+    .stat_rx_pfc_xon(stat_rx_pfc_xon),
+    .stat_rx_pfc_xoff(stat_rx_pfc_xoff),
+    .stat_rx_pfc_paused(stat_rx_pfc_paused),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+    .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
+    .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
+    .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
+    .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
+    .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
+    .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
+    .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
+    .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
+    .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
+    .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
+    .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
+    .cfg_mcf_rx_forward(cfg_mcf_rx_forward),
+    .cfg_mcf_rx_enable(cfg_mcf_rx_enable),
+    .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
+    .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
+    .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
+    .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
+    .cfg_tx_lfc_en(cfg_tx_lfc_en),
+    .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
+    .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
+    .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
+    .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
+    .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
+    .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
+    .cfg_tx_pfc_en(cfg_tx_pfc_en),
+    .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
+    .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
+    .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
+    .cfg_rx_lfc_en(cfg_rx_lfc_en),
+    .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
+    .cfg_rx_pfc_en(cfg_rx_pfc_en)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_10g_fifo/Makefile

@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_10g_fifo
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_AXIS_DATA_W := $(PARAM_DATA_W)
+export PARAM_PADDING_EN := 1
+export PARAM_DIC_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
+export PARAM_TX_TAG_W := 16
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+export PARAM_TX_FIFO_DEPTH := 16384
+export PARAM_TX_FIFO_RAM_PIPELINE := 1
+export PARAM_TX_FRAME_FIFO := 1
+export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
+export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
+export PARAM_TX_DROP_WHEN_FULL := 0
+export PARAM_TX_CPL_FIFO_DEPTH := 64
+export PARAM_RX_FIFO_DEPTH := 16384
+export PARAM_RX_FIFO_RAM_PIPELINE := 1
+export PARAM_RX_FRAME_FIFO := 1
+export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
+export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py

@@ -0,0 +1,392 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        if len(dut.xgmii_txd) == 64:
+            self.clk_period = 6.4
+        else:
+            self.clk_period = 3.2
+
+        cocotb.start_soon(Clock(dut.logic_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.ptp_sample_clk, 9.9, units="ns").start())
+
+        self.xgmii_source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.rx_clk, dut.rx_rst)
+        self.xgmii_sink = XgmiiSink(dut.xgmii_txd, dut.xgmii_txc, dut.tx_clk, dut.tx_rst)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.logic_clk)
+
+        dut.ptp_ts_step.setimmediatevalue(0)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.logic_rst.setimmediatevalue(0)
+        self.dut.rx_rst.setimmediatevalue(0)
+        self.dut.tx_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.logic_clk)
+        await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.logic_clk)
+        await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.logic_clk)
+        await RisingEdge(self.dut.logic_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    tb.log.info("Wait for PTP CDC lock")
+    while not dut.uut.rx_ptp_locked.value.integer:
+        await RisingEdge(dut.rx_clk)
+    for k in range(1000):
+        await RisingEdge(dut.rx_clk)
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.xgmii_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        if tx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            tx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period) < tb.clk_period*2
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    tb.log.info("Wait for PTP CDC lock")
+    while not dut.uut.tx_ptp_locked.value.integer:
+        await RisingEdge(dut.tx_clk)
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+    for test_data in test_frames:
+        rx_frame = await tb.xgmii_sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        if rx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            rx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.ctrl is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < tb.clk_period*2
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
+
+    dic_en = int(cocotb.top.DIC_EN.value)
+
+    tb = TB(dut)
+
+    byte_width = tb.axis_source.width // 8
+
+    tb.xgmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    tb.log.info("Wait for PTP CDC lock")
+    while not dut.uut.tx_ptp_locked.value.integer:
+        await RisingEdge(dut.tx_clk)
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    for length in range(60, 92):
+
+        for k in range(10):
+            await RisingEdge(dut.tx_clk)
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+        for test_data in test_frames:
+            rx_frame = await tb.xgmii_sink.recv()
+            tx_cpl = await tb.tx_cpl_sink.recv()
+
+            ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+            rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+            if rx_frame.start_lane == 4:
+                # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+                rx_frame_sfd_ns -= 3.2
+
+            tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+            tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+            tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < tb.clk_period*2
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_width
+
+            if dic_en:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.logic_clk)
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12, 0])
+        factory.generate_tests()
+
+    factory = TestFactory(run_test_tx_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("dic_en", [1, 0])
+@pytest.mark.parametrize("data_w", [32, 64])
+def test_taxi_eth_mac_10g_fifo(request, data_w, dic_en):
+    dut = "taxi_eth_mac_10g_fifo"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['AXIS_DATA_W'] = parameters['DATA_W']
+    parameters['PADDING_EN'] = 1
+    parameters['DIC_EN'] = dic_en
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+    parameters['TX_TAG_W'] = 16
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+    parameters['TX_FIFO_DEPTH'] = 16384
+    parameters['TX_FIFO_RAM_PIPELINE'] = 1
+    parameters['TX_FRAME_FIFO'] = 1
+    parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
+    parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
+    parameters['TX_DROP_WHEN_FULL'] = 0
+    parameters['TX_CPL_FIFO_DEPTH'] = 64
+    parameters['RX_FIFO_DEPTH'] = 16384
+    parameters['RX_FIFO_RAM_PIPELINE'] = 1
+    parameters['RX_FRAME_FIFO'] = 1
+    parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
+    parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
+    parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.sv

@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 10G Ethernet MAC with TX and RX FIFOs testbench
+ */
+module test_taxi_eth_mac_10g_fifo #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 8,
+    parameter AXIS_DATA_W = 8,
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter TX_TAG_W = 16,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC",
+    parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_RAM_PIPELINE = 1,
+    parameter logic TX_FRAME_FIFO = 1'b1,
+    parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
+    parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
+    parameter logic TX_DROP_WHEN_FULL = 1'b0,
+    parameter TX_CPL_FIFO_DEPTH = 64,
+    parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_RAM_PIPELINE = 1,
+    parameter logic RX_FRAME_FIFO = 1'b1,
+    parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
+    parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
+    parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam CTRL_W = DATA_W/8;
+localparam TX_USER_W = 1;
+localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+logic logic_clk;
+logic logic_rst;
+logic ptp_sample_clk;
+
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic [DATA_W-1:0] xgmii_rxd;
+logic [CTRL_W-1:0] xgmii_rxc;
+logic [DATA_W-1:0] xgmii_txd;
+logic [CTRL_W-1:0] xgmii_txc;
+
+logic [PTP_TS_W-1:0] ptp_ts;
+logic ptp_ts_step;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_error_underflow;
+logic tx_fifo_overflow;
+logic tx_fifo_bad_frame;
+logic tx_fifo_good_frame;
+logic rx_error_bad_frame;
+logic rx_error_bad_fcs;
+logic rx_fifo_overflow;
+logic rx_fifo_bad_frame;
+logic rx_fifo_good_frame;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+taxi_eth_mac_10g_fifo #(
+    .DATA_W(DATA_W),
+    .CTRL_W(CTRL_W),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR),
+    .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
+    .TX_FRAME_FIFO(TX_FRAME_FIFO),
+    .TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
+    .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
+    .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
+    .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
+    .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
+    .RX_FRAME_FIFO(RX_FRAME_FIFO),
+    .RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
+    .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
+    .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
+)
+uut (
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+    .logic_clk(logic_clk),
+    .logic_rst(logic_rst),
+    .ptp_sample_clk(ptp_sample_clk),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * XGMII interface
+     */
+    .xgmii_rxd(xgmii_rxd),
+    .xgmii_rxc(xgmii_rxc),
+    .xgmii_txd(xgmii_txd),
+    .xgmii_txc(xgmii_txc),
+
+    /*
+     * PTP clock
+     */
+    .ptp_ts(ptp_ts),
+    .ptp_ts_step(ptp_ts_step),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(tx_error_underflow),
+    .tx_fifo_overflow(tx_fifo_overflow),
+    .tx_fifo_bad_frame(tx_fifo_bad_frame),
+    .tx_fifo_good_frame(tx_fifo_good_frame),
+    .rx_error_bad_frame(rx_error_bad_frame),
+    .rx_error_bad_fcs(rx_error_bad_fcs),
+    .rx_fifo_overflow(rx_fifo_overflow),
+    .rx_fifo_bad_frame(rx_fifo_bad_frame),
+    .rx_fifo_good_frame(rx_fifo_good_frame),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_1g/Makefile

@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_1g
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 8
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_W := 96
+export PARAM_TX_TAG_W := 16
+export PARAM_PFC_EN := 1
+export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py

@@ -0,0 +1,866 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import struct
+import os
+
+from scapy.layers.l2 import Ether
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        self._enable_generator_rx = None
+        self._enable_generator_tx = None
+        self._enable_cr_rx = None
+        self._enable_cr_tx = None
+
+        cocotb.start_soon(Clock(dut.rx_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.tx_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
+
+        self.gmii_source = GmiiSource(dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv,
+            dut.rx_clk, dut.rx_rst, dut.rx_clk_enable, dut.rx_mii_select)
+        self.gmii_sink = GmiiSink(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en,
+            dut.tx_clk, dut.tx_rst, dut.tx_clk_enable, dut.tx_mii_select)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.tx_clk, dut.tx_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.rx_clk, dut.rx_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
+        self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
+
+        dut.tx_lfc_req.setimmediatevalue(0)
+        dut.tx_lfc_resend.setimmediatevalue(0)
+        dut.rx_lfc_en.setimmediatevalue(0)
+        dut.rx_lfc_ack.setimmediatevalue(0)
+
+        dut.tx_pfc_req.setimmediatevalue(0)
+        dut.tx_pfc_resend.setimmediatevalue(0)
+        dut.rx_pfc_en.setimmediatevalue(0)
+        dut.rx_pfc_ack.setimmediatevalue(0)
+
+        dut.tx_lfc_pause_en.setimmediatevalue(0)
+        dut.tx_pause_req.setimmediatevalue(0)
+
+        dut.rx_clk_enable.setimmediatevalue(1)
+        dut.tx_clk_enable.setimmediatevalue(1)
+        dut.rx_mii_select.setimmediatevalue(0)
+        dut.tx_mii_select.setimmediatevalue(0)
+
+        dut.stat_rx_fifo_drop.setimmediatevalue(0)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_type.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_forward.setimmediatevalue(0)
+        dut.cfg_mcf_rx_enable.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_lfc_en.setimmediatevalue(0)
+        dut.cfg_tx_lfc_quanta.setimmediatevalue(0)
+        dut.cfg_tx_lfc_refresh.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_pfc_en.setimmediatevalue(0)
+        dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
+        dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
+        dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_lfc_en.setimmediatevalue(0)
+        dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_pfc_en.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rx_rst.setimmediatevalue(0)
+        self.dut.tx_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+
+    def set_enable_generator_rx(self, generator=None):
+        if self._enable_cr_rx is not None:
+            self._enable_cr_rx.kill()
+            self._enable_cr_rx = None
+
+        self._enable_generator_rx = generator
+
+        if self._enable_generator_rx is not None:
+            self._enable_cr_rx = cocotb.start_soon(self._run_enable_rx())
+
+    def set_enable_generator_tx(self, generator=None):
+        if self._enable_cr_tx is not None:
+            self._enable_cr_tx.kill()
+            self._enable_cr_tx = None
+
+        self._enable_generator_tx = generator
+
+        if self._enable_generator_tx is not None:
+            self._enable_cr_tx = cocotb.start_soon(self._run_enable_tx())
+
+    def clear_enable_generator_rx(self):
+        self.set_enable_generator_rx(None)
+
+    def clear_enable_generator_tx(self):
+        self.set_enable_generator_tx(None)
+
+    async def _run_enable_rx(self):
+        for val in self._enable_generator_rx:
+            self.dut.rx_clk_enable.value = val
+            await RisingEdge(self.dut.rx_clk)
+
+    async def _run_enable_tx(self):
+        for val in self._enable_generator_tx:
+            self.dut.tx_clk_enable.value = val
+            await RisingEdge(self.dut.tx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.gmii_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - (32 if enable_gen else 8)) < 0.01
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+    for test_data in test_frames:
+        rx_frame = await tb.gmii_sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - (32 if enable_gen else 8)) < 0.01
+
+    assert tb.gmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_underrun(dut, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.axis_source.send(test_frame)
+
+    for k in range(200 if mii_sel else 100):
+        while True:
+            await RisingEdge(dut.tx_clk)
+            if dut.tx_clk_enable.value.integer:
+                break
+
+    tb.axis_source.pause = True
+
+    for k in range(10):
+        while True:
+            await RisingEdge(dut.tx_clk)
+            if dut.tx_clk_enable.value.integer:
+                break
+
+    tb.axis_source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.gmii_sink.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.gmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_error(dut, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.axis_source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.gmii_sink.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.gmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_rx_oversize(dut, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 1518
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 1518
+    tb.dut.cfg_rx_enable.value = 1
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = GmiiFrame.from_payload(test_data)
+        if k == 1:
+            test_frame = GmiiFrame.from_payload(bytes(x % 256 for x in range(1515)))
+        await tb.gmii_source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.axis_sink.recv()
+
+        if k == 1:
+            frame_error = rx_frame.tuser[-1] & 1
+            assert frame_error
+        else:
+            frame_error = rx_frame.tuser & 1
+            assert rx_frame.tdata == test_data
+            assert frame_error == 0
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_tx_oversize(dut, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 1518
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 1518
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame = AxiStreamFrame(bytes(x % 256 for x in range(1515)))
+        await tb.axis_source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.gmii_sink.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.gmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_lfc(dut, ifg=12, enable_gen=None, mii_sel=True):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    dut.tx_lfc_req.value = 0
+    dut.tx_lfc_resend.value = 0
+    dut.rx_lfc_en.value = 1
+    dut.rx_lfc_ack.value = 0
+
+    dut.tx_lfc_pause_en.value = 1
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_lfc_eth_type.value = 0x8808
+    dut.cfg_tx_lfc_opcode.value = 0x0001
+    dut.cfg_tx_lfc_en.value = 1
+    dut.cfg_tx_lfc_quanta.value = 0xFFFF
+    dut.cfg_tx_lfc_refresh.value = 0x7F00
+
+    dut.cfg_rx_lfc_opcode.value = 0x0001
+    dut.cfg_rx_lfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 128
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+        await tb.gmii_source.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+            await tb.gmii_source.send(test_frame)
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while not dut.rx_lfc_req.value.integer:
+        await RisingEdge(dut.tx_clk)
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_lfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.gmii_sink.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_lfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_lfc_cnt == 4
+
+    assert tb.axis_sink.empty()
+    assert tb.gmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    dut.tx_pfc_req.value = 0x00
+    dut.tx_pfc_resend.value = 0
+    dut.rx_pfc_en.value = 0xff
+    dut.rx_pfc_ack.value = 0x00
+
+    dut.tx_lfc_pause_en.value = 0
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_pfc_eth_type.value = 0x8808
+    dut.cfg_tx_pfc_opcode.value = 0x0101
+    dut.cfg_tx_pfc_en.value = 1
+    dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
+    dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
+
+    dut.cfg_rx_pfc_opcode.value = 0x0101
+    dut.cfg_rx_pfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 128
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+        await tb.gmii_source.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+            await tb.gmii_source.send(test_frame)
+
+    dut.rx_pfc_ack.value = 0xff
+
+    for i in range(8):
+        for k in range(500):
+            await RisingEdge(dut.tx_clk)
+
+        dut.tx_pfc_req.value = 0xff >> (7-i)
+
+    for k in range(500):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_pfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.gmii_sink.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_pfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_pfc_cnt > 2 and tx_pfc_cnt <= 9
+
+    assert tb.axis_sink.empty()
+    assert tb.gmii_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [
+                run_test_rx,
+                run_test_tx,
+            ]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.add_option("enable_gen", [None, cycle_en])
+        factory.add_option("mii_sel", [False, True])
+        factory.generate_tests()
+
+    for test in [
+                run_test_tx_underrun,
+                run_test_tx_error,
+                run_test_rx_oversize,
+                run_test_tx_oversize,
+            ]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.add_option("enable_gen", [None, cycle_en])
+        factory.add_option("mii_sel", [False, True])
+        factory.generate_tests()
+
+    if cocotb.top.PFC_EN.value:
+        for test in [
+                    run_test_lfc,
+                    run_test_pfc,
+                ]:
+
+            factory = TestFactory(test)
+            factory.add_option("ifg", [12])
+            factory.add_option("enable_gen", [None, cycle_en])
+            factory.add_option("mii_sel", [False, True])
+            factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("pfc_en", [1, 0])
+def test_taxi_eth_mac_1g(request, pfc_en):
+    dut = "taxi_eth_mac_1g"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 8
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_W'] = 96
+    parameters['TX_TAG_W'] = 16
+    parameters['PFC_EN'] = pfc_en
+    parameters['PAUSE_EN'] = parameters['PFC_EN']
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_1g/test_taxi_eth_mac_1g.sv

@@ -0,0 +1,355 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 1G Ethernet MAC testbench
+ */
+module test_taxi_eth_mac_1g #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 8,
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter PTP_TS_W = 96,
+    parameter TX_TAG_W = 16,
+    parameter logic PFC_EN = 1'b0,
+    parameter logic PAUSE_EN = PFC_EN,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam TX_USER_W = 1;
+localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic [DATA_W-1:0] gmii_rxd;
+logic gmii_rx_dv;
+logic gmii_rx_er;
+logic [DATA_W-1:0] gmii_txd;
+logic gmii_tx_en;
+logic gmii_tx_er;
+
+logic [PTP_TS_W-1:0] tx_ptp_ts;
+logic [PTP_TS_W-1:0] rx_ptp_ts;
+
+logic tx_lfc_req;
+logic tx_lfc_resend;
+logic rx_lfc_en;
+logic rx_lfc_req;
+logic rx_lfc_ack;
+
+logic [7:0] tx_pfc_req;
+logic tx_pfc_resend;
+logic [7:0] rx_pfc_en;
+logic [7:0] rx_pfc_req;
+logic [7:0] rx_pfc_ack;
+
+logic tx_lfc_pause_en;
+logic tx_pause_req;
+logic tx_pause_ack;
+
+logic rx_clk_enable;
+logic tx_clk_enable;
+logic rx_mii_select;
+logic tx_mii_select;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_start_packet;
+logic stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+logic rx_start_packet;
+logic stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+logic stat_rx_fifo_drop;
+logic stat_tx_mcf;
+logic stat_rx_mcf;
+logic stat_tx_lfc_pkt;
+logic stat_tx_lfc_xon;
+logic stat_tx_lfc_xoff;
+logic stat_tx_lfc_paused;
+logic stat_tx_pfc_pkt;
+logic [7:0] stat_tx_pfc_xon;
+logic [7:0] stat_tx_pfc_xoff;
+logic [7:0] stat_tx_pfc_paused;
+logic stat_rx_lfc_pkt;
+logic stat_rx_lfc_xon;
+logic stat_rx_lfc_xoff;
+logic stat_rx_lfc_paused;
+logic stat_rx_pfc_pkt;
+logic [7:0] stat_rx_pfc_xon;
+logic [7:0] stat_rx_pfc_xoff;
+logic [7:0] stat_rx_pfc_paused;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+logic [47:0] cfg_mcf_rx_eth_dst_mcast;
+logic cfg_mcf_rx_check_eth_dst_mcast;
+logic [47:0] cfg_mcf_rx_eth_dst_ucast;
+logic cfg_mcf_rx_check_eth_dst_ucast;
+logic [47:0] cfg_mcf_rx_eth_src;
+logic cfg_mcf_rx_check_eth_src;
+logic [15:0] cfg_mcf_rx_eth_type;
+logic [15:0] cfg_mcf_rx_opcode_lfc;
+logic cfg_mcf_rx_check_opcode_lfc;
+logic [15:0] cfg_mcf_rx_opcode_pfc;
+logic cfg_mcf_rx_check_opcode_pfc;
+logic cfg_mcf_rx_forward;
+logic cfg_mcf_rx_enable;
+logic [47:0] cfg_tx_lfc_eth_dst;
+logic [47:0] cfg_tx_lfc_eth_src;
+logic [15:0] cfg_tx_lfc_eth_type;
+logic [15:0] cfg_tx_lfc_opcode;
+logic cfg_tx_lfc_en;
+logic [15:0] cfg_tx_lfc_quanta;
+logic [15:0] cfg_tx_lfc_refresh;
+logic [47:0] cfg_tx_pfc_eth_dst;
+logic [47:0] cfg_tx_pfc_eth_src;
+logic [15:0] cfg_tx_pfc_eth_type;
+logic [15:0] cfg_tx_pfc_opcode;
+logic cfg_tx_pfc_en;
+logic [15:0] cfg_tx_pfc_quanta[8];
+logic [15:0] cfg_tx_pfc_refresh[8];
+logic [15:0] cfg_rx_lfc_opcode;
+logic cfg_rx_lfc_en;
+logic [15:0] cfg_rx_pfc_opcode;
+logic cfg_rx_pfc_en;
+
+taxi_eth_mac_1g #(
+    .DATA_W(DATA_W),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W),
+    .PFC_EN(PFC_EN),
+    .PAUSE_EN(PAUSE_EN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR)
+)
+uut (
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * GMII interface
+     */
+    .gmii_rxd(gmii_rxd),
+    .gmii_rx_dv(gmii_rx_dv),
+    .gmii_rx_er(gmii_rx_er),
+    .gmii_txd(gmii_txd),
+    .gmii_tx_en(gmii_tx_en),
+    .gmii_tx_er(gmii_tx_er),
+
+    /*
+     * PTP
+     */
+    .tx_ptp_ts(tx_ptp_ts),
+    .rx_ptp_ts(rx_ptp_ts),
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req(tx_lfc_req),
+    .tx_lfc_resend(tx_lfc_resend),
+    .rx_lfc_en(rx_lfc_en),
+    .rx_lfc_req(rx_lfc_req),
+    .rx_lfc_ack(rx_lfc_ack),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req(tx_pfc_req),
+    .tx_pfc_resend(tx_pfc_resend),
+    .rx_pfc_en(rx_pfc_en),
+    .rx_pfc_req(rx_pfc_req),
+    .rx_pfc_ack(rx_pfc_ack),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en(tx_lfc_pause_en),
+    .tx_pause_req(tx_pause_req),
+    .tx_pause_ack(tx_pause_ack),
+
+    /*
+     * Control
+     */
+    .rx_clk_enable(rx_clk_enable),
+    .tx_clk_enable(tx_clk_enable),
+    .rx_mii_select(rx_mii_select),
+    .tx_mii_select(tx_mii_select),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow),
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble),
+    .stat_rx_fifo_drop(stat_rx_fifo_drop),
+    .stat_tx_mcf(stat_tx_mcf),
+    .stat_rx_mcf(stat_rx_mcf),
+    .stat_tx_lfc_pkt(stat_tx_lfc_pkt),
+    .stat_tx_lfc_xon(stat_tx_lfc_xon),
+    .stat_tx_lfc_xoff(stat_tx_lfc_xoff),
+    .stat_tx_lfc_paused(stat_tx_lfc_paused),
+    .stat_tx_pfc_pkt(stat_tx_pfc_pkt),
+    .stat_tx_pfc_xon(stat_tx_pfc_xon),
+    .stat_tx_pfc_xoff(stat_tx_pfc_xoff),
+    .stat_tx_pfc_paused(stat_tx_pfc_paused),
+    .stat_rx_lfc_pkt(stat_rx_lfc_pkt),
+    .stat_rx_lfc_xon(stat_rx_lfc_xon),
+    .stat_rx_lfc_xoff(stat_rx_lfc_xoff),
+    .stat_rx_lfc_paused(stat_rx_lfc_paused),
+    .stat_rx_pfc_pkt(stat_rx_pfc_pkt),
+    .stat_rx_pfc_xon(stat_rx_pfc_xon),
+    .stat_rx_pfc_xoff(stat_rx_pfc_xoff),
+    .stat_rx_pfc_paused(stat_rx_pfc_paused),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+    .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
+    .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
+    .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
+    .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
+    .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
+    .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
+    .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
+    .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
+    .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
+    .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
+    .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
+    .cfg_mcf_rx_forward(cfg_mcf_rx_forward),
+    .cfg_mcf_rx_enable(cfg_mcf_rx_enable),
+    .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
+    .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
+    .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
+    .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
+    .cfg_tx_lfc_en(cfg_tx_lfc_en),
+    .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
+    .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
+    .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
+    .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
+    .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
+    .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
+    .cfg_tx_pfc_en(cfg_tx_pfc_en),
+    .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
+    .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
+    .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
+    .cfg_rx_lfc_en(cfg_rx_lfc_en),
+    .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
+    .cfg_rx_pfc_en(cfg_rx_pfc_en)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_1g_fifo/Makefile

@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_1g_fifo
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 8
+export PARAM_AXIS_DATA_W := 8
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_TX_TAG_W := 16
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+export PARAM_TX_FIFO_DEPTH := 16384
+export PARAM_TX_FIFO_RAM_PIPELINE := 1
+export PARAM_TX_FRAME_FIFO := 1
+export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
+export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
+export PARAM_TX_DROP_WHEN_FULL := 0
+export PARAM_TX_CPL_FIFO_DEPTH := 64
+export PARAM_RX_FIFO_DEPTH := 16384
+export PARAM_RX_FIFO_RAM_PIPELINE := 1
+export PARAM_RX_FRAME_FIFO := 1
+export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
+export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.py

@@ -0,0 +1,295 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        self._enable_generator_rx = None
+        self._enable_generator_tx = None
+        self._enable_cr_rx = None
+        self._enable_cr_tx = None
+
+        cocotb.start_soon(Clock(dut.logic_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.rx_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.tx_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
+
+        self.gmii_source = GmiiSource(dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv,
+            dut.rx_clk, dut.rx_rst, dut.rx_clk_enable, dut.rx_mii_select)
+        self.gmii_sink = GmiiSink(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en,
+            dut.tx_clk, dut.tx_rst, dut.tx_clk_enable, dut.tx_mii_select)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+        dut.rx_clk_enable.setimmediatevalue(1)
+        dut.tx_clk_enable.setimmediatevalue(1)
+        dut.rx_mii_select.setimmediatevalue(0)
+        dut.tx_mii_select.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.logic_rst.setimmediatevalue(0)
+        self.dut.rx_rst.setimmediatevalue(0)
+        self.dut.tx_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        for k in range(10):
+            await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
+        self.dut.stat_rst.value = 1
+        for k in range(10):
+            await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
+        self.dut.stat_rst.value = 0
+        for k in range(10):
+            await RisingEdge(self.dut.logic_clk)
+
+    def set_enable_generator_rx(self, generator=None):
+        if self._enable_cr_rx is not None:
+            self._enable_cr_rx.kill()
+            self._enable_cr_rx = None
+
+        self._enable_generator_rx = generator
+
+        if self._enable_generator_rx is not None:
+            self._enable_cr_rx = cocotb.start_soon(self._run_enable_rx())
+
+    def set_enable_generator_tx(self, generator=None):
+        if self._enable_cr_tx is not None:
+            self._enable_cr_tx.kill()
+            self._enable_cr_tx = None
+
+        self._enable_generator_tx = generator
+
+        if self._enable_generator_tx is not None:
+            self._enable_cr_tx = cocotb.start_soon(self._run_enable_tx())
+
+    def clear_enable_generator_rx(self):
+        self.set_enable_generator_rx(None)
+
+    def clear_enable_generator_tx(self):
+        self.set_enable_generator_tx(None)
+
+    async def _run_enable_rx(self):
+        for val in self._enable_generator_rx:
+            self.dut.rx_clk_enable.value = val
+            await RisingEdge(self.dut.rx_clk)
+
+    async def _run_enable_tx(self):
+        for val in self._enable_generator_tx:
+            self.dut.tx_clk_enable.value = val
+            await RisingEdge(self.dut.tx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data)
+        await tb.gmii_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+
+        assert rx_frame.tdata == test_data
+        assert rx_frame.tuser == 0
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enable_gen=None, mii_sel=False):
+
+    tb = TB(dut)
+
+    tb.gmii_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.rx_mii_select.value = mii_sel
+    tb.dut.tx_mii_select.value = mii_sel
+
+    if enable_gen is not None:
+        tb.set_enable_generator_rx(enable_gen())
+        tb.set_enable_generator_tx(enable_gen())
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(test_data)
+
+    for test_data in test_frames:
+        rx_frame = await tb.gmii_sink.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    assert tb.gmii_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.add_option("enable_gen", [None, cycle_en])
+        factory.add_option("mii_sel", [False, True])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_eth_mac_1g_fifo(request):
+    dut = "taxi_eth_mac_1g_fifo"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 8
+    parameters['AXIS_DATA_W'] = 8
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['TX_TAG_W'] = 16
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+    parameters['TX_FIFO_DEPTH'] = 16384
+    parameters['TX_FIFO_RAM_PIPELINE'] = 1
+    parameters['TX_FRAME_FIFO'] = 1
+    parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
+    parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
+    parameters['TX_DROP_WHEN_FULL'] = 0
+    parameters['TX_CPL_FIFO_DEPTH'] = 64
+    parameters['RX_FIFO_DEPTH'] = 16384
+    parameters['RX_FIFO_RAM_PIPELINE'] = 1
+    parameters['RX_FRAME_FIFO'] = 1
+    parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
+    parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
+    parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv

@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 1G Ethernet MAC with TX and RX FIFOs testbench
+ */
+module test_taxi_eth_mac_1g_fifo #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 8,
+    parameter AXIS_DATA_W = 8,
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter TX_TAG_W = 16,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC",
+    parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_RAM_PIPELINE = 1,
+    parameter logic TX_FRAME_FIFO = 1'b1,
+    parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
+    parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
+    parameter logic TX_DROP_WHEN_FULL = 1'b0,
+    parameter TX_CPL_FIFO_DEPTH = 64,
+    parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_RAM_PIPELINE = 1,
+    parameter logic RX_FRAME_FIFO = 1'b1,
+    parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
+    parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
+    parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam TX_USER_W = 1;
+localparam RX_USER_W = 1;
+
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+logic logic_clk;
+logic logic_rst;
+
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic [DATA_W-1:0] gmii_rxd;
+logic gmii_rx_dv;
+logic gmii_rx_er;
+logic [DATA_W-1:0] gmii_txd;
+logic gmii_tx_en;
+logic gmii_tx_er;
+
+logic rx_clk_enable;
+logic tx_clk_enable;
+logic rx_mii_select;
+logic tx_mii_select;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_error_underflow;
+logic tx_fifo_overflow;
+logic tx_fifo_bad_frame;
+logic tx_fifo_good_frame;
+logic rx_error_bad_frame;
+logic rx_error_bad_fcs;
+logic rx_fifo_overflow;
+logic rx_fifo_bad_frame;
+logic rx_fifo_good_frame;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+taxi_eth_mac_1g_fifo #(
+    .DATA_W(DATA_W),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR),
+    .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
+    .TX_FRAME_FIFO(TX_FRAME_FIFO),
+    .TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
+    .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
+    .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
+    .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
+    .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
+    .RX_FRAME_FIFO(RX_FRAME_FIFO),
+    .RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
+    .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
+    .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
+)
+uut (
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+    .logic_clk(logic_clk),
+    .logic_rst(logic_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * GMII interface
+     */
+    .gmii_rxd(gmii_rxd),
+    .gmii_rx_dv(gmii_rx_dv),
+    .gmii_rx_er(gmii_rx_er),
+    .gmii_txd(gmii_txd),
+    .gmii_tx_en(gmii_tx_en),
+    .gmii_tx_er(gmii_tx_er),
+
+    /*
+     * Control
+     */
+    .rx_clk_enable(rx_clk_enable),
+    .tx_clk_enable(tx_clk_enable),
+    .rx_mii_select(rx_mii_select),
+    .tx_mii_select(tx_mii_select),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(tx_error_underflow),
+    .tx_fifo_overflow(tx_fifo_overflow),
+    .tx_fifo_bad_frame(tx_fifo_bad_frame),
+    .tx_fifo_good_frame(tx_fifo_good_frame),
+    .rx_error_bad_frame(rx_error_bad_frame),
+    .rx_error_bad_fcs(rx_error_bad_fcs),
+    .rx_fifo_overflow(rx_fifo_overflow),
+    .rx_fifo_bad_frame(rx_fifo_bad_frame),
+    .rx_fifo_good_frame(rx_fifo_good_frame),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_1g_gmii/Makefile

@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_1g_gmii
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := 1
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtex7\""
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_W := 96
+export PARAM_TX_TAG_W := 16
+export PARAM_PFC_EN := 1
+export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.py

@@ -0,0 +1,717 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import struct
+import os
+
+from scapy.layers.l2 import Ether
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, GmiiPhy, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.gtx_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
+
+        self.gmii_phy = GmiiPhy(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en, dut.mii_tx_clk, dut.gmii_tx_clk,
+            dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv, dut.gmii_rx_clk, speed=speed)
+
+        # the UUT forwards tx_clk/rx_clk, which can cause problems in cocotb
+        if speed == 1000e6:
+            self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.gtx_clk, dut.tx_rst)
+            self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.gtx_clk, dut.tx_rst)
+        else:
+            self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.mii_tx_clk, dut.tx_rst)
+            self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.mii_tx_clk, dut.tx_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.gmii_rx_clk, dut.rx_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
+        self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
+
+        dut.tx_lfc_req.setimmediatevalue(0)
+        dut.tx_lfc_resend.setimmediatevalue(0)
+        dut.rx_lfc_en.setimmediatevalue(0)
+        dut.rx_lfc_ack.setimmediatevalue(0)
+
+        dut.tx_pfc_req.setimmediatevalue(0)
+        dut.tx_pfc_resend.setimmediatevalue(0)
+        dut.rx_pfc_en.setimmediatevalue(0)
+        dut.rx_pfc_ack.setimmediatevalue(0)
+
+        dut.tx_lfc_pause_en.setimmediatevalue(0)
+        dut.tx_pause_req.setimmediatevalue(0)
+
+        dut.stat_rx_fifo_drop.setimmediatevalue(0)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_type.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_forward.setimmediatevalue(0)
+        dut.cfg_mcf_rx_enable.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_lfc_en.setimmediatevalue(0)
+        dut.cfg_tx_lfc_quanta.setimmediatevalue(0)
+        dut.cfg_tx_lfc_refresh.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_pfc_en.setimmediatevalue(0)
+        dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
+        dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
+        dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_lfc_en.setimmediatevalue(0)
+        dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_pfc_en.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.gtx_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+        self.dut.gtx_rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+        self.dut.gtx_rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.gmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    if speed == 10e6:
+        assert dut.link_speed == 0
+    elif speed == 100e6:
+        assert dut.link_speed == 1
+    else:
+        assert dut.link_speed == 2
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.gmii_phy.rx.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        if speed == 10e6:
+            assert abs(ptp_ts_ns - tx_frame_sfd_ns - 800) < 0.01
+        elif speed == 100e6:
+            assert abs(ptp_ts_ns - tx_frame_sfd_ns - 80) < 0.01
+        else:
+            assert abs(ptp_ts_ns - tx_frame_sfd_ns - 16) < 0.01
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.gmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    if speed == 10e6:
+        assert dut.link_speed == 0
+    elif speed == 100e6:
+        assert dut.link_speed == 1
+    else:
+        assert dut.link_speed == 2
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(test_data)
+
+    for test_data in test_frames:
+        rx_frame = await tb.gmii_phy.tx.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+        if speed == 10e6:
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - 800) < 0.01
+        elif speed == 100e6:
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - 80) < 0.01
+        else:
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - 12) < 0.01
+
+    assert tb.gmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_underrun(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.gmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.axis_source.send(test_frame)
+
+    for k in range(200 if speed != 1000e6 else 100):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = True
+
+    for k in range(10):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.gmii_phy.tx.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.gmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_error(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.gmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.axis_source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.gmii_phy.tx.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.gmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_lfc(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.gmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    dut.tx_lfc_req.value = 0
+    dut.tx_lfc_resend.value = 0
+    dut.rx_lfc_en.value = 1
+    dut.rx_lfc_ack.value = 0
+
+    dut.tx_lfc_pause_en.value = 1
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_lfc_eth_type.value = 0x8808
+    dut.cfg_tx_lfc_opcode.value = 0x0001
+    dut.cfg_tx_lfc_en.value = 1
+    dut.cfg_tx_lfc_quanta.value = 0xFFFF
+    dut.cfg_tx_lfc_refresh.value = 0x7F00
+
+    dut.cfg_rx_lfc_opcode.value = 0x0001
+    dut.cfg_rx_lfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 128
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+        await tb.gmii_phy.rx.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+            await tb.gmii_phy.rx.send(test_frame)
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while not dut.rx_lfc_req.value.integer:
+        await RisingEdge(dut.tx_clk)
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_lfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.gmii_phy.tx.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_lfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_lfc_cnt == 4
+
+    assert tb.axis_sink.empty()
+    assert tb.gmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_pfc(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.gmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+    dut.tx_pfc_resend.value = 0
+    dut.rx_pfc_en.value = 0xff
+    dut.rx_pfc_ack.value = 0x00
+
+    dut.tx_lfc_pause_en.value = 0
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_pfc_eth_type.value = 0x8808
+    dut.cfg_tx_pfc_opcode.value = 0x0101
+    dut.cfg_tx_pfc_en.value = 1
+    dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
+    dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
+
+    dut.cfg_rx_pfc_opcode.value = 0x0101
+    dut.cfg_rx_pfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 128
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+        await tb.gmii_phy.rx.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+            await tb.gmii_phy.rx.send(test_frame)
+
+    dut.rx_pfc_ack.value = 0xff
+
+    for i in range(8):
+        for k in range(500):
+            await RisingEdge(dut.tx_clk)
+
+        dut.tx_pfc_req.value = 0xff >> (7-i)
+
+    for k in range(500):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_pfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.gmii_phy.tx.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_pfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_pfc_cnt > 2 and tx_pfc_cnt <= 9
+
+    assert tb.axis_sink.empty()
+    assert tb.gmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.add_option("speed", [1000e6, 100e6, 10e6])
+        factory.generate_tests()
+
+    for test in [run_test_tx_underrun, run_test_tx_error]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.add_option("speed", [1000e6, 100e6, 10e6])
+        factory.generate_tests()
+
+    if cocotb.top.PFC_EN.value:
+        for test in [run_test_lfc, run_test_pfc]:
+            factory = TestFactory(test)
+            factory.add_option("ifg", [12])
+            factory.add_option("speed", [1000e6, 100e6, 10e6])
+            factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("pfc_en", [1, 0])
+def test_taxi_eth_mac_1g_gmii(request, pfc_en):
+    dut = "taxi_eth_mac_1g_gmii"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = 1
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtex7\""
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_W'] = 96
+    parameters['TX_TAG_W'] = 16
+    parameters['PFC_EN'] = pfc_en
+    parameters['PAUSE_EN'] = parameters['PFC_EN']
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv

@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 1G Ethernet MAC with GMII interface testbench
+ */
+module test_taxi_eth_mac_1g_gmii #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter logic SIM = 1'b1,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter PTP_TS_W = 96,
+    parameter TX_TAG_W = 16,
+    parameter logic PFC_EN = 1'b0,
+    parameter logic PAUSE_EN = PFC_EN,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam DATA_W = 8;
+localparam TX_USER_W = 1;
+localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic gtx_clk;
+logic gtx_rst;
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic gmii_rx_clk;
+logic [7:0] gmii_rxd;
+logic gmii_rx_dv;
+logic gmii_rx_er;
+logic mii_tx_clk;
+logic gmii_tx_clk;
+logic [7:0] gmii_txd;
+logic gmii_tx_en;
+logic gmii_tx_er;
+
+logic [PTP_TS_W-1:0] tx_ptp_ts;
+logic [PTP_TS_W-1:0] rx_ptp_ts;
+
+logic tx_lfc_req;
+logic tx_lfc_resend;
+logic rx_lfc_en;
+logic rx_lfc_req;
+logic rx_lfc_ack;
+
+logic [7:0] tx_pfc_req;
+logic tx_pfc_resend;
+logic [7:0] rx_pfc_en;
+logic [7:0] rx_pfc_req;
+logic [7:0] rx_pfc_ack;
+
+logic tx_lfc_pause_en;
+logic tx_pause_req;
+logic tx_pause_ack;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_start_packet;
+logic stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+logic rx_start_packet;
+logic stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+logic stat_rx_fifo_drop;
+logic [1:0] link_speed;
+logic stat_tx_mcf;
+logic stat_rx_mcf;
+logic stat_tx_lfc_pkt;
+logic stat_tx_lfc_xon;
+logic stat_tx_lfc_xoff;
+logic stat_tx_lfc_paused;
+logic stat_tx_pfc_pkt;
+logic [7:0] stat_tx_pfc_xon;
+logic [7:0] stat_tx_pfc_xoff;
+logic [7:0] stat_tx_pfc_paused;
+logic stat_rx_lfc_pkt;
+logic stat_rx_lfc_xon;
+logic stat_rx_lfc_xoff;
+logic stat_rx_lfc_paused;
+logic stat_rx_pfc_pkt;
+logic [7:0] stat_rx_pfc_xon;
+logic [7:0] stat_rx_pfc_xoff;
+logic [7:0] stat_rx_pfc_paused;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+logic [47:0] cfg_mcf_rx_eth_dst_mcast;
+logic cfg_mcf_rx_check_eth_dst_mcast;
+logic [47:0] cfg_mcf_rx_eth_dst_ucast;
+logic cfg_mcf_rx_check_eth_dst_ucast;
+logic [47:0] cfg_mcf_rx_eth_src;
+logic cfg_mcf_rx_check_eth_src;
+logic [15:0] cfg_mcf_rx_eth_type;
+logic [15:0] cfg_mcf_rx_opcode_lfc;
+logic cfg_mcf_rx_check_opcode_lfc;
+logic [15:0] cfg_mcf_rx_opcode_pfc;
+logic cfg_mcf_rx_check_opcode_pfc;
+logic cfg_mcf_rx_forward;
+logic cfg_mcf_rx_enable;
+logic [47:0] cfg_tx_lfc_eth_dst;
+logic [47:0] cfg_tx_lfc_eth_src;
+logic [15:0] cfg_tx_lfc_eth_type;
+logic [15:0] cfg_tx_lfc_opcode;
+logic cfg_tx_lfc_en;
+logic [15:0] cfg_tx_lfc_quanta;
+logic [15:0] cfg_tx_lfc_refresh;
+logic [47:0] cfg_tx_pfc_eth_dst;
+logic [47:0] cfg_tx_pfc_eth_src;
+logic [15:0] cfg_tx_pfc_eth_type;
+logic [15:0] cfg_tx_pfc_opcode;
+logic cfg_tx_pfc_en;
+logic [15:0] cfg_tx_pfc_quanta[8];
+logic [15:0] cfg_tx_pfc_refresh[8];
+logic [15:0] cfg_rx_lfc_opcode;
+logic cfg_rx_lfc_en;
+logic [15:0] cfg_rx_pfc_opcode;
+logic cfg_rx_pfc_en;
+
+taxi_eth_mac_1g_gmii #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W),
+    .PFC_EN(PFC_EN),
+    .PAUSE_EN(PAUSE_EN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR)
+)
+uut (
+    .gtx_clk(gtx_clk),
+    .gtx_rst(gtx_rst),
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * GMII interface
+     */
+    .gmii_rx_clk(gmii_rx_clk),
+    .gmii_rxd(gmii_rxd),
+    .gmii_rx_dv(gmii_rx_dv),
+    .gmii_rx_er(gmii_rx_er),
+    .mii_tx_clk(mii_tx_clk),
+    .gmii_tx_clk(gmii_tx_clk),
+    .gmii_txd(gmii_txd),
+    .gmii_tx_en(gmii_tx_en),
+    .gmii_tx_er(gmii_tx_er),
+
+    /*
+     * PTP
+     */
+    .tx_ptp_ts(tx_ptp_ts),
+    .rx_ptp_ts(rx_ptp_ts),
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req(tx_lfc_req),
+    .tx_lfc_resend(tx_lfc_resend),
+    .rx_lfc_en(rx_lfc_en),
+    .rx_lfc_req(rx_lfc_req),
+    .rx_lfc_ack(rx_lfc_ack),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req(tx_pfc_req),
+    .tx_pfc_resend(tx_pfc_resend),
+    .rx_pfc_en(rx_pfc_en),
+    .rx_pfc_req(rx_pfc_req),
+    .rx_pfc_ack(rx_pfc_ack),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en(tx_lfc_pause_en),
+    .tx_pause_req(tx_pause_req),
+    .tx_pause_ack(tx_pause_ack),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow),
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble),
+    .stat_rx_fifo_drop(stat_rx_fifo_drop),
+    .link_speed(link_speed),
+    .stat_tx_mcf(stat_tx_mcf),
+    .stat_rx_mcf(stat_rx_mcf),
+    .stat_tx_lfc_pkt(stat_tx_lfc_pkt),
+    .stat_tx_lfc_xon(stat_tx_lfc_xon),
+    .stat_tx_lfc_xoff(stat_tx_lfc_xoff),
+    .stat_tx_lfc_paused(stat_tx_lfc_paused),
+    .stat_tx_pfc_pkt(stat_tx_pfc_pkt),
+    .stat_tx_pfc_xon(stat_tx_pfc_xon),
+    .stat_tx_pfc_xoff(stat_tx_pfc_xoff),
+    .stat_tx_pfc_paused(stat_tx_pfc_paused),
+    .stat_rx_lfc_pkt(stat_rx_lfc_pkt),
+    .stat_rx_lfc_xon(stat_rx_lfc_xon),
+    .stat_rx_lfc_xoff(stat_rx_lfc_xoff),
+    .stat_rx_lfc_paused(stat_rx_lfc_paused),
+    .stat_rx_pfc_pkt(stat_rx_pfc_pkt),
+    .stat_rx_pfc_xon(stat_rx_pfc_xon),
+    .stat_rx_pfc_xoff(stat_rx_pfc_xoff),
+    .stat_rx_pfc_paused(stat_rx_pfc_paused),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+    .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
+    .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
+    .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
+    .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
+    .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
+    .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
+    .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
+    .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
+    .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
+    .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
+    .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
+    .cfg_mcf_rx_forward(cfg_mcf_rx_forward),
+    .cfg_mcf_rx_enable(cfg_mcf_rx_enable),
+    .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
+    .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
+    .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
+    .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
+    .cfg_tx_lfc_en(cfg_tx_lfc_en),
+    .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
+    .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
+    .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
+    .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
+    .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
+    .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
+    .cfg_tx_pfc_en(cfg_tx_pfc_en),
+    .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
+    .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
+    .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
+    .cfg_rx_lfc_en(cfg_rx_lfc_en),
+    .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
+    .cfg_rx_pfc_en(cfg_rx_pfc_en)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_1g_gmii_fifo/Makefile

@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_1g_gmii_fifo
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := 1
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtex7\""
+export PARAM_AXIS_DATA_W := 8
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_TX_TAG_W := 16
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+export PARAM_TX_FIFO_DEPTH := 16384
+export PARAM_TX_FIFO_RAM_PIPELINE := 1
+export PARAM_TX_FRAME_FIFO := 1
+export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
+export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
+export PARAM_TX_DROP_WHEN_FULL := 0
+export PARAM_TX_CPL_FIFO_DEPTH := 64
+export PARAM_RX_FIFO_DEPTH := 16384
+export PARAM_RX_FIFO_RAM_PIPELINE := 1
+export PARAM_RX_FRAME_FIFO := 1
+export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
+export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.py

@@ -0,0 +1,250 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, GmiiPhy
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.gtx_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.logic_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
+
+        self.gmii_phy = GmiiPhy(dut.gmii_txd, dut.gmii_tx_er, dut.gmii_tx_en, dut.mii_tx_clk, dut.gmii_tx_clk,
+            dut.gmii_rxd, dut.gmii_rx_er, dut.gmii_rx_dv, dut.gmii_rx_clk, speed=speed)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.gtx_rst.setimmediatevalue(0)
+        self.dut.logic_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.gtx_clk)
+        await RisingEdge(self.dut.gtx_clk)
+        self.dut.gtx_rst.value = 1
+        self.dut.logic_rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.gtx_clk)
+        await RisingEdge(self.dut.gtx_clk)
+        self.dut.gtx_rst.value = 0
+        self.dut.logic_rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.gtx_clk)
+        await RisingEdge(self.dut.gtx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.gmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.gmii_rx_clk)
+
+    if speed == 10e6:
+        assert dut.link_speed == 0
+    elif speed == 100e6:
+        assert dut.link_speed == 1
+    else:
+        assert dut.link_speed == 2
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data)
+        await tb.gmii_phy.rx.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+
+        assert rx_frame.tdata == test_data
+        assert rx_frame.tuser == 0
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.gmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.gmii_rx_clk)
+
+    if speed == 10e6:
+        assert dut.link_speed == 0
+    elif speed == 100e6:
+        assert dut.link_speed == 1
+    else:
+        assert dut.link_speed == 2
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(test_data)
+
+    for test_data in test_frames:
+        rx_frame = await tb.gmii_phy.tx.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    assert tb.gmii_phy.tx.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.add_option("speed", [1000e6, 100e6, 10e6])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_eth_mac_1g_gmii_fifo(request):
+    dut = "taxi_eth_mac_1g_gmii_fifo"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = 1
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtex7\""
+    parameters['AXIS_DATA_W'] = 8
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['TX_TAG_W'] = 16
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+    parameters['TX_FIFO_DEPTH'] = 16384
+    parameters['TX_FIFO_RAM_PIPELINE'] = 1
+    parameters['TX_FRAME_FIFO'] = 1
+    parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
+    parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
+    parameters['TX_DROP_WHEN_FULL'] = 0
+    parameters['TX_CPL_FIFO_DEPTH'] = 64
+    parameters['RX_FIFO_DEPTH'] = 16384
+    parameters['RX_FIFO_RAM_PIPELINE'] = 1
+    parameters['RX_FRAME_FIFO'] = 1
+    parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
+    parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
+    parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv

@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 1G Ethernet MAC with GMII interface and TX and RX FIFOs testbench
+ */
+module test_taxi_eth_mac_1g_gmii_fifo #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter logic SIM = 1'b1,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
+    parameter AXIS_DATA_W = 8,
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter TX_TAG_W = 16,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC",
+    parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_RAM_PIPELINE = 1,
+    parameter logic TX_FRAME_FIFO = 1'b1,
+    parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
+    parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
+    parameter logic TX_DROP_WHEN_FULL = 1'b0,
+    parameter TX_CPL_FIFO_DEPTH = 64,
+    parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_RAM_PIPELINE = 1,
+    parameter logic RX_FRAME_FIFO = 1'b1,
+    parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
+    parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
+    parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam DATA_W = 8;
+localparam TX_USER_W = 1;
+localparam RX_USER_W = 1;
+
+logic gtx_clk;
+logic gtx_rst;
+logic logic_clk;
+logic logic_rst;
+
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic gmii_rx_clk;
+logic [7:0] gmii_rxd;
+logic gmii_rx_dv;
+logic gmii_rx_er;
+logic mii_tx_clk;
+logic gmii_tx_clk;
+logic [7:0] gmii_txd;
+logic gmii_tx_en;
+logic gmii_tx_er;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_error_underflow;
+logic tx_fifo_overflow;
+logic tx_fifo_bad_frame;
+logic tx_fifo_good_frame;
+logic rx_error_bad_frame;
+logic rx_error_bad_fcs;
+logic rx_fifo_overflow;
+logic rx_fifo_bad_frame;
+logic rx_fifo_good_frame;
+logic [1:0] link_speed;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+taxi_eth_mac_1g_gmii_fifo #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR),
+    .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
+    .TX_FRAME_FIFO(TX_FRAME_FIFO),
+    .TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
+    .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
+    .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
+    .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
+    .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
+    .RX_FRAME_FIFO(RX_FRAME_FIFO),
+    .RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
+    .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
+    .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
+)
+uut (
+    .gtx_clk(gtx_clk),
+    .gtx_rst(gtx_rst),
+    .logic_clk(logic_clk),
+    .logic_rst(logic_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * GMII interface
+     */
+    .gmii_rx_clk(gmii_rx_clk),
+    .gmii_rxd(gmii_rxd),
+    .gmii_rx_dv(gmii_rx_dv),
+    .gmii_rx_er(gmii_rx_er),
+    .mii_tx_clk(mii_tx_clk),
+    .gmii_tx_clk(gmii_tx_clk),
+    .gmii_txd(gmii_txd),
+    .gmii_tx_en(gmii_tx_en),
+    .gmii_tx_er(gmii_tx_er),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(tx_error_underflow),
+    .tx_fifo_overflow(tx_fifo_overflow),
+    .tx_fifo_bad_frame(tx_fifo_bad_frame),
+    .tx_fifo_good_frame(tx_fifo_good_frame),
+    .rx_error_bad_frame(rx_error_bad_frame),
+    .rx_error_bad_fcs(rx_error_bad_fcs),
+    .rx_fifo_overflow(rx_fifo_overflow),
+    .rx_fifo_bad_frame(rx_fifo_bad_frame),
+    .rx_fifo_good_frame(rx_fifo_good_frame),
+    .link_speed(link_speed),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_1g_rgmii/Makefile

@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_1g_rgmii
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := 1
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtex7\""
+export PARAM_USE_CLK90 := 1
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_W := 96
+export PARAM_TX_TAG_W := 16
+export PARAM_PFC_EN := 1
+export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.py

@@ -0,0 +1,722 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import struct
+import os
+
+from scapy.layers.l2 import Ether
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, RgmiiPhy, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
+
+        self.rgmii_phy = RgmiiPhy(dut.rgmii_txd, dut.rgmii_tx_ctl, dut.rgmii_tx_clk,
+            dut.rgmii_rxd, dut.rgmii_rx_ctl, dut.rgmii_rx_clk, speed=speed)
+
+        # the UUT forwards tx_clk/rx_clk, which can cause problems in cocotb
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.gtx_clk, dut.tx_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.gtx_clk, dut.tx_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.rx_clk, dut.rx_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
+        self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
+
+        dut.tx_lfc_req.setimmediatevalue(0)
+        dut.tx_lfc_resend.setimmediatevalue(0)
+        dut.rx_lfc_en.setimmediatevalue(0)
+        dut.rx_lfc_ack.setimmediatevalue(0)
+
+        dut.tx_pfc_req.setimmediatevalue(0)
+        dut.tx_pfc_resend.setimmediatevalue(0)
+        dut.rx_pfc_en.setimmediatevalue(0)
+        dut.rx_pfc_ack.setimmediatevalue(0)
+
+        dut.tx_lfc_pause_en.setimmediatevalue(0)
+        dut.tx_pause_req.setimmediatevalue(0)
+
+        dut.stat_rx_fifo_drop.setimmediatevalue(0)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_type.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_forward.setimmediatevalue(0)
+        dut.cfg_mcf_rx_enable.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_lfc_en.setimmediatevalue(0)
+        dut.cfg_tx_lfc_quanta.setimmediatevalue(0)
+        dut.cfg_tx_lfc_refresh.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_pfc_en.setimmediatevalue(0)
+        dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
+        dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
+        dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_lfc_en.setimmediatevalue(0)
+        dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_pfc_en.setimmediatevalue(0)
+
+        dut.gtx_clk.setimmediatevalue(0)
+        dut.gtx_clk90.setimmediatevalue(0)
+
+        cocotb.start_soon(self._run_gtx_clk())
+
+    async def reset(self):
+        self.dut.gtx_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.gtx_clk)
+        await RisingEdge(self.dut.gtx_clk)
+        self.dut.gtx_rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.gtx_clk)
+        await RisingEdge(self.dut.gtx_clk)
+        self.dut.gtx_rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.gtx_clk)
+        await RisingEdge(self.dut.gtx_clk)
+
+    async def _run_gtx_clk(self):
+        t = Timer(2, 'ns')
+        while True:
+            self.dut.gtx_clk.value = 1
+            await t
+            self.dut.gtx_clk90.value = 1
+            await t
+            self.dut.gtx_clk.value = 0
+            await t
+            self.dut.gtx_clk90.value = 0
+            await t
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.rgmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    if speed == 10e6:
+        assert dut.link_speed == 0
+    elif speed == 100e6:
+        assert dut.link_speed == 1
+    else:
+        assert dut.link_speed == 2
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.rgmii_phy.rx.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        if speed == 10e6:
+            assert abs(ptp_ts_ns - tx_frame_sfd_ns - 1200) < 0.01
+        elif speed == 100e6:
+            assert abs(ptp_ts_ns - tx_frame_sfd_ns - 120) < 0.01
+        else:
+            assert abs(ptp_ts_ns - tx_frame_sfd_ns - 24) < 0.01
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.rgmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    if speed == 10e6:
+        assert dut.link_speed == 0
+    elif speed == 100e6:
+        assert dut.link_speed == 1
+    else:
+        assert dut.link_speed == 2
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(test_data)
+
+    for test_data in test_frames:
+        rx_frame = await tb.rgmii_phy.tx.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    assert tb.rgmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_underrun(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.rgmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.axis_source.send(test_frame)
+
+    for k in range(200 if speed != 1000e6 else 100):
+        while True:
+            await RisingEdge(dut.tx_clk)
+            if dut.uut.mac_gmii_tx_clk_en.value.integer:
+                break
+
+    tb.axis_source.pause = True
+
+    for k in range(10):
+        while True:
+            await RisingEdge(dut.tx_clk)
+            if dut.uut.mac_gmii_tx_clk_en.value.integer:
+                break
+
+    tb.axis_source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.rgmii_phy.tx.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.rgmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_error(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.rgmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.axis_source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.rgmii_phy.tx.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.rgmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_lfc(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.rgmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    dut.tx_lfc_req.value = 0
+    dut.tx_lfc_resend.value = 0
+    dut.rx_lfc_en.value = 1
+    dut.rx_lfc_ack.value = 0
+
+    dut.tx_lfc_pause_en.value = 1
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_lfc_eth_type.value = 0x8808
+    dut.cfg_tx_lfc_opcode.value = 0x0001
+    dut.cfg_tx_lfc_en.value = 1
+    dut.cfg_tx_lfc_quanta.value = 0xFFFF
+    dut.cfg_tx_lfc_refresh.value = 0x7F00
+
+    dut.cfg_rx_lfc_opcode.value = 0x0001
+    dut.cfg_rx_lfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 128
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+        await tb.rgmii_phy.rx.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+            await tb.rgmii_phy.rx.send(test_frame)
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while not dut.rx_lfc_req.value.integer:
+        await RisingEdge(dut.tx_clk)
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_lfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.rgmii_phy.tx.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_lfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_lfc_cnt == 4
+
+    assert tb.axis_sink.empty()
+    assert tb.rgmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_pfc(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.rgmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+    dut.tx_pfc_resend.value = 0
+    dut.rx_pfc_en.value = 0xff
+    dut.rx_pfc_ack.value = 0x00
+
+    dut.tx_lfc_pause_en.value = 0
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_pfc_eth_type.value = 0x8808
+    dut.cfg_tx_pfc_opcode.value = 0x0101
+    dut.cfg_tx_pfc_en.value = 1
+    dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
+    dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
+
+    dut.cfg_rx_pfc_opcode.value = 0x0101
+    dut.cfg_rx_pfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 128
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+        await tb.rgmii_phy.rx.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+            await tb.rgmii_phy.rx.send(test_frame)
+
+    dut.rx_pfc_ack.value = 0xff
+
+    for i in range(8):
+        for k in range(500):
+            await RisingEdge(dut.rx_clk)
+
+        await RisingEdge(dut.tx_clk)
+        dut.tx_pfc_req.value = 0xff >> (7-i)
+
+    for k in range(500):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_pfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.rgmii_phy.tx.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_pfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_pfc_cnt > 2 and tx_pfc_cnt <= 9
+
+    assert tb.axis_sink.empty()
+    assert tb.rgmii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.add_option("speed", [1000e6, 100e6, 10e6])
+        factory.generate_tests()
+
+    for test in [run_test_tx_underrun, run_test_tx_error]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.add_option("speed", [1000e6, 100e6, 10e6])
+        factory.generate_tests()
+
+    if cocotb.top.PFC_EN.value:
+        for test in [run_test_lfc, run_test_pfc]:
+            factory = TestFactory(test)
+            factory.add_option("ifg", [12])
+            factory.add_option("speed", [1000e6, 100e6, 10e6])
+            factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("pfc_en", [1, 0])
+def test_taxi_eth_mac_1g_rgmii(request, pfc_en):
+    dut = "taxi_eth_mac_1g_rgmii"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = 1
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtex7\""
+    parameters['USE_CLK90'] = 1
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_W'] = 96
+    parameters['TX_TAG_W'] = 16
+    parameters['PFC_EN'] = pfc_en
+    parameters['PAUSE_EN'] = parameters['PFC_EN']
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv

@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 1G Ethernet MAC with RGMII interface testbench
+ */
+module test_taxi_eth_mac_1g_rgmii #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter logic SIM = 1'b1,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
+    parameter logic USE_CLK90 = 1'b1,
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter PTP_TS_W = 96,
+    parameter TX_TAG_W = 16,
+    parameter logic PFC_EN = 1'b0,
+    parameter logic PAUSE_EN = PFC_EN,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam DATA_W = 8;
+localparam TX_USER_W = 1;
+localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic gtx_clk;
+logic gtx_clk90;
+logic gtx_rst;
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic rgmii_rx_clk;
+logic [3:0] rgmii_rxd;
+logic rgmii_rx_ctl;
+logic rgmii_tx_clk;
+logic [3:0] rgmii_txd;
+logic rgmii_tx_ctl;
+
+logic [PTP_TS_W-1:0] tx_ptp_ts;
+logic [PTP_TS_W-1:0] rx_ptp_ts;
+
+logic tx_lfc_req;
+logic tx_lfc_resend;
+logic rx_lfc_en;
+logic rx_lfc_req;
+logic rx_lfc_ack;
+
+logic [7:0] tx_pfc_req;
+logic tx_pfc_resend;
+logic [7:0] rx_pfc_en;
+logic [7:0] rx_pfc_req;
+logic [7:0] rx_pfc_ack;
+
+logic tx_lfc_pause_en;
+logic tx_pause_req;
+logic tx_pause_ack;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_start_packet;
+logic stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+logic rx_start_packet;
+logic stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+logic stat_rx_fifo_drop;
+logic [1:0] link_speed;
+logic stat_tx_mcf;
+logic stat_rx_mcf;
+logic stat_tx_lfc_pkt;
+logic stat_tx_lfc_xon;
+logic stat_tx_lfc_xoff;
+logic stat_tx_lfc_paused;
+logic stat_tx_pfc_pkt;
+logic [7:0] stat_tx_pfc_xon;
+logic [7:0] stat_tx_pfc_xoff;
+logic [7:0] stat_tx_pfc_paused;
+logic stat_rx_lfc_pkt;
+logic stat_rx_lfc_xon;
+logic stat_rx_lfc_xoff;
+logic stat_rx_lfc_paused;
+logic stat_rx_pfc_pkt;
+logic [7:0] stat_rx_pfc_xon;
+logic [7:0] stat_rx_pfc_xoff;
+logic [7:0] stat_rx_pfc_paused;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+logic [47:0] cfg_mcf_rx_eth_dst_mcast;
+logic cfg_mcf_rx_check_eth_dst_mcast;
+logic [47:0] cfg_mcf_rx_eth_dst_ucast;
+logic cfg_mcf_rx_check_eth_dst_ucast;
+logic [47:0] cfg_mcf_rx_eth_src;
+logic cfg_mcf_rx_check_eth_src;
+logic [15:0] cfg_mcf_rx_eth_type;
+logic [15:0] cfg_mcf_rx_opcode_lfc;
+logic cfg_mcf_rx_check_opcode_lfc;
+logic [15:0] cfg_mcf_rx_opcode_pfc;
+logic cfg_mcf_rx_check_opcode_pfc;
+logic cfg_mcf_rx_forward;
+logic cfg_mcf_rx_enable;
+logic [47:0] cfg_tx_lfc_eth_dst;
+logic [47:0] cfg_tx_lfc_eth_src;
+logic [15:0] cfg_tx_lfc_eth_type;
+logic [15:0] cfg_tx_lfc_opcode;
+logic cfg_tx_lfc_en;
+logic [15:0] cfg_tx_lfc_quanta;
+logic [15:0] cfg_tx_lfc_refresh;
+logic [47:0] cfg_tx_pfc_eth_dst;
+logic [47:0] cfg_tx_pfc_eth_src;
+logic [15:0] cfg_tx_pfc_eth_type;
+logic [15:0] cfg_tx_pfc_opcode;
+logic cfg_tx_pfc_en;
+logic [15:0] cfg_tx_pfc_quanta[8];
+logic [15:0] cfg_tx_pfc_refresh[8];
+logic [15:0] cfg_rx_lfc_opcode;
+logic cfg_rx_lfc_en;
+logic [15:0] cfg_rx_pfc_opcode;
+logic cfg_rx_pfc_en;
+
+taxi_eth_mac_1g_rgmii #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .USE_CLK90(USE_CLK90),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W),
+    .PFC_EN(PFC_EN),
+    .PAUSE_EN(PAUSE_EN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR)
+)
+uut (
+    .gtx_clk(gtx_clk),
+    .gtx_clk90(gtx_clk90),
+    .gtx_rst(gtx_rst),
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * RGMII interface
+     */
+    .rgmii_rx_clk(rgmii_rx_clk),
+    .rgmii_rxd(rgmii_rxd),
+    .rgmii_rx_ctl(rgmii_rx_ctl),
+    .rgmii_tx_clk(rgmii_tx_clk),
+    .rgmii_txd(rgmii_txd),
+    .rgmii_tx_ctl(rgmii_tx_ctl),
+
+    /*
+     * PTP
+     */
+    .tx_ptp_ts(tx_ptp_ts),
+    .rx_ptp_ts(rx_ptp_ts),
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req(tx_lfc_req),
+    .tx_lfc_resend(tx_lfc_resend),
+    .rx_lfc_en(rx_lfc_en),
+    .rx_lfc_req(rx_lfc_req),
+    .rx_lfc_ack(rx_lfc_ack),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req(tx_pfc_req),
+    .tx_pfc_resend(tx_pfc_resend),
+    .rx_pfc_en(rx_pfc_en),
+    .rx_pfc_req(rx_pfc_req),
+    .rx_pfc_ack(rx_pfc_ack),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en(tx_lfc_pause_en),
+    .tx_pause_req(tx_pause_req),
+    .tx_pause_ack(tx_pause_ack),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow),
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble),
+    .stat_rx_fifo_drop(stat_rx_fifo_drop),
+    .link_speed(link_speed),
+    .stat_tx_mcf(stat_tx_mcf),
+    .stat_rx_mcf(stat_rx_mcf),
+    .stat_tx_lfc_pkt(stat_tx_lfc_pkt),
+    .stat_tx_lfc_xon(stat_tx_lfc_xon),
+    .stat_tx_lfc_xoff(stat_tx_lfc_xoff),
+    .stat_tx_lfc_paused(stat_tx_lfc_paused),
+    .stat_tx_pfc_pkt(stat_tx_pfc_pkt),
+    .stat_tx_pfc_xon(stat_tx_pfc_xon),
+    .stat_tx_pfc_xoff(stat_tx_pfc_xoff),
+    .stat_tx_pfc_paused(stat_tx_pfc_paused),
+    .stat_rx_lfc_pkt(stat_rx_lfc_pkt),
+    .stat_rx_lfc_xon(stat_rx_lfc_xon),
+    .stat_rx_lfc_xoff(stat_rx_lfc_xoff),
+    .stat_rx_lfc_paused(stat_rx_lfc_paused),
+    .stat_rx_pfc_pkt(stat_rx_pfc_pkt),
+    .stat_rx_pfc_xon(stat_rx_pfc_xon),
+    .stat_rx_pfc_xoff(stat_rx_pfc_xoff),
+    .stat_rx_pfc_paused(stat_rx_pfc_paused),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+    .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
+    .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
+    .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
+    .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
+    .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
+    .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
+    .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
+    .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
+    .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
+    .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
+    .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
+    .cfg_mcf_rx_forward(cfg_mcf_rx_forward),
+    .cfg_mcf_rx_enable(cfg_mcf_rx_enable),
+    .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
+    .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
+    .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
+    .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
+    .cfg_tx_lfc_en(cfg_tx_lfc_en),
+    .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
+    .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
+    .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
+    .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
+    .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
+    .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
+    .cfg_tx_pfc_en(cfg_tx_pfc_en),
+    .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
+    .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
+    .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
+    .cfg_rx_lfc_en(cfg_rx_lfc_en),
+    .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
+    .cfg_rx_pfc_en(cfg_rx_pfc_en)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/Makefile

@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_1g_rgmii_fifo
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := 1
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtex7\""
+export PARAM_USE_CLK90 := 1
+export PARAM_AXIS_DATA_W := 8
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_TX_TAG_W := 16
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+export PARAM_TX_FIFO_DEPTH := 16384
+export PARAM_TX_FIFO_RAM_PIPELINE := 1
+export PARAM_TX_FRAME_FIFO := 1
+export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
+export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
+export PARAM_TX_DROP_WHEN_FULL := 0
+export PARAM_TX_CPL_FIFO_DEPTH := 64
+export PARAM_RX_FIFO_DEPTH := 16384
+export PARAM_RX_FIFO_RAM_PIPELINE := 1
+export PARAM_RX_FRAME_FIFO := 1
+export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
+export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.py

@@ -0,0 +1,267 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, RgmiiPhy
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.logic_clk, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
+
+        self.rgmii_phy = RgmiiPhy(dut.rgmii_txd, dut.rgmii_tx_ctl, dut.rgmii_tx_clk,
+            dut.rgmii_rxd, dut.rgmii_rx_ctl, dut.rgmii_rx_clk, speed=speed)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+        dut.gtx_clk.setimmediatevalue(0)
+        dut.gtx_clk90.setimmediatevalue(0)
+
+        cocotb.start_soon(self._run_gtx_clk())
+
+    async def reset(self):
+        self.dut.gtx_rst.setimmediatevalue(0)
+        self.dut.logic_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.gtx_clk)
+        await RisingEdge(self.dut.gtx_clk)
+        self.dut.gtx_rst.value = 1
+        self.dut.logic_rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.gtx_clk)
+        await RisingEdge(self.dut.gtx_clk)
+        self.dut.gtx_rst.value = 0
+        self.dut.logic_rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.gtx_clk)
+        await RisingEdge(self.dut.gtx_clk)
+
+    async def _run_gtx_clk(self):
+        t = Timer(2, 'ns')
+        while True:
+            self.dut.gtx_clk.value = 1
+            await t
+            self.dut.gtx_clk90.value = 1
+            await t
+            self.dut.gtx_clk.value = 0
+            await t
+            self.dut.gtx_clk90.value = 0
+            await t
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.rgmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rgmii_rx_clk)
+
+    if speed == 10e6:
+        assert dut.link_speed == 0
+    elif speed == 100e6:
+        assert dut.link_speed == 1
+    else:
+        assert dut.link_speed == 2
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data)
+        await tb.rgmii_phy.rx.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+
+        assert rx_frame.tdata == test_data
+        assert rx_frame.tuser == 0
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.rgmii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rgmii_rx_clk)
+
+    if speed == 10e6:
+        assert dut.link_speed == 0
+    elif speed == 100e6:
+        assert dut.link_speed == 1
+    else:
+        assert dut.link_speed == 2
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(test_data)
+
+    for test_data in test_frames:
+        rx_frame = await tb.rgmii_phy.tx.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    assert tb.rgmii_phy.tx.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.add_option("speed", [1000e6, 100e6, 10e6])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_eth_mac_1g_rgmii_fifo(request):
+    dut = "taxi_eth_mac_1g_rgmii_fifo"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = 1
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtex7\""
+    parameters['USE_CLK90'] = 1
+    parameters['AXIS_DATA_W'] = 8
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['TX_TAG_W'] = 16
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+    parameters['TX_FIFO_DEPTH'] = 16384
+    parameters['TX_FIFO_RAM_PIPELINE'] = 1
+    parameters['TX_FRAME_FIFO'] = 1
+    parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
+    parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
+    parameters['TX_DROP_WHEN_FULL'] = 0
+    parameters['TX_CPL_FIFO_DEPTH'] = 64
+    parameters['RX_FIFO_DEPTH'] = 16384
+    parameters['RX_FIFO_RAM_PIPELINE'] = 1
+    parameters['RX_FRAME_FIFO'] = 1
+    parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
+    parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
+    parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv

@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 1G Ethernet MAC with RGMII interface and TX and RX FIFOs testbench
+ */
+module test_taxi_eth_mac_1g_rgmii_fifo #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter logic SIM = 1'b1,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
+    parameter logic USE_CLK90 = 1'b1,
+    parameter AXIS_DATA_W = 8,
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter TX_TAG_W = 16,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC",
+    parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_RAM_PIPELINE = 1,
+    parameter logic TX_FRAME_FIFO = 1'b1,
+    parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
+    parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
+    parameter logic TX_DROP_WHEN_FULL = 1'b0,
+    parameter TX_CPL_FIFO_DEPTH = 64,
+    parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_RAM_PIPELINE = 1,
+    parameter logic RX_FRAME_FIFO = 1'b1,
+    parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
+    parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
+    parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam DATA_W = 8;
+localparam TX_USER_W = 1;
+localparam RX_USER_W = 1;
+
+logic gtx_clk;
+logic gtx_clk90;
+logic gtx_rst;
+logic logic_clk;
+logic logic_rst;
+
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic rgmii_rx_clk;
+logic [3:0] rgmii_rxd;
+logic rgmii_rx_ctl;
+logic rgmii_tx_clk;
+logic [3:0] rgmii_txd;
+logic rgmii_tx_ctl;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_error_underflow;
+logic tx_fifo_overflow;
+logic tx_fifo_bad_frame;
+logic tx_fifo_good_frame;
+logic rx_error_bad_frame;
+logic rx_error_bad_fcs;
+logic rx_fifo_overflow;
+logic rx_fifo_bad_frame;
+logic rx_fifo_good_frame;
+logic [1:0] link_speed;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+taxi_eth_mac_1g_rgmii_fifo #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .USE_CLK90(USE_CLK90),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR),
+    .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
+    .TX_FRAME_FIFO(TX_FRAME_FIFO),
+    .TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
+    .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
+    .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
+    .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
+    .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
+    .RX_FRAME_FIFO(RX_FRAME_FIFO),
+    .RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
+    .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
+    .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
+)
+uut (
+    .gtx_clk(gtx_clk),
+    .gtx_clk90(gtx_clk90),
+    .gtx_rst(gtx_rst),
+    .logic_clk(logic_clk),
+    .logic_rst(logic_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * RGMII interface
+     */
+    .rgmii_rx_clk(rgmii_rx_clk),
+    .rgmii_rxd(rgmii_rxd),
+    .rgmii_rx_ctl(rgmii_rx_ctl),
+    .rgmii_tx_clk(rgmii_tx_clk),
+    .rgmii_txd(rgmii_txd),
+    .rgmii_tx_ctl(rgmii_tx_ctl),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(tx_error_underflow),
+    .tx_fifo_overflow(tx_fifo_overflow),
+    .tx_fifo_bad_frame(tx_fifo_bad_frame),
+    .tx_fifo_good_frame(tx_fifo_good_frame),
+    .rx_error_bad_frame(rx_error_bad_frame),
+    .rx_error_bad_fcs(rx_error_bad_fcs),
+    .rx_fifo_overflow(rx_fifo_overflow),
+    .rx_fifo_bad_frame(rx_fifo_bad_frame),
+    .rx_fifo_good_frame(rx_fifo_good_frame),
+    .link_speed(link_speed),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_mii/Makefile

@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_mii
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := 1
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtex7\""
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_W := 96
+export PARAM_TX_TAG_W := 16
+export PARAM_PFC_EN := 1
+export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_mii/test_taxi_eth_mac_mii.py

@@ -0,0 +1,680 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import struct
+import os
+
+from scapy.layers.l2 import Ether
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, MiiPhy, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+
+class TB:
+    def __init__(self, dut, speed=100e6):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
+
+        self.mii_phy = MiiPhy(dut.mii_txd, dut.mii_tx_er, dut.mii_tx_en, dut.mii_tx_clk,
+            dut.mii_rxd, dut.mii_rx_er, dut.mii_rx_dv, dut.mii_rx_clk, speed=speed)
+
+        # the UUT forwards mii_tx_clk/mii_rx_clk as tx_clk/rx_clk, which can cause problems in cocotb
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.mii_tx_clk, dut.tx_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.mii_tx_clk, dut.tx_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.mii_rx_clk, dut.rx_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
+        self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
+
+        dut.tx_lfc_req.setimmediatevalue(0)
+        dut.tx_lfc_resend.setimmediatevalue(0)
+        dut.rx_lfc_en.setimmediatevalue(0)
+        dut.rx_lfc_ack.setimmediatevalue(0)
+
+        dut.tx_pfc_req.setimmediatevalue(0)
+        dut.tx_pfc_resend.setimmediatevalue(0)
+        dut.rx_pfc_en.setimmediatevalue(0)
+        dut.rx_pfc_ack.setimmediatevalue(0)
+
+        dut.tx_lfc_pause_en.setimmediatevalue(0)
+        dut.tx_pause_req.setimmediatevalue(0)
+
+        dut.stat_rx_fifo_drop.setimmediatevalue(0)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_type.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_forward.setimmediatevalue(0)
+        dut.cfg_mcf_rx_enable.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_lfc_en.setimmediatevalue(0)
+        dut.cfg_tx_lfc_quanta.setimmediatevalue(0)
+        dut.cfg_tx_lfc_refresh.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_pfc_en.setimmediatevalue(0)
+        dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
+        dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
+        dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_lfc_en.setimmediatevalue(0)
+        dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_pfc_en.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+        self.dut.rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+        self.dut.rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=100e6):
+
+    tb = TB(dut, speed)
+
+    tb.mii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.mii_phy.rx.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        if speed == 10e6:
+            assert abs(ptp_ts_ns - tx_frame_sfd_ns - 800) < 0.01
+        elif speed == 100e6:
+            assert abs(ptp_ts_ns - tx_frame_sfd_ns - 80) < 0.01
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=100e6):
+
+    tb = TB(dut, speed)
+
+    tb.mii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(test_data)
+
+    for test_data in test_frames:
+        rx_frame = await tb.mii_phy.tx.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    assert tb.mii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_underrun(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.mii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.axis_source.send(test_frame)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = True
+
+    for k in range(10):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.mii_phy.tx.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.mii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_error(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.mii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.axis_source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.mii_phy.tx.recv()
+
+        if k == 1:
+            assert rx_frame.error[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.error is None
+
+    assert tb.mii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_lfc(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.mii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    dut.tx_lfc_req.value = 0
+    dut.tx_lfc_resend.value = 0
+    dut.rx_lfc_en.value = 1
+    dut.rx_lfc_ack.value = 0
+
+    dut.tx_lfc_pause_en.value = 1
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_lfc_eth_type.value = 0x8808
+    dut.cfg_tx_lfc_opcode.value = 0x0001
+    dut.cfg_tx_lfc_en.value = 1
+    dut.cfg_tx_lfc_quanta.value = 0xFFFF
+    dut.cfg_tx_lfc_refresh.value = 0x7F00
+
+    dut.cfg_rx_lfc_opcode.value = 0x0001
+    dut.cfg_rx_lfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 128
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+        await tb.mii_phy.rx.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+            await tb.mii_phy.rx.send(test_frame)
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while not dut.rx_lfc_req.value.integer:
+        await RisingEdge(dut.tx_clk)
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_lfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.mii_phy.tx.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_lfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_lfc_cnt == 4
+
+    assert tb.axis_sink.empty()
+    assert tb.mii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_pfc(dut, ifg=12, speed=1000e6):
+
+    tb = TB(dut, speed)
+
+    tb.mii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+    dut.tx_pfc_resend.value = 0
+    dut.rx_pfc_en.value = 0xff
+    dut.rx_pfc_ack.value = 0x00
+
+    dut.tx_lfc_pause_en.value = 0
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_pfc_eth_type.value = 0x8808
+    dut.cfg_tx_pfc_opcode.value = 0x0101
+    dut.cfg_tx_pfc_en.value = 1
+    dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
+    dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
+
+    dut.cfg_rx_pfc_opcode.value = 0x0101
+    dut.cfg_rx_pfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 128
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+        await tb.mii_phy.rx.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = GmiiFrame.from_payload(bytes(test_pkt))
+            await tb.mii_phy.rx.send(test_frame)
+
+    dut.rx_pfc_ack.value = 0xff
+
+    for i in range(8):
+        for k in range(500):
+            await RisingEdge(dut.tx_clk)
+
+        dut.tx_pfc_req.value = 0xff >> (7-i)
+
+    for k in range(500):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_pfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.mii_phy.tx.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_pfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_pfc_cnt > 2 and tx_pfc_cnt <= 9
+
+    assert tb.axis_sink.empty()
+    assert tb.mii_phy.tx.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.add_option("speed", [100e6, 10e6])
+        factory.generate_tests()
+
+    for test in [run_test_tx_underrun, run_test_tx_error]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.generate_tests()
+
+    if cocotb.top.PFC_EN.value:
+        for test in [run_test_lfc, run_test_pfc]:
+            factory = TestFactory(test)
+            factory.add_option("ifg", [12])
+            factory.add_option("speed", [100e6, 10e6])
+            factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("pfc_en", [1, 0])
+def test_taxi_eth_mac_mii(request, pfc_en):
+    dut = "taxi_eth_mac_mii"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = 1
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtex7\""
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_W'] = 96
+    parameters['TX_TAG_W'] = 16
+    parameters['PFC_EN'] = pfc_en
+    parameters['PAUSE_EN'] = parameters['PFC_EN']
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv

@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 10M/100M Ethernet MAC with MII interface testbench
+ */
+module test_taxi_eth_mac_mii #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter logic SIM = 1'b1,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter PTP_TS_W = 96,
+    parameter TX_TAG_W = 16,
+    parameter logic PFC_EN = 1'b0,
+    parameter logic PAUSE_EN = PFC_EN,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam DATA_W = 8;
+localparam TX_USER_W = 1;
+localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic rst;
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic mii_rx_clk;
+logic [3:0] mii_rxd;
+logic mii_rx_dv;
+logic mii_rx_er;
+logic mii_tx_clk;
+logic [3:0] mii_txd;
+logic mii_tx_en;
+logic mii_tx_er;
+
+logic [PTP_TS_W-1:0] tx_ptp_ts;
+logic [PTP_TS_W-1:0] rx_ptp_ts;
+
+logic tx_lfc_req;
+logic tx_lfc_resend;
+logic rx_lfc_en;
+logic rx_lfc_req;
+logic rx_lfc_ack;
+
+logic [7:0] tx_pfc_req;
+logic tx_pfc_resend;
+logic [7:0] rx_pfc_en;
+logic [7:0] rx_pfc_req;
+logic [7:0] rx_pfc_ack;
+
+logic tx_lfc_pause_en;
+logic tx_pause_req;
+logic tx_pause_ack;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_start_packet;
+logic stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+logic rx_start_packet;
+logic stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+logic stat_rx_fifo_drop;
+logic stat_tx_mcf;
+logic stat_rx_mcf;
+logic stat_tx_lfc_pkt;
+logic stat_tx_lfc_xon;
+logic stat_tx_lfc_xoff;
+logic stat_tx_lfc_paused;
+logic stat_tx_pfc_pkt;
+logic [7:0] stat_tx_pfc_xon;
+logic [7:0] stat_tx_pfc_xoff;
+logic [7:0] stat_tx_pfc_paused;
+logic stat_rx_lfc_pkt;
+logic stat_rx_lfc_xon;
+logic stat_rx_lfc_xoff;
+logic stat_rx_lfc_paused;
+logic stat_rx_pfc_pkt;
+logic [7:0] stat_rx_pfc_xon;
+logic [7:0] stat_rx_pfc_xoff;
+logic [7:0] stat_rx_pfc_paused;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+logic [47:0] cfg_mcf_rx_eth_dst_mcast;
+logic cfg_mcf_rx_check_eth_dst_mcast;
+logic [47:0] cfg_mcf_rx_eth_dst_ucast;
+logic cfg_mcf_rx_check_eth_dst_ucast;
+logic [47:0] cfg_mcf_rx_eth_src;
+logic cfg_mcf_rx_check_eth_src;
+logic [15:0] cfg_mcf_rx_eth_type;
+logic [15:0] cfg_mcf_rx_opcode_lfc;
+logic cfg_mcf_rx_check_opcode_lfc;
+logic [15:0] cfg_mcf_rx_opcode_pfc;
+logic cfg_mcf_rx_check_opcode_pfc;
+logic cfg_mcf_rx_forward;
+logic cfg_mcf_rx_enable;
+logic [47:0] cfg_tx_lfc_eth_dst;
+logic [47:0] cfg_tx_lfc_eth_src;
+logic [15:0] cfg_tx_lfc_eth_type;
+logic [15:0] cfg_tx_lfc_opcode;
+logic cfg_tx_lfc_en;
+logic [15:0] cfg_tx_lfc_quanta;
+logic [15:0] cfg_tx_lfc_refresh;
+logic [47:0] cfg_tx_pfc_eth_dst;
+logic [47:0] cfg_tx_pfc_eth_src;
+logic [15:0] cfg_tx_pfc_eth_type;
+logic [15:0] cfg_tx_pfc_opcode;
+logic cfg_tx_pfc_en;
+logic [15:0] cfg_tx_pfc_quanta[8];
+logic [15:0] cfg_tx_pfc_refresh[8];
+logic [15:0] cfg_rx_lfc_opcode;
+logic cfg_rx_lfc_en;
+logic [15:0] cfg_rx_pfc_opcode;
+logic cfg_rx_pfc_en;
+
+taxi_eth_mac_mii #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_W(PTP_TS_W),
+    .PFC_EN(PFC_EN),
+    .PAUSE_EN(PAUSE_EN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR)
+)
+uut (
+    .rst(rst),
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * MII interface
+     */
+    .mii_rx_clk(mii_rx_clk),
+    .mii_rxd(mii_rxd),
+    .mii_rx_dv(mii_rx_dv),
+    .mii_rx_er(mii_rx_er),
+    .mii_tx_clk(mii_tx_clk),
+    .mii_txd(mii_txd),
+    .mii_tx_en(mii_tx_en),
+    .mii_tx_er(mii_tx_er),
+
+    /*
+     * PTP
+     */
+    .tx_ptp_ts(tx_ptp_ts),
+    .rx_ptp_ts(rx_ptp_ts),
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req(tx_lfc_req),
+    .tx_lfc_resend(tx_lfc_resend),
+    .rx_lfc_en(rx_lfc_en),
+    .rx_lfc_req(rx_lfc_req),
+    .rx_lfc_ack(rx_lfc_ack),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req(tx_pfc_req),
+    .tx_pfc_resend(tx_pfc_resend),
+    .rx_pfc_en(rx_pfc_en),
+    .rx_pfc_req(rx_pfc_req),
+    .rx_pfc_ack(rx_pfc_ack),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en(tx_lfc_pause_en),
+    .tx_pause_req(tx_pause_req),
+    .tx_pause_ack(tx_pause_ack),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow),
+    .rx_start_packet(rx_start_packet),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble),
+    .stat_rx_fifo_drop(stat_rx_fifo_drop),
+    .stat_tx_mcf(stat_tx_mcf),
+    .stat_rx_mcf(stat_rx_mcf),
+    .stat_tx_lfc_pkt(stat_tx_lfc_pkt),
+    .stat_tx_lfc_xon(stat_tx_lfc_xon),
+    .stat_tx_lfc_xoff(stat_tx_lfc_xoff),
+    .stat_tx_lfc_paused(stat_tx_lfc_paused),
+    .stat_tx_pfc_pkt(stat_tx_pfc_pkt),
+    .stat_tx_pfc_xon(stat_tx_pfc_xon),
+    .stat_tx_pfc_xoff(stat_tx_pfc_xoff),
+    .stat_tx_pfc_paused(stat_tx_pfc_paused),
+    .stat_rx_lfc_pkt(stat_rx_lfc_pkt),
+    .stat_rx_lfc_xon(stat_rx_lfc_xon),
+    .stat_rx_lfc_xoff(stat_rx_lfc_xoff),
+    .stat_rx_lfc_paused(stat_rx_lfc_paused),
+    .stat_rx_pfc_pkt(stat_rx_pfc_pkt),
+    .stat_rx_pfc_xon(stat_rx_pfc_xon),
+    .stat_rx_pfc_xoff(stat_rx_pfc_xoff),
+    .stat_rx_pfc_paused(stat_rx_pfc_paused),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+    .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
+    .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
+    .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
+    .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
+    .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
+    .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
+    .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
+    .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
+    .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
+    .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
+    .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
+    .cfg_mcf_rx_forward(cfg_mcf_rx_forward),
+    .cfg_mcf_rx_enable(cfg_mcf_rx_enable),
+    .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
+    .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
+    .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
+    .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
+    .cfg_tx_lfc_en(cfg_tx_lfc_en),
+    .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
+    .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
+    .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
+    .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
+    .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
+    .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
+    .cfg_tx_pfc_en(cfg_tx_pfc_en),
+    .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
+    .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
+    .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
+    .cfg_rx_lfc_en(cfg_rx_lfc_en),
+    .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
+    .cfg_rx_pfc_en(cfg_rx_pfc_en)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_mii_fifo/Makefile

@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_mii_fifo
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := 1
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtex7\""
+export PARAM_AXIS_DATA_W := 8
+export PARAM_PADDING_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_TX_TAG_W := 16
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+export PARAM_TX_FIFO_DEPTH := 16384
+export PARAM_TX_FIFO_RAM_PIPELINE := 1
+export PARAM_TX_FRAME_FIFO := 1
+export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
+export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
+export PARAM_TX_DROP_WHEN_FULL := 0
+export PARAM_TX_CPL_FIFO_DEPTH := 64
+export PARAM_RX_FIFO_DEPTH := 16384
+export PARAM_RX_FIFO_RAM_PIPELINE := 1
+export PARAM_RX_FRAME_FIFO := 1
+export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
+export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.py

@@ -0,0 +1,226 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import GmiiFrame, MiiPhy
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
+
+
+class TB:
+    def __init__(self, dut, speed=100e6):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.logic_clk, 40, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
+
+        self.mii_phy = MiiPhy(dut.mii_txd, dut.mii_tx_er, dut.mii_tx_en, dut.mii_tx_clk,
+            dut.mii_rxd, dut.mii_rx_er, dut.mii_rx_dv, dut.mii_rx_clk, speed=speed)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.logic_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        for k in range(10):
+            await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 1
+        self.dut.stat_rst.value = 1
+        for k in range(10):
+            await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 0
+        self.dut.stat_rst.value = 0
+        for k in range(10):
+            await RisingEdge(self.dut.logic_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=100e6):
+
+    tb = TB(dut, speed)
+
+    tb.mii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = GmiiFrame.from_payload(test_data)
+        await tb.mii_phy.rx.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+
+        assert rx_frame.tdata == test_data
+        assert rx_frame.tuser == 0
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, speed=100e6):
+
+    tb = TB(dut, speed)
+
+    tb.mii_phy.rx.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(test_data)
+
+    for test_data in test_frames:
+        rx_frame = await tb.mii_phy.tx.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    assert tb.mii_phy.tx.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.add_option("speed", [100e6, 10e6])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_eth_mac_mii_fifo(request):
+    dut = "taxi_eth_mac_mii_fifo"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = 1
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtex7\""
+    parameters['AXIS_DATA_W'] = 8
+    parameters['PADDING_EN'] = 1
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['TX_TAG_W'] = 16
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+    parameters['TX_FIFO_DEPTH'] = 16384
+    parameters['TX_FIFO_RAM_PIPELINE'] = 1
+    parameters['TX_FRAME_FIFO'] = 1
+    parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
+    parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
+    parameters['TX_DROP_WHEN_FULL'] = 0
+    parameters['TX_CPL_FIFO_DEPTH'] = 64
+    parameters['RX_FIFO_DEPTH'] = 16384
+    parameters['RX_FIFO_RAM_PIPELINE'] = 1
+    parameters['RX_FRAME_FIFO'] = 1
+    parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
+    parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
+    parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv

@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 10M/100M Ethernet MAC with MII interface and TX and RX FIFOs testbench
+ */
+module test_taxi_eth_mac_mii_fifo #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter logic SIM = 1'b1,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtex7",
+    parameter AXIS_DATA_W = 8,
+    parameter logic PADDING_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter TX_TAG_W = 16,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC",
+    parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_RAM_PIPELINE = 1,
+    parameter logic TX_FRAME_FIFO = 1'b1,
+    parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
+    parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
+    parameter logic TX_DROP_WHEN_FULL = 1'b0,
+    parameter TX_CPL_FIFO_DEPTH = 64,
+    parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_RAM_PIPELINE = 1,
+    parameter logic RX_FRAME_FIFO = 1'b1,
+    parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
+    parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
+    parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam TX_USER_W = 1;
+localparam RX_USER_W = 1;
+
+logic rst;
+logic logic_clk;
+logic logic_rst;
+
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic mii_rx_clk;
+logic [3:0] mii_rxd;
+logic mii_rx_dv;
+logic mii_rx_er;
+logic mii_tx_clk;
+logic [3:0] mii_txd;
+logic mii_tx_en;
+logic mii_tx_er;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_error_underflow;
+logic tx_fifo_overflow;
+logic tx_fifo_bad_frame;
+logic tx_fifo_good_frame;
+logic rx_error_bad_frame;
+logic rx_error_bad_fcs;
+logic rx_fifo_overflow;
+logic rx_fifo_bad_frame;
+logic rx_fifo_good_frame;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+
+taxi_eth_mac_mii_fifo #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PADDING_EN(PADDING_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR),
+    .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
+    .TX_FRAME_FIFO(TX_FRAME_FIFO),
+    .TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
+    .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
+    .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
+    .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
+    .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
+    .RX_FRAME_FIFO(RX_FRAME_FIFO),
+    .RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
+    .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
+    .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
+)
+uut (
+    .rst(rst),
+    .logic_clk(logic_clk),
+    .logic_rst(logic_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * MII interface
+     */
+    .mii_rx_clk(mii_rx_clk),
+    .mii_rxd(mii_rxd),
+    .mii_rx_dv(mii_rx_dv),
+    .mii_rx_er(mii_rx_er),
+    .mii_tx_clk(mii_tx_clk),
+    .mii_txd(mii_txd),
+    .mii_tx_en(mii_tx_en),
+    .mii_tx_er(mii_tx_er),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(tx_error_underflow),
+    .tx_fifo_overflow(tx_fifo_overflow),
+    .tx_fifo_bad_frame(tx_fifo_bad_frame),
+    .tx_fifo_good_frame(tx_fifo_good_frame),
+    .rx_error_bad_frame(rx_error_bad_frame),
+    .rx_error_bad_fcs(rx_error_bad_fcs),
+    .rx_fifo_overflow(rx_fifo_overflow),
+    .rx_fifo_bad_frame(rx_fifo_bad_frame),
+    .rx_fifo_good_frame(rx_fifo_good_frame),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_phy_10g/Makefile

@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_phy_10g
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_HDR_W := 2
+export PARAM_PADDING_EN := 1
+export PARAM_DIC_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
+export PARAM_TX_TAG_W := 16
+export PARAM_BIT_REVERSE := 0
+export PARAM_SCRAMBLER_DISABLE := 0
+export PARAM_PRBS31_EN := 1
+export PARAM_TX_SERDES_PIPELINE := 2
+export PARAM_RX_SERDES_PIPELINE := 2
+export PARAM_BITSLIP_HIGH_CYCLES := 0
+export PARAM_BITSLIP_LOW_CYCLES := 7
+export PARAM_COUNT_125US := 195
+export PARAM_PFC_EN := 1
+export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_phy_10g/baser.py

@@ -0,0 +1 @@
+../baser.py

src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py

@@ -0,0 +1,854 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import struct
+import sys
+
+from scapy.layers.l2 import Ether
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+try:
+    from baser import BaseRSerdesSource, BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource, BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        if len(dut.serdes_tx_data) == 64:
+            self.clk_period = 6.4
+        else:
+            self.clk_period = 3.2
+
+        cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, self.clk_period, units="ns").start())
+
+        self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip)
+        self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.tx_clk, dut.tx_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.rx_clk, dut.rx_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts, clock=dut.rx_clk)
+        self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts, clock=dut.tx_clk)
+
+        dut.stat_rx_fifo_drop.setimmediatevalue(0)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+        dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
+        dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_type.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_forward.setimmediatevalue(0)
+        dut.cfg_mcf_rx_enable.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_lfc_en.setimmediatevalue(0)
+        dut.cfg_tx_lfc_quanta.setimmediatevalue(0)
+        dut.cfg_tx_lfc_refresh.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_pfc_en.setimmediatevalue(0)
+        dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
+        dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
+        dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_lfc_en.setimmediatevalue(0)
+        dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_pfc_en.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rx_rst.setimmediatevalue(0)
+        self.dut.tx_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.rx_clk)
+        await RisingEdge(self.dut.rx_clk)
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.rx_clk)
+        await RisingEdge(self.dut.rx_clk)
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.rx_clk)
+        await RisingEdge(self.dut.rx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+
+    await tb.reset()
+
+    tb.dut.cfg_rx_enable.value = 0
+
+    tb.log.info("Wait for block lock")
+    while not int(dut.rx_block_lock.value):
+        await RisingEdge(dut.rx_clk)
+
+    tb.dut.cfg_rx_enable.value = 1
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.serdes_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        print(tx_frame)
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        if tx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            tx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*4) < 0.01
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+
+    await tb.reset()
+
+    tb.dut.cfg_tx_enable.value = 1
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+    for test_data in test_frames:
+        rx_frame = await tb.serdes_sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        if rx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            rx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.ctrl is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < 0.01
+
+    assert tb.serdes_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
+
+    dic_en = int(cocotb.top.DIC_EN.value)
+
+    tb = TB(dut)
+
+    byte_width = tb.axis_source.width // 8
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+
+    await tb.reset()
+
+    tb.dut.cfg_tx_enable.value = 1
+
+    for length in range(60, 92):
+
+        for k in range(10):
+            await RisingEdge(dut.tx_clk)
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+        for test_data in test_frames:
+            rx_frame = await tb.serdes_sink.recv()
+            tx_cpl = await tb.tx_cpl_sink.recv()
+
+            ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+            rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+            if rx_frame.start_lane == 4:
+                # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+                rx_frame_sfd_ns -= 3.2
+
+            tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+            tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+            tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < 0.01
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_width
+
+            if dic_en:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.tx_clk)
+
+    assert tb.serdes_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_underrun(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+
+    await tb.reset()
+
+    tb.dut.cfg_tx_enable.value = 1
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        await tb.axis_source.send(test_frame)
+
+    for k in range(64*16 // tb.axis_source.width):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = True
+
+    for k in range(4):
+        await RisingEdge(dut.tx_clk)
+
+    tb.axis_source.pause = False
+
+    for k in range(3):
+        rx_frame = await tb.serdes_sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.serdes_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_tx_error(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+
+    await tb.reset()
+
+    tb.dut.cfg_tx_enable.value = 1
+
+    test_data = bytes(x for x in range(60))
+
+    for k in range(3):
+        test_frame = AxiStreamFrame(test_data)
+        if k == 1:
+            test_frame.tuser = 1
+        await tb.axis_source.send(test_frame)
+
+    for k in range(3):
+        rx_frame = await tb.serdes_sink.recv()
+
+        if k == 1:
+            assert rx_frame.data[-1] == 0xFE
+            assert rx_frame.ctrl[-1] == 1
+        else:
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+    assert tb.serdes_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_rx_frame_sync(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.log.info("Wait for block lock")
+    while not int(dut.rx_block_lock.value):
+        await RisingEdge(dut.rx_clk)
+
+    assert int(dut.rx_block_lock.value)
+
+    tb.log.info("Change offset")
+    tb.serdes_source.bit_offset = 33
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Check for lock lost")
+    assert not int(dut.rx_block_lock.value)
+    assert int(dut.rx_high_ber.value)
+
+    for k in range(500):
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Check for block lock")
+    assert int(dut.rx_block_lock.value)
+
+    for k in range(300):
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Check for high BER deassert")
+    assert not int(dut.rx_high_ber.value)
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_lfc(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+
+    await tb.reset()
+
+    tb.log.info("Wait for block lock")
+    while not int(dut.rx_block_lock.value):
+        await RisingEdge(dut.rx_clk)
+
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_enable.value = 1
+
+    dut.tx_lfc_req.value = 0
+    dut.tx_lfc_resend.value = 0
+    dut.rx_lfc_en.value = 1
+    dut.rx_lfc_ack.value = 0
+
+    dut.tx_lfc_pause_en.value = 1
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_lfc_eth_type.value = 0x8808
+    dut.cfg_tx_lfc_opcode.value = 0x0001
+    dut.cfg_tx_lfc_en.value = 1
+    dut.cfg_tx_lfc_quanta.value = 0xFFFF
+    dut.cfg_tx_lfc_refresh.value = 0x7F00
+
+    dut.cfg_rx_lfc_opcode.value = 0x0001
+    dut.cfg_rx_lfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 512
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+        await tb.serdes_source.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+            await tb.serdes_source.send(test_frame)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while not dut.rx_lfc_req.value.integer:
+        await RisingEdge(dut.tx_clk)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 1
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_lfc_req.value = 0
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_lfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.serdes_sink.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_lfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_lfc_cnt == 4
+
+    assert tb.axis_sink.empty()
+    assert tb.serdes_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_pfc(dut, ifg=12):
+
+    tb = TB(dut)
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+
+    await tb.reset()
+
+    tb.log.info("Wait for block lock")
+    while not int(dut.rx_block_lock.value):
+        await RisingEdge(dut.rx_clk)
+
+    tb.dut.cfg_tx_enable.value = 1
+    tb.dut.cfg_rx_enable.value = 1
+
+    dut.tx_pfc_req.value = 0x00
+    dut.tx_pfc_resend.value = 0
+    dut.rx_pfc_en.value = 0xff
+    dut.rx_pfc_ack.value = 0x00
+
+    dut.tx_lfc_pause_en.value = 0
+    dut.tx_pause_req.value = 0
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_pfc_eth_type.value = 0x8808
+    dut.cfg_tx_pfc_opcode.value = 0x0101
+    dut.cfg_tx_pfc_en.value = 1
+    dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
+    dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
+
+    dut.cfg_rx_pfc_opcode.value = 0x0101
+    dut.cfg_rx_pfc_en.value = 1
+
+    test_tx_pkts = []
+    test_rx_pkts = []
+
+    for k in range(32):
+        length = 512
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / payload
+        test_tx_pkts.append(test_pkt.copy())
+
+        await tb.axis_source.send(bytes(test_pkt))
+
+        eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
+        test_pkt = eth / payload
+        test_rx_pkts.append(test_pkt.copy())
+
+        test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+        await tb.serdes_source.send(test_frame)
+
+        if k == 16:
+            eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
+            test_rx_pkts.append(test_pkt.copy())
+
+            test_frame = XgmiiFrame.from_payload(bytes(test_pkt))
+            await tb.serdes_source.send(test_frame)
+
+    dut.rx_pfc_ack.value = 0xff
+
+    for i in range(8):
+        for k in range(200):
+            await RisingEdge(dut.tx_clk)
+
+        dut.tx_pfc_req.value = 0xff >> (7-i)
+
+    for k in range(200):
+        await RisingEdge(dut.tx_clk)
+
+    dut.tx_pfc_req.value = 0x00
+
+    while test_rx_pkts:
+        rx_frame = await tb.axis_sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        if rx_pkt.type == 0x8808:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert rx_frame.tuser[-1] & 1
+            else:
+                assert rx_frame.tuser & 1
+        else:
+            test_pkt = test_rx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            if isinstance(rx_frame.tuser, list):
+                assert not rx_frame.tuser[-1] & 1
+            else:
+                assert not rx_frame.tuser & 1
+
+    tx_pfc_cnt = 0
+
+    while test_tx_pkts:
+        tx_frame = await tb.serdes_sink.recv()
+
+        tx_pkt = Ether(bytes(tx_frame.get_payload()))
+
+        tb.log.info("TX packet: %s", repr(tx_pkt))
+
+        if tx_pkt.type == 0x8808:
+            tx_pfc_cnt += 1
+        else:
+            test_pkt = test_tx_pkts.pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tx_pfc_cnt == 9
+
+    assert tb.axis_sink.empty()
+    assert tb.serdes_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12, 0])
+        factory.generate_tests()
+
+    factory = TestFactory(run_test_tx_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    for test in [run_test_tx_underrun, run_test_tx_error]:
+
+        factory = TestFactory(test)
+        factory.add_option("ifg", [12])
+        factory.generate_tests()
+
+    factory = TestFactory(run_test_rx_frame_sync)
+    factory.generate_tests()
+
+    if cocotb.top.PFC_EN.value:
+        for test in [run_test_lfc, run_test_pfc]:
+            factory = TestFactory(test)
+            factory.add_option("ifg", [12])
+            factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize(("dic_en", "pfc_en"), [(1, 1), (1, 0), (0, 0)])
+@pytest.mark.parametrize("data_w", [64])
+def test_taxi_eth_mac_phy_10g(request, data_w, dic_en, pfc_en):
+    dut = "taxi_eth_mac_phy_10g"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['HDR_W'] = 2
+    parameters['PADDING_EN'] = 1
+    parameters['DIC_EN'] = dic_en
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+    parameters['TX_TAG_W'] = 16
+    parameters['BIT_REVERSE'] = 0
+    parameters['SCRAMBLER_DISABLE'] = 0
+    parameters['PRBS31_EN'] = 1
+    parameters['TX_SERDES_PIPELINE'] = 2
+    parameters['RX_SERDES_PIPELINE'] = 2
+    parameters['BITSLIP_HIGH_CYCLES'] = 0
+    parameters['BITSLIP_LOW_CYCLES'] = 7
+    parameters['COUNT_125US'] = int(1250/6.4)
+    parameters['PFC_EN'] = pfc_en
+    parameters['PAUSE_EN'] = parameters['PFC_EN']
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv

@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 10G Ethernet MAC/PHY testbench
+ */
+module test_taxi_eth_mac_phy_10g #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter HDR_W = 2,
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter TX_TAG_W = 16,
+    parameter logic BIT_REVERSE = 1'b0,
+    parameter logic SCRAMBLER_DISABLE = 1'b0,
+    parameter logic PRBS31_EN = 1'b0,
+    parameter TX_SERDES_PIPELINE = 0,
+    parameter RX_SERDES_PIPELINE = 0,
+    parameter BITSLIP_HIGH_CYCLES = 0,
+    parameter BITSLIP_LOW_CYCLES = 7,
+    parameter COUNT_125US = 125000/6.4,
+    parameter logic PFC_EN = 1'b0,
+    parameter logic PAUSE_EN = PFC_EN,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam TX_USER_W = 1;
+localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic [DATA_W-1:0] serdes_tx_data;
+logic [HDR_W-1:0] serdes_tx_hdr;
+logic [DATA_W-1:0] serdes_rx_data;
+logic [HDR_W-1:0] serdes_rx_hdr;
+logic serdes_rx_bitslip;
+logic serdes_rx_reset_req;
+
+logic [PTP_TS_W-1:0] tx_ptp_ts;
+logic [PTP_TS_W-1:0] rx_ptp_ts;
+
+logic tx_lfc_req;
+logic tx_lfc_resend;
+logic rx_lfc_en;
+logic rx_lfc_req;
+logic rx_lfc_ack;
+
+logic [7:0] tx_pfc_req;
+logic tx_pfc_resend;
+logic [7:0] rx_pfc_en;
+logic [7:0] rx_pfc_req;
+logic [7:0] rx_pfc_ack;
+
+logic tx_lfc_pause_en;
+logic tx_pause_req;
+logic tx_pause_ack;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(24), .KEEP_W(1), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic [1:0] tx_start_packet;
+logic [3:0] stat_tx_byte;
+logic [15:0] stat_tx_pkt_len;
+logic stat_tx_pkt_ucast;
+logic stat_tx_pkt_mcast;
+logic stat_tx_pkt_bcast;
+logic stat_tx_pkt_vlan;
+logic stat_tx_pkt_good;
+logic stat_tx_pkt_bad;
+logic stat_tx_err_oversize;
+logic stat_tx_err_user;
+logic stat_tx_err_underflow;
+logic [1:0] rx_start_packet;
+logic [6:0] rx_error_count;
+logic rx_block_lock;
+logic rx_high_ber;
+logic rx_status;
+logic [3:0] stat_rx_byte;
+logic [15:0] stat_rx_pkt_len;
+logic stat_rx_pkt_fragment;
+logic stat_rx_pkt_jabber;
+logic stat_rx_pkt_ucast;
+logic stat_rx_pkt_mcast;
+logic stat_rx_pkt_bcast;
+logic stat_rx_pkt_vlan;
+logic stat_rx_pkt_good;
+logic stat_rx_pkt_bad;
+logic stat_rx_err_oversize;
+logic stat_rx_err_bad_fcs;
+logic stat_rx_err_bad_block;
+logic stat_rx_err_framing;
+logic stat_rx_err_preamble;
+logic stat_rx_fifo_drop;
+logic stat_tx_mcf;
+logic stat_rx_mcf;
+logic stat_tx_lfc_pkt;
+logic stat_tx_lfc_xon;
+logic stat_tx_lfc_xoff;
+logic stat_tx_lfc_paused;
+logic stat_tx_pfc_pkt;
+logic [7:0] stat_tx_pfc_xon;
+logic [7:0] stat_tx_pfc_xoff;
+logic [7:0] stat_tx_pfc_paused;
+logic stat_rx_lfc_pkt;
+logic stat_rx_lfc_xon;
+logic stat_rx_lfc_xoff;
+logic stat_rx_lfc_paused;
+logic stat_rx_pfc_pkt;
+logic [7:0] stat_rx_pfc_xon;
+logic [7:0] stat_rx_pfc_xoff;
+logic [7:0] stat_rx_pfc_paused;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+logic cfg_tx_prbs31_enable;
+logic cfg_rx_prbs31_enable;
+logic [47:0] cfg_mcf_rx_eth_dst_mcast;
+logic cfg_mcf_rx_check_eth_dst_mcast;
+logic [47:0] cfg_mcf_rx_eth_dst_ucast;
+logic cfg_mcf_rx_check_eth_dst_ucast;
+logic [47:0] cfg_mcf_rx_eth_src;
+logic cfg_mcf_rx_check_eth_src;
+logic [15:0] cfg_mcf_rx_eth_type;
+logic [15:0] cfg_mcf_rx_opcode_lfc;
+logic cfg_mcf_rx_check_opcode_lfc;
+logic [15:0] cfg_mcf_rx_opcode_pfc;
+logic cfg_mcf_rx_check_opcode_pfc;
+logic cfg_mcf_rx_forward;
+logic cfg_mcf_rx_enable;
+logic [47:0] cfg_tx_lfc_eth_dst;
+logic [47:0] cfg_tx_lfc_eth_src;
+logic [15:0] cfg_tx_lfc_eth_type;
+logic [15:0] cfg_tx_lfc_opcode;
+logic cfg_tx_lfc_en;
+logic [15:0] cfg_tx_lfc_quanta;
+logic [15:0] cfg_tx_lfc_refresh;
+logic [47:0] cfg_tx_pfc_eth_dst;
+logic [47:0] cfg_tx_pfc_eth_src;
+logic [15:0] cfg_tx_pfc_eth_type;
+logic [15:0] cfg_tx_pfc_opcode;
+logic cfg_tx_pfc_en;
+logic [15:0] cfg_tx_pfc_quanta[8];
+logic [15:0] cfg_tx_pfc_refresh[8];
+logic [15:0] cfg_rx_lfc_opcode;
+logic cfg_rx_lfc_en;
+logic [15:0] cfg_rx_pfc_opcode;
+logic cfg_rx_pfc_en;
+
+taxi_eth_mac_phy_10g #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W),
+    .BIT_REVERSE(BIT_REVERSE),
+    .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
+    .PRBS31_EN(PRBS31_EN),
+    .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
+    .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
+    .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
+    .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
+    .COUNT_125US(COUNT_125US),
+    .PFC_EN(PFC_EN),
+    .PAUSE_EN(PAUSE_EN),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR)
+)
+uut (
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * SERDES interface
+     */
+    .serdes_tx_data(serdes_tx_data),
+    .serdes_tx_hdr(serdes_tx_hdr),
+    .serdes_rx_data(serdes_rx_data),
+    .serdes_rx_hdr(serdes_rx_hdr),
+    .serdes_rx_bitslip(serdes_rx_bitslip),
+    .serdes_rx_reset_req(serdes_rx_reset_req),
+
+    /*
+     * PTP
+     */
+    .tx_ptp_ts(tx_ptp_ts),
+    .rx_ptp_ts(rx_ptp_ts),
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req(tx_lfc_req),
+    .tx_lfc_resend(tx_lfc_resend),
+    .rx_lfc_en(rx_lfc_en),
+    .rx_lfc_req(rx_lfc_req),
+    .rx_lfc_ack(rx_lfc_ack),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req(tx_pfc_req),
+    .tx_pfc_resend(tx_pfc_resend),
+    .rx_pfc_en(rx_pfc_en),
+    .rx_pfc_req(rx_pfc_req),
+    .rx_pfc_ack(rx_pfc_ack),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en(tx_lfc_pause_en),
+    .tx_pause_req(tx_pause_req),
+    .tx_pause_ack(tx_pause_ack),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(tx_start_packet),
+    .stat_tx_byte(stat_tx_byte),
+    .stat_tx_pkt_len(stat_tx_pkt_len),
+    .stat_tx_pkt_ucast(stat_tx_pkt_ucast),
+    .stat_tx_pkt_mcast(stat_tx_pkt_mcast),
+    .stat_tx_pkt_bcast(stat_tx_pkt_bcast),
+    .stat_tx_pkt_vlan(stat_tx_pkt_vlan),
+    .stat_tx_pkt_good(stat_tx_pkt_good),
+    .stat_tx_pkt_bad(stat_tx_pkt_bad),
+    .stat_tx_err_oversize(stat_tx_err_oversize),
+    .stat_tx_err_user(stat_tx_err_user),
+    .stat_tx_err_underflow(stat_tx_err_underflow),
+    .rx_start_packet(rx_start_packet),
+    .rx_error_count(rx_error_count),
+    .rx_block_lock(rx_block_lock),
+    .rx_high_ber(rx_high_ber),
+    .rx_status(rx_status),
+    .stat_rx_byte(stat_rx_byte),
+    .stat_rx_pkt_len(stat_rx_pkt_len),
+    .stat_rx_pkt_fragment(stat_rx_pkt_fragment),
+    .stat_rx_pkt_jabber(stat_rx_pkt_jabber),
+    .stat_rx_pkt_ucast(stat_rx_pkt_ucast),
+    .stat_rx_pkt_mcast(stat_rx_pkt_mcast),
+    .stat_rx_pkt_bcast(stat_rx_pkt_bcast),
+    .stat_rx_pkt_vlan(stat_rx_pkt_vlan),
+    .stat_rx_pkt_good(stat_rx_pkt_good),
+    .stat_rx_pkt_bad(stat_rx_pkt_bad),
+    .stat_rx_err_oversize(stat_rx_err_oversize),
+    .stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
+    .stat_rx_err_bad_block(stat_rx_err_bad_block),
+    .stat_rx_err_framing(stat_rx_err_framing),
+    .stat_rx_err_preamble(stat_rx_err_preamble),
+    .stat_rx_fifo_drop(stat_rx_fifo_drop),
+    .stat_tx_mcf(stat_tx_mcf),
+    .stat_rx_mcf(stat_rx_mcf),
+    .stat_tx_lfc_pkt(stat_tx_lfc_pkt),
+    .stat_tx_lfc_xon(stat_tx_lfc_xon),
+    .stat_tx_lfc_xoff(stat_tx_lfc_xoff),
+    .stat_tx_lfc_paused(stat_tx_lfc_paused),
+    .stat_tx_pfc_pkt(stat_tx_pfc_pkt),
+    .stat_tx_pfc_xon(stat_tx_pfc_xon),
+    .stat_tx_pfc_xoff(stat_tx_pfc_xoff),
+    .stat_tx_pfc_paused(stat_tx_pfc_paused),
+    .stat_rx_lfc_pkt(stat_rx_lfc_pkt),
+    .stat_rx_lfc_xon(stat_rx_lfc_xon),
+    .stat_rx_lfc_xoff(stat_rx_lfc_xoff),
+    .stat_rx_lfc_paused(stat_rx_lfc_paused),
+    .stat_rx_pfc_pkt(stat_rx_pfc_pkt),
+    .stat_rx_pfc_xon(stat_rx_pfc_xon),
+    .stat_rx_pfc_xoff(stat_rx_pfc_xoff),
+    .stat_rx_pfc_paused(stat_rx_pfc_paused),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+    .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
+    .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable),
+    .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
+    .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
+    .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
+    .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
+    .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
+    .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
+    .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
+    .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
+    .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
+    .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
+    .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
+    .cfg_mcf_rx_forward(cfg_mcf_rx_forward),
+    .cfg_mcf_rx_enable(cfg_mcf_rx_enable),
+    .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
+    .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
+    .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
+    .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
+    .cfg_tx_lfc_en(cfg_tx_lfc_en),
+    .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
+    .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
+    .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
+    .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
+    .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
+    .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
+    .cfg_tx_pfc_en(cfg_tx_pfc_en),
+    .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
+    .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
+    .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
+    .cfg_rx_lfc_en(cfg_rx_lfc_en),
+    .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
+    .cfg_rx_pfc_en(cfg_rx_pfc_en)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_mac_phy_10g_fifo/Makefile

@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_mac_phy_10g_fifo
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_HDR_W := 2
+export PARAM_AXIS_DATA_W := $(PARAM_DATA_W)
+export PARAM_PADDING_EN := 1
+export PARAM_DIC_EN := 1
+export PARAM_MIN_FRAME_LEN := 64
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
+export PARAM_TX_TAG_W := 16
+export PARAM_BIT_REVERSE := 0
+export PARAM_SCRAMBLER_DISABLE := 0
+export PARAM_PRBS31_EN := 1
+export PARAM_TX_SERDES_PIPELINE := 2
+export PARAM_RX_SERDES_PIPELINE := 2
+export PARAM_BITSLIP_HIGH_CYCLES := 0
+export PARAM_BITSLIP_LOW_CYCLES := 7
+export PARAM_COUNT_125US := 195
+export PARAM_STAT_EN := 1
+export PARAM_STAT_TX_LEVEL := 2
+export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
+export PARAM_STAT_ID_BASE := 0
+export PARAM_STAT_UPDATE_PERIOD := 1024
+export PARAM_STAT_STR_EN := 1
+export PARAM_STAT_PREFIX_STR := "\"MAC\""
+export PARAM_TX_FIFO_DEPTH := 16384
+export PARAM_TX_FIFO_RAM_PIPELINE := 1
+export PARAM_TX_FRAME_FIFO := 1
+export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
+export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
+export PARAM_TX_DROP_WHEN_FULL := 0
+export PARAM_TX_CPL_FIFO_DEPTH := 64
+export PARAM_RX_FIFO_DEPTH := 16384
+export PARAM_RX_FIFO_RAM_PIPELINE := 1
+export PARAM_RX_FRAME_FIFO := 1
+export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
+export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_mac_phy_10g_fifo/baser.py

@@ -0,0 +1 @@
+../baser.py

src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py

@@ -0,0 +1,462 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+
+try:
+    from baser import BaseRSerdesSource, BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource, BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        if len(dut.serdes_tx_data) == 64:
+            self.clk_period = 6.4
+        else:
+            self.clk_period = 3.2
+
+        cocotb.start_soon(Clock(dut.logic_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.stat_clk, self.clk_period, units="ns").start())
+        cocotb.start_soon(Clock(dut.ptp_sample_clk, 9.9, units="ns").start())
+
+        self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip)
+        self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk)
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
+        self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.logic_clk)
+
+        dut.ptp_ts_step.setimmediatevalue(0)
+
+        dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_tx_ifg.setimmediatevalue(0)
+        dut.cfg_tx_enable.setimmediatevalue(0)
+        dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
+        dut.cfg_rx_enable.setimmediatevalue(0)
+        dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
+        dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.logic_rst.setimmediatevalue(0)
+        self.dut.rx_rst.setimmediatevalue(0)
+        self.dut.tx_rst.setimmediatevalue(0)
+        self.dut.stat_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.logic_clk)
+        await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 1
+        self.dut.rx_rst.value = 1
+        self.dut.tx_rst.value = 1
+        self.dut.stat_rst.value = 1
+        await RisingEdge(self.dut.logic_clk)
+        await RisingEdge(self.dut.logic_clk)
+        self.dut.logic_rst.value = 0
+        self.dut.rx_rst.value = 0
+        self.dut.tx_rst.value = 0
+        self.dut.stat_rst.value = 0
+        await RisingEdge(self.dut.logic_clk)
+        await RisingEdge(self.dut.logic_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_rx_max_pkt_len.value = 9218
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    tb.log.info("Wait for block lock")
+    while not dut.rx_block_lock.value.integer:
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Wait for PTP CDC lock")
+    while not dut.uut.rx_ptp_locked.value.integer:
+        await RisingEdge(dut.rx_clk)
+    for k in range(1000):
+        await RisingEdge(dut.rx_clk)
+
+    # clear out sink buffer
+    tb.axis_sink.clear()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.serdes_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.axis_sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        if tx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            tx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*4) < tb.clk_period*2
+
+    assert tb.axis_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    tb.log.info("Wait for PTP CDC lock")
+    while not dut.uut.tx_ptp_locked.value.integer:
+        await RisingEdge(dut.tx_clk)
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+    for test_data in test_frames:
+        rx_frame = await tb.serdes_sink.recv()
+        tx_cpl = await tb.tx_cpl_sink.recv()
+
+        ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+        rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+        if rx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            rx_frame_sfd_ns -= tb.clk_period/2
+
+        tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+        assert rx_frame.ctrl is None
+        assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < tb.clk_period*2
+
+    assert tb.serdes_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
+
+    dic_en = int(cocotb.top.DIC_EN.value)
+
+    tb = TB(dut)
+
+    byte_width = tb.axis_source.width // 8
+
+    tb.serdes_source.ifg = ifg
+    tb.dut.cfg_tx_max_pkt_len.value = 9218
+    tb.dut.cfg_tx_ifg.value = ifg
+    tb.dut.cfg_tx_enable.value = 1
+
+    await tb.reset()
+
+    tb.log.info("Wait for PTP CDC lock")
+    while not dut.uut.tx_ptp_locked.value.integer:
+        await RisingEdge(dut.tx_clk)
+    for k in range(1000):
+        await RisingEdge(dut.tx_clk)
+
+    for length in range(60, 92):
+
+        for k in range(10):
+            await RisingEdge(dut.tx_clk)
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
+
+        for test_data in test_frames:
+            rx_frame = await tb.serdes_sink.recv()
+            tx_cpl = await tb.tx_cpl_sink.recv()
+
+            ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
+
+            rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
+
+            if rx_frame.start_lane == 4:
+                # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+                rx_frame_sfd_ns -= 3.2
+
+            tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
+            tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
+            tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+            assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*5) < tb.clk_period*2
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_width
+
+            if dic_en:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_width
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.logic_clk)
+
+    assert tb.serdes_sink.empty()
+
+    await RisingEdge(dut.logic_clk)
+    await RisingEdge(dut.logic_clk)
+
+
+async def run_test_rx_frame_sync(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.log.info("Wait for block lock")
+    while not dut.rx_block_lock.value.integer:
+        await RisingEdge(dut.rx_clk)
+
+    assert dut.rx_block_lock.value.integer
+
+    tb.log.info("Change offset")
+    tb.serdes_source.bit_offset = 33
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Check for lock lost")
+    assert not dut.rx_block_lock.value.integer
+    assert dut.rx_high_ber.value.integer
+
+    for k in range(500):
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Check for block lock")
+    assert dut.rx_block_lock.value.integer
+
+    for k in range(300):
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Check for high BER deassert")
+    assert not dut.rx_high_ber.value.integer
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12, 0])
+        factory.generate_tests()
+
+    factory = TestFactory(run_test_tx_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_rx_frame_sync)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("dic_en", [1, 0])
+@pytest.mark.parametrize("data_w", [64])
+def test_taxi_eth_mac_phy_10g_fifo(request, data_w, dic_en):
+    dut = "taxi_eth_mac_phy_10g_fifo"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['HDR_W'] = 2
+    parameters['AXIS_DATA_W'] = parameters['DATA_W']
+    parameters['PADDING_EN'] = 1
+    parameters['DIC_EN'] = dic_en
+    parameters['MIN_FRAME_LEN'] = 64
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+    parameters['TX_TAG_W'] = 16
+    parameters['BIT_REVERSE'] = 0
+    parameters['SCRAMBLER_DISABLE'] = 0
+    parameters['PRBS31_EN'] = 1
+    parameters['TX_SERDES_PIPELINE'] = 2
+    parameters['RX_SERDES_PIPELINE'] = 2
+    parameters['BITSLIP_HIGH_CYCLES'] = 0
+    parameters['BITSLIP_LOW_CYCLES'] = 7
+    parameters['COUNT_125US'] = int(1250/6.4)
+    parameters['STAT_EN'] = 1
+    parameters['STAT_TX_LEVEL'] = 2
+    parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
+    parameters['STAT_ID_BASE'] = 0
+    parameters['STAT_UPDATE_PERIOD'] = 1024
+    parameters['STAT_STR_EN'] = 1
+    parameters['STAT_PREFIX_STR'] = "\"MAC\""
+    parameters['TX_FIFO_DEPTH'] = 16384
+    parameters['TX_FIFO_RAM_PIPELINE'] = 1
+    parameters['TX_FRAME_FIFO'] = 1
+    parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
+    parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
+    parameters['TX_DROP_WHEN_FULL'] = 0
+    parameters['TX_CPL_FIFO_DEPTH'] = 64
+    parameters['RX_FIFO_DEPTH'] = 16384
+    parameters['RX_FIFO_RAM_PIPELINE'] = 1
+    parameters['RX_FRAME_FIFO'] = 1
+    parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
+    parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
+    parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv

@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * 10G Ethernet MAC with TX and RX FIFOs testbench
+ */
+module test_taxi_eth_mac_phy_10g_fifo #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 8,
+    parameter HDR_W = 2,
+    parameter AXIS_DATA_W = 8,
+    parameter logic PADDING_EN = 1'b1,
+    parameter logic DIC_EN = 1'b1,
+    parameter MIN_FRAME_LEN = 64,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
+    parameter TX_TAG_W = 16,
+    parameter logic BIT_REVERSE = 1'b0,
+    parameter logic SCRAMBLER_DISABLE = 1'b0,
+    parameter logic PRBS31_EN = 1'b0,
+    parameter TX_SERDES_PIPELINE = 0,
+    parameter RX_SERDES_PIPELINE = 0,
+    parameter BITSLIP_HIGH_CYCLES = 0,
+    parameter BITSLIP_LOW_CYCLES = 7,
+    parameter COUNT_125US = 125000/6.4,
+    parameter logic STAT_EN = 1'b0,
+    parameter STAT_TX_LEVEL = 1,
+    parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
+    parameter STAT_ID_BASE = 0,
+    parameter STAT_UPDATE_PERIOD = 1024,
+    parameter logic STAT_STR_EN = 1'b1,
+    parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC",
+    parameter TX_FIFO_DEPTH = 4096,
+    parameter TX_FIFO_RAM_PIPELINE = 1,
+    parameter logic TX_FRAME_FIFO = 1'b1,
+    parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
+    parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
+    parameter logic TX_DROP_WHEN_FULL = 1'b0,
+    parameter TX_CPL_FIFO_DEPTH = 64,
+    parameter RX_FIFO_DEPTH = 4096,
+    parameter RX_FIFO_RAM_PIPELINE = 1,
+    parameter logic RX_FRAME_FIFO = 1'b1,
+    parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
+    parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
+    parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam TX_USER_W = 1;
+localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic rx_clk;
+logic rx_rst;
+logic tx_clk;
+logic tx_rst;
+logic logic_clk;
+logic logic_rst;
+logic ptp_sample_clk;
+
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
+taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
+
+logic [DATA_W-1:0] serdes_tx_data;
+logic [HDR_W-1:0] serdes_tx_hdr;
+logic [DATA_W-1:0] serdes_rx_data;
+logic [HDR_W-1:0] serdes_rx_hdr;
+logic serdes_rx_bitslip;
+logic serdes_rx_reset_req;
+
+logic [PTP_TS_W-1:0] ptp_ts;
+logic ptp_ts_step;
+
+logic stat_clk;
+logic stat_rst;
+taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
+
+logic tx_error_underflow;
+logic tx_fifo_overflow;
+logic tx_fifo_bad_frame;
+logic tx_fifo_good_frame;
+logic rx_error_bad_frame;
+logic rx_error_bad_fcs;
+logic rx_bad_block;
+logic rx_sequence_error;
+logic rx_block_lock;
+logic rx_high_ber;
+logic rx_status;
+logic rx_fifo_overflow;
+logic rx_fifo_bad_frame;
+logic rx_fifo_good_frame;
+
+logic [15:0] cfg_tx_max_pkt_len;
+logic [7:0] cfg_tx_ifg;
+logic cfg_tx_enable;
+logic [15:0] cfg_rx_max_pkt_len;
+logic cfg_rx_enable;
+logic cfg_tx_prbs31_enable;
+logic cfg_rx_prbs31_enable;
+
+taxi_eth_mac_phy_10g_fifo #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .PADDING_EN(PADDING_EN),
+    .DIC_EN(DIC_EN),
+    .MIN_FRAME_LEN(MIN_FRAME_LEN),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W),
+    .BIT_REVERSE(BIT_REVERSE),
+    .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
+    .PRBS31_EN(PRBS31_EN),
+    .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
+    .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
+    .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
+    .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
+    .COUNT_125US(COUNT_125US),
+    .STAT_EN(STAT_EN),
+    .STAT_TX_LEVEL(STAT_TX_LEVEL),
+    .STAT_RX_LEVEL(STAT_RX_LEVEL),
+    .STAT_ID_BASE(STAT_ID_BASE),
+    .STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
+    .STAT_STR_EN(STAT_STR_EN),
+    .STAT_PREFIX_STR(STAT_PREFIX_STR),
+    .TX_FIFO_DEPTH(TX_FIFO_DEPTH),
+    .TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
+    .TX_FRAME_FIFO(TX_FRAME_FIFO),
+    .TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
+    .TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
+    .TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
+    .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
+    .RX_FIFO_DEPTH(RX_FIFO_DEPTH),
+    .RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
+    .RX_FRAME_FIFO(RX_FRAME_FIFO),
+    .RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
+    .RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
+    .RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
+)
+uut (
+    .rx_clk(rx_clk),
+    .rx_rst(rx_rst),
+    .tx_clk(tx_clk),
+    .tx_rst(tx_rst),
+    .logic_clk(logic_clk),
+    .logic_rst(logic_rst),
+    .ptp_sample_clk(ptp_sample_clk),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(s_axis_tx),
+    .m_axis_tx_cpl(m_axis_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * SERDES interface
+     */
+    .serdes_tx_data(serdes_tx_data),
+    .serdes_tx_hdr(serdes_tx_hdr),
+    .serdes_rx_data(serdes_rx_data),
+    .serdes_rx_hdr(serdes_rx_hdr),
+    .serdes_rx_bitslip(serdes_rx_bitslip),
+    .serdes_rx_reset_req(serdes_rx_reset_req),
+
+    /*
+     * PTP clock
+     */
+    .ptp_ts(ptp_ts),
+    .ptp_ts_step(ptp_ts_step),
+
+    /*
+     * Statistics
+     */
+    .stat_clk(stat_clk),
+    .stat_rst(stat_rst),
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(tx_error_underflow),
+    .tx_fifo_overflow(tx_fifo_overflow),
+    .tx_fifo_bad_frame(tx_fifo_bad_frame),
+    .tx_fifo_good_frame(tx_fifo_good_frame),
+    .rx_error_bad_frame(rx_error_bad_frame),
+    .rx_error_bad_fcs(rx_error_bad_fcs),
+    .rx_bad_block(rx_bad_block),
+    .rx_sequence_error(rx_sequence_error),
+    .rx_block_lock(rx_block_lock),
+    .rx_high_ber(rx_high_ber),
+    .rx_status(rx_status),
+    .rx_fifo_overflow(rx_fifo_overflow),
+    .rx_fifo_bad_frame(rx_fifo_bad_frame),
+    .rx_fifo_good_frame(rx_fifo_good_frame),
+
+    /*
+     * Configuration
+     */
+    .cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
+    .cfg_tx_ifg(cfg_tx_ifg),
+    .cfg_tx_enable(cfg_tx_enable),
+    .cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
+    .cfg_rx_enable(cfg_rx_enable),
+    .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
+    .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_eth_phy_10g/Makefile

@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_eth_phy_10g
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_HDR_W := 2
+export PARAM_BIT_REVERSE := "1'b0"
+export PARAM_SCRAMBLER_DISABLE := "1'b0"
+export PARAM_PRBS31_EN := "1'b1"
+export PARAM_TX_SERDES_PIPELINE := 2
+export PARAM_RX_SERDES_PIPELINE := 2
+export PARAM_BITSLIP_HIGH_CYCLES := 0
+export PARAM_BITSLIP_LOW_CYCLES := 7
+export PARAM_COUNT_125US := 195
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_eth_phy_10g/baser.py

@@ -0,0 +1 @@
+../baser.py

src/eth/tb/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py

@@ -0,0 +1,259 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame
+
+try:
+    from baser import BaseRSerdesSource, BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource, BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.tx_clk, 6.4, units="ns").start())
+        cocotb.start_soon(Clock(dut.rx_clk, 6.4, units="ns").start())
+
+        self.xgmii_source = XgmiiSource(dut.xgmii_txd, dut.xgmii_txc, dut.tx_clk, dut.tx_rst)
+        self.xgmii_sink = XgmiiSink(dut.xgmii_rxd, dut.xgmii_rxc, dut.rx_clk, dut.rx_rst)
+
+        self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip)
+        self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk)
+
+        dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
+        dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.tx_rst.setimmediatevalue(0)
+        self.dut.rx_rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+        self.dut.tx_rst.value = 1
+        self.dut.rx_rst.value = 1
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+        self.dut.tx_rst.value = 0
+        self.dut.rx_rst.value = 0
+        await RisingEdge(self.dut.tx_clk)
+        await RisingEdge(self.dut.tx_clk)
+
+
+async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.serdes_source.ifg = ifg
+
+    await tb.reset()
+
+    tb.log.info("Wait for block lock")
+    while not int(dut.rx_block_lock.value):
+        await RisingEdge(dut.rx_clk)
+
+    # clear out sink buffer
+    tb.xgmii_sink.clear()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data)
+        await tb.serdes_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.xgmii_sink.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+
+    assert tb.xgmii_sink.empty()
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.xgmii_source.ifg = ifg
+    tb.serdes_source.ifg = ifg
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data)
+        await tb.xgmii_source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.serdes_sink.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+
+    assert tb.serdes_sink.empty()
+
+    await RisingEdge(dut.tx_clk)
+    await RisingEdge(dut.tx_clk)
+
+
+async def run_test_rx_frame_sync(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.log.info("Wait for block lock")
+    while not int(dut.rx_block_lock.value):
+        await RisingEdge(dut.rx_clk)
+
+    assert int(dut.rx_block_lock.value)
+
+    tb.log.info("Change offset")
+    tb.serdes_source.bit_offset = 33
+
+    for k in range(100):
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Check for lock lost")
+    assert not int(dut.rx_block_lock.value)
+    assert int(dut.rx_high_ber.value)
+
+    for k in range(500):
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Check for block lock")
+    assert int(dut.rx_block_lock.value)
+
+    for k in range(300):
+        await RisingEdge(dut.rx_clk)
+
+    tb.log.info("Check for high BER deassert")
+    assert not int(dut.rx_high_ber.value)
+
+    await RisingEdge(dut.rx_clk)
+    await RisingEdge(dut.rx_clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_rx, run_test_tx]:
+
+        factory = TestFactory(test)
+        factory.add_option("payload_lengths", [size_list])
+        factory.add_option("payload_data", [incrementing_payload])
+        factory.add_option("ifg", [12])
+        factory.generate_tests()
+
+    factory = TestFactory(run_test_rx_frame_sync)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_eth_phy_10g(request):
+    dut = "taxi_eth_phy_10g"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 64
+    parameters['CTRL_W'] = parameters['DATA_W'] // 8
+    parameters['HDR_W'] = 2
+    parameters['BIT_REVERSE'] = "1'b0"
+    parameters['SCRAMBLER_DISABLE'] = "1'b0"
+    parameters['PRBS31_EN'] = "1'b1"
+    parameters['TX_SERDES_PIPELINE'] = 2
+    parameters['RX_SERDES_PIPELINE'] = 2
+    parameters['BITSLIP_HIGH_CYCLES'] = 0
+    parameters['BITSLIP_LOW_CYCLES'] = 7
+    parameters['COUNT_125US'] = int(1250/6.4)
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    extra_env['COCOTB_RESOLVE_X'] = 'RANDOM'
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_mac_ctrl_rx/Makefile

@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_mac_ctrl_rx
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 8
+export PARAM_ID_W := 8
+export PARAM_DEST_W := 8
+export PARAM_USER_W := 1
+export PARAM_USE_READY := 1
+export PARAM_MCF_PARAMS_SIZE := 18
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.py

@@ -0,0 +1,594 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+from scapy.layers.l2 import Ether
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+from cocotbext.axi.stream import define_stream
+
+
+McfBus, McfTransaction, McfSource, McfSink, McfMonitor = define_stream("Mcf",
+    signals=["valid", "eth_dst", "eth_src", "eth_type", "opcode", "params"],
+    optional_signals=["ready", "id", "dest", "user"]
+)
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
+
+        self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
+        self.mcf_sink = McfSink(McfBus.from_prefix(dut, "mcf"), dut.clk, dut.rst)
+
+        dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0)
+        dut.cfg_mcf_rx_eth_type.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0)
+        dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0)
+
+        dut.cfg_mcf_rx_forward.setimmediatevalue(0)
+        dut.cfg_mcf_rx_enable.setimmediatevalue(0)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.source.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.sink.set_pause_generator(generator())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+    async def send(self, pkt):
+        await self.source.send(bytes(pkt))
+
+    async def recv(self):
+        rx_frame = await self.sink.recv()
+
+        assert not rx_frame.tuser
+
+        return Ether(bytes(rx_frame))
+
+    async def recv_mcf(self):
+        rx_frame = await self.mcf_sink.recv()
+
+        data = bytearray()
+        data.extend(rx_frame.eth_dst.integer.to_bytes(6, 'big'))
+        data.extend(rx_frame.eth_src.integer.to_bytes(6, 'big'))
+        data.extend(rx_frame.eth_type.integer.to_bytes(2, 'big'))
+        data.extend(rx_frame.opcode.integer.to_bytes(2, 'big'))
+        data.extend(rx_frame.params.integer.to_bytes(44, 'little'))
+
+        return Ether(data)
+
+
+async def run_test_data(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    id_width = len(tb.source.bus.tid)
+    id_count = 2**id_width
+    id_mask = id_count-1
+
+    src_width = 1
+    src_mask = 2**src_width-1 if src_width else 0
+    src_shift = id_width-src_width
+    max_count = 2**src_shift
+    count_mask = max_count-1
+
+    cur_id = 1
+
+    await tb.reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    test_frames = []
+
+    for test_data in [payload_data(x) for x in payload_lengths()]:
+        test_frame = AxiStreamFrame(test_data)
+        test_frame.tid = cur_id
+        test_frame.tdest = cur_id | (0 << src_shift)
+
+        test_frames.append(test_frame)
+        await tb.source.send(test_frame)
+
+        cur_id = (cur_id + 1) % max_count
+
+    for test_frame in test_frames:
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.tdata == test_frame.tdata
+        assert rx_frame.tid == test_frame.tid
+        assert rx_frame.tdest == test_frame.tdest
+        assert not rx_frame.tuser
+
+    assert tb.sink.empty()
+    assert tb.mcf_sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_mcf(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    id_width = len(tb.source.bus.tid)
+    id_count = 2**id_width
+    id_mask = id_count-1
+
+    src_width = 1
+    src_mask = 2**src_width-1 if src_width else 0
+    src_shift = id_width-src_width
+    max_count = 2**src_shift
+    count_mask = max_count-1
+
+    cur_id = 1
+
+    await tb.reset()
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 0
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 0
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    test_pkts = []
+
+    for payload in [payload_data(x) for x in payload_lengths()]:
+        eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+        test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload)
+        test_pkts.append((cur_id, test_pkt.copy()))
+
+        test_frame = AxiStreamFrame(bytes(test_pkt))
+        test_frame.tid = cur_id
+        test_frame.tdest = cur_id | (1 << src_shift)
+
+        await tb.source.send(test_frame)
+
+        cur_id = (cur_id + 1) % max_count
+
+    for cur_id, test_pkt in test_pkts:
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.tdata == bytes(test_pkt)
+        assert rx_frame.tid == cur_id
+        assert rx_frame.tdest == cur_id | (1 << src_shift)
+        assert rx_frame.tuser
+
+        rx_pkt = await tb.recv_mcf()
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        # check prefix as padding may be different
+        assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tb.sink.empty()
+    assert tb.mcf_sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_tuser_assert(dut):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.source.byte_lanes
+
+    await tb.reset()
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 0
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 0
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    # data
+    payload = bytearray(itertools.islice(itertools.cycle(range(256)), byte_lanes*16))
+    eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+    test_pkt = eth / payload
+    test_frame = AxiStreamFrame(bytes(test_pkt), tuser=1)
+    await tb.source.send(test_frame)
+
+    rx_frame = await tb.sink.recv()
+
+    assert rx_frame.tdata == test_frame.tdata
+    assert rx_frame.tuser
+
+    # MAC control
+    payload = bytearray(itertools.islice(itertools.cycle(range(256)), 18))
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    test_frame = AxiStreamFrame(bytes(test_pkt), tuser=1)
+    await tb.source.send(test_frame)
+
+    rx_frame = await tb.sink.recv()
+
+    assert rx_frame.tdata == test_frame.tdata
+    assert rx_frame.tuser
+
+    assert tb.sink.empty()
+    assert tb.mcf_sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_mcf_filter(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 0
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 0
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    async def check(tb, pkt, should_match):
+        await tb.source.send(bytes(pkt))
+
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.tdata == bytes(pkt)
+
+        if should_match:
+            assert rx_frame.tuser
+
+            rx_pkt = await tb.recv_mcf()
+
+            assert bytes(rx_pkt).find(bytes(pkt)) == 0
+        else:
+            assert not rx_frame.tuser
+
+        assert tb.sink.empty()
+        assert tb.mcf_sink.empty()
+
+    payload = bytearray(itertools.islice(itertools.cycle(range(256)), 18))
+
+    # Multicast destination address
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    await check(tb, test_pkt, True)
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8808)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    await check(tb, test_pkt, False)
+
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0
+
+    # Unicast destination address
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 1
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8808)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    await check(tb, test_pkt, True)
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    await check(tb, test_pkt, False)
+
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+
+    # Source address
+    dut.cfg_mcf_rx_check_eth_src.value = 1
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    await check(tb, test_pkt, True)
+
+    eth = Ether(src='5A:51:52:AA:AA:AA', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    await check(tb, test_pkt, False)
+
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+
+    # Ethertype
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    await check(tb, test_pkt, True)
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8880)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    await check(tb, test_pkt, False)
+
+    # Opcode
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 1
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 1
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (b'\x00\x01' + payload)
+    await check(tb, test_pkt, True)
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (b'\x01\x01' + payload)
+    await check(tb, test_pkt, True)
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (b'\x00\x00' + payload)
+    await check(tb, test_pkt, False)
+
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 0
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 0
+
+    assert tb.sink.empty()
+    assert tb.mcf_sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.source.byte_lanes
+    id_width = len(tb.source.bus.tid)
+    id_count = 2**id_width
+    id_mask = id_count-1
+
+    src_width = 1
+    src_mask = 2**src_width-1 if src_width else 0
+    src_shift = id_width-src_width
+    max_count = 2**src_shift
+    count_mask = max_count-1
+
+    cur_id = 1
+
+    await tb.reset()
+
+    dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
+    dut.cfg_mcf_rx_check_eth_dst_mcast.value = 0
+    dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
+    dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
+    dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
+    dut.cfg_mcf_rx_check_eth_src.value = 0
+    dut.cfg_mcf_rx_eth_type.value = 0x8808
+    dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
+    dut.cfg_mcf_rx_check_opcode_lfc.value = 0
+    dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
+    dut.cfg_mcf_rx_check_opcode_pfc.value = 0
+
+    dut.cfg_mcf_rx_forward.value = 0
+    dut.cfg_mcf_rx_enable.value = 1
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    test_pkts = []
+
+    for k in range(256):
+        if random.randrange(8) != 0:
+            length = random.randint(1, byte_lanes*16)
+            payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+            eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+            test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload)
+            test_pkts.append((cur_id, test_pkt.copy()))
+            dest = cur_id | (0 << src_shift)
+        else:
+            length = random.randint(1, 18)
+            payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+            eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+            test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload)
+            test_pkts.append((cur_id, test_pkt.copy()))
+            dest = cur_id | (1 << src_shift)
+
+        test_frame = AxiStreamFrame(bytes(test_pkt))
+        test_frame.tid = cur_id
+        test_frame.tdest = dest
+
+        await tb.source.send(test_frame)
+
+        cur_id = (cur_id + 1) % max_count
+
+    for cur_id, test_pkt in test_pkts:
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.tdata == bytes(test_pkt)
+        assert rx_frame.tid == cur_id
+        assert (rx_frame.tdest & count_mask) == cur_id
+
+        if rx_frame.tdest >> src_shift:
+            assert rx_frame.tuser
+
+            rx_pkt = await tb.recv_mcf()
+
+            tb.log.info("RX packet: %s", repr(rx_pkt))
+
+            # check prefix as padding may be different
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+        else:
+            assert not rx_frame.tuser
+
+    for k in range(1000):
+        await RisingEdge(dut.clk)
+
+    assert tb.sink.empty()
+    assert tb.mcf_sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+def size_list():
+    return list(range(1, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def mcf_size_list():
+    return list(range(1, 19))
+
+
+def incrementing_payload(length):
+    return bytes(itertools.islice(itertools.cycle(range(256)), length))
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test_data)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_mcf)
+    factory.add_option("payload_lengths", [mcf_size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_tuser_assert)
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_mcf_filter)
+    factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32, 64, 128, 256, 512])
+def test_taxi_mac_ctrl_rx(request, data_w):
+    dut = "taxi_mac_ctrl_rx"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['ID_W'] = 8
+    parameters['DEST_W'] = 8
+    parameters['USER_W'] = 1
+    parameters['USE_READY'] = 1
+    parameters['MCF_PARAMS_SIZE'] = 18
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.sv

@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * MAC control receiver testbench
+ */
+module test_taxi_mac_ctrl_rx #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter ID_W = 8,
+    parameter DEST_W = 8,
+    parameter USER_W = 1,
+    parameter logic USE_READY = 1'b0,
+    parameter MCF_PARAMS_SIZE = 18
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .ID_EN(1), .ID_W(ID_W), .DEST_EN(1), .DEST_W(DEST_W), .USER_EN(1), .USER_W(USER_W)) s_axis(), m_axis();
+
+logic mcf_valid;
+logic [47:0] mcf_eth_dst;
+logic [47:0] mcf_eth_src;
+logic [15:0] mcf_eth_type;
+logic [15:0] mcf_opcode;
+logic [MCF_PARAMS_SIZE*8-1:0] mcf_params;
+logic [ID_W-1:0] mcf_id;
+logic [DEST_W-1:0] mcf_dest;
+logic [USER_W-1:0] mcf_user;
+
+logic [47:0] cfg_mcf_rx_eth_dst_mcast;
+logic cfg_mcf_rx_check_eth_dst_mcast;
+logic [47:0] cfg_mcf_rx_eth_dst_ucast;
+logic cfg_mcf_rx_check_eth_dst_ucast;
+logic [47:0] cfg_mcf_rx_eth_src;
+logic cfg_mcf_rx_check_eth_src;
+logic [15:0] cfg_mcf_rx_eth_type;
+logic [15:0] cfg_mcf_rx_opcode_lfc;
+logic cfg_mcf_rx_check_opcode_lfc;
+logic [15:0] cfg_mcf_rx_opcode_pfc;
+logic cfg_mcf_rx_check_opcode_pfc;
+logic cfg_mcf_rx_forward;
+logic cfg_mcf_rx_enable;
+
+logic stat_rx_mcf;
+
+taxi_mac_ctrl_rx #(
+    .ID_W(ID_W),
+    .DEST_W(DEST_W),
+    .USER_W(USER_W),
+    .USE_READY(USE_READY),
+    .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    .s_axis(s_axis),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis(m_axis),
+
+    /*
+     * MAC control frame interface
+     */
+    .mcf_valid(mcf_valid),
+    .mcf_eth_dst(mcf_eth_dst),
+    .mcf_eth_src(mcf_eth_src),
+    .mcf_eth_type(mcf_eth_type),
+    .mcf_opcode(mcf_opcode),
+    .mcf_params(mcf_params),
+    .mcf_id(mcf_id),
+    .mcf_dest(mcf_dest),
+    .mcf_user(mcf_user),
+
+    /*
+     * Configuration
+     */
+    .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
+    .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
+    .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
+    .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
+    .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
+    .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
+    .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
+    .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
+    .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
+    .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
+    .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
+    .cfg_mcf_rx_forward(cfg_mcf_rx_forward),
+    .cfg_mcf_rx_enable(cfg_mcf_rx_enable),
+
+    /*
+     * Status
+     */
+    .stat_rx_mcf(stat_rx_mcf)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_mac_ctrl_tx/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_mac_ctrl_tx
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 8
+export PARAM_ID_W := 8
+export PARAM_DEST_W := 8
+export PARAM_USER_W := 1
+export PARAM_MCF_PARAMS_SIZE := 18
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.py

@@ -0,0 +1,475 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+from scapy.layers.l2 import Ether
+from scapy.utils import mac2str
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import FallingEdge, RisingEdge, Event
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
+from cocotbext.axi.stream import define_stream
+
+
+McfBus, McfTransaction, McfSource, McfSink, McfMonitor = define_stream("Mcf",
+    signals=["valid", "eth_dst", "eth_src", "eth_type", "opcode", "params"],
+    optional_signals=["ready", "id", "dest", "user"]
+)
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
+
+        self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
+        self.mcf_source = McfSource(McfBus.from_prefix(dut, "mcf"), dut.clk, dut.rst)
+
+        dut.tx_pause_req.setimmediatevalue(0)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.source.set_pause_generator(generator())
+            self.mcf_source.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.sink.set_pause_generator(generator())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+    async def send(self, pkt):
+        await self.source.send(bytes(pkt))
+
+    async def send_mcf(self, pkt):
+        mcf = McfTransaction()
+        mcf.eth_dst = int.from_bytes(mac2str(pkt[Ether].dst), 'big')
+        mcf.eth_src = int.from_bytes(mac2str(pkt[Ether].src), 'big')
+        mcf.eth_type = pkt[Ether].type
+        mcf.opcode = int.from_bytes(bytes(pkt[Ether].payload)[0:2], 'big')
+        mcf.params = int.from_bytes(bytes(pkt[Ether].payload)[2:], 'little')
+
+        await self.mcf_source.send(mcf)
+
+    async def recv(self):
+        rx_frame = await self.sink.recv()
+
+        assert not rx_frame.tuser
+
+        return Ether(bytes(rx_frame))
+
+
+async def run_test_data(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    id_width = len(tb.source.bus.tid)
+    id_count = 2**id_width
+    id_mask = id_count-1
+
+    src_width = 1
+    src_mask = 2**src_width-1 if src_width else 0
+    src_shift = id_width-src_width
+    max_count = 2**src_shift
+    count_mask = max_count-1
+
+    cur_id = 1
+
+    await tb.reset()
+
+    dut.tx_pause_req.value = 0
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    test_frames = []
+
+    for test_data in [payload_data(x) for x in payload_lengths()]:
+        test_frame = AxiStreamFrame(test_data)
+        test_frame.tid = cur_id | (0 << src_shift)
+        test_frame.tdest = cur_id
+
+        test_frames.append(test_frame)
+        await tb.source.send(test_frame)
+
+        cur_id = (cur_id + 1) % max_count
+
+    for test_frame in test_frames:
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.tdata == test_frame.tdata
+        assert rx_frame.tid == test_frame.tid
+        assert rx_frame.tdest == test_frame.tdest
+        assert not rx_frame.tuser
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_mcf(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    dut.tx_pause_req.value = 0
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    test_pkts = []
+
+    opcode = 1
+
+    for payload in [payload_data(x) for x in payload_lengths()]:
+        eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+        test_pkt = eth / (opcode.to_bytes(2, 'big') + payload)
+        test_pkts.append(test_pkt.copy())
+
+        await tb.send_mcf(test_pkt)
+
+        opcode += 1
+
+    for test_pkt in test_pkts:
+        rx_pkt = await tb.recv()
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        # check prefix as frame gets zero-padded
+        assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_tuser_assert(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    dut.tx_pause_req.value = 0
+
+    test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
+    test_frame = AxiStreamFrame(test_data, tuser=1)
+    await tb.source.send(test_frame)
+
+    rx_frame = await tb.sink.recv()
+
+    assert rx_frame.tdata == test_frame.tdata
+    assert rx_frame.tuser
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_arb_test(dut):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.source.byte_lanes
+    id_width = len(tb.source.bus.tid)
+    id_count = 2**id_width
+    id_mask = id_count-1
+
+    src_width = 1
+    src_mask = 2**src_width-1 if src_width else 0
+    src_shift = id_width-src_width
+    max_count = 2**src_shift
+    count_mask = max_count-1
+
+    cur_id = 1
+
+    await tb.reset()
+
+    dut.tx_pause_req.value = 0
+
+    test_pkts = []
+    test_frames = []
+
+    for k in range(4):
+        length = byte_lanes*16
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload)
+        test_pkts.append((cur_id, test_pkt.copy()))
+
+        test_frame = AxiStreamFrame(bytes(test_pkt), tx_complete=Event())
+        test_frame.tid = cur_id | (0 << src_shift)
+        test_frame.tdest = cur_id
+        test_frames.append(test_frame)
+
+        await tb.source.send(test_frame)
+
+        cur_id = (cur_id + 1) % max_count
+
+    length = random.randint(1, 18)
+    payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload)
+    test_pkts.append((cur_id, test_pkt.copy()))
+
+    # start transmit in the middle of frame 2
+    await test_frames[1].tx_complete.wait()
+    for j in range(8):
+        await RisingEdge(dut.clk)
+    await tb.send_mcf(test_pkt)
+    await FallingEdge(dut.mcf_valid)
+
+    cur_id = (cur_id + 1) % max_count
+
+    for k in [0, 1, 2, 4, 3]:
+        rx_frame = await tb.sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        cur_id, test_pkt = test_pkts[k]
+
+        if rx_pkt.type == 0x8808:
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            assert rx_frame.tid == 0
+            assert rx_frame.tdest == 0
+        else:
+            assert bytes(rx_pkt) == bytes(test_pkt)
+            assert rx_frame.tid == cur_id | (0 << src_shift)
+            assert rx_frame.tdest == cur_id
+
+        assert not rx_frame.tuser
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.source.byte_lanes
+    id_width = len(tb.source.bus.tid)
+    id_count = 2**id_width
+    id_mask = id_count-1
+
+    src_width = 1
+    src_mask = 2**src_width-1 if src_width else 0
+    src_shift = id_width-src_width
+    max_count = 2**src_shift
+    count_mask = max_count-1
+
+    cur_id = 1
+
+    await tb.reset()
+
+    dut.tx_pause_req.value = 0
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    test_pkts = [list() for x in range(2)]
+
+    for k in range(256):
+        length = random.randint(1, byte_lanes*16)
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
+        test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload)
+        test_pkts[0].append((cur_id, test_pkt.copy()))
+
+        test_frame = AxiStreamFrame(bytes(test_pkt))
+        test_frame.tid = cur_id | (0 << src_shift)
+        test_frame.tdest = cur_id
+
+        await tb.source.send(test_frame)
+
+        cur_id = (cur_id + 1) % max_count
+
+    for k in range(16):
+        length = random.randint(1, 18)
+        payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+        eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+        test_pkt = eth / (cur_id.to_bytes(2, 'big') + payload)
+        test_pkts[1].append((cur_id, test_pkt.copy()))
+
+        for c in range(random.randint(8, 64)):
+            await RisingEdge(dut.clk)
+        await tb.send_mcf(test_pkt)
+        await FallingEdge(dut.mcf_valid)
+
+        cur_id = (cur_id + 1) % max_count
+
+    while any(test_pkts):
+        rx_frame = await tb.sink.recv()
+
+        rx_pkt = Ether(bytes(rx_frame))
+
+        tb.log.info("RX packet: %s", repr(rx_pkt))
+
+        test_pkt = None
+
+        if rx_pkt.type == 0x8808:
+            cur_id, test_pkt = test_pkts[1].pop(0)
+            # check prefix as frame gets zero-padded
+            assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
+            assert rx_frame.tid == 0
+            assert rx_frame.tdest == 0
+        else:
+            cur_id, test_pkt = test_pkts[0].pop(0)
+            assert bytes(rx_pkt) == bytes(test_pkt)
+            assert rx_frame.tid == cur_id | (0 << src_shift)
+            assert rx_frame.tdest == cur_id
+
+        assert not rx_frame.tuser
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+def size_list():
+    return list(range(1, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def mcf_size_list():
+    return list(range(1, 19))
+
+
+def incrementing_payload(length):
+    return bytes(itertools.islice(itertools.cycle(range(256)), length))
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test_data)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_mcf)
+    factory.add_option("payload_lengths", [mcf_size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_tuser_assert)
+    factory.generate_tests()
+
+    factory = TestFactory(run_arb_test)
+    factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32, 64, 128, 256, 512])
+def test_taxi_mac_ctrl_tx(request, data_w):
+    dut = "taxi_mac_ctrl_tx"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['ID_W'] = 8
+    parameters['DEST_W'] = 8
+    parameters['USER_W'] = 1
+    parameters['MCF_PARAMS_SIZE'] = 18
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.sv

@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * MAC control transmitter testbench
+ */
+module test_taxi_mac_ctrl_tx #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter ID_W = 8,
+    parameter DEST_W = 8,
+    parameter USER_W = 1,
+    parameter MCF_PARAMS_SIZE = 18
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(DATA_W), .ID_EN(1), .ID_W(ID_W), .DEST_EN(1), .DEST_W(DEST_W), .USER_EN(1), .USER_W(USER_W)) s_axis(), m_axis();
+
+logic mcf_valid;
+logic mcf_ready;
+logic [47:0] mcf_eth_dst;
+logic [47:0] mcf_eth_src;
+logic [15:0] mcf_eth_type;
+logic [15:0] mcf_opcode;
+logic [MCF_PARAMS_SIZE*8-1:0] mcf_params;
+logic [ID_W-1:0] mcf_id;
+logic [DEST_W-1:0] mcf_dest;
+logic [USER_W-1:0] mcf_user;
+
+logic tx_pause_req;
+logic tx_pause_ack;
+
+logic stat_tx_mcf;
+
+taxi_mac_ctrl_tx #(
+    .ID_W(ID_W),
+    .DEST_W(DEST_W),
+    .USER_W(USER_W),
+    .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    .s_axis(s_axis),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis(m_axis),
+
+    /*
+     * MAC control frame interface
+     */
+    .mcf_valid(mcf_valid),
+    .mcf_ready(mcf_ready),
+    .mcf_eth_dst(mcf_eth_dst),
+    .mcf_eth_src(mcf_eth_src),
+    .mcf_eth_type(mcf_eth_type),
+    .mcf_opcode(mcf_opcode),
+    .mcf_params(mcf_params),
+    .mcf_id(mcf_id),
+    .mcf_dest(mcf_dest),
+    .mcf_user(mcf_user),
+
+    /*
+     * Pause interface
+     */
+    .tx_pause_req(tx_pause_req),
+    .tx_pause_ack(tx_pause_ack),
+
+    /*
+     * Status
+     */
+    .stat_tx_mcf(stat_tx_mcf)
+);
+
+endmodule
+
+`resetall

src/eth/tb/taxi_mac_pause_ctrl_rx/Makefile

@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_mac_pause_ctrl_rx
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_MCF_PARAMS_SIZE := 18
+export PARAM_PFC_EN := "1'b1"
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_mac_pause_ctrl_rx/test_taxi_mac_pause_ctrl_rx.py

@@ -0,0 +1,426 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+import struct
+
+from scapy.layers.l2 import Ether
+from scapy.utils import mac2str
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+from cocotb.utils import get_sim_time
+
+from cocotbext.axi.stream import define_stream
+
+
+McfBus, McfTransaction, McfSource, McfSink, McfMonitor = define_stream("Mcf",
+    signals=["valid", "eth_dst", "eth_src", "eth_type", "opcode", "params"],
+    optional_signals=["ready", "id", "dest", "user"]
+)
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.mcf_source = McfSource(McfBus.from_prefix(dut, "mcf"), dut.clk, dut.rst)
+
+        dut.rx_lfc_en.setimmediatevalue(0)
+        dut.rx_lfc_ack.setimmediatevalue(0)
+
+        dut.rx_pfc_en.setimmediatevalue(0)
+        dut.rx_pfc_ack.setimmediatevalue(0)
+
+        dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_lfc_en.setimmediatevalue(0)
+        dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_rx_pfc_en.setimmediatevalue(0)
+        dut.cfg_quanta_step.setimmediatevalue(256)
+        dut.cfg_quanta_clk_en.setimmediatevalue(1)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+    async def send_mcf(self, pkt):
+        mcf = McfTransaction()
+        mcf.eth_dst = int.from_bytes(mac2str(pkt[Ether].dst), 'big')
+        mcf.eth_src = int.from_bytes(mac2str(pkt[Ether].src), 'big')
+        mcf.eth_type = pkt[Ether].type
+        mcf.opcode = int.from_bytes(bytes(pkt[Ether].payload)[0:2], 'big')
+        mcf.params = int.from_bytes(bytes(pkt[Ether].payload)[2:], 'little')
+
+        await self.mcf_source.send(mcf)
+
+
+async def run_test_lfc(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    dut.rx_lfc_en.value = 1
+    dut.rx_lfc_ack.value = 0
+
+    dut.rx_pfc_en.value = 0
+    dut.rx_pfc_ack.value = 0
+
+    dut.cfg_rx_lfc_opcode.value = 0x0001
+    dut.cfg_rx_lfc_en.value = 1
+    dut.cfg_rx_pfc_opcode.value = 0x0101
+    dut.cfg_rx_pfc_en.value = 0
+    dut.cfg_quanta_step.value = int(10000*256 / (512*156.25))
+    dut.cfg_quanta_clk_en.value = 1
+
+    tb.log.info("Test release time accuracy")
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_lfc_req.value == 0:
+        await RisingEdge(dut.clk)
+    dut.rx_lfc_ack.value = 1
+
+    start_time = get_sim_time('sec')
+    while dut.rx_lfc_req.value:
+        await RisingEdge(dut.clk)
+    stop_time = get_sim_time('sec')
+
+    dut.rx_lfc_ack.value = 0
+
+    pause_time = stop_time-start_time
+    pause_quanta = pause_time / (512 * 1/10e9)
+
+    tb.log.info("pause time   : %g s", pause_time)
+    tb.log.info("pause quanta : %f", pause_quanta)
+
+    assert round(pause_quanta/4) == 100//4
+
+    tb.log.info("Test release time accuracy (with refresh)")
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_lfc_req.value == 0:
+        await RisingEdge(dut.clk)
+    dut.rx_lfc_ack.value = 1
+
+    for k in range(400):
+        await RisingEdge(dut.clk)
+
+    await tb.send_mcf(test_pkt)
+
+    start_time = get_sim_time('sec')
+    while dut.rx_lfc_req.value:
+        await RisingEdge(dut.clk)
+    stop_time = get_sim_time('sec')
+
+    dut.rx_lfc_ack.value = 0
+
+    pause_time = stop_time-start_time
+    pause_quanta = pause_time / (512 * 1/10e9)
+
+    tb.log.info("pause time   : %g s", pause_time)
+    tb.log.info("pause quanta : %f", pause_quanta)
+
+    assert round(pause_quanta/4) == 100//4
+
+    tb.log.info("Test explicit release")
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH', 0x0001, 100)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_lfc_req.value == 0:
+        await RisingEdge(dut.clk)
+    dut.rx_lfc_ack.value = 1
+
+    start_time = get_sim_time('sec')
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH', 0x0001, 0)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_lfc_req.value:
+        await RisingEdge(dut.clk)
+    stop_time = get_sim_time('sec')
+
+    dut.rx_lfc_ack.value = 0
+
+    pause_time = stop_time-start_time
+    pause_quanta = pause_time / (512 * 1/10e9)
+
+    tb.log.info("pause time   : %g s", pause_time)
+    tb.log.info("pause quanta : %f", pause_quanta)
+
+    assert round(pause_quanta) < 50
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_pfc(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    dut.rx_lfc_en.value = 0
+    dut.rx_lfc_ack.value = 0
+
+    dut.rx_pfc_en.value = 0xFF
+    dut.rx_pfc_ack.value = 0
+
+    dut.cfg_rx_lfc_opcode.value = 0x0001
+    dut.cfg_rx_lfc_en.value = 0
+    dut.cfg_rx_pfc_opcode.value = 0x0101
+    dut.cfg_rx_pfc_en.value = 1
+    dut.cfg_quanta_step.value = int(10000*256 / (512*156.25))
+    dut.cfg_quanta_clk_en.value = 1
+
+    tb.log.info("Test release time accuracy")
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_pfc_req.value == 0x00:
+        await RisingEdge(dut.clk)
+    dut.rx_pfc_ack.value = 0x01
+
+    start_time = get_sim_time('sec')
+    while dut.rx_pfc_req.value:
+        await RisingEdge(dut.clk)
+    stop_time = get_sim_time('sec')
+
+    dut.rx_pfc_ack.value = 0x00
+
+    pause_time = stop_time-start_time
+    pause_quanta = pause_time / (512 * 1/10e9)
+
+    tb.log.info("pause time   : %g s", pause_time)
+    tb.log.info("pause quanta : %f", pause_quanta)
+
+    assert round(pause_quanta/4) == 100//4
+
+    tb.log.info("Test release time accuracy (with refresh)")
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_pfc_req.value == 0x00:
+        await RisingEdge(dut.clk)
+    dut.rx_pfc_ack.value = 0x01
+
+    for k in range(400):
+        await RisingEdge(dut.clk)
+
+    await tb.send_mcf(test_pkt)
+
+    start_time = get_sim_time('sec')
+    while dut.rx_pfc_req.value:
+        await RisingEdge(dut.clk)
+    stop_time = get_sim_time('sec')
+
+    dut.rx_pfc_ack.value = 0x00
+
+    pause_time = stop_time-start_time
+    pause_quanta = pause_time / (512 * 1/10e9)
+
+    tb.log.info("pause time   : %g s", pause_time)
+    tb.log.info("pause quanta : %f", pause_quanta)
+
+    assert round(pause_quanta/4) == 100//4
+
+    tb.log.info("Test explicit release")
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_pfc_req.value == 0x00:
+        await RisingEdge(dut.clk)
+    dut.rx_pfc_ack.value = 0x01
+
+    start_time = get_sim_time('sec')
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 0, 0, 0, 0, 0, 0, 0, 0)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_pfc_req.value:
+        await RisingEdge(dut.clk)
+    stop_time = get_sim_time('sec')
+
+    dut.rx_pfc_ack.value = 0x00
+
+    pause_time = stop_time-start_time
+    pause_quanta = pause_time / (512 * 1/10e9)
+
+    tb.log.info("pause time   : %g s", pause_time)
+    tb.log.info("pause quanta : %f", pause_quanta)
+
+    assert round(pause_quanta) < 50
+
+    tb.log.info("Test all channels")
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_pfc_req.value != 0xff:
+        await RisingEdge(dut.clk)
+    dut.rx_pfc_ack.value = 0xff
+
+    start_time = get_sim_time('sec')
+
+    for k in range(8):
+        while dut.rx_pfc_req.value & (1 << k) != 0x00:
+            await RisingEdge(dut.clk)
+        stop_time = get_sim_time('sec')
+
+        pause_time = stop_time-start_time
+        pause_quanta = pause_time / (512 * 1/10e9)
+
+        tb.log.info("pause time   : %g s", pause_time)
+        tb.log.info("pause quanta : %f", pause_quanta)
+
+        assert round(pause_quanta/4) == (k+1)*10//4
+
+    dut.rx_pfc_ack.value = 0
+
+    tb.log.info("Test isolation")
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0001, 100, 0, 0, 0, 0, 0, 0, 0)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_pfc_req.value & 0x01 == 0x00:
+        await RisingEdge(dut.clk)
+    dut.rx_pfc_ack.value = 0x01
+
+    start_time = get_sim_time('sec')
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0002, 0, 200, 0, 0, 0, 0, 0, 0)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_pfc_req.value & 0x02 == 0x00:
+        await RisingEdge(dut.clk)
+    dut.rx_pfc_ack.value = 0x03
+
+    eth = Ether(src='5A:51:52:53:54:55', dst='01:80:C2:00:00:01', type=0x8808)
+    test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x0002, 0, 0, 0, 0, 0, 0, 0, 0)
+
+    await tb.send_mcf(test_pkt)
+
+    while dut.rx_pfc_req.value:
+        await RisingEdge(dut.clk)
+    stop_time = get_sim_time('sec')
+
+    dut.rx_pfc_ack.value = 0x00
+
+    pause_time = stop_time-start_time
+    pause_quanta = pause_time / (512 * 1/10e9)
+
+    tb.log.info("pause time   : %g s", pause_time)
+    tb.log.info("pause quanta : %f", pause_quanta)
+
+    assert round(pause_quanta/4) == 100//4
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_lfc, run_test_pfc]:
+
+        factory = TestFactory(test)
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_mac_pause_ctrl_rx(request):
+    dut = "taxi_mac_pause_ctrl_rx"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['MCF_PARAMS_SIZE'] = 18
+    parameters['PFC_EN'] = "1'b1"
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_mac_pause_ctrl_tx/Makefile

@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_mac_pause_ctrl_tx
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_MCF_PARAMS_SIZE := 18
+export PARAM_PFC_EN := "1'b1"
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_mac_pause_ctrl_tx/test_taxi_mac_pause_ctrl_tx.py

@@ -0,0 +1,377 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+import struct
+
+from scapy.layers.l2 import Ether
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+from cocotb.utils import get_sim_time
+
+from cocotbext.axi.stream import define_stream
+
+
+McfBus, McfTransaction, McfSource, McfSink, McfMonitor = define_stream("Mcf",
+    signals=["valid", "eth_dst", "eth_src", "eth_type", "opcode", "params"],
+    optional_signals=["ready", "id", "dest", "user"]
+)
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.mcf_sink = McfSink(McfBus.from_prefix(dut, "mcf"), dut.clk, dut.rst)
+
+        dut.tx_lfc_req.setimmediatevalue(0)
+        dut.tx_lfc_resend.setimmediatevalue(0)
+
+        dut.tx_pfc_req.setimmediatevalue(0)
+        dut.tx_pfc_resend.setimmediatevalue(0)
+
+        dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_lfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_lfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_lfc_en.setimmediatevalue(0)
+        dut.cfg_tx_lfc_quanta.setimmediatevalue(0)
+        dut.cfg_tx_lfc_refresh.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_src.setimmediatevalue(0)
+        dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
+        dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
+        dut.cfg_tx_pfc_en.setimmediatevalue(0)
+        dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
+        dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
+        dut.cfg_quanta_step.setimmediatevalue(256)
+        dut.cfg_quanta_clk_en.setimmediatevalue(1)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+    async def recv_mcf(self):
+        rx_frame = await self.mcf_sink.recv()
+
+        data = bytearray()
+        data.extend(rx_frame.eth_dst.integer.to_bytes(6, 'big'))
+        data.extend(rx_frame.eth_src.integer.to_bytes(6, 'big'))
+        data.extend(rx_frame.eth_type.integer.to_bytes(2, 'big'))
+        data.extend(rx_frame.opcode.integer.to_bytes(2, 'big'))
+        data.extend(rx_frame.params.integer.to_bytes(44, 'little'))
+
+        return Ether(data)
+
+
+def check_lfc_frame(tb, pkt, quanta):
+    tb.log.info("Pause frame: %s", repr(pkt))
+
+    op, q = struct.unpack_from('!HH', bytes(pkt[Ether].payload), 0)
+    tb.log.info("opcode: 0x%x", op)
+    tb.log.info("quanta: %d", q)
+
+    assert pkt[Ether].dst == '01:80:c2:00:00:01'
+    assert pkt[Ether].src == '5a:51:52:53:54:55'
+    assert pkt[Ether].type == 0x8808
+    assert op == 0x0001
+    assert q == quanta
+
+
+async def run_test_lfc(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    dut.tx_lfc_req.value = 0
+    dut.tx_lfc_resend.value = 0
+
+    dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_lfc_eth_type.value = 0x8808
+    dut.cfg_tx_lfc_opcode.value = 0x0001
+    dut.cfg_tx_lfc_en.value = 1
+    dut.cfg_tx_lfc_quanta.value = 0xFFFF
+    dut.cfg_tx_lfc_refresh.value = 0x7F00
+    dut.cfg_quanta_step.value = int(10000*256 / (512*156.25))
+    dut.cfg_quanta_clk_en.value = 1
+
+    tb.log.info("Test pause")
+
+    dut.cfg_tx_lfc_refresh.value = 100
+
+    dut.tx_lfc_req.value = 1
+    start_time = None
+
+    for k in range(4):
+        rx_pkt = await tb.recv_mcf()
+        stop_time = get_sim_time('sec')
+
+        check_lfc_frame(tb, rx_pkt, 0xFFFF)
+
+        if start_time:
+            refresh_time = stop_time-start_time
+            refresh_quanta = refresh_time / (512 * 1/10e9)
+
+            tb.log.info("refresh time   : %g s", refresh_time)
+            tb.log.info("refresh quanta : %f", refresh_quanta)
+
+            assert round(refresh_quanta/4) == 100//4
+
+        start_time = get_sim_time('sec')
+
+    dut.tx_lfc_req.value = 0
+
+    rx_pkt = await tb.recv_mcf()
+
+    check_lfc_frame(tb, rx_pkt, 0x0)
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def check_pfc_frame(tb, pkt, enable_mask, quanta_mask, quanta):
+    tb.log.info("PFC frame: %s", repr(pkt))
+
+    op, enable, *q = struct.unpack_from('!HH8H', bytes(pkt[Ether].payload), 0)
+    tb.log.info("opcode: 0x%x", op)
+    tb.log.info("enable: 0x%x", enable)
+    tb.log.info("quanta: %r", q)
+
+    assert pkt[Ether].dst == '01:80:c2:00:00:01'
+    assert pkt[Ether].src == '5a:51:52:53:54:55'
+    assert pkt[Ether].type == 0x8808
+    assert op == 0x0101
+    assert enable == enable_mask
+    for k in range(8):
+        if quanta_mask & (1 << k):
+            assert q[k] == quanta
+        else:
+            assert q[k] == 0
+
+
+async def run_test_pfc(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    dut.tx_pfc_req.value = 0x00
+    dut.tx_pfc_resend.value = 0
+
+    dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
+    dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
+    dut.cfg_tx_pfc_eth_type.value = 0x8808
+    dut.cfg_tx_pfc_opcode.value = 0x0101
+    dut.cfg_tx_pfc_en.value = 1
+    dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
+    dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
+    dut.cfg_quanta_step.value = int(10000*256 / (512*156.25))
+    dut.cfg_quanta_clk_en.value = 1
+
+    tb.log.info("Test pause")
+
+    dut.cfg_tx_pfc_refresh.value = [0x0064]*8
+
+    dut.tx_pfc_req.value = 0x01
+    start_time = None
+
+    for k in range(4):
+        rx_pkt = await tb.recv_mcf()
+        stop_time = get_sim_time('sec')
+
+        check_pfc_frame(tb, rx_pkt, 0x01, 0x01, 0xFFFF)
+
+        if start_time:
+            refresh_time = stop_time-start_time
+            refresh_quanta = refresh_time / (512 * 1/10e9)
+
+            tb.log.info("refresh time   : %g s", refresh_time)
+            tb.log.info("refresh quanta : %f", refresh_quanta)
+
+            assert round(refresh_quanta/4) == 100//4
+
+        start_time = get_sim_time('sec')
+
+    dut.tx_pfc_req.value = 0x00
+
+    rx_pkt = await tb.recv_mcf()
+
+    check_pfc_frame(tb, rx_pkt, 0x01, 0x00, 0xFFFF)
+
+    tb.log.info("Test all channels")
+
+    dut.cfg_tx_pfc_refresh.value = [0x0064]*8
+
+    for ch in range(8):
+
+        dut.tx_pfc_req.value = 0xFF >> (7-ch)
+        start_time = None
+
+        for k in range(3):
+            rx_pkt = await tb.recv_mcf()
+            stop_time = get_sim_time('sec')
+
+            check_pfc_frame(tb, rx_pkt, 0xFF >> (7-ch), 0xFF >> (7-ch), 0xFFFF)
+
+            if start_time:
+                refresh_time = stop_time-start_time
+                refresh_quanta = refresh_time / (512 * 1/10e9)
+
+                tb.log.info("refresh time   : %g s", refresh_time)
+                tb.log.info("refresh quanta : %f", refresh_quanta)
+
+                assert round(refresh_quanta/4) == 100//4
+
+            start_time = get_sim_time('sec')
+
+    dut.tx_pfc_req.value = 0x00
+
+    rx_pkt = await tb.recv_mcf()
+
+    check_pfc_frame(tb, rx_pkt, 0xFF, 0x00, 0xFFFF)
+
+    tb.log.info("Test isolation")
+
+    dut.cfg_tx_pfc_refresh.value = [0x0064]*8
+
+    dut.tx_pfc_req.value = 0x01
+    start_time = None
+
+    rx_pkt = await tb.recv_mcf()
+    stop_time = get_sim_time('sec')
+
+    check_pfc_frame(tb, rx_pkt, 0x01, 0x01, 0xFFFF)
+
+    dut.tx_pfc_req.value = 0x03
+    start_time = None
+
+    rx_pkt = await tb.recv_mcf()
+    stop_time = get_sim_time('sec')
+
+    check_pfc_frame(tb, rx_pkt, 0x03, 0x03, 0xFFFF)
+
+    dut.tx_pfc_req.value = 0x01
+    start_time = None
+
+    rx_pkt = await tb.recv_mcf()
+    stop_time = get_sim_time('sec')
+
+    check_pfc_frame(tb, rx_pkt, 0x03, 0x01, 0xFFFF)
+
+    start_time = get_sim_time('sec')
+
+    for k in range(4):
+        rx_pkt = await tb.recv_mcf()
+        stop_time = get_sim_time('sec')
+
+        check_pfc_frame(tb, rx_pkt, 0x01, 0x01, 0xFFFF)
+
+        if start_time:
+            refresh_time = stop_time-start_time
+            refresh_quanta = refresh_time / (512 * 1/10e9)
+
+            tb.log.info("refresh time   : %g s", refresh_time)
+            tb.log.info("refresh quanta : %f", refresh_quanta)
+
+            assert round(refresh_quanta/4) == 100//4
+
+        start_time = get_sim_time('sec')
+
+    dut.tx_pfc_req.value = 0x00
+
+    rx_pkt = await tb.recv_mcf()
+
+    check_pfc_frame(tb, rx_pkt, 0x01, 0x00, 0xFFFF)
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_lfc, run_test_pfc]:
+
+        factory = TestFactory(test)
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_mac_pause_ctrl_tx(request):
+    dut = "taxi_mac_pause_ctrl_tx"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['MCF_PARAMS_SIZE'] = 18
+    parameters['PFC_EN'] = "1'b1"
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_xgmii_baser_dec_64/Makefile

@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_xgmii_baser_dec_64
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_HDR_W := 2
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_xgmii_baser_dec_64/baser.py

@@ -0,0 +1 @@
+../baser.py

src/eth/tb/taxi_xgmii_baser_dec_64/test_taxi_xgmii_baser_dec_64.py

@@ -0,0 +1,245 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiSink, XgmiiFrame
+
+try:
+    from baser import BaseRSerdesSource
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.source = BaseRSerdesSource(dut.encoded_rx_data, dut.encoded_rx_hdr, dut.clk, scramble=False)
+        self.sink = XgmiiSink(dut.xgmii_rxd, dut.xgmii_rxc, dut.clk, dut.rst)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_dic=True,
+        force_offset_start=False):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.source.enable_dic = enable_dic
+    tb.source.force_offset_start = force_offset_start
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data)
+        await tb.source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_alignment(dut, payload_data=None, ifg=12, enable_dic=True,
+        force_offset_start=False):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.source.byte_lanes
+
+    tb.source.ifg = ifg
+    tb.source.enable_dic = enable_dic
+    tb.source.force_offset_start = force_offset_start
+
+    for length in range(60, 92):
+
+        await tb.reset()
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            test_frame = XgmiiFrame.from_payload(test_data)
+            await tb.source.send(test_frame)
+
+        for test_data in test_frames:
+            rx_frame = await tb.sink.recv()
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+            if force_offset_start and byte_lanes > 4:
+                lane = 4
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_lanes
+
+            if enable_dic:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_lanes
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_lanes
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.clk)
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.add_option("enable_dic", [True, False])
+    factory.add_option("force_offset_start", [False, True])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.add_option("enable_dic", [True, False])
+    factory.add_option("force_offset_start", [False, True])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_xgmii_baser_dec_64(request):
+    dut = "taxi_xgmii_baser_dec_64"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 64
+    parameters['CTRL_W'] = parameters['DATA_W'] // 8
+    parameters['HDR_W'] = 2
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/eth/tb/taxi_xgmii_baser_enc_64/Makefile

@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = taxi_xgmii_baser_enc_64
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 )
+export PARAM_HDR_W := 2
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/eth/tb/taxi_xgmii_baser_enc_64/baser.py

@@ -0,0 +1 @@
+../baser.py

src/eth/tb/taxi_xgmii_baser_enc_64/test_taxi_xgmii_baser_enc_64.py

@@ -0,0 +1,245 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiSource, XgmiiFrame
+
+try:
+    from baser import BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.source = XgmiiSource(dut.xgmii_txd, dut.xgmii_txc, dut.clk, dut.rst)
+        self.sink = BaseRSerdesSink(dut.encoded_tx_data, dut.encoded_tx_hdr, dut.clk, scramble=False)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_dic=True,
+        force_offset_start=False):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.source.enable_dic = enable_dic
+    tb.source.force_offset_start = force_offset_start
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data)
+        await tb.source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.get_payload() == test_data
+        assert rx_frame.check_fcs()
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_alignment(dut, payload_data=None, ifg=12, enable_dic=True,
+        force_offset_start=False):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.source.byte_lanes
+
+    tb.source.ifg = ifg
+    tb.source.enable_dic = enable_dic
+    tb.source.force_offset_start = force_offset_start
+
+    for length in range(60, 92):
+
+        await tb.reset()
+
+        test_frames = [payload_data(length) for k in range(10)]
+        start_lane = []
+
+        for test_data in test_frames:
+            test_frame = XgmiiFrame.from_payload(test_data)
+            await tb.source.send(test_frame)
+
+        for test_data in test_frames:
+            rx_frame = await tb.sink.recv()
+
+            assert rx_frame.get_payload() == test_data
+            assert rx_frame.check_fcs()
+            assert rx_frame.ctrl is None
+
+            start_lane.append(rx_frame.start_lane)
+
+        tb.log.info("length: %d", length)
+        tb.log.info("start_lane: %s", start_lane)
+
+        start_lane_ref = []
+
+        # compute expected starting lanes
+        lane = 0
+        deficit_idle_count = 0
+
+        for test_data in test_frames:
+            if ifg == 0:
+                lane = 0
+            if force_offset_start and byte_lanes > 4:
+                lane = 4
+
+            start_lane_ref.append(lane)
+            lane = (lane + len(test_data)+4+ifg) % byte_lanes
+
+            if enable_dic:
+                offset = lane % 4
+                if deficit_idle_count+offset >= 4:
+                    offset += 4
+                lane = (lane - offset) % byte_lanes
+                deficit_idle_count = (deficit_idle_count + offset) % 4
+            else:
+                offset = lane % 4
+                if offset > 0:
+                    offset += 4
+                lane = (lane - offset) % byte_lanes
+
+        tb.log.info("start_lane_ref: %s", start_lane_ref)
+
+        assert start_lane_ref == start_lane
+
+        await RisingEdge(dut.clk)
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.add_option("enable_dic", [True, False])
+    factory.add_option("force_offset_start", [False, True])
+    factory.generate_tests()
+
+    factory = TestFactory(run_test_alignment)
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12])
+    factory.add_option("enable_dic", [True, False])
+    factory.add_option("force_offset_start", [False, True])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_xgmii_baser_enc_64(request):
+    dut = "taxi_xgmii_baser_enc_64"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 64
+    parameters['CTRL_W'] = parameters['DATA_W'] // 8
+    parameters['HDR_W'] = 2
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )