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https://github.com/fpganinja/taxi.git
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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
332
src/hip/rtl/us/taxi_mmcm_frac.sv
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332
src/hip/rtl/us/taxi_mmcm_frac.sv
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2024-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Fractional MMCM
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*/
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module taxi_mmcm_frac #(
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parameter MMCM_INPUT_CLK_PERIOD = 8.0,
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parameter MMCM_INPUT_REF_JITTER = 0.010,
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parameter MMCM_INPUT_DIV = 1,
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parameter MMCM_MULT = 8,
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parameter MMCM_OUTPUT_DIV = MMCM_MULT,
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parameter logic PSCLK_EN = 1'b0,
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parameter PSCLK_DIV = MMCM_OUTPUT_DIV,
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parameter logic EXTRA_MMCM = 1'b1,
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parameter MMCM2_CASC_DIV = MMCM_OUTPUT_DIV,
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parameter MMCM2_INPUT_DIV = 1,
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parameter MMCM2_MULT = MMCM_OUTPUT_DIV,
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parameter MMCM2_OUTPUT_DIV = MMCM2_MULT,
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parameter OFFSET_NUM = 1,
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parameter OFFSET_DENOM = 65536
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)
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(
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input wire input_clk,
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input wire input_rst,
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output wire output_clk,
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output wire output_offset_clk,
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output wire locked
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);
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localparam MMCM_OUTPUT_CLK_PERIOD = MMCM_INPUT_CLK_PERIOD*MMCM_INPUT_DIV/MMCM_MULT*MMCM_OUTPUT_DIV;
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localparam MMCM2_INPUT_CLK_PERIOD = MMCM_INPUT_CLK_PERIOD*MMCM_INPUT_DIV/MMCM_MULT*MMCM2_CASC_DIV;
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localparam PSCLK_DIV_INT = PSCLK_EN ? PSCLK_DIV : MMCM_OUTPUT_DIV;
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// 1 phase shifter tap is 1/56th of the VCO period
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// To shift the frequency by OFFSET_NUM/OFFSET_DENOM, we need to shift the VCO output
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// by OFFSET_NUM VCO periods (56*OFFSET_NUM taps) every OFFSET_DENOM VCO periods.
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// Since the PSCLK is divided with respect to the VCO, rescale numerator by division factor
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localparam DIR = OFFSET_NUM >= 0;
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localparam NUM_1 = (DIR ? OFFSET_NUM : -OFFSET_NUM)*56*PSCLK_DIV_INT;
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localparam DENOM_1 = OFFSET_DENOM;
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localparam MMCM_MIN_PSCLK_CYCLES = 12;
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if (DENOM_1 / NUM_1 < MMCM_MIN_PSCLK_CYCLES)
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$fatal(0, "Error: requested offset is too large for MMCM dynamic phase shifter");
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localparam CNT_W = $clog2(DENOM_1)+1;
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wire mmcm_locked;
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wire mmcm2_locked;
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wire mmcm_clkfb;
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wire mmcm_clk_out;
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wire mmcm_clk_bufg;
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wire mmcm_offset_clk_out;
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wire mmcm_offset_clk_bufg;
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wire mmcm_ps_clk_out;
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wire mmcm_ps_clk_bufg;
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wire mmcm2_clkfb;
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wire mmcm2_offset_clk_out;
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wire mmcm2_offset_clk_bufg;
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assign locked = mmcm_locked && mmcm2_locked;
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assign output_clk = mmcm_clk_bufg;
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assign output_offset_clk = EXTRA_MMCM ? mmcm2_offset_clk_bufg : mmcm_offset_clk_bufg;
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wire ps_clk = PSCLK_EN ? mmcm_ps_clk_bufg : output_clk;
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logic [CNT_W-1:0] cnt_reg = '0;
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logic ps_en_reg = 1'b0;
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always_ff @(posedge ps_clk) begin
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ps_en_reg <= 1'b0;
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if (cnt_reg + NUM_1 >= DENOM_1) begin
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cnt_reg <= cnt_reg + NUM_1 - DENOM_1;
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ps_en_reg <= 1'b1;
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end else begin
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cnt_reg <= cnt_reg + NUM_1;
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end
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end
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MMCME3_ADV #(
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// input clocks
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.CLKIN1_PERIOD(MMCM_INPUT_CLK_PERIOD),
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.REF_JITTER1(MMCM_INPUT_REF_JITTER),
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.CLKIN2_PERIOD(0.000),
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.REF_JITTER2(0.010),
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// divide for PFD input
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// US/US+: range 10 MHz to 500 MHz
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.DIVCLK_DIVIDE(MMCM_INPUT_DIV),
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// multiply for VCO output
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// US: range 600 MHz to 1440 MHz
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// US+: range 800 MHz to 1600 MHz
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.CLKFBOUT_MULT_F(MMCM_MULT),
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.CLKFBOUT_PHASE(0),
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.CLKFBOUT_USE_FINE_PS("FALSE"),
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// divide
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.CLKOUT0_DIVIDE_F(MMCM_OUTPUT_DIV),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT0_USE_FINE_PS("FALSE"),
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// divide and phase shift
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.CLKOUT1_DIVIDE(EXTRA_MMCM ? MMCM2_CASC_DIV : MMCM_OUTPUT_DIV),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT1_USE_FINE_PS("TRUE"),
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// phase shifter clock
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.CLKOUT2_DIVIDE(PSCLK_EN ? PSCLK_DIV : 1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT2_USE_FINE_PS("FALSE"),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT3_USE_FINE_PS("FALSE"),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_USE_FINE_PS("FALSE"),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT5_USE_FINE_PS("FALSE"),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKOUT6_USE_FINE_PS("FALSE"),
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// no spread spectrum
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.SS_EN("FALSE"),
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.SS_MODE("CENTER_HIGH"),
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.SS_MOD_PERIOD(10000),
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.COMPENSATION("AUTO"),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// input clocks
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.CLKIN1(input_clk),
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.CLKIN2(1'b0),
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// select CLKIN1
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.CLKINSEL(1'b1),
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// direct clkfb feedback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// output (no offset)
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.CLKOUT0(mmcm_clk_out),
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.CLKOUT0B(),
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// offset output
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.CLKOUT1(mmcm_offset_clk_out),
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.CLKOUT1B(),
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// phase shifter clock
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.CLKOUT2(mmcm_ps_clk_out),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(input_rst),
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// don't power down
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.PWRDWN(1'b0),
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// DRP
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.DADDR(7'd0),
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.DI(16'd0),
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.DWE(1'b0),
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.DEN(1'b0),
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.DCLK(1'b0),
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.DO(),
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// dynamic phase shift
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.PSINCDEC(DIR ? 1'b0 : 1'b1),
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.PSEN(ps_en_reg),
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.PSCLK(ps_clk),
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.PSDONE(),
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// locked output
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.LOCKED(mmcm_locked),
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// input status
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.CLKINSTOPPED(),
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.CLKFBSTOPPED(),
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// CDDC
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.CDDCREQ(1'b0),
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.CDDCDONE()
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);
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BUFG
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mmcm_clk_bufg_inst (
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.I(mmcm_clk_out),
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.O(mmcm_clk_bufg)
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);
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BUFG
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mmcm_offset_clk_bufg_inst (
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.I(mmcm_offset_clk_out),
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.O(mmcm_offset_clk_bufg)
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);
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BUFG
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mmcm_ps_clk_bufg_inst (
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.I(mmcm_ps_clk_out),
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.O(mmcm_ps_clk_bufg)
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);
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if (EXTRA_MMCM) begin : extra_mmcm
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// MMCM instance
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MMCME3_BASE #(
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// 125 MHz input
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.CLKIN1_PERIOD(MMCM2_INPUT_CLK_PERIOD),
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.REF_JITTER1(MMCM_INPUT_REF_JITTER),
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// divide for PFD input
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// US/US+: range 10 MHz to 500 MHz
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.DIVCLK_DIVIDE(MMCM2_INPUT_DIV),
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// multiply for VCO output
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// US: range 600 MHz to 1440 MHz
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// US+: range 800 MHz to 1600 MHz
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.CLKFBOUT_MULT_F(MMCM2_MULT),
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.CLKFBOUT_PHASE(0),
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// divide
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.CLKOUT0_DIVIDE_F(MMCM2_OUTPUT_DIV),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// Not used
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm2_inst (
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// 125 MHz input
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.CLKIN1(mmcm_offset_clk_bufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm2_clkfb),
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.CLKFBOUT(mmcm2_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(mmcm2_offset_clk_out),
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.CLKOUT0B(),
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// Not used
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.CLKOUT1(),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(input_rst || !mmcm_locked),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm2_locked)
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);
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BUFG
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mmcm2_offset_clk_bufg_inst (
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.I(mmcm2_offset_clk_out),
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.O(mmcm2_offset_clk_bufg)
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);
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end else begin
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assign mmcm2_locked = mmcm_locked;
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assign mmcm2_offset_clk_bufg = mmcm_offset_clk_bufg;
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end
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endmodule
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`resetall
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