Reorganize repository

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/lfsr/tb/taxi_lfsr/Makefile

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+
+DUT      = taxi_lfsr
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_LFSR_W ?= 32
+export PARAM_LFSR_POLY ?= "32'h4c11db7"
+export PARAM_LFSR_GALOIS ?= "1'b1"
+export PARAM_LFSR_FEED_FORWARD ?= "1'b0"
+export PARAM_REVERSE ?= "1'b1"
+export PARAM_DATA_W ?= 8
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/lfsr/tb/taxi_lfsr/test_taxi_lfsr.py

@@ -0,0 +1,238 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import zlib
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.triggers import Timer
+from cocotb.regression import TestFactory
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        dut.data_in.setimmediatevalue(0)
+        dut.state_in.setimmediatevalue(0)
+
+
+def chunks(lst, n, padvalue=None):
+    return itertools.zip_longest(*[iter(lst)]*n, fillvalue=padvalue)
+
+
+def crc32(data):
+    return zlib.crc32(data) & 0xffffffff
+
+
+def crc32c(data, crc=0xffffffff, poly=0x82f63b78):
+    for d in data:
+        crc = crc ^ d
+        for bit in range(0, 8):
+            if crc & 1:
+                crc = (crc >> 1) ^ poly
+            else:
+                crc = crc >> 1
+    return ~crc & 0xffffffff
+
+
+async def run_test_crc(dut, ref_crc):
+
+    data_width = len(dut.data_in)
+    byte_lanes = data_width // 8
+
+    state_width = len(dut.state_in)
+    state_mask = 2**state_width-1
+
+    tb = TB(dut)
+
+    await Timer(10, 'ns')
+
+    block = bytes([(x+1)*0x11 for x in range(byte_lanes)])
+
+    dut.state_in.value = state_mask
+    dut.data_in.value = int.from_bytes(block, 'little')
+    await Timer(10, 'ns')
+
+    val = ~dut.state_out.value.integer & state_mask
+    ref = ref_crc(block)
+
+    tb.log.info("CRC: 0x%x (ref: 0x%x)", val, ref)
+
+    assert val == ref
+
+    await Timer(10, 'ns')
+
+    block = bytearray(itertools.islice(itertools.cycle(range(256)), 1024))
+
+    dut.state_in.value = state_mask
+    for b in chunks(block, byte_lanes):
+        dut.data_in.value = int.from_bytes(b, 'little')
+        await Timer(10, 'ns')
+        dut.state_in.value = dut.state_out.value
+
+    val = ~int(dut.state_out.value) & state_mask
+    ref = ref_crc(block)
+
+    tb.log.info("CRC: 0x%x (ref: 0x%x)", val, ref)
+
+    assert val == ref
+
+    await Timer(10, 'ns')
+
+
+def prbs9(state=0x1ff):
+    while True:
+        for i in range(8):
+            if bool(state & 0x10) ^ bool(state & 0x100):
+                state = ((state & 0xff) << 1) | 1
+            else:
+                state = (state & 0xff) << 1
+        yield ~state & 0xff
+
+
+def prbs31(state=0x7fffffff):
+    while True:
+        for i in range(8):
+            if bool(state & 0x08000000) ^ bool(state & 0x40000000):
+                state = ((state & 0x3fffffff) << 1) | 1
+            else:
+                state = (state & 0x3fffffff) << 1
+        yield ~state & 0xff
+
+
+async def run_test_prbs(dut, ref_prbs):
+
+    data_width = len(dut.data_in)
+    byte_lanes = data_width // 8
+    data_mask = 2**data_width-1
+
+    state_width = len(dut.state_in)
+    state_mask = 2**state_width-1
+
+    tb = TB(dut)
+
+    await Timer(10, 'ns')
+
+    dut.state_in.value = state_mask
+    dut.data_in.value = 0
+    gen = chunks(ref_prbs(), byte_lanes)
+
+    await Timer(10, 'ns')
+
+    for i in range(512):
+        ref = int.from_bytes(bytes(next(gen)), 'big')
+        val = ~int(dut.data_out.value) & data_mask
+
+        tb.log.info("PRBS: 0x%x (ref: 0x%x)", val, ref)
+
+        assert ref == val
+
+        dut.state_in.value = dut.state_out.value
+
+        await Timer(10, 'ns')
+
+
+if cocotb.SIM_NAME:
+
+    if cocotb.top.LFSR_POLY.value == 0x4c11db7:
+        factory = TestFactory(run_test_crc)
+        factory.add_option("ref_crc", [crc32])
+        factory.generate_tests()
+
+    if cocotb.top.LFSR_POLY.value == 0x1edc6f41:
+        factory = TestFactory(run_test_crc)
+        factory.add_option("ref_crc", [crc32c])
+        factory.generate_tests()
+
+    if cocotb.top.LFSR_POLY.value == 0x021:
+        factory = TestFactory(run_test_prbs)
+        factory.add_option("ref_prbs", [prbs9])
+        factory.generate_tests()
+
+    if cocotb.top.LFSR_POLY.value == 0x10000001:
+        factory = TestFactory(run_test_prbs)
+        factory.add_option("ref_prbs", [prbs31])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize(("lfsr_w", "lfsr_poly", "lfsr_galois", "reverse", "data_w"), [
+            (32, "32'h4c11db7", 1, 1, 8),
+            (32, "32'h4c11db7", 1, 1, 64),
+            (32, "32'h1edc6f41", 1, 1, 8),
+            (32, "32'h1edc6f41", 1, 1, 64),
+            (9,  "9'h021", 0, 0, 8),
+            (9,  "9'h021", 0, 0, 64),
+            (31, "31'h10000001", 0, 0, 8),
+            (31, "31'h10000001", 0, 0, 64),
+        ])
+def test_taxi_lfsr(request, lfsr_w, lfsr_poly, lfsr_galois, reverse, data_w):
+    dut = "taxi_lfsr"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['LFSR_W'] = lfsr_w
+    parameters['LFSR_POLY'] = lfsr_poly
+    parameters['LFSR_GALOIS'] = f"1'b{lfsr_galois}"
+    parameters['LFSR_FEED_FORWARD'] = "1'b0"
+    parameters['REVERSE'] = f"1'b{reverse}"
+    parameters['DATA_W'] = data_w
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/lfsr/tb/taxi_lfsr_crc/Makefile

@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+
+DUT      = taxi_lfsr_crc
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_LFSR_W ?= 32
+export PARAM_LFSR_POLY ?= "32'h4c11db7"
+export PARAM_LFSR_INIT ?= "'1"
+export PARAM_LFSR_GALOIS ?= "1'b1"
+export PARAM_REVERSE ?= "1'b1"
+export PARAM_INVERT ?= "1'b1"
+export PARAM_DATA_W ?= 8
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/lfsr/tb/taxi_lfsr_crc/test_taxi_lfsr_crc.py

@@ -0,0 +1,189 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import zlib
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        dut.data_in.setimmediatevalue(0)
+        dut.data_in_valid.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+def chunks(lst, n, padvalue=None):
+    return itertools.zip_longest(*[iter(lst)]*n, fillvalue=padvalue)
+
+
+def crc32(data):
+    return zlib.crc32(data) & 0xffffffff
+
+
+def crc32c(data, crc=0xffffffff, poly=0x82f63b78):
+    for d in data:
+        crc = crc ^ d
+        for bit in range(0, 8):
+            if crc & 1:
+                crc = (crc >> 1) ^ poly
+            else:
+                crc = crc >> 1
+    return ~crc & 0xffffffff
+
+
+async def run_test_crc(dut, ref_crc):
+
+    data_width = len(dut.data_in)
+    byte_lanes = data_width // 8
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    block = bytes([(x+1)*0x11 for x in range(byte_lanes)])
+
+    dut.data_in.value = int.from_bytes(block, 'little')
+    dut.data_in_valid.value = 1
+    await RisingEdge(dut.clk)
+    dut.data_in_valid.value = 0
+
+    await RisingEdge(dut.clk)
+    val = dut.crc_out.value.integer
+    ref = ref_crc(block)
+
+    tb.log.info("CRC: 0x%x (ref: 0x%x)", val, ref)
+
+    assert val == ref
+
+    await tb.reset()
+
+    block = bytearray(itertools.islice(itertools.cycle(range(256)), 1024))
+
+    for b in chunks(block, byte_lanes):
+        dut.data_in.value = int.from_bytes(b, 'little')
+        dut.data_in_valid.value = 1
+        await RisingEdge(dut.clk)
+    dut.data_in_valid.value = 0
+
+    await RisingEdge(dut.clk)
+    val = dut.crc_out.value.integer
+    ref = ref_crc(block)
+
+    tb.log.info("CRC: 0x%x (ref: 0x%x)", val, ref)
+
+    assert val == ref
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    if int(cocotb.top.LFSR_POLY.value) == 0x4c11db7:
+        factory = TestFactory(run_test_crc)
+        factory.add_option("ref_crc", [crc32])
+        factory.generate_tests()
+
+    if int(cocotb.top.LFSR_POLY.value) == 0x1edc6f41:
+        factory = TestFactory(run_test_crc)
+        factory.add_option("ref_crc", [crc32c])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize(("lfsr_w", "lfsr_poly", "lfsr_init", "lfsr_galois", "reverse", "invert", "data_w"), [
+            (32, "32'h4c11db7", "'1", 1, 1, 1, 8),
+            (32, "32'h4c11db7", "'1", 1, 1, 1, 64),
+            (32, "32'h1edc6f41", "'1", 1, 1, 1, 8),
+            (32, "32'h1edc6f41", "'1", 1, 1, 1, 64),
+        ])
+def test_taxi_lfsr_crc(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois, reverse, invert, data_w):
+    dut = "taxi_lfsr_crc"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_lfsr.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['LFSR_W'] = lfsr_w
+    parameters['LFSR_POLY'] = lfsr_poly
+    parameters['LFSR_INIT'] = lfsr_init
+    parameters['LFSR_GALOIS'] = f"1'b{lfsr_galois}"
+    parameters['REVERSE'] = f"1'b{reverse}"
+    parameters['INVERT'] = f"1'b{invert}"
+    parameters['DATA_W'] = data_w
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/lfsr/tb/taxi_lfsr_descramble/Makefile

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+
+DUT      = taxi_lfsr_descramble
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_LFSR_W ?= 58
+export PARAM_LFSR_POLY ?= "58'h8000000001"
+export PARAM_LFSR_INIT ?= "'1"
+export PARAM_LFSR_GALOIS ?= "1'b0"
+export PARAM_REVERSE ?= "1'b1"
+export PARAM_DATA_W ?= 8
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/lfsr/tb/taxi_lfsr_descramble/test_taxi_lfsr_descramble.py

@@ -0,0 +1,187 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        dut.data_in.setimmediatevalue(0)
+        dut.data_in_valid.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+def chunks(lst, n, padvalue=None):
+    return itertools.zip_longest(*[iter(lst)]*n, fillvalue=padvalue)
+
+
+def scramble_64b66b(data, state=0x3ffffffffffffff):
+    data_out = bytearray()
+    for d in data:
+        b = 0
+        for i in range(8):
+            if bool(state & (1 << 38)) ^ bool(state & (1 << 57)) ^ bool(d & (1 << i)):
+                state = ((state & 0x1ffffffffffffff) << 1) | 1
+                b = b | (1 << i)
+            else:
+                state = (state & 0x1ffffffffffffff) << 1
+        data_out.append(b)
+    return data_out
+
+
+def descramble_64b66b(data, state=0x3ffffffffffffff):
+    data_out = bytearray()
+    for d in data:
+        b = 0
+        for i in range(8):
+            if bool(state & (1 << 38)) ^ bool(state & (1 << 57)) ^ bool(d & (1 << i)):
+                b = b | (1 << i)
+            state = (state & 0x1ffffffffffffff) << 1 | bool(d & (1 << i))
+        data_out += bytearray([b])
+    return data_out
+
+
+async def run_test_descramble(dut, ref_scramble):
+
+    data_width = len(dut.data_in)
+    byte_lanes = data_width // 8
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    block = bytearray(itertools.islice(itertools.cycle(range(256)), 1024))
+
+    scr = scramble_64b66b(block)
+
+    dscr = descramble_64b66b(scr)
+
+    assert dscr == block
+
+    ref_iter = iter(chunks(block, byte_lanes))
+
+    first = True
+    for b in chunks(scr, byte_lanes):
+        dut.data_in.value = int.from_bytes(b, 'little')
+        dut.data_in_valid.value = 1
+        await RisingEdge(dut.clk)
+
+        val = dut.data_out.value.integer
+
+        if not first:
+            ref = int.from_bytes(bytes(next(ref_iter)), 'little')
+
+            tb.log.info("Descrambled: 0x%x (ref: 0x%x)", val, ref)
+
+            assert ref == val
+
+        first = False
+
+    dut.data_in_valid.value = 0
+
+    await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    # if cocotb.top.LFSR_POLY.value == 0x8000000001:
+    if int(cocotb.top.LFSR_W.value) == 58:
+        factory = TestFactory(run_test_descramble)
+        factory.add_option("ref_scramble", [scramble_64b66b])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize(("lfsr_w", "lfsr_poly", "lfsr_init", "lfsr_galois", "reverse", "data_w"), [
+            (58,  "58'h8000000001", "'1", 0, 1, 8),
+            (58,  "58'h8000000001", "'1", 0, 1, 64),
+        ])
+def test_taxi_lfsr_descramble(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois, reverse, data_w):
+    dut = "taxi_lfsr_descramble"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_lfsr.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['LFSR_W'] = lfsr_w
+    parameters['LFSR_POLY'] = lfsr_poly
+    parameters['LFSR_INIT'] = lfsr_init
+    parameters['LFSR_GALOIS'] = f"1'b{lfsr_galois}"
+    parameters['REVERSE'] = f"1'b{reverse}"
+    parameters['DATA_W'] = data_w
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/lfsr/tb/taxi_lfsr_prbs_check/Makefile

@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+
+DUT      = taxi_lfsr_prbs_check
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_LFSR_W ?= 31
+export PARAM_LFSR_POLY ?= "31'h10000001"
+export PARAM_LFSR_INIT ?= "'1"
+export PARAM_LFSR_GALOIS ?= "1'b0"
+export PARAM_REVERSE ?= "1'b0"
+export PARAM_INVERT ?= "1'b1"
+export PARAM_DATA_W ?= 8
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/lfsr/tb/taxi_lfsr_prbs_check/test_taxi_lfsr_prbs_check.py

@@ -0,0 +1,223 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        dut.data_in.setimmediatevalue(0)
+        dut.data_in_valid.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+def chunks(lst, n, padvalue=None):
+    return itertools.zip_longest(*[iter(lst)]*n, fillvalue=padvalue)
+
+
+def prbs9(state=0x1ff):
+    while True:
+        for i in range(8):
+            if bool(state & 0x10) ^ bool(state & 0x100):
+                state = ((state & 0xff) << 1) | 1
+            else:
+                state = (state & 0xff) << 1
+        yield ~state & 0xff
+
+
+def prbs31(state=0x7fffffff):
+    while True:
+        for i in range(8):
+            if bool(state & 0x08000000) ^ bool(state & 0x40000000):
+                state = ((state & 0x3fffffff) << 1) | 1
+            else:
+                state = (state & 0x3fffffff) << 1
+        yield ~state & 0xff
+
+
+def count_set_bits(n):
+    cnt = 0
+    while n:
+        n &= n - 1
+        cnt += 1
+    return cnt
+
+
+async def run_test_prbs(dut, ref_prbs):
+
+    data_width = len(dut.data_out)
+    byte_lanes = data_width // 8
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    gen = chunks(ref_prbs(), byte_lanes)
+
+    err_cnt = 0
+
+    for i in range(512):
+
+        dut.data_in.value = int.from_bytes(bytes(next(gen)), 'big')
+        dut.data_in_valid.value = 1
+
+        val = dut.data_out.value.integer
+
+        tb.log.info("Error value: 0x%x", val)
+
+        err_cnt += count_set_bits(val)
+
+        assert val == 0
+
+        await RisingEdge(dut.clk)
+
+    dut.data_in_valid.value = 0
+
+    tb.log.info("Error count: %d", err_cnt)
+
+    assert err_cnt == 0
+
+    await tb.reset()
+
+    tb.log.info("Single error test")
+
+    gen = chunks(ref_prbs(), byte_lanes)
+
+    err_cnt = 0
+
+    for i in range(64):
+
+        val = int.from_bytes(bytes(next(gen)), 'big')
+
+        if i == 32:
+            val = val ^ (1 << (data_width // 2))
+
+        dut.data_in.value = val
+        dut.data_in_valid.value = 1
+
+        val = dut.data_out.value.integer
+
+        tb.log.info("Error value: 0x%x", val)
+
+        err_cnt += count_set_bits(val)
+
+        await RisingEdge(dut.clk)
+
+    dut.data_in_valid.value = 0
+
+    tb.log.info("Error count: %d", err_cnt)
+
+    # one bit set per tap
+    assert err_cnt == 3
+
+
+if cocotb.SIM_NAME:
+
+    if int(cocotb.top.LFSR_POLY.value) == 0x021:
+        factory = TestFactory(run_test_prbs)
+        factory.add_option("ref_prbs", [prbs9])
+        factory.generate_tests()
+
+    if int(cocotb.top.LFSR_POLY.value) == 0x10000001:
+        factory = TestFactory(run_test_prbs)
+        factory.add_option("ref_prbs", [prbs31])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize(("lfsr_w", "lfsr_poly", "lfsr_init", "lfsr_galois", "reverse", "invert", "data_w"), [
+            (9,  "9'h021", "'1", 0, 0, 1, 8),
+            (9,  "9'h021", "'1", 0, 0, 1, 64),
+            (31, "31'h10000001", "'1", 0, 0, 1, 8),
+            (31, "31'h10000001", "'1", 0, 0, 1, 64),
+        ])
+def test_taxi_lfsr_prbs_check(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois, reverse, invert, data_w):
+    dut = "taxi_lfsr_prbs_check"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_lfsr.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['LFSR_W'] = lfsr_w
+    parameters['LFSR_POLY'] = lfsr_poly
+    parameters['LFSR_INIT'] = lfsr_init
+    parameters['LFSR_GALOIS'] = f"1'b{lfsr_galois}"
+    parameters['REVERSE'] = f"1'b{reverse}"
+    parameters['INVERT'] = f"1'b{invert}"
+    parameters['DATA_W'] = data_w
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/lfsr/tb/taxi_lfsr_prbs_gen/Makefile

@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+
+DUT      = taxi_lfsr_prbs_gen
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_LFSR_W ?= 31
+export PARAM_LFSR_POLY ?= "31'h10000001"
+export PARAM_LFSR_INIT ?= "'1"
+export PARAM_LFSR_GALOIS ?= "1'b0"
+export PARAM_REVERSE ?= "1'b0"
+export PARAM_INVERT ?= "1'b1"
+export PARAM_DATA_W ?= 8
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/lfsr/tb/taxi_lfsr_prbs_gen/test_taxi_lfsr_prbs_gen.py

@@ -0,0 +1,171 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        dut.enable.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+def chunks(lst, n, padvalue=None):
+    return itertools.zip_longest(*[iter(lst)]*n, fillvalue=padvalue)
+
+
+def prbs9(state=0x1ff):
+    while True:
+        for i in range(8):
+            if bool(state & 0x10) ^ bool(state & 0x100):
+                state = ((state & 0xff) << 1) | 1
+            else:
+                state = (state & 0xff) << 1
+        yield ~state & 0xff
+
+
+def prbs31(state=0x7fffffff):
+    while True:
+        for i in range(8):
+            if bool(state & 0x08000000) ^ bool(state & 0x40000000):
+                state = ((state & 0x3fffffff) << 1) | 1
+            else:
+                state = (state & 0x3fffffff) << 1
+        yield ~state & 0xff
+
+
+async def run_test_prbs(dut, ref_prbs):
+
+    data_width = len(dut.data_out)
+    byte_lanes = data_width // 8
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    gen = chunks(ref_prbs(), byte_lanes)
+
+    dut.enable.value = 1
+    await RisingEdge(dut.clk)
+
+    for i in range(512):
+        ref = int.from_bytes(bytes(next(gen)), 'big')
+        val = dut.data_out.value.integer
+
+        tb.log.info("PRBS: 0x%x (ref: 0x%x)", val, ref)
+
+        assert ref == val
+
+        await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    if int(cocotb.top.LFSR_POLY.value) == 0x021:
+        factory = TestFactory(run_test_prbs)
+        factory.add_option("ref_prbs", [prbs9])
+        factory.generate_tests()
+
+    if int(cocotb.top.LFSR_POLY.value) == 0x10000001:
+        factory = TestFactory(run_test_prbs)
+        factory.add_option("ref_prbs", [prbs31])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize(("lfsr_w", "lfsr_poly", "lfsr_init", "lfsr_galois", "reverse", "invert", "data_w"), [
+            (9,  "9'h021", "'1", 0, 0, 1, 8),
+            (9,  "9'h021", "'1", 0, 0, 1, 64),
+            (31, "31'h10000001", "'1", 0, 0, 1, 8),
+            (31, "31'h10000001", "'1", 0, 0, 1, 64),
+        ])
+def test_taxi_lfsr_prbs_gen(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois, reverse, invert, data_w):
+    dut = "taxi_lfsr_prbs_gen"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_lfsr.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['LFSR_W'] = lfsr_w
+    parameters['LFSR_POLY'] = lfsr_poly
+    parameters['LFSR_INIT'] = lfsr_init
+    parameters['LFSR_GALOIS'] = f"1'b{lfsr_galois}"
+    parameters['REVERSE'] = f"1'b{reverse}"
+    parameters['INVERT'] = f"1'b{invert}"
+    parameters['DATA_W'] = data_w
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

src/lfsr/tb/taxi_lfsr_scramble/Makefile

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2023-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+RTL_DIR = ../../rtl
+
+DUT      = taxi_lfsr_scramble
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
+VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_LFSR_W ?= 58
+export PARAM_LFSR_POLY ?= "58'h8000000001"
+export PARAM_LFSR_INIT ?= "'1"
+export PARAM_LFSR_GALOIS ?= "1'b0"
+export PARAM_REVERSE ?= "1'b1"
+export PARAM_DATA_W ?= 8
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/lfsr/tb/taxi_lfsr_scramble/test_taxi_lfsr_scramble.py

@@ -0,0 +1,170 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2023-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import pytest
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        dut.data_in.setimmediatevalue(0)
+        dut.data_in_valid.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+def chunks(lst, n, padvalue=None):
+    return itertools.zip_longest(*[iter(lst)]*n, fillvalue=padvalue)
+
+
+def scramble_64b66b(data, state=0x3ffffffffffffff):
+    data_out = bytearray()
+    for d in data:
+        b = 0
+        for i in range(8):
+            if bool(state & (1 << 38)) ^ bool(state & (1 << 57)) ^ bool(d & (1 << i)):
+                state = ((state & 0x1ffffffffffffff) << 1) | 1
+                b = b | (1 << i)
+            else:
+                state = (state & 0x1ffffffffffffff) << 1
+        data_out.append(b)
+    return data_out
+
+
+async def run_test_scramble(dut, ref_scramble):
+
+    data_width = len(dut.data_in)
+    byte_lanes = data_width // 8
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    block = bytearray(itertools.islice(itertools.cycle(range(256)), 1024))
+
+    scr = scramble_64b66b(block)
+    scr_iter = iter(chunks(scr, byte_lanes))
+
+    first = True
+    for b in chunks(block, byte_lanes):
+        dut.data_in.value = int.from_bytes(b, 'little')
+        dut.data_in_valid.value = 1
+        await RisingEdge(dut.clk)
+
+        val = dut.data_out.value.integer
+
+        if not first:
+            ref = int.from_bytes(bytes(next(scr_iter)), 'little')
+
+            tb.log.info("Scrambled: 0x%x (ref: 0x%x)", val, ref)
+
+            assert ref == val
+
+        first = False
+
+    dut.data_in_valid.value = 0
+
+    await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    # if cocotb.top.LFSR_POLY.value == 0x8000000001:
+    if int(cocotb.top.LFSR_W.value) == 58:
+        factory = TestFactory(run_test_scramble)
+        factory.add_option("ref_scramble", [scramble_64b66b])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize(("lfsr_w", "lfsr_poly", "lfsr_init", "lfsr_galois", "reverse", "data_w"), [
+            (58,  "58'h8000000001", "'1", 0, 1, 8),
+            (58,  "58'h8000000001", "'1", 0, 1, 64),
+        ])
+def test_taxi_lfsr_scramble(request, lfsr_w, lfsr_poly, lfsr_init, lfsr_galois, reverse, data_w):
+    dut = "taxi_lfsr_scramble"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(rtl_dir, "taxi_lfsr.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['LFSR_W'] = lfsr_w
+    parameters['LFSR_POLY'] = lfsr_poly
+    parameters['LFSR_INIT'] = lfsr_init
+    parameters['LFSR_GALOIS'] = f"1'b{lfsr_galois}"
+    parameters['REVERSE'] = f"1'b{reverse}"
+    parameters['DATA_W'] = data_w
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )