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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-05-18 12:25:59 -07:00
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2015-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* I2C master
*/
module taxi_i2c_master (
input wire logic clk,
input wire logic rst,
/*
* Host interface
*/
taxi_axis_if.snk s_axis_cmd,
taxi_axis_if.snk s_axis_data,
taxi_axis_if.src m_axis_data,
/*
* I2C interface
*/
input wire logic scl_i,
output wire logic scl_o,
input wire logic sda_i,
output wire logic sda_o,
/*
* Status
*/
output wire logic busy,
output wire logic bus_control,
output wire logic bus_active,
output wire logic missed_ack,
/*
* Configuration
*/
input wire logic [15:0] prescale,
input wire logic stop_on_idle
);
/*
I2C
Read
__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/
____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
Write
__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/
____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
Command encoding:
cmd[6:0] address
cmd[7] start
cmd[8] read
cmd[9] write
cmd[10] write_multiple
cmd[11] stop
Commands:
read
read data byte
set start to force generation of a start condition
start is implied when bus is inactive or active with write or different address
set stop to issue a stop condition after reading current byte
if stop is set with read command, then m_axis_data_tlast will be set
write
write data byte
set start to force generation of a start condition
start is implied when bus is inactive or active with read or different address
set stop to issue a stop condition after writing current byte
write multiple
write multiple data bytes (until s_axis_data_tlast)
set start to force generation of a start condition
start is implied when bus is inactive or active with read or different address
set stop to issue a stop condition after writing block
stop
issue stop condition if bus is active
Status:
busy
module is communicating over the bus
bus_control
module has control of bus in active state
bus_active
bus is active, not necessarily controlled by this module
missed_ack
strobed when a slave ack is missed
Parameters:
prescale
set prescale to 1/4 of the minimum clock period in units
of input clk cycles (prescale = Fclk / (FI2Cclk * 4))
stop_on_idle
automatically issue stop when command input is not valid
Example of interfacing with tristate pins:
assign scl_i = scl_pin;
assign scl_pin = scl_o ? 1'bz : 1'b0;
assign sda_i = sda_pin;
assign sda_pin = sda_o ? 1'bz : 1'b0;
Example of two interconnected internal I2C devices:
assign scl_1_i = scl_1_o & scl_2_o;
assign scl_2_i = scl_1_o & scl_2_o;
assign sda_1_i = sda_1_o & sda_2_o;
assign sda_2_i = sda_1_o & sda_2_o;
Example of two I2C devices sharing the same pins:
assign scl_1_i = scl_pin;
assign scl_2_i = scl_pin;
assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;
assign sda_1_i = sda_pin;
assign sda_2_i = sda_pin;
assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;
Notes:
scl_o should not be connected directly to scl_i, only via AND logic or a tristate
I/O pin. This would prevent devices from stretching the clock period.
*/
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_ACTIVE_WRITE = 4'd1,
STATE_ACTIVE_READ = 4'd2,
STATE_START_WAIT = 4'd3,
STATE_START = 4'd4,
STATE_ADDRESS_1 = 4'd5,
STATE_ADDRESS_2 = 4'd6,
STATE_WRITE_1 = 4'd7,
STATE_WRITE_2 = 4'd8,
STATE_WRITE_3 = 4'd9,
STATE_READ = 4'd10,
STATE_STOP = 4'd11;
logic [3:0] state_reg = STATE_IDLE, state_next;
localparam [3:0]
PHY_STATE_IDLE = 4'd0,
PHY_STATE_ACTIVE = 4'd1,
PHY_STATE_REPEATED_START_1 = 4'd2,
PHY_STATE_REPEATED_START_2 = 4'd3,
PHY_STATE_START_1 = 4'd4,
PHY_STATE_START_2 = 4'd5,
PHY_STATE_WRITE_BIT_1 = 4'd6,
PHY_STATE_WRITE_BIT_2 = 4'd7,
PHY_STATE_WRITE_BIT_3 = 4'd8,
PHY_STATE_READ_BIT_1 = 4'd9,
PHY_STATE_READ_BIT_2 = 4'd10,
PHY_STATE_READ_BIT_3 = 4'd11,
PHY_STATE_READ_BIT_4 = 4'd12,
PHY_STATE_STOP_1 = 4'd13,
PHY_STATE_STOP_2 = 4'd14,
PHY_STATE_STOP_3 = 4'd15;
logic [3:0] phy_state_reg = STATE_IDLE, phy_state_next;
logic phy_start_bit;
logic phy_stop_bit;
logic phy_write_bit;
logic phy_read_bit;
logic phy_release_bus;
logic phy_tx_data;
logic phy_rx_data_reg = 1'b0, phy_rx_data_next;
logic [6:0] addr_reg = '0, addr_next;
logic [7:0] data_reg = '0, data_next;
logic last_reg = 1'b0, last_next;
logic mode_read_reg = 1'b0, mode_read_next;
logic mode_write_multiple_reg = 1'b0, mode_write_multiple_next;
logic mode_stop_reg = 1'b0, mode_stop_next;
logic [16:0] delay_reg = '0, delay_next;
logic delay_scl_reg = 1'b0, delay_scl_next;
logic delay_sda_reg = 1'b0, delay_sda_next;
logic [3:0] bit_count_reg = '0, bit_count_next;
logic s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next;
logic s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next;
logic [7:0] m_axis_data_tdata_reg = '0, m_axis_data_tdata_next;
logic m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next;
logic m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next;
logic scl_i_reg = 1'b1;
logic sda_i_reg = 1'b1;
logic scl_o_reg = 1'b1, scl_o_next;
logic sda_o_reg = 1'b1, sda_o_next;
logic last_scl_i_reg = 1'b1;
logic last_sda_i_reg = 1'b1;
logic busy_reg = 1'b0;
logic bus_active_reg = 1'b0;
logic bus_control_reg = 1'b0, bus_control_next;
logic missed_ack_reg = 1'b0, missed_ack_next;
wire [6:0] s_axis_cmd_address = s_axis_cmd.tdata[6:0];
wire s_axis_cmd_start = s_axis_cmd.tdata[7];
wire s_axis_cmd_read = s_axis_cmd.tdata[8];
wire s_axis_cmd_write = s_axis_cmd.tdata[9];
wire s_axis_cmd_write_multi = s_axis_cmd.tdata[10];
wire s_axis_cmd_stop = s_axis_cmd.tdata[11];
assign s_axis_cmd.tready = s_axis_cmd_ready_reg;
assign s_axis_data.tready = s_axis_data_tready_reg;
assign m_axis_data.tdata = m_axis_data_tdata_reg;
assign m_axis_data.tkeep = '1;
assign m_axis_data.tstrb = m_axis_data.tkeep;
assign m_axis_data.tvalid = m_axis_data_tvalid_reg;
assign m_axis_data.tlast = m_axis_data_tlast_reg;
assign m_axis_data.tid = '0;
assign m_axis_data.tdest = '0;
assign m_axis_data.tuser = '0;
assign scl_o = scl_o_reg;
assign sda_o = sda_o_reg;
assign busy = busy_reg;
assign bus_active = bus_active_reg;
assign bus_control = bus_control_reg;
assign missed_ack = missed_ack_reg;
wire scl_posedge = scl_i_reg && !last_scl_i_reg;
wire scl_negedge = !scl_i_reg && last_scl_i_reg;
wire sda_posedge = sda_i_reg && !last_sda_i_reg;
wire sda_negedge = !sda_i_reg && last_sda_i_reg;
wire start_bit = sda_negedge && scl_i_reg;
wire stop_bit = sda_posedge && scl_i_reg;
always_comb begin
state_next = STATE_IDLE;
phy_start_bit = 1'b0;
phy_stop_bit = 1'b0;
phy_write_bit = 1'b0;
phy_read_bit = 1'b0;
phy_tx_data = 1'b0;
phy_release_bus = 1'b0;
addr_next = addr_reg;
data_next = data_reg;
last_next = last_reg;
mode_read_next = mode_read_reg;
mode_write_multiple_next = mode_write_multiple_reg;
mode_stop_next = mode_stop_reg;
bit_count_next = bit_count_reg;
s_axis_cmd_ready_next = 1'b0;
s_axis_data_tready_next = 1'b0;
m_axis_data_tdata_next = m_axis_data_tdata_reg;
m_axis_data_tvalid_next = m_axis_data_tvalid_reg && !m_axis_data.tready;
m_axis_data_tlast_next = m_axis_data_tlast_reg;
missed_ack_next = 1'b0;
// generate delays
if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin
// wait for phy operation
state_next = state_reg;
end else begin
// process states
case (state_reg)
STATE_IDLE: begin
// line idle
s_axis_cmd_ready_next = 1'b1;
if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin
// command valid
if (s_axis_cmd_read ^ (s_axis_cmd_write || s_axis_cmd_write_multi)) begin
// read or write command
addr_next = s_axis_cmd_address;
mode_read_next = s_axis_cmd_read;
mode_write_multiple_next = s_axis_cmd_write_multi;
mode_stop_next = s_axis_cmd_stop;
s_axis_cmd_ready_next = 1'b0;
// start bit
if (bus_active) begin
state_next = STATE_START_WAIT;
end else begin
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
end else begin
// invalid or unspecified - ignore
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_ACTIVE_WRITE: begin
// line active with current address and read/write mode
s_axis_cmd_ready_next = 1'b1;
if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin
// command valid
if (s_axis_cmd_read ^ (s_axis_cmd_write || s_axis_cmd_write_multi)) begin
// read or write command
addr_next = s_axis_cmd_address;
mode_read_next = s_axis_cmd_read;
mode_write_multiple_next = s_axis_cmd_write_multi;
mode_stop_next = s_axis_cmd_stop;
s_axis_cmd_ready_next = 1'b0;
if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin
// address or mode mismatch or forced start - repeated start
// repeated start bit
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end else begin
// address and mode match
// start write
s_axis_data_tready_next = 1'b1;
state_next = STATE_WRITE_1;
end
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multi)) begin
// stop command
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid or unspecified - ignore
state_next = STATE_ACTIVE_WRITE;
end
end else begin
if (stop_on_idle && s_axis_cmd.tready && !s_axis_cmd.tvalid) begin
// no waiting command and stop_on_idle selected, issue stop condition
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_ACTIVE_WRITE;
end
end
end
STATE_ACTIVE_READ: begin
// line active to current address
s_axis_cmd_ready_next = !m_axis_data.tvalid;
if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin
// command valid
if (s_axis_cmd_read ^ (s_axis_cmd_write || s_axis_cmd_write_multi)) begin
// read or write command
addr_next = s_axis_cmd_address;
mode_read_next = s_axis_cmd_read;
mode_write_multiple_next = s_axis_cmd_write_multi;
mode_stop_next = s_axis_cmd_stop;
s_axis_cmd_ready_next = 1'b0;
if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin
// address or mode mismatch or forced start - repeated start
// write nack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// repeated start bit
state_next = STATE_START;
end else begin
// address and mode match
// write ack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b0;
// start next read
bit_count_next = 4'd8;
data_next = 8'd0;
state_next = STATE_READ;
end
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multi)) begin
// stop command
// write nack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// send stop bit
state_next = STATE_STOP;
end else begin
// invalid or unspecified - ignore
state_next = STATE_ACTIVE_READ;
end
end else begin
if (stop_on_idle && s_axis_cmd.tready && !s_axis_cmd.tvalid) begin
// no waiting command and stop_on_idle selected, issue stop condition
// write ack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// send stop bit
state_next = STATE_STOP;
end else begin
state_next = STATE_ACTIVE_READ;
end
end
end
STATE_START_WAIT: begin
// wait for bus idle
if (bus_active) begin
state_next = STATE_START_WAIT;
end else begin
// bus is idle, take control
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
end
STATE_START: begin
// send start bit
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
STATE_ADDRESS_1: begin
// send address
bit_count_next = bit_count_reg - 1;
if (bit_count_reg > 1) begin
// send address
phy_write_bit = 1'b1;
phy_tx_data = addr_reg[bit_count_reg-2];
state_next = STATE_ADDRESS_1;
end else if (bit_count_reg != 0) begin
// send read/write bit
phy_write_bit = 1'b1;
phy_tx_data = mode_read_reg;
state_next = STATE_ADDRESS_1;
end else begin
// read ack bit
phy_read_bit = 1'b1;
state_next = STATE_ADDRESS_2;
end
end
STATE_ADDRESS_2: begin
// read ack bit
missed_ack_next = phy_rx_data_reg;
if (mode_read_reg) begin
// start read
bit_count_next = 4'd8;
state_next = STATE_READ;
end else begin
// start write
s_axis_data_tready_next = 1'b1;
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_1: begin
s_axis_data_tready_next = 1'b1;
if (s_axis_data.tready && s_axis_data.tvalid) begin
// got data, start write
data_next = s_axis_data.tdata;
last_next = s_axis_data.tlast;
bit_count_next = 4'd8;
s_axis_data_tready_next = 1'b0;
state_next = STATE_WRITE_2;
end else begin
// wait for data
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_2: begin
// send data
bit_count_next = bit_count_reg - 1;
if (bit_count_reg != 0) begin
// write data bit
phy_write_bit = 1'b1;
phy_tx_data = data_reg[bit_count_reg-1];
state_next = STATE_WRITE_2;
end else begin
// read ack bit
phy_read_bit = 1'b1;
state_next = STATE_WRITE_3;
end
end
STATE_WRITE_3: begin
// read ack bit
missed_ack_next = phy_rx_data_reg;
if (mode_write_multiple_reg && !last_reg) begin
// more to write
state_next = STATE_WRITE_1;
end else if (mode_stop_reg) begin
// last cycle and stop selected
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
// otherwise, return to bus active state
state_next = STATE_ACTIVE_WRITE;
end
end
STATE_READ: begin
// read data
bit_count_next = bit_count_reg - 1;
data_next = {data_reg[6:0], phy_rx_data_reg};
if (bit_count_reg != 0) begin
// read next bit
phy_read_bit = 1'b1;
state_next = STATE_READ;
end else begin
// output data word
m_axis_data_tdata_next = data_next;
m_axis_data_tvalid_next = 1'b1;
m_axis_data_tlast_next = 1'b0;
if (mode_stop_reg) begin
// send nack and stop
m_axis_data_tlast_next = 1'b1;
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
state_next = STATE_STOP;
end else begin
// return to bus active state
state_next = STATE_ACTIVE_READ;
end
end
end
STATE_STOP: begin
// send stop bit
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end
default: begin
state_next = STATE_IDLE;
end
endcase
end
end
always_comb begin
phy_state_next = PHY_STATE_IDLE;
phy_rx_data_next = phy_rx_data_reg;
delay_next = delay_reg;
delay_scl_next = delay_scl_reg;
delay_sda_next = delay_sda_reg;
scl_o_next = scl_o_reg;
sda_o_next = sda_o_reg;
bus_control_next = bus_control_reg;
if (phy_release_bus) begin
// release bus and return to idle state
sda_o_next = 1'b1;
scl_o_next = 1'b1;
delay_scl_next = 1'b0;
delay_sda_next = 1'b0;
delay_next = '0;
phy_state_next = PHY_STATE_IDLE;
end else if (delay_scl_reg) begin
// wait for SCL to match command
delay_scl_next = scl_o_reg && !scl_i_reg;
phy_state_next = phy_state_reg;
end else if (delay_sda_reg) begin
// wait for SDA to match command
delay_sda_next = sda_o_reg && !sda_i_reg;
phy_state_next = phy_state_reg;
end else if (delay_reg != 0) begin
// time delay
delay_next = delay_reg - 1;
phy_state_next = phy_state_reg;
end else begin
case (phy_state_reg)
PHY_STATE_IDLE: begin
// bus idle - wait for start command
sda_o_next = 1'b1;
scl_o_next = 1'b1;
if (phy_start_bit) begin
sda_o_next = 1'b0;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_START_1;
end else begin
phy_state_next = PHY_STATE_IDLE;
end
end
PHY_STATE_ACTIVE: begin
// bus active
if (phy_start_bit) begin
sda_o_next = 1'b1;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_REPEATED_START_1;
end else if (phy_write_bit) begin
sda_o_next = phy_tx_data;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_WRITE_BIT_1;
end else if (phy_read_bit) begin
sda_o_next = 1'b1;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_READ_BIT_1;
end else if (phy_stop_bit) begin
sda_o_next = 1'b0;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_STOP_1;
end else begin
phy_state_next = PHY_STATE_ACTIVE;
end
end
PHY_STATE_REPEATED_START_1: begin
// generate repeated start bit
// ______
// sda XXX/ \_______
// _______
// scl ______/ \___
//
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_REPEATED_START_2;
end
PHY_STATE_REPEATED_START_2: begin
// generate repeated start bit
// ______
// sda XXX/ \_______
// _______
// scl ______/ \___
//
sda_o_next = 1'b0;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_START_1;
end
PHY_STATE_START_1: begin
// generate start bit
// ___
// sda \_______
// _______
// scl \___
//
scl_o_next = 1'b0;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_START_2;
end
PHY_STATE_START_2: begin
// generate start bit
// ___
// sda \_______
// _______
// scl \___
//
bus_control_next = 1'b1;
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_WRITE_BIT_1: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_WRITE_BIT_2;
end
PHY_STATE_WRITE_BIT_2: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b0;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_WRITE_BIT_3;
end
PHY_STATE_WRITE_BIT_3: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_READ_BIT_1: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_READ_BIT_2;
end
PHY_STATE_READ_BIT_2: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_rx_data_next = sda_i_reg;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_READ_BIT_3;
end
PHY_STATE_READ_BIT_3: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b0;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_READ_BIT_4;
end
PHY_STATE_READ_BIT_4: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_STOP_1: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_STOP_2;
end
PHY_STATE_STOP_2: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
sda_o_next = 1'b1;
delay_next = 17'(prescale);
phy_state_next = PHY_STATE_STOP_3;
end
PHY_STATE_STOP_3: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
bus_control_next = 1'b0;
phy_state_next = PHY_STATE_IDLE;
end
default: begin
phy_state_next = PHY_STATE_IDLE;
end
endcase
end
end
always_ff @(posedge clk) begin
state_reg <= state_next;
phy_state_reg <= phy_state_next;
phy_rx_data_reg <= phy_rx_data_next;
addr_reg <= addr_next;
data_reg <= data_next;
last_reg <= last_next;
mode_read_reg <= mode_read_next;
mode_write_multiple_reg <= mode_write_multiple_next;
mode_stop_reg <= mode_stop_next;
delay_reg <= delay_next;
delay_scl_reg <= delay_scl_next;
delay_sda_reg <= delay_sda_next;
bit_count_reg <= bit_count_next;
s_axis_cmd_ready_reg <= s_axis_cmd_ready_next;
s_axis_data_tready_reg <= s_axis_data_tready_next;
m_axis_data_tdata_reg <= m_axis_data_tdata_next;
m_axis_data_tlast_reg <= m_axis_data_tlast_next;
m_axis_data_tvalid_reg <= m_axis_data_tvalid_next;
scl_i_reg <= scl_i;
sda_i_reg <= sda_i;
scl_o_reg <= scl_o_next;
sda_o_reg <= sda_o_next;
last_scl_i_reg <= scl_i_reg;
last_sda_i_reg <= sda_i_reg;
busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE);
if (start_bit) begin
bus_active_reg <= 1'b1;
end else if (stop_bit) begin
bus_active_reg <= 1'b0;
end else begin
bus_active_reg <= bus_active_reg;
end
bus_control_reg <= bus_control_next;
missed_ack_reg <= missed_ack_next;
if (rst) begin
state_reg <= STATE_IDLE;
phy_state_reg <= PHY_STATE_IDLE;
delay_reg <= '0;
delay_scl_reg <= 1'b0;
delay_sda_reg <= 1'b0;
s_axis_cmd_ready_reg <= 1'b0;
s_axis_data_tready_reg <= 1'b0;
m_axis_data_tvalid_reg <= 1'b0;
scl_o_reg <= 1'b1;
sda_o_reg <= 1'b1;
busy_reg <= 1'b0;
bus_active_reg <= 1'b0;
bus_control_reg <= 1'b0;
missed_ack_reg <= 1'b0;
end
end
endmodule
`resetall

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src/lss/rtl/taxi_i2c_single_reg.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2023-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* I2C single register
*/
module taxi_i2c_single_reg #(
parameter FILTER_LEN = 4,
parameter logic [6:0] DEV_ADDR = 7'h70
)
(
input wire logic clk,
input wire logic rst,
/*
* I2C interface
*/
input wire logic scl_i,
output wire logic scl_o,
input wire logic sda_i,
output wire logic sda_o,
/*
* Data register
*/
input wire logic [7:0] data_in = '0,
input wire logic data_latch = '0,
output wire logic [7:0] data_out
);
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_ADDRESS = 3'd1,
STATE_ACK = 3'd2,
STATE_WRITE_1 = 3'd3,
STATE_WRITE_2 = 3'd4,
STATE_READ_1 = 3'd5,
STATE_READ_2 = 3'd6,
STATE_READ_3 = 3'd7;
logic [2:0] state_reg = STATE_IDLE;
logic [7:0] data_reg = '0;
logic [7:0] shift_reg = '0;
logic mode_read_reg = 1'b0;
logic [3:0] bit_count_reg = '0;
logic [FILTER_LEN-1:0] scl_i_filter_reg = '1;
logic [FILTER_LEN-1:0] sda_i_filter_reg = '1;
logic scl_i_reg = 1'b1;
logic sda_i_reg = 1'b1;
logic sda_o_reg = 1'b1;
logic last_scl_i_reg = 1'b1;
logic last_sda_i_reg = 1'b1;
assign scl_o = 1'b1;
assign sda_o = sda_o_reg;
assign data_out = data_reg;
wire scl_posedge = scl_i_reg && !last_scl_i_reg;
wire scl_negedge = !scl_i_reg && last_scl_i_reg;
wire sda_posedge = sda_i_reg && !last_sda_i_reg;
wire sda_negedge = !sda_i_reg && last_sda_i_reg;
wire start_bit = sda_negedge && scl_i_reg;
wire stop_bit = sda_posedge && scl_i_reg;
always_ff @(posedge clk) begin
if (start_bit) begin
sda_o_reg <= 1'b1;
bit_count_reg <= 4'd7;
state_reg <= STATE_ADDRESS;
end else if (stop_bit) begin
sda_o_reg <= 1'b1;
state_reg <= STATE_IDLE;
end else begin
case (state_reg)
STATE_IDLE: begin
// line idle
sda_o_reg <= 1'b1;
state_reg <= STATE_IDLE;
end
STATE_ADDRESS: begin
// read address
sda_o_reg <= 1'b1;
if (scl_posedge) begin
if (bit_count_reg > 0) begin
// shift in address
bit_count_reg <= bit_count_reg-1;
shift_reg <= {shift_reg[6:0], sda_i_reg};
state_reg <= STATE_ADDRESS;
end else begin
// check address
mode_read_reg <= sda_i_reg;
if (shift_reg[6:0] == DEV_ADDR) begin
// it's a match, send ACK
state_reg <= STATE_ACK;
end else begin
// no match, return to idle
state_reg <= STATE_IDLE;
end
end
end else begin
state_reg <= STATE_ADDRESS;
end
end
STATE_ACK: begin
// send ACK bit
if (scl_negedge) begin
sda_o_reg <= 1'b0;
bit_count_reg <= 4'd7;
if (mode_read_reg) begin
// reading
shift_reg <= data_reg;
state_reg <= STATE_READ_1;
end else begin
// writing
state_reg <= STATE_WRITE_1;
end
end else begin
state_reg <= STATE_ACK;
end
end
STATE_WRITE_1: begin
// write data byte
if (scl_negedge) begin
sda_o_reg <= 1'b1;
state_reg <= STATE_WRITE_2;
end else begin
state_reg <= STATE_WRITE_1;
end
end
STATE_WRITE_2: begin
// write data byte
sda_o_reg <= 1'b1;
if (scl_posedge) begin
// shift in data bit
shift_reg <= {shift_reg[6:0], sda_i_reg};
if (bit_count_reg > 0) begin
bit_count_reg <= bit_count_reg-1;
state_reg <= STATE_WRITE_2;
end else begin
data_reg <= {shift_reg[6:0], sda_i_reg};
state_reg <= STATE_ACK;
end
end else begin
state_reg <= STATE_WRITE_2;
end
end
STATE_READ_1: begin
// read data byte
if (scl_negedge) begin
// shift out data bit
{sda_o_reg, shift_reg} <= {shift_reg, sda_i_reg};
if (bit_count_reg > 0) begin
bit_count_reg <= bit_count_reg-1;
state_reg <= STATE_READ_1;
end else begin
state_reg <= STATE_READ_2;
end
end else begin
state_reg <= STATE_READ_1;
end
end
STATE_READ_2: begin
// read ACK bit
if (scl_negedge) begin
// release SDA
sda_o_reg <= 1'b1;
state_reg <= STATE_READ_3;
end else begin
state_reg <= STATE_READ_2;
end
end
STATE_READ_3: begin
// read ACK bit
if (scl_posedge) begin
if (sda_i_reg) begin
// NACK, return to idle
state_reg <= STATE_IDLE;
end else begin
// ACK, read another byte
bit_count_reg <= 4'd7;
shift_reg <= data_reg;
state_reg <= STATE_READ_1;
end
end else begin
state_reg <= STATE_READ_3;
end
end
endcase
end
if (data_latch) begin
data_reg <= data_in;
end
scl_i_filter_reg <= {scl_i_filter_reg[FILTER_LEN-2:0], scl_i};
sda_i_filter_reg <= {sda_i_filter_reg[FILTER_LEN-2:0], sda_i};
if (scl_i_filter_reg == '1) begin
scl_i_reg <= 1'b1;
end else if (scl_i_filter_reg == '0) begin
scl_i_reg <= 1'b0;
end
if (sda_i_filter_reg == '1) begin
sda_i_reg <= 1'b1;
end else if (sda_i_filter_reg == '0) begin
sda_i_reg <= 1'b0;
end
last_scl_i_reg <= scl_i_reg;
last_sda_i_reg <= sda_i_reg;
if (rst) begin
state_reg <= STATE_IDLE;
data_reg <= 8'd0;
sda_o_reg <= 1'b1;
end
end
endmodule
`resetall

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src/lss/rtl/taxi_mdio_master.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2015-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* MDIO master
*/
module taxi_mdio_master (
input wire logic clk,
input wire logic rst,
/*
* Host interface
*/
taxi_axis_if.snk s_axis_cmd,
taxi_axis_if.src m_axis_rd_data,
/*
* MDIO to PHY
*/
output wire logic mdc_o,
input wire logic mdio_i,
output wire logic mdio_o,
output wire logic mdio_t,
/*
* Status
*/
output wire logic busy,
/*
* Configuration
*/
input wire logic [7:0] prescale
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PREAMBLE = 2'd1,
STATE_TRANSFER = 2'd2;
logic [1:0] state_reg = STATE_IDLE, state_next;
logic [7:0] count_reg = '0, count_next;
logic [5:0] bit_count_reg = '0, bit_count_next;
logic cycle_reg = 1'b0, cycle_next;
logic [31:0] data_reg = '0, data_next;
logic [1:0] op_reg = 2'b00, op_next;
logic s_axis_cmd_ready_reg = 1'b0, cmd_ready_next;
logic [15:0] m_axis_rd_data_reg = '0, m_axis_rd_data_next;
logic m_axis_rd_data_valid_reg = 1'b0, m_axis_rd_data_valid_next;
logic mdio_i_reg = 1'b1;
logic mdc_o_reg = 1'b0, mdc_o_next;
logic mdio_o_reg = 1'b0, mdio_o_next;
logic mdio_t_reg = 1'b1, mdio_t_next;
logic busy_reg = 1'b0;
assign s_axis_cmd.tready = s_axis_cmd_ready_reg;
assign m_axis_rd_data.tdata = m_axis_rd_data_reg;
assign m_axis_rd_data.tkeep = '1;
assign m_axis_rd_data.tstrb = m_axis_rd_data.tkeep;
assign m_axis_rd_data.tvalid = m_axis_rd_data_valid_reg;
assign m_axis_rd_data.tlast = 1'b1;
assign m_axis_rd_data.tid = '0;
assign m_axis_rd_data.tdest = '0;
assign m_axis_rd_data.tuser = '0;
assign mdc_o = mdc_o_reg;
assign mdio_o = mdio_o_reg;
assign mdio_t = mdio_t_reg;
assign busy = busy_reg;
wire [1:0] cmd_st = s_axis_cmd.tdata[31:30];
wire [1:0] cmd_op = s_axis_cmd.tdata[29:28];
wire [9:0] cmd_addr = s_axis_cmd.tdata[27:18];
wire [15:0] cmd_data = s_axis_cmd.tdata[15:0];
always_comb begin
state_next = STATE_IDLE;
count_next = count_reg;
bit_count_next = bit_count_reg;
cycle_next = cycle_reg;
data_next = data_reg;
op_next = op_reg;
cmd_ready_next = 1'b0;
m_axis_rd_data_next = m_axis_rd_data_reg;
m_axis_rd_data_valid_next = m_axis_rd_data_valid_reg && !m_axis_rd_data.tready;
mdc_o_next = mdc_o_reg;
mdio_o_next = mdio_o_reg;
mdio_t_next = mdio_t_reg;
if (count_reg != 0) begin
count_next = count_reg - 8'd1;
state_next = state_reg;
end else if (cycle_reg) begin
cycle_next = 1'b0;
mdc_o_next = 1'b1;
count_next = prescale;
state_next = state_reg;
end else begin
mdc_o_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle - accept new command
if (s_axis_cmd.tvalid) begin
cmd_ready_next = 1'b1;
data_next = {cmd_st, cmd_op, cmd_addr, 2'b10, cmd_data};
op_next = cmd_op;
mdio_t_next = 1'b0;
mdio_o_next = 1'b1;
bit_count_next = 6'd32;
cycle_next = 1'b1;
count_next = prescale;
state_next = STATE_PREAMBLE;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PREAMBLE: begin
cycle_next = 1'b1;
count_next = prescale;
if (bit_count_reg > 6'd1) begin
bit_count_next = bit_count_reg - 6'd1;
state_next = STATE_PREAMBLE;
end else begin
bit_count_next = 6'd32;
{mdio_o_next, data_next} = {data_reg, mdio_i_reg};
state_next = STATE_TRANSFER;
end
end
STATE_TRANSFER: begin
cycle_next = 1'b1;
count_next = prescale;
if (op_reg[1] && bit_count_reg == 6'd19) begin
mdio_t_next = 1'b1;
end
if (bit_count_reg > 6'd1) begin
bit_count_next = bit_count_reg - 6'd1;
{mdio_o_next, data_next} = {data_reg, mdio_i_reg};
state_next = STATE_TRANSFER;
end else begin
if (op_reg[1]) begin
m_axis_rd_data_next = data_reg[15:0];
m_axis_rd_data_valid_next = 1'b1;
end
mdio_t_next = 1'b1;
state_next = STATE_IDLE;
end
end
default: begin
state_next = STATE_IDLE;
end
endcase
end
end
always_ff @(posedge clk) begin
state_reg <= state_next;
count_reg <= count_next;
bit_count_reg <= bit_count_next;
cycle_reg <= cycle_next;
data_reg <= data_next;
op_reg <= op_next;
s_axis_cmd_ready_reg <= cmd_ready_next;
m_axis_rd_data_reg <= m_axis_rd_data_next;
m_axis_rd_data_valid_reg <= m_axis_rd_data_valid_next;
mdio_i_reg <= mdio_i;
mdc_o_reg <= mdc_o_next;
mdio_o_reg <= mdio_o_next;
mdio_t_reg <= mdio_t_next;
busy_reg <= (state_next != STATE_IDLE || count_reg != 0 || cycle_reg || mdc_o);
if (rst) begin
state_reg <= STATE_IDLE;
count_reg <= '0;
bit_count_reg <= '0;
cycle_reg <= 1'b0;
s_axis_cmd_ready_reg <= 1'b0;
m_axis_rd_data_valid_reg <= 1'b0;
mdc_o_reg <= 1'b0;
mdio_o_reg <= 1'b0;
mdio_t_reg <= 1'b1;
busy_reg <= 1'b0;
end
end
endmodule
`resetall

5
src/lss/rtl/taxi_uart.f Normal file
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taxi_uart.sv
taxi_uart_rx.sv
taxi_uart_tx.sv
taxi_uart_brg.sv
../lib/taxi/src/axis/rtl/taxi_axis_if.sv

132
src/lss/rtl/taxi_uart.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream UART
*/
module taxi_uart #(
parameter PRE_W = 16
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis_tx,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis_rx,
/*
* UART interface
*/
input wire logic rxd,
output wire logic txd,
/*
* Status
*/
output wire logic tx_busy,
output wire logic rx_busy,
output wire logic rx_overrun_error,
output wire logic rx_frame_error,
/*
* Configuration
*/
input wire logic [PRE_W-1:0] prescale
);
wire baud_clk;
taxi_uart_brg #(
.PRE_W(PRE_W)
)
uart_brg_inst (
.clk(clk),
.rst(rst),
/*
* Baud rate pulse out
*/
.baud_clk(baud_clk),
/*
* Configuration
*/
.prescale(prescale)
);
taxi_uart_tx
uart_tx_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis_tx(s_axis_tx),
/*
* UART interface
*/
.txd(txd),
/*
* Status
*/
.busy(tx_busy),
/*
* Baud rate pulse in
*/
.baud_clk(baud_clk)
);
taxi_uart_rx
uart_rx_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream output (source)
*/
.m_axis_rx(m_axis_rx),
/*
* UART interface
*/
.rxd(rxd),
/*
* Status
*/
.busy(rx_busy),
.overrun_error(rx_overrun_error),
.frame_error(rx_frame_error),
/*
* Baud rate pulse in
*/
.baud_clk(baud_clk)
);
endmodule
`resetall

70
src/lss/rtl/taxi_uart_brg.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream UART baud rate generator
*/
module taxi_uart_brg #(
parameter PRE_W = 16
)
(
input wire logic clk,
input wire logic rst,
/*
* Baud rate pulse out
*/
output wire logic baud_clk,
/*
* Configuration
*/
input wire logic [PRE_W-1:0] prescale
);
localparam FRAC_W = 3;
localparam INT_W = PRE_W - FRAC_W;
logic [INT_W-1:0] prescale_int_reg = 0;
logic [FRAC_W-1:0] prescale_frac_reg = 0;
logic frac_ovf_reg = 1'b0;
logic baud_clk_reg = 1'b0;
assign baud_clk = baud_clk_reg;
always_ff @(posedge clk) begin
frac_ovf_reg <= 1'b0;
baud_clk_reg <= 1'b0;
if (frac_ovf_reg) begin
// delay extra cycle
frac_ovf_reg <= 1'b0;
end else if (prescale_int_reg != 0) begin
prescale_int_reg <= prescale_int_reg - 1;
end else begin
prescale_int_reg <= prescale[FRAC_W +: INT_W] - 1;
{frac_ovf_reg, prescale_frac_reg} <= prescale_frac_reg + prescale[FRAC_W-1:0];
baud_clk_reg <= 1'b1;
end
if (rst) begin
prescale_int_reg <= 0;
prescale_frac_reg <= 0;
baud_clk_reg <= 0;
end
end
endmodule
`resetall

139
src/lss/rtl/taxi_uart_rx.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream UART (RX)
*/
module taxi_uart_rx
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis_rx,
/*
* UART interface
*/
input wire logic rxd,
/*
* Status
*/
output wire logic busy,
output wire logic overrun_error,
output wire logic frame_error,
/*
* Baud rate pulse in
*/
input wire logic baud_clk
);
localparam DATA_W = m_axis_rx.DATA_W;
logic [DATA_W-1:0] m_axis_tdata_reg = 0;
logic m_axis_tvalid_reg = 1'b0;
logic rxd_reg = 1'b1;
logic overrun_error_reg = 1'b0;
logic frame_error_reg = 1'b0;
logic [DATA_W-1:0] data_reg = 0;
logic [2:0] baud_cnt_reg = 0;
logic run_reg = 1'b0;
logic start_reg = 1'b0;
logic stop_reg = 1'b0;
assign m_axis_rx.tdata = m_axis_tdata_reg;
assign m_axis_rx.tkeep = 1'b1;
assign m_axis_rx.tstrb = m_axis_rx.tkeep;
assign m_axis_rx.tvalid = m_axis_tvalid_reg;
assign m_axis_rx.tlast = 1'b1;
assign m_axis_rx.tid = '0;
assign m_axis_rx.tdest = '0;
assign m_axis_rx.tuser = '0;
assign busy = run_reg;
assign overrun_error = overrun_error_reg;
assign frame_error = frame_error_reg;
always_ff @(posedge clk) begin
rxd_reg <= rxd;
overrun_error_reg <= 1'b0;
frame_error_reg <= 1'b0;
if (m_axis_rx.tvalid && m_axis_rx.tready) begin
m_axis_tvalid_reg <= 1'b0;
end
if (!baud_clk) begin
// wait
end else if (baud_cnt_reg != 0) begin
baud_cnt_reg <= baud_cnt_reg - 1;
end else if (run_reg) begin
start_reg <= 1'b0;
if (start_reg) begin
// wait bit period for start bit
baud_cnt_reg <= '1;
if (rxd_reg) begin
// start bit high, clear run bit
run_reg <= 1'b0;
frame_error_reg <= 1'b1;
end
end else begin
{data_reg, stop_reg} <= {rxd_reg, data_reg};
if (stop_reg) begin
run_reg <= 1'b0;
if (rxd_reg) begin
// stop bit high, transfer data
m_axis_tdata_reg <= data_reg;
m_axis_tvalid_reg <= 1'b1;
overrun_error_reg <= m_axis_tvalid_reg;
end else begin
// stop bit low
frame_error_reg <= 1'b1;
end
end else begin
baud_cnt_reg <= '1;
end
end
end else begin
data_reg <= {1'b1, {DATA_W-1{1'b0}}}; // marker bit
start_reg <= 1'b1;
stop_reg <= 1'b0;
if (!rxd_reg) begin
// falling edge of start bit
// wait half bit period
baud_cnt_reg <= 3'b011;
run_reg <= 1'b1;
end
end
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
rxd_reg <= 1'b1;
run_reg <= 1'b0;
overrun_error_reg <= 1'b0;
frame_error_reg <= 1'b0;
end
end
endmodule
`resetall

97
src/lss/rtl/taxi_uart_tx.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2014-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream UART (TX)
*/
module taxi_uart_tx
(
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis_tx,
/*
* UART interface
*/
output wire logic txd,
/*
* Status
*/
output wire logic busy,
/*
* Baud rate pulse in
*/
input wire logic baud_clk
);
localparam DATA_W = s_axis_tx.DATA_W;
logic s_axis_tready_reg = 1'b0;
logic txd_reg = 1'b1;
logic busy_reg = 1'b0;
logic [DATA_W:0] data_reg = 0;
logic [2:0] baud_cnt_reg = 0;
logic [3:0] bit_cnt_reg = 0;
assign s_axis_tx.tready = s_axis_tready_reg;
assign txd = txd_reg;
assign busy = busy_reg;
always_ff @(posedge clk) begin
s_axis_tready_reg <= 1'b0;
if (!baud_clk) begin
// wait
end else if (baud_cnt_reg != 0) begin
baud_cnt_reg <= baud_cnt_reg - 1;
end else if (bit_cnt_reg == 0) begin
busy_reg <= 1'b0;
if (s_axis_tx.tvalid) begin
s_axis_tready_reg <= 1'b1;
baud_cnt_reg <= '1;
bit_cnt_reg <= DATA_W+1;
data_reg <= {1'b1, s_axis_tx.tdata};
txd_reg <= 1'b0;
busy_reg <= 1'b1;
end
end else begin
{data_reg, txd_reg} <= {1'b0, data_reg};
baud_cnt_reg <= '1;
bit_cnt_reg <= bit_cnt_reg - 1;
end
if (rst) begin
s_axis_tready_reg <= 1'b0;
txd_reg <= 1'b1;
baud_cnt_reg <= 0;
bit_cnt_reg <= 0;
busy_reg <= 1'b0;
end
end
endmodule
`resetall