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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
155
src/prim/rtl/taxi_arbiter.sv
Normal file
155
src/prim/rtl/taxi_arbiter.sv
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@@ -0,0 +1,155 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Arbiter module
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*/
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module taxi_arbiter #
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(
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parameter PORTS = 4,
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// select round robin arbitration
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parameter logic ARB_ROUND_ROBIN = 1'b1,
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// blocking arbiter enable
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parameter logic ARB_BLOCK = 1'b1,
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// block on acknowledge assert when nonzero, request deassert when 0
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parameter logic ARB_BLOCK_ACK = 1'b0,
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// LSB priority selection
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parameter logic LSB_HIGH_PRIO = 1'b0
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)
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(
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input wire logic clk,
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input wire logic rst,
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input wire logic [PORTS-1:0] req,
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input wire logic [PORTS-1:0] ack,
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output wire logic grant_valid,
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output wire logic [PORTS-1:0] grant,
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output wire logic [$clog2(PORTS)-1:0] grant_index
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);
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localparam CL_PORTS = $clog2(PORTS);
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logic [PORTS-1:0] grant_reg = 'd0, grant_next;
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logic grant_valid_reg = 1'b0, grant_valid_next;
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logic [CL_PORTS-1:0] grant_index_reg = 'd0, grant_index_next;
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assign grant_valid = grant_valid_reg;
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assign grant = grant_reg;
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assign grant_index = grant_index_reg;
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wire req_valid;
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wire [CL_PORTS-1:0] req_index;
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wire [PORTS-1:0] req_mask;
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taxi_penc #(
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.WIDTH(PORTS),
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.LSB_HIGH_PRIO(LSB_HIGH_PRIO)
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)
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penc_inst (
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.input_mask(req),
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.output_valid(req_valid),
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.output_index(req_index),
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.output_mask(req_mask)
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);
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logic [PORTS-1:0] mask_reg = 'd0, mask_next;
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wire masked_req_valid;
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wire [CL_PORTS-1:0] masked_req_index;
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wire [PORTS-1:0] masked_req_mask;
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if (ARB_ROUND_ROBIN) begin
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taxi_penc #(
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.WIDTH(PORTS),
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.LSB_HIGH_PRIO(LSB_HIGH_PRIO)
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)
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penc_masked (
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.input_mask(req & mask_reg),
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.output_valid(masked_req_valid),
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.output_index(masked_req_index),
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.output_mask(masked_req_mask)
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);
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end else begin
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assign masked_req_valid = 1'b0;
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assign masked_req_index = '0;
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assign masked_req_mask = '0;
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end
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always_comb begin
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grant_next = 'd0;
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grant_valid_next = 1'b0;
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grant_index_next = 'd0;
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mask_next = mask_reg;
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if (ARB_BLOCK && !ARB_BLOCK_ACK && ((grant_reg & req) != 0)) begin
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// granted req still asserted; hold it
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grant_valid_next = grant_valid_reg;
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grant_next = grant_reg;
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grant_index_next = grant_index_reg;
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end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && ((grant_reg & ack) == 0)) begin
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// granted req not yet acknowledged; hold it
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grant_valid_next = grant_valid_reg;
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grant_next = grant_reg;
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grant_index_next = grant_index_reg;
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end else if (req_valid) begin
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if (ARB_ROUND_ROBIN) begin
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if (masked_req_valid) begin
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grant_valid_next = 1'b1;
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grant_next = masked_req_mask;
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grant_index_next = masked_req_index;
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if (LSB_HIGH_PRIO) begin
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mask_next = {PORTS{1'b1}} << (masked_req_index + 1);
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end else begin
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mask_next = {PORTS{1'b1}} >> ((CL_PORTS+1)'(PORTS) - masked_req_index);
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end
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end else begin
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grant_valid_next = 1;
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grant_next = req_mask;
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grant_index_next = req_index;
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if (LSB_HIGH_PRIO) begin
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mask_next = {PORTS{1'b1}} << (req_index + 1);
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end else begin
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mask_next = {PORTS{1'b1}} >> ((CL_PORTS+1)'(PORTS) - req_index);
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end
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end
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end else begin
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grant_valid_next = 1'b1;
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grant_next = req_mask;
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grant_index_next = req_index;
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end
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end
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end
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always_ff @(posedge clk) begin
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grant_reg <= grant_next;
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grant_valid_reg <= grant_valid_next;
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grant_index_reg <= grant_index_next;
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mask_reg <= mask_next;
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if (rst) begin
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grant_reg <= 'd0;
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grant_valid_reg <= 1'b0;
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grant_index_reg <= 'd0;
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mask_reg <= 'd0;
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end
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end
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endmodule
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`resetall
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76
src/prim/rtl/taxi_penc.sv
Normal file
76
src/prim/rtl/taxi_penc.sv
Normal file
@@ -0,0 +1,76 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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||||
|
||||
Authors:
|
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- Alex Forencich
|
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|
||||
*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Priority encoder module
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*/
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module taxi_penc #
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(
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parameter WIDTH = 4,
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// LSB priority selection
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parameter logic LSB_HIGH_PRIO = 1'b0
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)
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(
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input wire logic [WIDTH-1:0] input_mask,
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output wire logic output_valid,
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output wire logic [$clog2(WIDTH)-1:0] output_index,
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output wire logic [WIDTH-1:0] output_mask
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);
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// hopefully a temporary workaround
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// verilator lint_off UNOPTFLAT
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localparam CL_WIDTH = $clog2(WIDTH);
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localparam LEVELS = WIDTH > 2 ? CL_WIDTH : 1;
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localparam W = 2**LEVELS;
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// pad input to even power of two
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wire [W-1:0] mask = {{W-WIDTH{1'b0}}, input_mask};
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wire [W/2-1:0] stage_valid[LEVELS];
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wire [W/2-1:0] stage_enc[LEVELS];
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// process input bits; generate valid bit and encoded bit for each pair
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for (genvar n = 0; n < W/2; n = n + 1) begin : loop_in
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assign stage_valid[0][n] = |mask[n*2+1:n*2];
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if (LSB_HIGH_PRIO) begin
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// bit 0 is highest priority
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assign stage_enc[0][n] = !mask[n*2+0];
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end else begin
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// bit 0 is lowest priority
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assign stage_enc[0][n] = mask[n*2+1];
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end
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end
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// compress down to single valid bit and encoded bus
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for (genvar l = 1; l < LEVELS; l = l + 1) begin : loop_levels
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for (genvar n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
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assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
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if (LSB_HIGH_PRIO) begin
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// bit 0 is highest priority
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assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
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end else begin
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// bit 0 is lowest priority
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assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
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end
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end
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end
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assign output_valid = stage_valid[LEVELS-1][0];
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assign output_index = CL_WIDTH'(stage_enc[LEVELS-1]);
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assign output_mask = WIDTH'(output_valid) << output_index;
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endmodule
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`resetall
|
||||
52
src/prim/tb/taxi_arbiter/Makefile
Normal file
52
src/prim/tb/taxi_arbiter/Makefile
Normal file
@@ -0,0 +1,52 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
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# Authors:
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# - Alex Forencich
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||||
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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RTL_DIR = ../../rtl
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DUT = taxi_arbiter
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = $(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
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VERILOG_SOURCES += $(RTL_DIR)/taxi_penc.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_PORTS := 32
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export PARAM_ARM_ROUND_ROBIN := "1'b1"
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export PARAM_ARM_BLOCK := "1'b1"
|
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export PARAM_ARM_BLOCK_ACK := "1'b0"
|
||||
export PARAM_LSB_HIGH_PRIO := "1'b0"
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
|
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|
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
336
src/prim/tb/taxi_arbiter/test_taxi_arbiter.py
Normal file
336
src/prim/tb/taxi_arbiter/test_taxi_arbiter.py
Normal file
@@ -0,0 +1,336 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
dut.req.setimmediatevalue(0)
|
||||
dut.ack.setimmediatevalue(0)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_single_bit(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
round_robin = bool(int(dut.ARB_ROUND_ROBIN.value))
|
||||
lsb_high_prio = bool(int(dut.LSB_HIGH_PRIO.value))
|
||||
|
||||
await tb.reset()
|
||||
|
||||
if lsb_high_prio:
|
||||
prev_index = 31
|
||||
else:
|
||||
prev_index = 0
|
||||
|
||||
for i in range(32):
|
||||
lst = [i]
|
||||
k = 0
|
||||
for y in lst:
|
||||
k = k | 1 << y
|
||||
|
||||
tb.log.info("Request: 0x%08x", k)
|
||||
|
||||
dut.req.value = k
|
||||
await RisingEdge(dut.clk)
|
||||
dut.req.value = 0
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
if round_robin:
|
||||
if lsb_high_prio:
|
||||
# emulate round robin
|
||||
lst2 = [x for x in lst if x > prev_index]
|
||||
if len(lst2) == 0:
|
||||
lst2 = lst
|
||||
g = min(lst2)
|
||||
else:
|
||||
# emulate round robin
|
||||
lst2 = [x for x in lst if x < prev_index]
|
||||
if len(lst2) == 0:
|
||||
lst2 = lst
|
||||
g = max(lst2)
|
||||
else:
|
||||
if lsb_high_prio:
|
||||
g = min(lst)
|
||||
else:
|
||||
g = max(lst)
|
||||
|
||||
tb.log.info("Grant (mask): 0x%08x", int(dut.grant.value))
|
||||
tb.log.info("Grant (index): %d", int(dut.grant_index.value))
|
||||
|
||||
assert int(dut.grant.value) == 1 << g
|
||||
assert int(dut.grant_index.value) == g
|
||||
|
||||
prev_index = int(g)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_cycle(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
round_robin = bool(int(dut.ARB_ROUND_ROBIN.value))
|
||||
lsb_high_prio = bool(int(dut.LSB_HIGH_PRIO.value))
|
||||
|
||||
await tb.reset()
|
||||
|
||||
if lsb_high_prio:
|
||||
prev_index = 31
|
||||
else:
|
||||
prev_index = 0
|
||||
|
||||
for i in range(32):
|
||||
lst = [0, 5, 10, 15, 20, 25, 30]
|
||||
k = 0
|
||||
for y in lst:
|
||||
k = k | 1 << y
|
||||
|
||||
tb.log.info("Request: 0x%08x", k)
|
||||
|
||||
dut.req.value = k
|
||||
await RisingEdge(dut.clk)
|
||||
dut.req.value = 0
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
if round_robin:
|
||||
if lsb_high_prio:
|
||||
# emulate round robin
|
||||
lst2 = [x for x in lst if x > prev_index]
|
||||
if len(lst2) == 0:
|
||||
lst2 = lst
|
||||
g = min(lst2)
|
||||
else:
|
||||
# emulate round robin
|
||||
lst2 = [x for x in lst if x < prev_index]
|
||||
if len(lst2) == 0:
|
||||
lst2 = lst
|
||||
g = max(lst2)
|
||||
else:
|
||||
if lsb_high_prio:
|
||||
g = min(lst)
|
||||
else:
|
||||
g = max(lst)
|
||||
|
||||
tb.log.info("Grant (mask): 0x%08x", int(dut.grant.value))
|
||||
tb.log.info("Grant (index): %d", int(dut.grant_index.value))
|
||||
|
||||
assert int(dut.grant.value) == 1 << g
|
||||
assert int(dut.grant_index.value) == g
|
||||
|
||||
prev_index = int(g)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_two_bits(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
round_robin = bool(int(dut.ARB_ROUND_ROBIN.value))
|
||||
lsb_high_prio = bool(int(dut.LSB_HIGH_PRIO.value))
|
||||
|
||||
await tb.reset()
|
||||
|
||||
if lsb_high_prio:
|
||||
prev_index = 31
|
||||
else:
|
||||
prev_index = 0
|
||||
|
||||
for i in range(32):
|
||||
for j in range(32):
|
||||
lst = [i, j]
|
||||
k = 0
|
||||
for y in lst:
|
||||
k = k | 1 << y
|
||||
|
||||
tb.log.info("Request: 0x%08x", k)
|
||||
|
||||
dut.req.value = k
|
||||
await RisingEdge(dut.clk)
|
||||
dut.req.value = 0
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
if round_robin:
|
||||
if lsb_high_prio:
|
||||
# emulate round robin
|
||||
lst2 = [x for x in lst if x > prev_index]
|
||||
if len(lst2) == 0:
|
||||
lst2 = lst
|
||||
g = min(lst2)
|
||||
else:
|
||||
# emulate round robin
|
||||
lst2 = [x for x in lst if x < prev_index]
|
||||
if len(lst2) == 0:
|
||||
lst2 = lst
|
||||
g = max(lst2)
|
||||
else:
|
||||
if lsb_high_prio:
|
||||
g = min(lst)
|
||||
else:
|
||||
g = max(lst)
|
||||
|
||||
tb.log.info("Grant (mask): 0x%08x", int(dut.grant.value))
|
||||
tb.log.info("Grant (index): %d", int(dut.grant_index.value))
|
||||
|
||||
assert int(dut.grant.value) == 1 << g
|
||||
assert int(dut.grant_index.value) == g
|
||||
|
||||
prev_index = int(g)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_five_bits(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
round_robin = bool(int(dut.ARB_ROUND_ROBIN.value))
|
||||
lsb_high_prio = bool(int(dut.LSB_HIGH_PRIO.value))
|
||||
|
||||
await tb.reset()
|
||||
|
||||
if lsb_high_prio:
|
||||
prev_index = 31
|
||||
else:
|
||||
prev_index = 0
|
||||
|
||||
for i in range(32):
|
||||
lst = [(i*x) % 32 for x in [1, 3, 5, 7, 11]]
|
||||
k = 0
|
||||
for y in lst:
|
||||
k = k | 1 << y
|
||||
|
||||
tb.log.info("Request: 0x%08x", k)
|
||||
|
||||
dut.req.value = k
|
||||
await RisingEdge(dut.clk)
|
||||
dut.req.value = 0
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
if round_robin:
|
||||
if lsb_high_prio:
|
||||
# emulate round robin
|
||||
lst2 = [x for x in lst if x > prev_index]
|
||||
if len(lst2) == 0:
|
||||
lst2 = lst
|
||||
g = min(lst2)
|
||||
else:
|
||||
# emulate round robin
|
||||
lst2 = [x for x in lst if x < prev_index]
|
||||
if len(lst2) == 0:
|
||||
lst2 = lst
|
||||
g = max(lst2)
|
||||
else:
|
||||
if lsb_high_prio:
|
||||
g = min(lst)
|
||||
else:
|
||||
g = max(lst)
|
||||
|
||||
tb.log.info("Grant (mask): 0x%08x", int(dut.grant.value))
|
||||
tb.log.info("Grant (index): %d", int(dut.grant_index.value))
|
||||
|
||||
assert int(dut.grant.value) == 1 << g
|
||||
assert int(dut.grant_index.value) == g
|
||||
|
||||
prev_index = int(g)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
src_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("lsb_high_prio", [0, 1])
|
||||
@pytest.mark.parametrize("round_robin", [0, 1])
|
||||
def test_taxi_arbiter(request, round_robin, lsb_high_prio):
|
||||
dut = "taxi_arbiter"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_penc.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['PORTS'] = 32
|
||||
parameters['ARB_ROUND_ROBIN'] = f"1'b{round_robin}"
|
||||
parameters['ARB_BLOCK'] = "1'b1"
|
||||
parameters['ARB_BLOCK_ACK'] = "1'b0"
|
||||
parameters['LSB_HIGH_PRIO'] = f"1'b{lsb_high_prio}"
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
48
src/prim/tb/taxi_penc/Makefile
Normal file
48
src/prim/tb/taxi_penc/Makefile
Normal file
@@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
|
||||
DUT = taxi_penc
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_WIDTH := 32
|
||||
export PARAM_LSB_HIGH_PRIO := "1'b0"
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
124
src/prim/tb/taxi_penc/test_taxi_penc.py
Normal file
124
src/prim/tb/taxi_penc/test_taxi_penc.py
Normal file
@@ -0,0 +1,124 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.triggers import Timer
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_single_bit(dut):
|
||||
|
||||
log = logging.getLogger("cocotb.tb")
|
||||
log.setLevel(logging.DEBUG)
|
||||
|
||||
for i in range(32):
|
||||
in_val = 1 << i
|
||||
|
||||
log.info("In: 0x%08x", in_val)
|
||||
dut.input_mask.value = in_val
|
||||
|
||||
await Timer(1, "ns")
|
||||
|
||||
log.info("Out (index): %d", int(dut.output_index.value))
|
||||
log.info("Out (mask): 0x%08x", int(dut.output_mask.value))
|
||||
|
||||
assert int(dut.output_valid.value)
|
||||
assert int(dut.output_index.value) == i
|
||||
assert int(dut.output_mask.value) == 1 << i
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_two_bits(dut):
|
||||
|
||||
lsb_high_prio = bool(int(dut.LSB_HIGH_PRIO.value))
|
||||
|
||||
log = logging.getLogger("cocotb.tb")
|
||||
log.setLevel(logging.DEBUG)
|
||||
|
||||
for i in range(32):
|
||||
for j in range(32):
|
||||
in_val = (1 << i) | (1 << j)
|
||||
|
||||
log.info("In: 0x%08x", in_val)
|
||||
dut.input_mask.value = in_val
|
||||
|
||||
await Timer(1, "ns")
|
||||
|
||||
log.info("Out (index): %d", int(dut.output_index.value))
|
||||
log.info("Out (mask): 0x%08x", int(dut.output_mask.value))
|
||||
|
||||
assert int(dut.output_valid.value)
|
||||
if lsb_high_prio:
|
||||
assert int(dut.output_index.value) == min(i, j)
|
||||
assert int(dut.output_mask.value) == 1 << min(i, j)
|
||||
else:
|
||||
assert int(dut.output_index.value) == max(i, j)
|
||||
assert int(dut.output_mask.value) == 1 << max(i, j)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
src_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("lsb_high_prio", [0, 1])
|
||||
def test_taxi_penc(request, lsb_high_prio):
|
||||
dut = "taxi_penc"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['WIDTH'] = 32
|
||||
parameters['LSB_HIGH_PRIO'] = f"1'b{lsb_high_prio}"
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Reference in New Issue
Block a user