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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
155
src/prim/rtl/taxi_arbiter.sv
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155
src/prim/rtl/taxi_arbiter.sv
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Arbiter module
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*/
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module taxi_arbiter #
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(
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parameter PORTS = 4,
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// select round robin arbitration
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parameter logic ARB_ROUND_ROBIN = 1'b1,
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// blocking arbiter enable
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parameter logic ARB_BLOCK = 1'b1,
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// block on acknowledge assert when nonzero, request deassert when 0
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parameter logic ARB_BLOCK_ACK = 1'b0,
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// LSB priority selection
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parameter logic LSB_HIGH_PRIO = 1'b0
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)
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(
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input wire logic clk,
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input wire logic rst,
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input wire logic [PORTS-1:0] req,
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input wire logic [PORTS-1:0] ack,
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output wire logic grant_valid,
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output wire logic [PORTS-1:0] grant,
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output wire logic [$clog2(PORTS)-1:0] grant_index
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);
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localparam CL_PORTS = $clog2(PORTS);
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logic [PORTS-1:0] grant_reg = 'd0, grant_next;
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logic grant_valid_reg = 1'b0, grant_valid_next;
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logic [CL_PORTS-1:0] grant_index_reg = 'd0, grant_index_next;
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assign grant_valid = grant_valid_reg;
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assign grant = grant_reg;
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assign grant_index = grant_index_reg;
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wire req_valid;
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wire [CL_PORTS-1:0] req_index;
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wire [PORTS-1:0] req_mask;
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taxi_penc #(
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.WIDTH(PORTS),
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.LSB_HIGH_PRIO(LSB_HIGH_PRIO)
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)
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penc_inst (
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.input_mask(req),
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.output_valid(req_valid),
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.output_index(req_index),
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.output_mask(req_mask)
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);
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logic [PORTS-1:0] mask_reg = 'd0, mask_next;
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wire masked_req_valid;
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wire [CL_PORTS-1:0] masked_req_index;
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wire [PORTS-1:0] masked_req_mask;
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if (ARB_ROUND_ROBIN) begin
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taxi_penc #(
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.WIDTH(PORTS),
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.LSB_HIGH_PRIO(LSB_HIGH_PRIO)
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)
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penc_masked (
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.input_mask(req & mask_reg),
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.output_valid(masked_req_valid),
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.output_index(masked_req_index),
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.output_mask(masked_req_mask)
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);
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end else begin
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assign masked_req_valid = 1'b0;
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assign masked_req_index = '0;
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assign masked_req_mask = '0;
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end
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always_comb begin
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grant_next = 'd0;
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grant_valid_next = 1'b0;
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grant_index_next = 'd0;
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mask_next = mask_reg;
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if (ARB_BLOCK && !ARB_BLOCK_ACK && ((grant_reg & req) != 0)) begin
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// granted req still asserted; hold it
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grant_valid_next = grant_valid_reg;
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grant_next = grant_reg;
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grant_index_next = grant_index_reg;
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end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && ((grant_reg & ack) == 0)) begin
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// granted req not yet acknowledged; hold it
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grant_valid_next = grant_valid_reg;
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grant_next = grant_reg;
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grant_index_next = grant_index_reg;
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end else if (req_valid) begin
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if (ARB_ROUND_ROBIN) begin
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if (masked_req_valid) begin
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grant_valid_next = 1'b1;
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grant_next = masked_req_mask;
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grant_index_next = masked_req_index;
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if (LSB_HIGH_PRIO) begin
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mask_next = {PORTS{1'b1}} << (masked_req_index + 1);
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end else begin
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mask_next = {PORTS{1'b1}} >> ((CL_PORTS+1)'(PORTS) - masked_req_index);
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end
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end else begin
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grant_valid_next = 1;
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grant_next = req_mask;
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grant_index_next = req_index;
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if (LSB_HIGH_PRIO) begin
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mask_next = {PORTS{1'b1}} << (req_index + 1);
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end else begin
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mask_next = {PORTS{1'b1}} >> ((CL_PORTS+1)'(PORTS) - req_index);
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end
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end
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end else begin
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grant_valid_next = 1'b1;
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grant_next = req_mask;
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grant_index_next = req_index;
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end
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end
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end
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always_ff @(posedge clk) begin
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grant_reg <= grant_next;
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grant_valid_reg <= grant_valid_next;
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grant_index_reg <= grant_index_next;
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mask_reg <= mask_next;
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if (rst) begin
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grant_reg <= 'd0;
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grant_valid_reg <= 1'b0;
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grant_index_reg <= 'd0;
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mask_reg <= 'd0;
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end
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end
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endmodule
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`resetall
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76
src/prim/rtl/taxi_penc.sv
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76
src/prim/rtl/taxi_penc.sv
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@@ -0,0 +1,76 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Priority encoder module
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*/
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module taxi_penc #
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(
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parameter WIDTH = 4,
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// LSB priority selection
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parameter logic LSB_HIGH_PRIO = 1'b0
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)
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(
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input wire logic [WIDTH-1:0] input_mask,
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output wire logic output_valid,
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output wire logic [$clog2(WIDTH)-1:0] output_index,
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output wire logic [WIDTH-1:0] output_mask
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);
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// hopefully a temporary workaround
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// verilator lint_off UNOPTFLAT
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localparam CL_WIDTH = $clog2(WIDTH);
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localparam LEVELS = WIDTH > 2 ? CL_WIDTH : 1;
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localparam W = 2**LEVELS;
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// pad input to even power of two
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wire [W-1:0] mask = {{W-WIDTH{1'b0}}, input_mask};
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wire [W/2-1:0] stage_valid[LEVELS];
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wire [W/2-1:0] stage_enc[LEVELS];
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// process input bits; generate valid bit and encoded bit for each pair
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for (genvar n = 0; n < W/2; n = n + 1) begin : loop_in
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assign stage_valid[0][n] = |mask[n*2+1:n*2];
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if (LSB_HIGH_PRIO) begin
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// bit 0 is highest priority
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assign stage_enc[0][n] = !mask[n*2+0];
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end else begin
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// bit 0 is lowest priority
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assign stage_enc[0][n] = mask[n*2+1];
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end
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end
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// compress down to single valid bit and encoded bus
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for (genvar l = 1; l < LEVELS; l = l + 1) begin : loop_levels
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for (genvar n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
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assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
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if (LSB_HIGH_PRIO) begin
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// bit 0 is highest priority
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assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
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end else begin
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// bit 0 is lowest priority
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assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
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end
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end
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end
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assign output_valid = stage_valid[LEVELS-1][0];
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assign output_index = CL_WIDTH'(stage_enc[LEVELS-1]);
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assign output_mask = WIDTH'(output_valid) << output_index;
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endmodule
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`resetall
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