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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
305
src/stats/rtl/taxi_stats_collect.sv
Normal file
305
src/stats/rtl/taxi_stats_collect.sv
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@@ -0,0 +1,305 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Statistics collector
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*/
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module taxi_stats_collect #
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(
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// Channel count
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parameter CNT = 8,
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// Increment width (bits)
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parameter INC_W = 8,
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// Base statistic ID
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parameter ID_BASE = 0,
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// Statistics counter update period (cycles)
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parameter UPDATE_PERIOD = 1024,
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// Enable strings
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parameter logic STR_EN = 1'b0,
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// Common prefix string (8 characters)
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parameter logic [8*8-1:0] PREFIX_STR = "BLK"
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* Increment inputs
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*/
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input wire logic [INC_W-1:0] stat_inc[CNT],
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input wire logic stat_valid[CNT] = '{CNT{1'b1}},
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input wire logic [8*8-1:0] stat_str[CNT] = '{CNT{'0}},
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/*
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* Statistics increment output
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*/
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taxi_axis_if.src m_axis_stat,
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/*
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* Control inputs
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*/
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input wire logic gate = 1'b1,
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input wire logic update = 1'b0
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);
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// check configuration
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if (STR_EN) begin
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if (!m_axis_stat.USER_EN)
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$fatal(0, "Error: statistics strings requires tuser (instance %m)");
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if (m_axis_stat.DATA_W < 16)
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$fatal(0, "Error: statistics strings requires tdata width of at least 16 (instance %m)");
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end
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if (ID_BASE+CNT > 2**m_axis_stat.ID_W)
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$fatal(0, "Error: insufficient tid width (instance %m)");
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localparam STAT_INC_W = m_axis_stat.DATA_W;
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localparam STAT_ID_W = m_axis_stat.ID_W;
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localparam CNT_W = $clog2(CNT);
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localparam PERIOD_CNT_W = $clog2(UPDATE_PERIOD+1);
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localparam ACC_W = INC_W+CNT_W+1;
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localparam [0:0]
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STATE_READ = 1'd0,
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STATE_WRITE = 1'd1;
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logic [0:0] state_reg = STATE_READ, state_next;
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logic [STAT_INC_W-1:0] m_axis_stat_tdata_reg = '0, m_axis_stat_tdata_next;
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logic [STAT_ID_W-1:0] m_axis_stat_tid_reg = '0, m_axis_stat_tid_next;
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logic m_axis_stat_tvalid_reg = 1'b0, m_axis_stat_tvalid_next;
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logic m_axis_stat_tuser_reg = 1'b0, m_axis_stat_tuser_next;
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logic [CNT_W-1:0] count_reg = '0, count_next;
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logic [PERIOD_CNT_W-1:0] update_period_reg = PERIOD_CNT_W'(UPDATE_PERIOD), update_period_next;
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logic zero_reg = 1'b1, zero_next;
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logic update_req_reg = 1'b0, update_req_next;
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logic update_reg = 1'b0, update_next;
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logic [CNT-1:0] update_shift_reg = '0, update_shift_next;
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logic [ACC_W-1:0] ch_reg = '0, ch_next;
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function automatic [8*6-1:0] pack_str(logic [8*8-1:0] str);
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// determine length
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integer j = 0;
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for (integer i = 0; i < 8; i = i + 1) begin
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if (str[i*8 +: 8] != 0) begin
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j = i;
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end
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end
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// convert to 6 bit and pack
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pack_str = '0;
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for (integer i = 0; i < 8 && i <= j; i = i + 1) begin
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pack_str[i*6 +: 6] = {str[8*(j-i) + 6], str[8*(j-i) +: 5]};
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end
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endfunction
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logic [3:0][11:0] prefix_str_rom = pack_str(PREFIX_STR);
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logic [CNT*4-1:0][11:0] str_rom;
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logic [CNT_W-1:0] str_sel_reg = '0, str_sel_next;
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logic str_prfx_reg = 1'b0, str_prfx_next;
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logic [1:0] str_ptr_reg = '0, str_ptr_next;
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logic str_update_reg = 1'b0, str_update_next;
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for (genvar n = 0; n < CNT; n = n + 1) begin
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assign str_rom[n*4 +: 4] = pack_str(stat_str[n]);
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end
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wire [ACC_W-1:0] acc_int[CNT];
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logic [CNT-1:0] acc_clear;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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logic [STAT_INC_W-1:0] mem_reg[CNT];
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logic [STAT_INC_W-1:0] mem_rd_data_reg = '0;
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logic mem_rd_en;
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logic mem_wr_en;
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logic [STAT_INC_W-1:0] mem_wr_data;
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assign m_axis_stat.tdata = m_axis_stat_tdata_reg;
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assign m_axis_stat.tkeep = 1'b1;
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assign m_axis_stat.tstrb = m_axis_stat.tkeep;
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assign m_axis_stat.tvalid = m_axis_stat_tvalid_reg;
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assign m_axis_stat.tlast = 1'b1;
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assign m_axis_stat.tid = m_axis_stat_tid_reg;
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assign m_axis_stat.tdest = '0;
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assign m_axis_stat.tuser = STR_EN ? m_axis_stat_tuser_reg : '0;
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for (genvar n = 0; n < CNT; n = n + 1) begin : ch
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logic [ACC_W-1:0] acc_reg = '0;
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assign acc_int[n] = acc_reg;
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always_ff @(posedge clk) begin
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if (acc_clear[n]) begin
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if (stat_valid[n] && gate) begin
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acc_reg <= ACC_W'(stat_inc[n]);
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end else begin
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acc_reg <= '0;
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end
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end else begin
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if (stat_valid[n] && gate) begin
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acc_reg <= acc_reg + ACC_W'(stat_inc[n]);
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end
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end
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if (rst) begin
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acc_reg <= '0;
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end
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end
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end
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always_comb begin
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state_next = STATE_READ;
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m_axis_stat_tdata_next = m_axis_stat_tdata_reg;
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m_axis_stat_tid_next = m_axis_stat_tid_reg;
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m_axis_stat_tvalid_next = m_axis_stat_tvalid_reg && !m_axis_stat.tready;
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m_axis_stat_tuser_next = m_axis_stat_tuser_reg;
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count_next = count_reg;
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update_period_next = update_period_reg;
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zero_next = zero_reg;
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update_req_next = update_req_reg;
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update_next = update_reg;
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update_shift_next = update_shift_reg;
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ch_next = ch_reg;
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str_sel_next = str_sel_reg;
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str_prfx_next = str_prfx_reg;
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str_ptr_next = str_ptr_reg;
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str_update_next = str_update_reg;
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acc_clear = '0;
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mem_rd_en = 1'b0;
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mem_wr_en = 1'b0;
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mem_wr_data = mem_rd_data_reg + STAT_INC_W'(ch_reg);
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if (!m_axis_stat_tvalid_reg) begin
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m_axis_stat_tdata_next = mem_rd_data_reg + STAT_INC_W'(ch_reg);
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m_axis_stat_tid_next = STAT_ID_W'(count_reg+ID_BASE);
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end
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case (state_reg)
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STATE_READ: begin
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acc_clear[count_reg] = 1'b1;
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ch_next = acc_int[count_reg];
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mem_rd_en = 1'b1;
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state_next = STATE_WRITE;
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end
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STATE_WRITE: begin
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mem_wr_en = 1'b1;
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update_shift_next = {update_reg || update_shift_reg[0], update_shift_reg[CNT-1:1]};
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if (zero_reg) begin
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mem_wr_data = STAT_INC_W'(ch_reg);
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end else if (!m_axis_stat_tvalid_reg && (update_reg || update_shift_reg[0])) begin
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update_shift_next[CNT-1] = 1'b0;
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mem_wr_data = '0;
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m_axis_stat_tdata_next = mem_rd_data_reg + STAT_INC_W'(ch_reg);
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m_axis_stat_tid_next = STAT_ID_W'(count_reg+ID_BASE);
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m_axis_stat_tvalid_next = mem_rd_data_reg != 0 || ch_reg != 0;
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m_axis_stat_tuser_next = 1'b0;
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end else begin
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mem_wr_data = mem_rd_data_reg + STAT_INC_W'(ch_reg);
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if (STR_EN && !m_axis_stat_tvalid_reg && str_update_reg && count_reg == str_sel_reg) begin
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str_update_next = 1'b0;
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m_axis_stat_tdata_next[15:4] = str_prfx_reg ? str_rom[{str_sel_reg, str_ptr_reg}] : prefix_str_rom[str_ptr_reg];
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m_axis_stat_tdata_next[3:0] = {1'b0, str_prfx_reg, str_ptr_reg};
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m_axis_stat_tid_next = STAT_ID_W'(count_reg+ID_BASE);
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m_axis_stat_tvalid_next = 1'b1;
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m_axis_stat_tuser_next = 1'b1;
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str_ptr_next = str_ptr_reg + 1;
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if (str_ptr_reg == 2'b11) begin
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str_prfx_next = !str_prfx_reg;
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if (str_prfx_reg) begin
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str_sel_next = str_sel_reg + 1;
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end
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end
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end
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end
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if (count_reg == CNT_W'(CNT-1)) begin
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zero_next = 1'b0;
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update_req_next = 1'b0;
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update_next = update_req_reg;
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if (update_req_reg) begin
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str_update_next = 1'b1;
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end
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count_next = '0;
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end else begin
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count_next = count_reg + 1;
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end
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state_next = STATE_READ;
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end
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endcase
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if (update_period_reg == 0 || update) begin
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update_req_next = 1'b1;
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update_period_next = PERIOD_CNT_W'(UPDATE_PERIOD);
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end else begin
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update_period_next = update_period_reg - 1;
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end
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end
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always_ff @(posedge clk) begin
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state_reg <= state_next;
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m_axis_stat_tdata_reg <= m_axis_stat_tdata_next;
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m_axis_stat_tid_reg <= m_axis_stat_tid_next;
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m_axis_stat_tvalid_reg <= m_axis_stat_tvalid_next;
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m_axis_stat_tuser_reg <= m_axis_stat_tuser_next;
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count_reg <= count_next;
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update_period_reg <= update_period_next;
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zero_reg <= zero_next;
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update_req_reg <= update_req_next;
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update_reg <= update_next;
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update_shift_reg <= update_shift_next;
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ch_reg <= ch_next;
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str_sel_reg <= str_sel_next;
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str_prfx_reg <= str_prfx_next;
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str_ptr_reg <= str_ptr_next;
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str_update_reg <= str_update_next;
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if (mem_wr_en) begin
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mem_reg[count_reg] <= mem_wr_data;
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end else if (mem_rd_en) begin
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mem_rd_data_reg <= mem_reg[count_reg];
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end
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if (rst) begin
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state_reg <= STATE_READ;
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m_axis_stat_tvalid_reg <= 1'b0;
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count_reg <= '0;
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update_period_reg <= PERIOD_CNT_W'(UPDATE_PERIOD);
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zero_reg <= 1'b1;
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update_req_reg <= 1'b0;
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update_reg <= 1'b0;
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str_sel_reg <= '0;
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str_prfx_reg <= 1'b0;
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str_ptr_reg <= '0;
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str_update_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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268
src/stats/rtl/taxi_stats_counter.sv
Normal file
268
src/stats/rtl/taxi_stats_counter.sv
Normal file
@@ -0,0 +1,268 @@
|
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// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Statistics counter
|
||||
*/
|
||||
module taxi_stats_counter #
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(
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// Statistics counter (bits)
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parameter STAT_COUNT_W = 32,
|
||||
// Pipeline length
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||||
parameter PIPELINE = 2
|
||||
)
|
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(
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input wire logic clk,
|
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input wire logic rst,
|
||||
|
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/*
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* Statistics increment input
|
||||
*/
|
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taxi_axis_if.snk s_axis_stat,
|
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|
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/*
|
||||
* AXI Lite register interface
|
||||
*/
|
||||
taxi_axil_if.wr_slv s_axil_wr,
|
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taxi_axil_if.rd_slv s_axil_rd
|
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);
|
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localparam STAT_INC_W = s_axis_stat.DATA_W;
|
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localparam STAT_ID_W = s_axis_stat.ID_W;
|
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|
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localparam AXIL_ADDR_W = s_axil_rd.ADDR_W;
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localparam AXIL_DATA_W = s_axil_rd.DATA_W;
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localparam ID_SHIFT = $clog2(((AXIL_DATA_W > STAT_COUNT_W ? AXIL_DATA_W : STAT_COUNT_W)+7)/8);
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localparam WORD_SELECT_SHIFT = $clog2(AXIL_DATA_W/8);
|
||||
localparam WORD_SELECT_W = STAT_COUNT_W > AXIL_DATA_W ? $clog2((STAT_COUNT_W+7)/8) - $clog2(AXIL_DATA_W/8) : 1;
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||||
|
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// check configuration
|
||||
if (AXIL_ADDR_W < STAT_ID_W+ID_SHIFT)
|
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$fatal(0, "Error: AXI lite address width too narrow (instance %m)");
|
||||
|
||||
if (PIPELINE < 2)
|
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$fatal(0, "Error: PIPELINE must be at least 2 (instance %m)");
|
||||
|
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logic init_reg = 1'b1, init_next;
|
||||
logic [STAT_ID_W-1:0] init_ptr_reg = 0, init_ptr_next;
|
||||
|
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logic op_acc_pipe_hazard;
|
||||
logic stage_active;
|
||||
|
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logic [PIPELINE-1:0] op_axil_read_pipe_reg = 0, op_axil_read_pipe_next;
|
||||
logic [PIPELINE-1:0] op_acc_pipe_reg = 0, op_acc_pipe_next;
|
||||
|
||||
logic [STAT_ID_W-1:0] mem_addr_pipeline_reg[PIPELINE], mem_addr_pipeline_next[PIPELINE];
|
||||
logic [WORD_SELECT_W-1:0] axil_shift_pipeline_reg[PIPELINE], axil_shift_pipeline_next[PIPELINE];
|
||||
logic [STAT_INC_W-1:0] stat_inc_pipeline_reg[PIPELINE], stat_inc_pipeline_next[PIPELINE];
|
||||
|
||||
logic s_axis_stat_tready_reg = 1'b0, s_axis_stat_tready_next;
|
||||
|
||||
logic s_axil_awready_reg = 0, s_axil_awready_next;
|
||||
logic s_axil_wready_reg = 0, s_axil_wready_next;
|
||||
logic s_axil_bvalid_reg = 0, s_axil_bvalid_next;
|
||||
logic s_axil_arready_reg = 0, s_axil_arready_next;
|
||||
logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = 0, s_axil_rdata_next;
|
||||
logic s_axil_rvalid_reg = 0, s_axil_rvalid_next;
|
||||
|
||||
(* ramstyle = "no_rw_check" *)
|
||||
logic [STAT_COUNT_W-1:0] mem[2**STAT_ID_W];
|
||||
|
||||
logic [STAT_ID_W-1:0] mem_rd_addr;
|
||||
logic [STAT_ID_W-1:0] mem_wr_addr;
|
||||
logic [STAT_COUNT_W-1:0] mem_wr_data;
|
||||
logic mem_wr_en;
|
||||
logic [STAT_COUNT_W-1:0] mem_read_data_reg = 0;
|
||||
logic [STAT_COUNT_W-1:0] mem_read_data_pipeline_reg[PIPELINE-1:1];
|
||||
|
||||
assign s_axis_stat.tready = s_axis_stat_tready_reg;
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
assign s_axil_wr.bresp = 2'b00;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
assign s_axil_rd.arready = s_axil_arready_reg;
|
||||
assign s_axil_rd.rdata = s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = 2'b00;
|
||||
assign s_axil_rd.rvalid = s_axil_rvalid_reg;
|
||||
|
||||
wire [STAT_ID_W-1:0] s_axil_araddr_id = STAT_ID_W'(s_axil_rd.araddr >> ID_SHIFT);
|
||||
wire [WORD_SELECT_W-1:0] s_axil_araddr_shift = WORD_SELECT_W'(s_axil_rd.araddr >> WORD_SELECT_SHIFT);
|
||||
|
||||
initial begin
|
||||
// break up loop to work around iteration termination
|
||||
for (integer i = 0; i < 2**STAT_ID_W; i = i + 2**(STAT_ID_W/2)) begin
|
||||
for (integer j = i; j < i + 2**(STAT_ID_W/2); j = j + 1) begin
|
||||
mem[j] = 0;
|
||||
end
|
||||
end
|
||||
|
||||
for (integer i = 0; i < PIPELINE; i = i + 1) begin
|
||||
mem_addr_pipeline_reg[i] = 0;
|
||||
axil_shift_pipeline_reg[i] = 0;
|
||||
stat_inc_pipeline_reg[i] = 0;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
init_next = init_reg;
|
||||
init_ptr_next = init_ptr_reg;
|
||||
|
||||
op_axil_read_pipe_next = PIPELINE'({op_axil_read_pipe_reg, 1'b0});
|
||||
op_acc_pipe_next = PIPELINE'({op_acc_pipe_reg, 1'b0});
|
||||
|
||||
mem_addr_pipeline_next[0] = 0;
|
||||
axil_shift_pipeline_next[0] = 0;
|
||||
stat_inc_pipeline_next[0] = 0;
|
||||
for (integer j = 1; j < PIPELINE; j = j + 1) begin
|
||||
mem_addr_pipeline_next[j] = mem_addr_pipeline_reg[j-1];
|
||||
axil_shift_pipeline_next[j] = axil_shift_pipeline_reg[j-1];
|
||||
stat_inc_pipeline_next[j] = stat_inc_pipeline_reg[j-1];
|
||||
end
|
||||
|
||||
s_axis_stat_tready_next = 1'b0;
|
||||
|
||||
s_axil_awready_next = 1'b0;
|
||||
s_axil_wready_next = 1'b0;
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
|
||||
|
||||
s_axil_arready_next = 1'b0;
|
||||
s_axil_rdata_next = s_axil_rdata_reg;
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rd.rready;
|
||||
|
||||
mem_rd_addr = 0;
|
||||
mem_wr_addr = mem_addr_pipeline_reg[PIPELINE-1];
|
||||
mem_wr_data = mem_read_data_pipeline_reg[PIPELINE-1] + STAT_COUNT_W'(stat_inc_pipeline_reg[PIPELINE-1]);
|
||||
mem_wr_en = 0;
|
||||
|
||||
op_acc_pipe_hazard = 1'b0;
|
||||
stage_active = 1'b0;
|
||||
|
||||
for (integer j = 0; j < PIPELINE; j = j + 1) begin
|
||||
stage_active = op_axil_read_pipe_reg[j] || op_acc_pipe_reg[j];
|
||||
op_acc_pipe_hazard = op_acc_pipe_hazard || (stage_active && mem_addr_pipeline_reg[j] == s_axis_stat.tid);
|
||||
end
|
||||
|
||||
// discard writes
|
||||
if (s_axil_wr.awvalid && s_axil_wr.wvalid && (!s_axil_wr.bvalid || s_axil_wr.bready) && (!s_axil_wr.awready && !s_axil_wr.wready)) begin
|
||||
s_axil_awready_next = 1'b1;
|
||||
s_axil_wready_next = 1'b1;
|
||||
s_axil_bvalid_next = 1'b1;
|
||||
end
|
||||
|
||||
// pipeline stage 0 - accept request
|
||||
if (init_reg) begin
|
||||
// zero all counters
|
||||
init_ptr_next = init_ptr_reg + 1;
|
||||
|
||||
mem_wr_addr = init_ptr_reg;
|
||||
mem_wr_data = 0;
|
||||
mem_wr_en = 1'b1;
|
||||
|
||||
if (&init_ptr_reg) begin
|
||||
init_next = 1'b0;
|
||||
end
|
||||
end else if (s_axil_rd.arvalid && (!s_axil_rd.rvalid || s_axil_rd.rready) && op_axil_read_pipe_reg == 0) begin
|
||||
// AXIL read
|
||||
op_axil_read_pipe_next[0] = 1'b1;
|
||||
|
||||
s_axil_arready_next = 1'b1;
|
||||
|
||||
mem_rd_addr = s_axil_araddr_id;
|
||||
mem_addr_pipeline_next[0] = s_axil_araddr_id;
|
||||
axil_shift_pipeline_next[0] = s_axil_araddr_shift;
|
||||
end else if (s_axis_stat.tvalid && !s_axis_stat.tready && !op_acc_pipe_hazard) begin
|
||||
// accumulate
|
||||
op_acc_pipe_next[0] = !s_axis_stat.USER_EN || !s_axis_stat.tuser;
|
||||
|
||||
s_axis_stat_tready_next = 1'b1;
|
||||
|
||||
stat_inc_pipeline_next[0] = s_axis_stat.tdata;
|
||||
|
||||
mem_rd_addr = s_axis_stat.tid;
|
||||
mem_addr_pipeline_next[0] = s_axis_stat.tid;
|
||||
end
|
||||
|
||||
// read complete, perform operation
|
||||
if (op_acc_pipe_reg[PIPELINE-1]) begin
|
||||
// accumulate
|
||||
mem_wr_addr = mem_addr_pipeline_reg[PIPELINE-1];
|
||||
mem_wr_data = mem_read_data_pipeline_reg[PIPELINE-1] + STAT_COUNT_W'(stat_inc_pipeline_reg[PIPELINE-1]);
|
||||
mem_wr_en = 1'b1;
|
||||
end else if (op_axil_read_pipe_reg[PIPELINE-1]) begin
|
||||
// AXIL read
|
||||
s_axil_rvalid_next = 1'b1;
|
||||
s_axil_rdata_next = 0;
|
||||
|
||||
if (STAT_COUNT_W > AXIL_DATA_W) begin
|
||||
s_axil_rdata_next = AXIL_DATA_W'(mem_read_data_pipeline_reg[PIPELINE-1] >> axil_shift_pipeline_reg[PIPELINE-1]*AXIL_DATA_W);
|
||||
end else begin
|
||||
s_axil_rdata_next = AXIL_DATA_W'(mem_read_data_pipeline_reg[PIPELINE-1]);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
init_reg <= init_next;
|
||||
init_ptr_reg <= init_ptr_next;
|
||||
|
||||
op_axil_read_pipe_reg <= op_axil_read_pipe_next;
|
||||
op_acc_pipe_reg <= op_acc_pipe_next;
|
||||
|
||||
s_axis_stat_tready_reg <= s_axis_stat_tready_next;
|
||||
|
||||
s_axil_awready_reg <= s_axil_awready_next;
|
||||
s_axil_wready_reg <= s_axil_wready_next;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
s_axil_arready_reg <= s_axil_arready_next;
|
||||
s_axil_rdata_reg <= s_axil_rdata_next;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
for (integer i = 0; i < PIPELINE; i = i + 1) begin
|
||||
mem_addr_pipeline_reg[i] <= mem_addr_pipeline_next[i];
|
||||
axil_shift_pipeline_reg[i] <= axil_shift_pipeline_next[i];
|
||||
stat_inc_pipeline_reg[i] <= stat_inc_pipeline_next[i];
|
||||
end
|
||||
|
||||
if (mem_wr_en) begin
|
||||
mem[mem_wr_addr] <= mem_wr_data;
|
||||
end
|
||||
mem_read_data_reg <= mem[mem_rd_addr];
|
||||
mem_read_data_pipeline_reg[1] <= mem_read_data_reg;
|
||||
for (integer i = 2; i < PIPELINE; i = i + 1) begin
|
||||
mem_read_data_pipeline_reg[i] <= mem_read_data_pipeline_reg[i-1];
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
init_reg <= 1'b1;
|
||||
init_ptr_reg <= 0;
|
||||
|
||||
op_axil_read_pipe_reg <= 0;
|
||||
op_acc_pipe_reg <= 0;
|
||||
|
||||
s_axis_stat_tready_reg <= 1'b0;
|
||||
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
241
src/stats/rtl/taxi_stats_strings_full.sv
Normal file
241
src/stats/rtl/taxi_stats_strings_full.sv
Normal file
@@ -0,0 +1,241 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Statistics strings collector (full)
|
||||
*/
|
||||
module taxi_stats_strings_full #
|
||||
(
|
||||
// Pipeline length
|
||||
parameter PIPELINE = 2
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
taxi_axis_if.mon s_axis_stat,
|
||||
|
||||
/*
|
||||
* AXI Lite register interface
|
||||
*/
|
||||
taxi_axil_if.wr_slv s_axil_wr,
|
||||
taxi_axil_if.rd_slv s_axil_rd
|
||||
);
|
||||
|
||||
// localparam STAT_INC_W = s_axis_stat.DATA_W;
|
||||
localparam STAT_ID_W = s_axis_stat.ID_W;
|
||||
|
||||
localparam AXIL_ADDR_W = s_axil_rd.ADDR_W;
|
||||
localparam AXIL_DATA_W = s_axil_rd.DATA_W;
|
||||
|
||||
localparam ID_SHIFT = $clog2(((AXIL_DATA_W > 128 ? AXIL_DATA_W : 128)+7)/8);
|
||||
localparam WORD_SELECT_SHIFT = $clog2(AXIL_DATA_W/8);
|
||||
localparam WORD_SELECT_W = 128 > AXIL_DATA_W ? $clog2((128+7)/8) - $clog2(AXIL_DATA_W/8) : 1;
|
||||
|
||||
// check configuration
|
||||
if (AXIL_ADDR_W < STAT_ID_W+ID_SHIFT)
|
||||
$fatal(0, "Error: AXI lite address width too narrow (instance %m)");
|
||||
|
||||
if (PIPELINE < 2)
|
||||
$fatal(0, "Error: PIPELINE must be at least 2 (instance %m)");
|
||||
|
||||
logic init_reg = 1'b1, init_next;
|
||||
logic [STAT_ID_W-1:0] init_ptr_reg = 0, init_ptr_next;
|
||||
|
||||
logic op_acc_pipe_hazard;
|
||||
logic stage_active;
|
||||
|
||||
logic [PIPELINE-1:0] op_axil_read_pipe_reg = 0, op_axil_read_pipe_next;
|
||||
|
||||
logic [STAT_ID_W-1:0] mem_addr_pipeline_reg[PIPELINE], mem_addr_pipeline_next[PIPELINE];
|
||||
logic [WORD_SELECT_W-1:0] axil_shift_pipeline_reg[PIPELINE], axil_shift_pipeline_next[PIPELINE];
|
||||
|
||||
logic s_axil_awready_reg = 0, s_axil_awready_next;
|
||||
logic s_axil_wready_reg = 0, s_axil_wready_next;
|
||||
logic s_axil_bvalid_reg = 0, s_axil_bvalid_next;
|
||||
logic s_axil_arready_reg = 0, s_axil_arready_next;
|
||||
logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = 0, s_axil_rdata_next;
|
||||
logic s_axil_rvalid_reg = 0, s_axil_rvalid_next;
|
||||
|
||||
(* ramstyle = "no_rw_check" *)
|
||||
logic [127:0] mem[2**STAT_ID_W];
|
||||
|
||||
logic [STAT_ID_W-1:0] mem_rd_addr;
|
||||
logic [STAT_ID_W-1:0] mem_wr_addr;
|
||||
logic [127:0] mem_wr_data;
|
||||
logic [15:0] mem_wr_strb;
|
||||
logic mem_wr_en;
|
||||
logic [127:0] mem_read_data_reg = 0;
|
||||
logic [127:0] mem_read_data_pipeline_reg[PIPELINE-1:1];
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
assign s_axil_wr.bresp = 2'b00;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
assign s_axil_rd.arready = s_axil_arready_reg;
|
||||
assign s_axil_rd.rdata = s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = 2'b00;
|
||||
assign s_axil_rd.rvalid = s_axil_rvalid_reg;
|
||||
|
||||
wire [STAT_ID_W-1:0] s_axil_araddr_id = STAT_ID_W'(s_axil_rd.araddr >> ID_SHIFT);
|
||||
wire [WORD_SELECT_W-1:0] s_axil_araddr_shift = WORD_SELECT_W'(s_axil_rd.araddr >> WORD_SELECT_SHIFT);
|
||||
|
||||
initial begin
|
||||
// break up loop to work around iteration termination
|
||||
for (integer i = 0; i < 2**STAT_ID_W; i = i + 2**(STAT_ID_W/2)) begin
|
||||
for (integer j = i; j < i + 2**(STAT_ID_W/2); j = j + 1) begin
|
||||
mem[j] = 0;
|
||||
end
|
||||
end
|
||||
|
||||
for (integer i = 0; i < PIPELINE; i = i + 1) begin
|
||||
mem_addr_pipeline_reg[i] = 0;
|
||||
axil_shift_pipeline_reg[i] = 0;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
init_next = init_reg;
|
||||
init_ptr_next = init_ptr_reg;
|
||||
|
||||
op_axil_read_pipe_next = PIPELINE'({op_axil_read_pipe_reg, 1'b0});
|
||||
|
||||
mem_addr_pipeline_next[0] = 0;
|
||||
axil_shift_pipeline_next[0] = 0;
|
||||
for (integer j = 1; j < PIPELINE; j = j + 1) begin
|
||||
mem_addr_pipeline_next[j] = mem_addr_pipeline_reg[j-1];
|
||||
axil_shift_pipeline_next[j] = axil_shift_pipeline_reg[j-1];
|
||||
end
|
||||
|
||||
s_axil_awready_next = 1'b0;
|
||||
s_axil_wready_next = 1'b0;
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
|
||||
|
||||
s_axil_arready_next = 1'b0;
|
||||
s_axil_rdata_next = s_axil_rdata_reg;
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rd.rready;
|
||||
|
||||
mem_rd_addr = s_axil_araddr_id;
|
||||
mem_wr_addr = s_axis_stat.tid;
|
||||
mem_wr_data = {8{1'b0, s_axis_stat.tdata[15], ~s_axis_stat.tdata[15], s_axis_stat.tdata[14:10], 1'b0, s_axis_stat.tdata[9], ~s_axis_stat.tdata[9], s_axis_stat.tdata[8:4]}};
|
||||
mem_wr_strb = '0;
|
||||
mem_wr_strb[s_axis_stat.tdata[2:0]*2 +: 2] = 2'b11;
|
||||
mem_wr_en = 0;
|
||||
|
||||
// discard writes
|
||||
if (s_axil_wr.awvalid && s_axil_wr.wvalid && (!s_axil_wr.bvalid || s_axil_wr.bready) && (!s_axil_wr.awready && !s_axil_wr.wready)) begin
|
||||
s_axil_awready_next = 1'b1;
|
||||
s_axil_wready_next = 1'b1;
|
||||
s_axil_bvalid_next = 1'b1;
|
||||
end
|
||||
|
||||
// store string data
|
||||
if (init_reg) begin
|
||||
// zero strings
|
||||
init_ptr_next = init_ptr_reg + 1;
|
||||
|
||||
mem_wr_addr = init_ptr_reg;
|
||||
mem_wr_data = '0;
|
||||
mem_wr_strb = '1;
|
||||
mem_wr_en = 1'b1;
|
||||
|
||||
if (&init_ptr_reg) begin
|
||||
init_next = 1'b0;
|
||||
end
|
||||
end else if (s_axis_stat.tvalid && s_axis_stat.tready && s_axis_stat.tuser) begin
|
||||
// store string data
|
||||
mem_wr_addr = s_axis_stat.tid;
|
||||
mem_wr_data = {8{1'b0, s_axis_stat.tdata[15], ~s_axis_stat.tdata[15], s_axis_stat.tdata[14:10], 1'b0, s_axis_stat.tdata[9], ~s_axis_stat.tdata[9], s_axis_stat.tdata[8:4]}};
|
||||
mem_wr_strb[s_axis_stat.tdata[2:0]*2 +: 2] = 2'b11;
|
||||
mem_wr_en = 1'b1;
|
||||
end
|
||||
|
||||
// pipeline stage 0 - accept request
|
||||
if (s_axil_rd.arvalid && (!s_axil_rd.rvalid || s_axil_rd.rready) && op_axil_read_pipe_reg == 0) begin
|
||||
// AXIL read
|
||||
op_axil_read_pipe_next[0] = 1'b1;
|
||||
|
||||
s_axil_arready_next = 1'b1;
|
||||
|
||||
mem_rd_addr = s_axil_araddr_id;
|
||||
mem_addr_pipeline_next[0] = s_axil_araddr_id;
|
||||
axil_shift_pipeline_next[0] = s_axil_araddr_shift;
|
||||
end
|
||||
|
||||
// read complete, perform operation
|
||||
if (op_axil_read_pipe_reg[PIPELINE-1]) begin
|
||||
// AXIL read
|
||||
s_axil_rvalid_next = 1'b1;
|
||||
s_axil_rdata_next = 0;
|
||||
|
||||
if (128 > AXIL_DATA_W) begin
|
||||
s_axil_rdata_next = AXIL_DATA_W'(mem_read_data_pipeline_reg[PIPELINE-1] >> axil_shift_pipeline_reg[PIPELINE-1]*AXIL_DATA_W);
|
||||
end else begin
|
||||
s_axil_rdata_next = AXIL_DATA_W'(mem_read_data_pipeline_reg[PIPELINE-1]);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
init_reg <= init_next;
|
||||
init_ptr_reg <= init_ptr_next;
|
||||
|
||||
op_axil_read_pipe_reg <= op_axil_read_pipe_next;
|
||||
|
||||
s_axil_awready_reg <= s_axil_awready_next;
|
||||
s_axil_wready_reg <= s_axil_wready_next;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
s_axil_arready_reg <= s_axil_arready_next;
|
||||
s_axil_rdata_reg <= s_axil_rdata_next;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
for (integer i = 0; i < PIPELINE; i = i + 1) begin
|
||||
mem_addr_pipeline_reg[i] <= mem_addr_pipeline_next[i];
|
||||
axil_shift_pipeline_reg[i] <= axil_shift_pipeline_next[i];
|
||||
end
|
||||
|
||||
if (mem_wr_en) begin
|
||||
for (integer i = 0; i < 16; i = i + 1) begin
|
||||
if (mem_wr_strb[i]) begin
|
||||
mem[mem_wr_addr][i*8 +: 8] <= mem_wr_data[i*8 +: 8];
|
||||
end
|
||||
end
|
||||
end
|
||||
mem_read_data_reg <= mem[mem_rd_addr];
|
||||
mem_read_data_pipeline_reg[1] <= mem_read_data_reg;
|
||||
for (integer i = 2; i < PIPELINE; i = i + 1) begin
|
||||
mem_read_data_pipeline_reg[i] <= mem_read_data_pipeline_reg[i-1];
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
init_reg <= 1'b1;
|
||||
init_ptr_reg <= 0;
|
||||
|
||||
op_axil_read_pipe_reg <= 0;
|
||||
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user