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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-05-18 12:25:59 -07:00
parent 8cdae180a1
commit 66b53d98a2
690 changed files with 2314 additions and 1581 deletions
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1
src/xfcp/lib/taxi Symbolic link
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../../../

5
src/xfcp/rtl/taxi_xfcp_if_uart.f Normal file
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taxi_xfcp_if_uart.sv
../lib/taxi/src/lss/rtl/taxi_uart.f
../lib/taxi/src/axis/rtl/taxi_axis_fifo.sv
../lib/taxi/src/axis/rtl/taxi_axis_cobs_encode.f
../lib/taxi/src/axis/rtl/taxi_axis_cobs_decode.sv

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src/xfcp/rtl/taxi_xfcp_if_uart.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2017-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP Interface (UART)
*/
module taxi_xfcp_if_uart #(
parameter PRE_W = 16,
parameter TX_FIFO_DEPTH = 512,
parameter RX_FIFO_DEPTH = 512
)
(
input wire logic clk,
input wire logic rst,
/*
* UART interface
*/
input wire logic uart_rxd,
output wire logic uart_txd,
/*
* XFCP downstream port
*/
taxi_axis_if.src xfcp_dsp_ds,
taxi_axis_if.snk xfcp_dsp_us,
/*
* Configuration
*/
input wire logic [PRE_W-1:0] prescale
);
taxi_axis_if #(.DATA_W(8), .LAST_EN(0)) uart_tx(), uart_rx();
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) fifo_tx(), fifo_rx();
taxi_uart #(
.PRE_W(PRE_W)
)
uart_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis_tx(uart_tx),
/*
* AXI4-Stream output (source)
*/
.m_axis_rx(uart_rx),
/*
* UART interface
*/
.rxd(uart_rxd),
.txd(uart_txd),
/*
* Status
*/
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
/*
* Configuration
*/
.prescale(prescale)
);
taxi_axis_cobs_encode #(
.APPEND_ZERO(1)
)
cobs_encode_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(fifo_tx),
/*
* AXI4-Stream output (source)
*/
.m_axis(uart_tx)
);
taxi_axis_cobs_decode
cobs_decode_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(uart_rx),
/*
* AXI4-Stream output (source)
*/
.m_axis(fifo_rx)
);
taxi_axis_fifo #(
.DEPTH(TX_FIFO_DEPTH),
.FRAME_FIFO(1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(0)
)
tx_fifo_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(xfcp_dsp_us),
/*
* AXI4-Stream output (source)
*/
.m_axis(fifo_tx),
/*
* Pause
*/
.pause_req(1'b0),
.pause_ack(),
/*
* Status
*/
.status_depth(),
.status_depth_commit(),
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
taxi_axis_fifo #(
.DEPTH(RX_FIFO_DEPTH),
.FRAME_FIFO(1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(1)
)
rx_fifo_inst (
.clk(clk),
.rst(rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(fifo_rx),
/*
* AXI4-Stream output (source)
*/
.m_axis(xfcp_dsp_ds),
/*
* Pause
*/
.pause_req(1'b0),
.pause_ack(),
/*
* Status
*/
.status_depth(),
.status_depth_commit(),
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall

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src/xfcp/rtl/taxi_xfcp_mod_axi.f Normal file
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taxi_xfcp_mod_axi.sv
taxi_xfcp_mod_axil.sv
../lib/taxi/src/axi/rtl/taxi_axi_if.sv
../lib/taxi/src/axi/rtl/taxi_axil_if.sv
../lib/taxi/src/axis/rtl/taxi_axis_if.sv

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src/xfcp/rtl/taxi_xfcp_mod_axi.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP AXI module
*/
module taxi_xfcp_mod_axi #
(
parameter logic [15:0] XFCP_ID_TYPE = 16'h8001,
parameter XFCP_ID_STR = "AXI Master",
parameter logic [8*16-1:0] XFCP_EXT_ID = 0,
parameter XFCP_EXT_ID_STR = "",
parameter COUNT_SIZE = 16
)
(
input wire logic clk,
input wire logic rst,
/*
* XFCP upstream port
*/
taxi_axis_if.snk xfcp_usp_ds,
taxi_axis_if.src xfcp_usp_us,
/*
* AXI master interface
*/
taxi_axi_if.wr_mst m_axi_wr,
taxi_axi_if.rd_mst m_axi_rd
);
taxi_axil_if #(
.DATA_W(m_axi_wr.DATA_W),
.ADDR_W(m_axi_wr.ADDR_W),
.STRB_W(m_axi_wr.STRB_W)
) axil_if();
// AW
assign m_axi_wr.awid = '0;
assign m_axi_wr.awaddr = axil_if.awaddr;
assign m_axi_wr.awlen = '0;
assign m_axi_wr.awsize = 3'($clog2(m_axi_wr.STRB_W));
assign m_axi_wr.awburst = 2'b01;
assign m_axi_wr.awlock = 1'b0;
assign m_axi_wr.awcache = 4'b0011;
assign m_axi_wr.awprot = axil_if.awprot;
assign m_axi_wr.awqos = 4'd0;
assign m_axi_wr.awregion = 4'd0;
assign m_axi_wr.awuser = axil_if.awuser;
assign m_axi_wr.awvalid = axil_if.awvalid;
assign axil_if.awready = m_axi_wr.awready;
// W
assign m_axi_wr.wdata = axil_if.wdata;
assign m_axi_wr.wstrb = axil_if.wstrb;
assign m_axi_wr.wlast = 1'b1;
assign m_axi_wr.wuser = axil_if.wuser;
assign m_axi_wr.wvalid = axil_if.wvalid;
assign axil_if.wready = m_axi_wr.wready;
// B
assign axil_if.bresp = m_axi_wr.bresp;
assign axil_if.buser = m_axi_wr.buser;
assign axil_if.bvalid = m_axi_wr.bvalid;
assign m_axi_wr.bready = axil_if.bready;
// AR
assign m_axi_rd.arid = '0;
assign m_axi_rd.araddr = axil_if.araddr;
assign m_axi_rd.arlen = '0;
assign m_axi_rd.arsize = 3'($clog2(m_axi_wr.STRB_W));
assign m_axi_rd.arburst = 2'b01;
assign m_axi_rd.arlock = 1'b0;
assign m_axi_rd.arcache = 4'b0011;
assign m_axi_rd.arprot = axil_if.arprot;
assign m_axi_rd.arqos = 4'd0;
assign m_axi_rd.arregion = 4'd0;
assign m_axi_rd.aruser = axil_if.aruser;
assign m_axi_rd.arvalid = axil_if.arvalid;
assign axil_if.arready = m_axi_rd.arready;
// R
assign axil_if.rdata = m_axi_rd.rdata;
assign axil_if.rresp = m_axi_rd.rresp;
assign axil_if.ruser = m_axi_rd.ruser;
assign axil_if.rvalid = m_axi_rd.rvalid;
assign m_axi_rd.rready = axil_if.rready;
taxi_xfcp_mod_axil #(
.XFCP_ID_TYPE(XFCP_ID_TYPE),
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
.COUNT_SIZE(COUNT_SIZE)
)
xfcp_mod_axil_inst (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_usp_ds),
.xfcp_usp_us(xfcp_usp_us),
/*
* AXI lite master interface
*/
.m_axil_wr(axil_if),
.m_axil_rd(axil_if)
);
endmodule
`resetall

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src/xfcp/rtl/taxi_xfcp_mod_axil.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2019-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP AXI lite module
*/
module taxi_xfcp_mod_axil #
(
parameter logic [15:0] XFCP_ID_TYPE = 16'h8001,
parameter XFCP_ID_STR = "AXIL Master",
parameter logic [8*16-1:0] XFCP_EXT_ID = 0,
parameter XFCP_EXT_ID_STR = "",
parameter COUNT_SIZE = 16
)
(
input wire logic clk,
input wire logic rst,
/*
* XFCP upstream port
*/
taxi_axis_if.snk xfcp_usp_ds,
taxi_axis_if.src xfcp_usp_us,
/*
* AXI lite master interface
*/
taxi_axil_if.wr_mst m_axil_wr,
taxi_axil_if.rd_mst m_axil_rd
);
// TODO various refactoring to fix width issues, among other things
// verilator lint_off WIDTH
localparam DATA_W = m_axil_wr.DATA_W;
localparam ADDR_W = m_axil_wr.ADDR_W;
localparam STRB_W = m_axil_wr.STRB_W;
// for interfaces that are more than one word wide, disable address lines
localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
// width of data port in words
localparam BYTE_LANES = STRB_W;
// size of words
localparam BYTE_W = DATA_W/BYTE_LANES;
localparam BYTE_AW = $clog2((BYTE_W+7)/8);
localparam WORD_AW = BYTE_AW + $clog2(STRB_W);
localparam BYTE_AM = {1'b0, {BYTE_AW{1'b1}}};
localparam WORD_AM = {1'b0, {WORD_AW{1'b1}}};
localparam ADDR_W_ADJ = ADDR_W+BYTE_AW;
localparam COUNT_BYTE_LANES = (COUNT_SIZE+8-1)/8;
localparam ADDR_BYTE_LANES = (ADDR_W_ADJ+8-1)/8;
// check configuration
if (BYTE_LANES * BYTE_W != DATA_W)
$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
if (2**$clog2(BYTE_LANES) != BYTE_LANES)
$fatal(0, "Error: AXI word width must be even power of two (instance %m)");
if (8*2**$clog2(BYTE_W/8) != BYTE_W)
$fatal(0, "Error: AXI word size must be a power of two multiple of 8 (instance %m)");
localparam START_TAG = 8'hFF;
localparam RPATH_TAG = 8'hFE;
localparam READ_REQ = 8'h10;
localparam READ_RESP = 8'h11;
localparam WRITE_REQ = 8'h12;
localparam WRITE_RESP = 8'h13;
localparam ID_REQ = 8'hFE;
localparam ID_RESP = 8'hFF;
// ID ROM
localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5;
localparam ID_ROM_SIZE = 2**ID_PTR_W;
reg [7:0] id_rom[ID_ROM_SIZE];
reg [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next;
integer j;
initial begin
// init ID ROM
for (integer i = 0; i < ID_ROM_SIZE; i = i + 1) begin
id_rom[i] = 0;
end
// binary part
{id_rom[1], id_rom[0]} = 16'h8000 | XFCP_ID_TYPE; // module type
{id_rom[3], id_rom[2]} = 16'(ADDR_W); // address bus width
{id_rom[5], id_rom[4]} = 16'(DATA_W); // data bus width
{id_rom[7], id_rom[6]} = 16'(BYTE_W); // word size
{id_rom[9], id_rom[8]} = 16'(COUNT_SIZE); // count size
// string part
// find string length
j = 0;
for (integer i = 1; i <= 16; i = i + 1) begin
if (j == i-1 && (XFCP_ID_STR >> (i*8)) > 0) begin
j = i;
end
end
// pack string
for (integer i = 0; i <= j; i = i + 1) begin
id_rom[i+16] = XFCP_ID_STR[8*(j-i) +: 8];
end
if (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) begin
// extended ID
// binary part
for (integer i = 0; i < 16; i = i + 1) begin
id_rom[i+32] = XFCP_EXT_ID[8*i +: 8];
end
// string part
// find string length
j = 0;
for (integer i = 1; i <= 16; i = i + 1) begin
if (j == i-1 && (XFCP_EXT_ID_STR >> (i*8)) > 0) begin
j = i;
end
end
// pack string
for (integer i = 0; i <= j; i = i + 1) begin
id_rom[i+48] = XFCP_EXT_ID_STR[8*(j-i) +: 8];
end
end
end
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_HEADER_1 = 4'd1,
STATE_HEADER_2 = 4'd2,
STATE_HEADER_3 = 4'd3,
STATE_READ_1 = 4'd4,
STATE_READ_2 = 4'd5,
STATE_WRITE_1 = 4'd6,
STATE_WRITE_2 = 4'd7,
STATE_WAIT_LAST = 4'd8,
STATE_ID = 4'd9;
logic [3:0] state_reg = STATE_IDLE, state_next;
logic [COUNT_SIZE-1:0] ptr_reg = '0, ptr_next;
logic [7:0] count_reg = 8'd0, count_next;
logic last_cycle_reg = 1'b0;
logic write_reg = 1'b0, write_next;
logic [ADDR_W_ADJ-1:0] addr_reg = '0, addr_next;
logic [DATA_W-1:0] data_reg = '0, data_next;
logic xfcp_usp_ds_tready_reg = 1'b0, xfcp_usp_ds_tready_next;
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
logic [STRB_W-1:0] m_axil_wstrb_reg = '0, m_axil_wstrb_next;
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
logic m_axil_bready_reg = 1'b0, m_axil_bready_next;
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
// internal datapath
logic [7:0] xfcp_usp_us_tdata_int;
logic xfcp_usp_us_tvalid_int;
logic xfcp_usp_us_tready_int_reg = 1'b0;
logic xfcp_usp_us_tlast_int;
logic xfcp_usp_us_tuser_int;
wire xfcp_usp_us_tready_int_early;
assign xfcp_usp_ds.tready = xfcp_usp_ds_tready_reg;
assign m_axil_wr.awaddr = addr_reg;
assign m_axil_wr.awprot = 3'b010;
assign m_axil_wr.awuser = '0;
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
assign m_axil_wr.wdata = data_reg;
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
assign m_axil_wr.wuser = '0;
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
assign m_axil_wr.bready = m_axil_bready_reg;
assign m_axil_rd.araddr = addr_reg;
assign m_axil_rd.arprot = 3'b010;
assign m_axil_rd.aruser = '0;
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
assign m_axil_rd.rready = m_axil_rready_reg;
always_comb begin
state_next = STATE_IDLE;
ptr_next = ptr_reg;
count_next = count_reg;
write_next = write_reg;
id_ptr_next = id_ptr_reg;
xfcp_usp_ds_tready_next = 1'b0;
xfcp_usp_us_tdata_int = '0;
xfcp_usp_us_tvalid_int = 1'b0;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
addr_next = addr_reg;
data_next = data_reg;
m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_wr.awready;
m_axil_wstrb_next = m_axil_wstrb_reg;
m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wr.wready;
m_axil_bready_next = 1'b0;
m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_rd.arready;
m_axil_rready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle, wait for start of packet
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
id_ptr_next = '0;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
if (xfcp_usp_ds.tlast) begin
// last asserted, ignore cycle
state_next = STATE_IDLE;
end else if (xfcp_usp_ds.tdata == RPATH_TAG) begin
// need to pass through rpath
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
state_next = STATE_HEADER_1;
end else if (xfcp_usp_ds.tdata == START_TAG) begin
// process header
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
state_next = STATE_HEADER_2;
end else begin
// bad start byte, drop packet
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_HEADER_1: begin
// transfer through header
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
// transfer through
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
if (xfcp_usp_ds.tlast) begin
// last asserted in header, mark as such and drop
xfcp_usp_us_tuser_int = 1'b1;
state_next = STATE_IDLE;
end else if (xfcp_usp_ds.tdata == START_TAG) begin
// process header
state_next = STATE_HEADER_2;
end else begin
state_next = STATE_HEADER_1;
end
end else begin
state_next = STATE_HEADER_1;
end
end
STATE_HEADER_2: begin
// read packet type
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
if (xfcp_usp_ds.tdata == READ_REQ && !xfcp_usp_ds.tlast) begin
// start of read
xfcp_usp_us_tdata_int = READ_RESP;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
write_next = 1'b0;
count_next = 8'(COUNT_BYTE_LANES+ADDR_BYTE_LANES-1);
state_next = STATE_HEADER_3;
end else if (xfcp_usp_ds.tdata == WRITE_REQ && !xfcp_usp_ds.tlast) begin
// start of write
xfcp_usp_us_tdata_int = WRITE_RESP;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
write_next = 1'b1;
count_next = 8'(COUNT_BYTE_LANES+ADDR_BYTE_LANES-1);
state_next = STATE_HEADER_3;
end else if (xfcp_usp_ds.tdata == ID_REQ) begin
// identify
xfcp_usp_us_tdata_int = ID_RESP;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
state_next = STATE_ID;
end else begin
// invalid start of packet
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b1;
xfcp_usp_us_tuser_int = 1'b1;
if (xfcp_usp_ds.tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end
end else begin
state_next = STATE_HEADER_2;
end
end
STATE_HEADER_3: begin
// store address and length
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
// pass through
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
// store pointers
if (count_reg < COUNT_BYTE_LANES) begin
ptr_next[8*(COUNT_BYTE_LANES-count_reg-1) +: 8] = xfcp_usp_ds.tdata;
end else begin
addr_next[8*(ADDR_BYTE_LANES-(count_reg-COUNT_BYTE_LANES)-1) +: 8] = xfcp_usp_ds.tdata;
end
count_next = count_reg - 1;
if (count_reg == 0) begin
// end of header
// set initial word offset
count_next = addr_reg & WORD_AM;
m_axil_wstrb_next = '0;
data_next = '0;
if (write_reg) begin
// start writing
if (xfcp_usp_ds.tlast) begin
// end of frame in header
xfcp_usp_us_tlast_int = 1'b1;
xfcp_usp_us_tuser_int = 1'b1;
state_next = STATE_IDLE;
end else begin
xfcp_usp_us_tlast_int = 1'b1;
state_next = STATE_WRITE_1;
end
end else begin
// start reading
xfcp_usp_ds_tready_next = !(last_cycle_reg || (xfcp_usp_ds.tvalid && xfcp_usp_ds.tlast));
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b1;
state_next = STATE_READ_1;
end
end else begin
if (xfcp_usp_ds.tlast) begin
// end of frame in header
xfcp_usp_us_tlast_int = 1'b1;
xfcp_usp_us_tuser_int = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_HEADER_3;
end
end
end else begin
state_next = STATE_HEADER_3;
end
end
STATE_READ_1: begin
// wait for data
m_axil_rready_next = 1'b1;
// drop padding
xfcp_usp_ds_tready_next = !(last_cycle_reg || (xfcp_usp_ds.tvalid && xfcp_usp_ds.tlast));
if (m_axil_rd.rready && m_axil_rd.rvalid) begin
// read cycle complete, store result
m_axil_rready_next = 1'b0;
data_next = m_axil_rd.rdata;
addr_next = addr_reg + (1 << (ADDR_W-VALID_ADDR_W+BYTE_AW));
state_next = STATE_READ_2;
end else begin
state_next = STATE_READ_1;
end
end
STATE_READ_2: begin
// send data
// drop padding
xfcp_usp_ds_tready_next = !(last_cycle_reg || (xfcp_usp_ds.tvalid && xfcp_usp_ds.tlast));
if (xfcp_usp_us_tready_int_reg) begin
// transfer word and update pointers
xfcp_usp_us_tdata_int = data_reg[8*count_reg +: 8];
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
count_next = count_reg + 1;
ptr_next = ptr_reg - 1;
if (ptr_reg == 1) begin
// last word of read
xfcp_usp_us_tlast_int = 1'b1;
if (!(last_cycle_reg || (xfcp_usp_ds.tvalid && xfcp_usp_ds.tlast))) begin
state_next = STATE_WAIT_LAST;
end else begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end
end else if (count_reg == (STRB_W*BYTE_W/8)-1) begin
// end of stored data word; read the next one
count_next = 0;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b1;
state_next = STATE_READ_1;
end else begin
state_next = STATE_READ_2;
end
end else begin
state_next = STATE_READ_2;
end
end
STATE_WRITE_1: begin
// write data
xfcp_usp_ds_tready_next = 1'b1;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
// store word
data_next[8*count_reg +: 8] = xfcp_usp_ds.tdata;
count_next = count_reg + 1;
ptr_next = ptr_reg - 1;
m_axil_wstrb_next[count_reg >> ((BYTE_W/8)-1)] = 1'b1;
if (count_reg == (STRB_W*BYTE_W/8)-1 || ptr_reg == 1) begin
// have full word or at end of block, start write operation
count_next = 0;
xfcp_usp_ds_tready_next = 1'b0;
m_axil_awvalid_next = 1'b1;
m_axil_wvalid_next = 1'b1;
m_axil_bready_next = 1'b1;
state_next = STATE_WRITE_2;
if (xfcp_usp_ds.tlast) begin
// last asserted, nothing further to write
ptr_next = 0;
end
end else if (xfcp_usp_ds.tlast) begin
// last asserted, return to idle
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_1;
end
end else begin
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_2: begin
// wait for write completion
m_axil_bready_next = 1'b1;
if (m_axil_wr.bready && m_axil_wr.bvalid) begin
// end of write operation
data_next = '0;
addr_next = addr_reg + (1 << (ADDR_W-VALID_ADDR_W+BYTE_AW));
m_axil_bready_next = 1'b0;
m_axil_wstrb_next = '0;
if (ptr_reg == 0) begin
// done writing
if (!last_cycle_reg) begin
xfcp_usp_ds_tready_next = 1'b1;
state_next = STATE_WAIT_LAST;
end else begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end
end else begin
// more to write
state_next = STATE_WRITE_1;
end
end else begin
state_next = STATE_WRITE_2;
end
end
STATE_ID: begin
// send ID
// drop padding
xfcp_usp_ds_tready_next = !(last_cycle_reg || (xfcp_usp_ds.tvalid && xfcp_usp_ds.tlast));
xfcp_usp_us_tdata_int = id_rom[id_ptr_reg];
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
if (xfcp_usp_us_tready_int_reg) begin
// increment pointer
id_ptr_next = id_ptr_reg + 1;
if (id_ptr_reg == ID_PTR_W'(ID_ROM_SIZE-1)) begin
// read out whole ID
xfcp_usp_us_tlast_int = 1'b1;
if (!(last_cycle_reg || (xfcp_usp_ds.tvalid && xfcp_usp_ds.tlast))) begin
state_next = STATE_WAIT_LAST;
end else begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_ID;
end
end else begin
state_next = STATE_ID;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame
xfcp_usp_ds_tready_next = 1'b1;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
// wait for tlast
if (xfcp_usp_ds.tlast) begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
default: begin
// return to idle
state_next = STATE_IDLE;
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
id_ptr_reg <= id_ptr_next;
ptr_reg <= ptr_next;
count_reg <= count_next;
write_reg <= write_next;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
last_cycle_reg <= xfcp_usp_ds.tlast;
end
addr_reg <= addr_next;
data_reg <= data_next;
xfcp_usp_ds_tready_reg <= xfcp_usp_ds_tready_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wstrb_reg <= m_axil_wstrb_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
if (rst) begin
state_reg <= STATE_IDLE;
xfcp_usp_ds_tready_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
m_axil_bready_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
m_axil_rready_reg <= 1'b0;
end
end
// output datapath logic
logic [7:0] xfcp_usp_us_tdata_reg = '0;
logic xfcp_usp_us_tvalid_reg = 1'b0, xfcp_usp_us_tvalid_next;
logic xfcp_usp_us_tlast_reg = 1'b0;
logic xfcp_usp_us_tuser_reg = 1'b0;
logic [7:0] temp_xfcp_usp_us_tdata_reg = '0;
logic temp_xfcp_usp_us_tvalid_reg = 1'b0, temp_xfcp_usp_us_tvalid_next;
logic temp_xfcp_usp_us_tlast_reg = 1'b0;
logic temp_xfcp_usp_us_tuser_reg = 1'b0;
// datapath control
reg store_xfcp_usp_us_int_to_output;
reg store_xfcp_usp_us_int_to_temp;
reg store_xfcp_usp_us_temp_to_output;
assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg;
assign xfcp_usp_us.tkeep = '1;
assign xfcp_usp_us.tstrb = xfcp_usp_us.tkeep;
assign xfcp_usp_us.tvalid = xfcp_usp_us_tvalid_reg;
assign xfcp_usp_us.tlast = xfcp_usp_us_tlast_reg;
assign xfcp_usp_us.tid = '0;
assign xfcp_usp_us.tdest = '0;
assign xfcp_usp_us.tuser = xfcp_usp_us_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign xfcp_usp_us_tready_int_early = xfcp_usp_us.tready || (!temp_xfcp_usp_us_tvalid_reg && (!xfcp_usp_us_tvalid_reg || !xfcp_usp_us_tvalid_int));
always_comb begin
// transfer sink ready state to source
xfcp_usp_us_tvalid_next = xfcp_usp_us_tvalid_reg;
temp_xfcp_usp_us_tvalid_next = temp_xfcp_usp_us_tvalid_reg;
store_xfcp_usp_us_int_to_output = 1'b0;
store_xfcp_usp_us_int_to_temp = 1'b0;
store_xfcp_usp_us_temp_to_output = 1'b0;
if (xfcp_usp_us_tready_int_reg) begin
// input is ready
if (xfcp_usp_us.tready || !xfcp_usp_us_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
xfcp_usp_us_tvalid_next = xfcp_usp_us_tvalid_int;
store_xfcp_usp_us_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_xfcp_usp_us_tvalid_next = xfcp_usp_us_tvalid_int;
store_xfcp_usp_us_int_to_temp = 1'b1;
end
end else if (xfcp_usp_us.tready) begin
// input is not ready, but output is ready
xfcp_usp_us_tvalid_next = temp_xfcp_usp_us_tvalid_reg;
temp_xfcp_usp_us_tvalid_next = 1'b0;
store_xfcp_usp_us_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
xfcp_usp_us_tvalid_reg <= xfcp_usp_us_tvalid_next;
xfcp_usp_us_tready_int_reg <= xfcp_usp_us_tready_int_early;
temp_xfcp_usp_us_tvalid_reg <= temp_xfcp_usp_us_tvalid_next;
// datapath
if (store_xfcp_usp_us_int_to_output) begin
xfcp_usp_us_tdata_reg <= xfcp_usp_us_tdata_int;
xfcp_usp_us_tlast_reg <= xfcp_usp_us_tlast_int;
xfcp_usp_us_tuser_reg <= xfcp_usp_us_tuser_int;
end else if (store_xfcp_usp_us_temp_to_output) begin
xfcp_usp_us_tdata_reg <= temp_xfcp_usp_us_tdata_reg;
xfcp_usp_us_tlast_reg <= temp_xfcp_usp_us_tlast_reg;
xfcp_usp_us_tuser_reg <= temp_xfcp_usp_us_tuser_reg;
end
if (store_xfcp_usp_us_int_to_temp) begin
temp_xfcp_usp_us_tdata_reg <= xfcp_usp_us_tdata_int;
temp_xfcp_usp_us_tlast_reg <= xfcp_usp_us_tlast_int;
temp_xfcp_usp_us_tuser_reg <= xfcp_usp_us_tuser_int;
end
if (rst) begin
xfcp_usp_us_tvalid_reg <= 1'b0;
xfcp_usp_us_tready_int_reg <= 1'b0;
temp_xfcp_usp_us_tvalid_reg <= 1'b0;
end
end
endmodule
`resetall

3
src/xfcp/rtl/taxi_xfcp_mod_i2c_master.f Normal file
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taxi_xfcp_mod_i2c_master.sv
../lib/taxi/src/lss/rtl/taxi_i2c_master.sv
../lib/taxi/src/axis/rtl/taxi_axis_if.sv

815
src/xfcp/rtl/taxi_xfcp_mod_i2c_master.sv Normal file
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@@ -0,0 +1,815 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2017-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP I2C master module
*/
module taxi_xfcp_mod_i2c_master #
(
parameter logic [15:0] XFCP_ID_TYPE = 16'h2C00,
parameter XFCP_ID_STR = "I2C Master",
parameter logic [8*16-1:0] XFCP_EXT_ID = 0,
parameter XFCP_EXT_ID_STR = "",
parameter logic [15:0] DEFAULT_PRESCALE = 16'(125000000/400000/4)
)
(
input wire logic clk,
input wire logic rst,
/*
* XFCP upstream port
*/
taxi_axis_if.snk xfcp_usp_ds,
taxi_axis_if.src xfcp_usp_us,
/*
* I2C interface
*/
input wire logic i2c_scl_i,
output wire logic i2c_scl_o,
input wire logic i2c_sda_i,
output wire logic i2c_sda_o
);
localparam START_TAG = 8'hFF;
localparam RPATH_TAG = 8'hFE;
localparam I2C_REQ = 8'h2C;
localparam I2C_RESP = 8'h2D;
localparam ID_REQ = 8'hFE;
localparam ID_RESP = 8'hFF;
// ID ROM
localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5;
localparam ID_ROM_SIZE = 2**ID_PTR_W;
logic [7:0] id_rom[ID_ROM_SIZE];
logic [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next;
integer j;
initial begin
// init ID ROM
for (integer i = 0; i < ID_ROM_SIZE; i = i + 1) begin
id_rom[i] = 0;
end
// binary part
{id_rom[1], id_rom[0]} = 16'h2C00 | (16'h00FF & XFCP_ID_TYPE); // module type
// string part
// find string length
j = 0;
for (integer i = 1; i <= 16; i = i + 1) begin
if (j == i-1 && (XFCP_ID_STR >> (i*8)) > 0) begin
j = i;
end
end
// pack string
for (integer i = 0; i <= j; i = i + 1) begin
id_rom[i+16] = XFCP_ID_STR[8*(j-i) +: 8];
end
if (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) begin
// extended ID
// binary part
for (integer i = 0; i < 16; i = i + 1) begin
id_rom[i+32] = XFCP_EXT_ID[8*i +: 8];
end
// string part
// find string length
j = 0;
for (integer i = 1; i <= 16; i = i + 1) begin
if (j == i-1 && (XFCP_EXT_ID_STR >> (i*8)) > 0) begin
j = i;
end
end
// pack string
for (integer i = 0; i <= j; i = i + 1) begin
id_rom[i+48] = XFCP_EXT_ID_STR[8*(j-i) +: 8];
end
end
end
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_HEADER_1 = 4'd1,
STATE_HEADER_2 = 4'd2,
STATE_PROCESS = 4'd3,
STATE_STATUS = 4'd4,
STATE_PRESCALE_L = 4'd5,
STATE_PRESCALE_H = 4'd6,
STATE_COUNT = 4'd7,
STATE_NEXT_CMD= 4'd8,
STATE_WRITE_DATA = 4'd9,
STATE_READ_DATA = 4'd10,
STATE_WAIT_LAST = 4'd11,
STATE_ID = 4'd12;
logic [3:0] state_reg = STATE_IDLE, state_next;
logic [7:0] count_reg = 8'd0, count_next;
logic last_cycle_reg = 1'b0;
logic [6:0] i2c_cmd_address_reg = 7'd0, i2c_cmd_address_next;
logic i2c_cmd_start_reg = 1'b0, i2c_cmd_start_next;
logic i2c_cmd_read_reg = 1'b0, i2c_cmd_read_next;
logic i2c_cmd_write_reg = 1'b0, i2c_cmd_write_next;
logic i2c_cmd_write_multi_reg = 1'b0, i2c_cmd_write_multi_next;
logic i2c_cmd_stop_reg = 1'b0, i2c_cmd_stop_next;
logic i2c_cmd_valid_reg = 1'b0, i2c_cmd_valid_next;
logic cmd_txn_stop_reg = 1'b0, cmd_txn_stop_next;
logic [7:0] i2c_wr_data_reg = 8'd0, i2c_wr_data_next;
logic i2c_wr_data_valid_reg = 1'b0, i2c_wr_data_valid_next;
logic i2c_wr_data_last_reg = 1'b0, i2c_wr_data_last_next;
logic i2c_rd_data_ready_reg = 1'b0, i2c_rd_data_ready_next;
logic [15:0] prescale_reg = DEFAULT_PRESCALE, prescale_next;
logic stop_on_idle_reg = 1'b0, stop_on_idle_next;
logic missed_ack_reg = 1'b0, missed_ack_next;
logic xfcp_usp_ds_tready_reg = 1'b0, xfcp_usp_ds_tready_next;
// internal datapath
logic [7:0] xfcp_usp_us_tdata_int;
logic xfcp_usp_us_tvalid_int;
logic xfcp_usp_us_tready_int_reg = 1'b0;
logic xfcp_usp_us_tlast_int;
logic xfcp_usp_us_tuser_int;
wire xfcp_usp_us_tready_int_early;
taxi_axis_if #(.DATA_W(12), .KEEP_W(1)) i2c_cmd();
taxi_axis_if #(.DATA_W(8)) i2c_rd_data(), i2c_wr_data();
assign i2c_cmd.tdata[6:0] = i2c_cmd_address_reg;
assign i2c_cmd.tdata[7] = i2c_cmd_start_reg;
assign i2c_cmd.tdata[8] = i2c_cmd_read_reg;
assign i2c_cmd.tdata[9] = i2c_cmd_write_reg;
assign i2c_cmd.tdata[10] = i2c_cmd_write_multi_reg;
assign i2c_cmd.tdata[11] = i2c_cmd_stop_reg;
assign i2c_cmd.tvalid = i2c_cmd_valid_reg;
assign i2c_wr_data.tdata = i2c_wr_data_reg;
assign i2c_wr_data.tvalid = i2c_wr_data_valid_reg;
assign i2c_wr_data.tlast = i2c_wr_data_last_reg;
assign i2c_rd_data.tready = i2c_rd_data_ready_reg;
wire busy;
wire bus_control;
wire bus_active;
wire missed_ack;
assign xfcp_usp_ds.tready = xfcp_usp_ds_tready_reg;
always_comb begin
state_next = STATE_IDLE;
count_next = count_reg;
id_ptr_next = id_ptr_reg;
i2c_cmd_address_next = i2c_cmd_address_reg;
i2c_cmd_start_next = i2c_cmd_start_reg;
i2c_cmd_read_next = i2c_cmd_read_reg;
i2c_cmd_write_next = i2c_cmd_write_reg;
i2c_cmd_write_multi_next = i2c_cmd_write_multi_reg;
i2c_cmd_stop_next = i2c_cmd_stop_reg;
i2c_cmd_valid_next = i2c_cmd_valid_reg && !i2c_cmd.tready;
cmd_txn_stop_next = cmd_txn_stop_reg;
i2c_wr_data_next = i2c_wr_data_reg;
i2c_wr_data_valid_next = i2c_wr_data_valid_reg && !i2c_wr_data.tready;
i2c_wr_data_last_next = i2c_wr_data_last_reg;
i2c_rd_data_ready_next = 1'b0;
prescale_next = prescale_reg;
stop_on_idle_next = stop_on_idle_reg;
missed_ack_next = missed_ack_reg || missed_ack;
xfcp_usp_ds_tready_next = 1'b0;
xfcp_usp_us_tdata_int = 8'd0;
xfcp_usp_us_tvalid_int = 1'b0;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle, wait for start of packet
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
id_ptr_next = 5'd0;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
if (xfcp_usp_ds.tlast) begin
// last asserted, ignore cycle
state_next = STATE_IDLE;
end else if (xfcp_usp_ds.tdata == RPATH_TAG) begin
// need to pass through rpath
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
state_next = STATE_HEADER_1;
end else if (xfcp_usp_ds.tdata == START_TAG) begin
// process header
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
state_next = STATE_HEADER_2;
end else begin
// bad start byte, drop packet
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_HEADER_1: begin
// transfer through header
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
// transfer through
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
if (xfcp_usp_ds.tlast) begin
// last asserted in header, mark as such and drop
xfcp_usp_us_tuser_int = 1'b1;
state_next = STATE_IDLE;
end else if (xfcp_usp_ds.tdata == START_TAG) begin
// process header
state_next = STATE_HEADER_2;
end else begin
state_next = STATE_HEADER_1;
end
end else begin
state_next = STATE_HEADER_1;
end
end
STATE_HEADER_2: begin
// read packet type
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
if (xfcp_usp_ds.tdata == I2C_REQ && !xfcp_usp_ds.tlast) begin
// start of read
xfcp_usp_us_tdata_int = I2C_RESP;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
state_next = STATE_PROCESS;
end else if (xfcp_usp_ds.tdata == ID_REQ) begin
// identify
xfcp_usp_us_tdata_int = ID_RESP;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
state_next = STATE_ID;
end else begin
// invalid
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b1;
xfcp_usp_us_tuser_int = 1'b1;
if (xfcp_usp_ds.tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end
end else begin
state_next = STATE_HEADER_2;
end
end
STATE_PROCESS: begin
// process commands
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_cmd_valid_reg;
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = xfcp_usp_ds.tready && xfcp_usp_ds.tvalid;
xfcp_usp_us_tlast_int = xfcp_usp_ds.tlast;
xfcp_usp_us_tuser_int = 1'b0;
count_next = 8'd0;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
if (xfcp_usp_ds.tdata[7]) begin
// set address
i2c_cmd_address_next = xfcp_usp_ds.tdata[6:0];
state_next = STATE_PROCESS;
end else if (xfcp_usp_ds.tdata[6]) begin
if (xfcp_usp_ds.tdata[5:0] == 6'b000000) begin
// status query
xfcp_usp_ds_tready_next = 1'b0;
xfcp_usp_us_tlast_int = 1'b0;
state_next = STATE_STATUS;
end else if (xfcp_usp_ds.tdata[5:0] == 6'b100000) begin
// set prescale
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_PRESCALE_L;
end else begin
// unknown command
if (xfcp_usp_ds.tlast) begin
// last cycle; return to idle
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PROCESS;
end
end
end else begin
i2c_cmd_start_next = xfcp_usp_ds.tdata[0];
i2c_cmd_read_next = xfcp_usp_ds.tdata[1];
i2c_cmd_write_next = xfcp_usp_ds.tdata[2];
i2c_cmd_stop_next = xfcp_usp_ds.tdata[3];
i2c_cmd_valid_next = (i2c_cmd_start_next || i2c_cmd_read_next || i2c_cmd_write_next || i2c_cmd_stop_next);
cmd_txn_stop_next = i2c_cmd_stop_next;
if (xfcp_usp_ds.tdata[4]) begin
i2c_cmd_stop_next = 1'b0;
if (xfcp_usp_ds.tlast) begin
// last cycle; return to idle
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
// read in count value
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_COUNT;
end
end else if (i2c_cmd_write_next && !i2c_cmd_read_next) begin
// write
if (xfcp_usp_ds.tlast) begin
// last cycle; return to idle
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
// start writing
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_wr_data_valid_reg;
state_next = STATE_WRITE_DATA;
end
end else if (i2c_cmd_read_next && !i2c_cmd_write_next) begin
// read
xfcp_usp_ds_tready_next = 1'b0;
xfcp_usp_us_tlast_int = 1'b0;
state_next = STATE_READ_DATA;
end else begin
// unknown
if (xfcp_usp_ds.tlast) begin
// last cycle; return to idle
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PROCESS;
end
end
end
end else begin
state_next = STATE_PROCESS;
end
end
STATE_STATUS: begin
// read status
xfcp_usp_ds_tready_next = 1'b0;
xfcp_usp_us_tdata_int = '0;
xfcp_usp_us_tdata_int[0] = busy;
xfcp_usp_us_tdata_int[1] = bus_control;
xfcp_usp_us_tdata_int[2] = bus_active;
xfcp_usp_us_tdata_int[3] = missed_ack_reg;
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = last_cycle_reg;
xfcp_usp_us_tuser_int = 1'b0;
if (xfcp_usp_us_tready_int_reg) begin
missed_ack_next = missed_ack;
if (last_cycle_reg) begin
// last cycle; return to idle
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
// process next command
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_cmd_valid_reg;
state_next = STATE_PROCESS;
end
end else begin
state_next = STATE_STATUS;
end
end
STATE_PRESCALE_L: begin
// store prescale value
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = xfcp_usp_ds.tready && xfcp_usp_ds.tvalid;
xfcp_usp_us_tlast_int = xfcp_usp_ds.tlast;
xfcp_usp_us_tuser_int = 1'b0;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
prescale_next[7:0] = xfcp_usp_ds.tdata;
if (xfcp_usp_ds.tlast) begin
// last cycle; return to idle
state_next = STATE_IDLE;
end else begin
state_next = STATE_PRESCALE_H;
end
end else begin
state_next = STATE_PRESCALE_L;
end
end
STATE_PRESCALE_H: begin
// store prescale value
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = xfcp_usp_ds.tready && xfcp_usp_ds.tvalid;
xfcp_usp_us_tlast_int = xfcp_usp_ds.tlast;
xfcp_usp_us_tuser_int = 1'b0;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
prescale_next[15:8] = xfcp_usp_ds.tdata;
if (xfcp_usp_ds.tlast) begin
// last cycle; return to idle
state_next = STATE_IDLE;
end else begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_cmd_valid_reg;
state_next = STATE_PROCESS;
end
end else begin
state_next = STATE_PRESCALE_H;
end
end
STATE_COUNT: begin
// store count value
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = xfcp_usp_ds.tready && xfcp_usp_ds.tvalid;
xfcp_usp_us_tlast_int = xfcp_usp_ds.tlast;
xfcp_usp_us_tuser_int = 1'b0;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
count_next = xfcp_usp_ds.tdata;
if (i2c_cmd_write_reg && !i2c_cmd_read_reg) begin
// write
if (xfcp_usp_ds.tlast) begin
// last cycle; return to idle
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
// start writing
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_wr_data_valid_reg;
state_next = STATE_WRITE_DATA;
end
end else if (i2c_cmd_read_reg && !i2c_cmd_write_reg) begin
// start reading
xfcp_usp_ds_tready_next = 1'b0;
xfcp_usp_us_tlast_int = 1'b0;
state_next = STATE_READ_DATA;
end else begin
// neither, process next command
if (xfcp_usp_ds.tlast) begin
// last cycle; return to idle
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_cmd_valid_reg;
state_next = STATE_PROCESS;
end
end
end else begin
state_next = STATE_COUNT;
end
end
STATE_NEXT_CMD: begin
// next command
if (~i2c_cmd_valid_reg) begin
i2c_cmd_start_next = 1'b0;
i2c_cmd_valid_next = 1'b1;
count_next = count_reg - 1;
if (count_reg == 2) begin
i2c_cmd_stop_next = cmd_txn_stop_reg;
end
if (i2c_cmd_write_reg) begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_wr_data_valid_reg;
state_next = STATE_WRITE_DATA;
end else if (i2c_cmd_read_reg) begin
xfcp_usp_ds_tready_next = 1'b0;
state_next = STATE_READ_DATA;
end
end else begin
state_next = STATE_NEXT_CMD;
end
end
STATE_WRITE_DATA: begin
// write data
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_wr_data_valid_reg;
xfcp_usp_us_tdata_int = xfcp_usp_ds.tdata;
xfcp_usp_us_tvalid_int = xfcp_usp_ds.tready && xfcp_usp_ds.tvalid;
xfcp_usp_us_tlast_int = xfcp_usp_ds.tlast;
xfcp_usp_us_tuser_int = 1'b0;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
i2c_wr_data_next = xfcp_usp_ds.tdata;
i2c_wr_data_valid_next = 1'b1;
if (xfcp_usp_ds.tlast) begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
if (count_reg > 1) begin
xfcp_usp_ds_tready_next = 1'b0;
state_next = STATE_NEXT_CMD;
end else begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_cmd_valid_reg;
state_next = STATE_PROCESS;
end
end
end else begin
state_next = STATE_WRITE_DATA;
end
end
STATE_READ_DATA: begin
// read data
xfcp_usp_ds_tready_next = 1'b0;
i2c_rd_data_ready_next = xfcp_usp_us_tready_int_early;
xfcp_usp_us_tdata_int = i2c_rd_data.tdata;
xfcp_usp_us_tvalid_int = i2c_rd_data.tvalid;
xfcp_usp_us_tlast_int = last_cycle_reg;
xfcp_usp_us_tuser_int = 1'b0;
if (i2c_rd_data_ready_reg && i2c_rd_data.tvalid) begin
if (count_reg > 1) begin
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_ds_tready_next = 1'b0;
state_next = STATE_NEXT_CMD;
end else begin
if (last_cycle_reg) begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early && !i2c_cmd_valid_reg;
state_next = STATE_PROCESS;
end
end
end else begin
state_next = STATE_READ_DATA;
end
end
STATE_ID: begin
// send ID
// drop padding
xfcp_usp_ds_tready_next = !(last_cycle_reg || (xfcp_usp_ds.tvalid && xfcp_usp_ds.tlast));
xfcp_usp_us_tdata_int = id_rom[id_ptr_reg];
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
if (xfcp_usp_us_tready_int_reg) begin
id_ptr_next = id_ptr_reg + 1;
if (id_ptr_reg == ID_ROM_SIZE-1) begin
xfcp_usp_us_tlast_int = 1'b1;
if (!(last_cycle_reg || (xfcp_usp_ds.tvalid && xfcp_usp_ds.tlast))) begin
state_next = STATE_WAIT_LAST;
end else begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_ID;
end
end else begin
state_next = STATE_ID;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame
xfcp_usp_ds_tready_next = 1'b1;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
if (xfcp_usp_ds.tlast) begin
xfcp_usp_ds_tready_next = xfcp_usp_us_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
default: begin
// return to idle
state_next = STATE_IDLE;
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
id_ptr_reg <= id_ptr_next;
count_reg <= count_next;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
last_cycle_reg <= xfcp_usp_ds.tlast;
end
i2c_cmd_address_reg <= i2c_cmd_address_next;
i2c_cmd_start_reg <= i2c_cmd_start_next;
i2c_cmd_read_reg <= i2c_cmd_read_next;
i2c_cmd_write_reg <= i2c_cmd_write_next;
i2c_cmd_write_multi_reg <= i2c_cmd_write_multi_next;
i2c_cmd_stop_reg <= i2c_cmd_stop_next;
i2c_cmd_valid_reg <= i2c_cmd_valid_next;
cmd_txn_stop_reg <= cmd_txn_stop_next;
i2c_wr_data_reg <= i2c_wr_data_next;
i2c_wr_data_valid_reg <= i2c_wr_data_valid_next;
i2c_wr_data_last_reg <= i2c_wr_data_last_next;
i2c_rd_data_ready_reg <= i2c_rd_data_ready_next;
prescale_reg <= prescale_next;
stop_on_idle_reg <= stop_on_idle_next;
missed_ack_reg <= missed_ack_next;
xfcp_usp_ds_tready_reg <= xfcp_usp_ds_tready_next;
if (rst) begin
state_reg <= STATE_IDLE;
i2c_cmd_address_reg <= 7'd0;
i2c_cmd_valid_reg <= 1'b0;
i2c_wr_data_valid_reg <= 1'b0;
i2c_rd_data_ready_reg <= 1'b0;
prescale_reg <= DEFAULT_PRESCALE;
stop_on_idle_reg <= 1'b0;
missed_ack_reg <= 1'b0;
xfcp_usp_ds_tready_reg <= 1'b0;
end
end
// output datapath logic
reg [7:0] xfcp_usp_us_tdata_reg = 8'd0;
reg xfcp_usp_us_tvalid_reg = 1'b0, xfcp_usp_us_tvalid_next;
reg xfcp_usp_us_tlast_reg = 1'b0;
reg xfcp_usp_us_tuser_reg = 1'b0;
reg [7:0] temp_xfcp_usp_us_tdata_reg = 8'd0;
reg temp_xfcp_usp_us_tvalid_reg = 1'b0, temp_xfcp_usp_us_tvalid_next;
reg temp_xfcp_usp_us_tlast_reg = 1'b0;
reg temp_xfcp_usp_us_tuser_reg = 1'b0;
// datapath control
reg store_up_xfcp_int_to_output;
reg store_up_xfcp_int_to_temp;
reg store_up_xfcp_temp_to_output;
assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg;
assign xfcp_usp_us.tkeep = '1;
assign xfcp_usp_us.tstrb = xfcp_usp_us.tkeep;
assign xfcp_usp_us.tvalid = xfcp_usp_us_tvalid_reg;
assign xfcp_usp_us.tlast = xfcp_usp_us_tlast_reg;
assign xfcp_usp_us.tid = '0;
assign xfcp_usp_us.tdest = '0;
assign xfcp_usp_us.tuser = xfcp_usp_us_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign xfcp_usp_us_tready_int_early = xfcp_usp_us.tready || (!temp_xfcp_usp_us_tvalid_reg && (!xfcp_usp_us_tvalid_reg || !xfcp_usp_us_tvalid_int));
always_comb begin
// transfer sink ready state to source
xfcp_usp_us_tvalid_next = xfcp_usp_us_tvalid_reg;
temp_xfcp_usp_us_tvalid_next = temp_xfcp_usp_us_tvalid_reg;
store_up_xfcp_int_to_output = 1'b0;
store_up_xfcp_int_to_temp = 1'b0;
store_up_xfcp_temp_to_output = 1'b0;
if (xfcp_usp_us_tready_int_reg) begin
// input is ready
if (xfcp_usp_us.tready || !xfcp_usp_us_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
xfcp_usp_us_tvalid_next = xfcp_usp_us_tvalid_int;
store_up_xfcp_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_xfcp_usp_us_tvalid_next = xfcp_usp_us_tvalid_int;
store_up_xfcp_int_to_temp = 1'b1;
end
end else if (xfcp_usp_us.tready) begin
// input is not ready, but output is ready
xfcp_usp_us_tvalid_next = temp_xfcp_usp_us_tvalid_reg;
temp_xfcp_usp_us_tvalid_next = 1'b0;
store_up_xfcp_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
if (rst) begin
xfcp_usp_us_tvalid_reg <= 1'b0;
xfcp_usp_us_tready_int_reg <= 1'b0;
temp_xfcp_usp_us_tvalid_reg <= 1'b0;
end else begin
xfcp_usp_us_tvalid_reg <= xfcp_usp_us_tvalid_next;
xfcp_usp_us_tready_int_reg <= xfcp_usp_us_tready_int_early;
temp_xfcp_usp_us_tvalid_reg <= temp_xfcp_usp_us_tvalid_next;
end
// datapath
if (store_up_xfcp_int_to_output) begin
xfcp_usp_us_tdata_reg <= xfcp_usp_us_tdata_int;
xfcp_usp_us_tlast_reg <= xfcp_usp_us_tlast_int;
xfcp_usp_us_tuser_reg <= xfcp_usp_us_tuser_int;
end else if (store_up_xfcp_temp_to_output) begin
xfcp_usp_us_tdata_reg <= temp_xfcp_usp_us_tdata_reg;
xfcp_usp_us_tlast_reg <= temp_xfcp_usp_us_tlast_reg;
xfcp_usp_us_tuser_reg <= temp_xfcp_usp_us_tuser_reg;
end
if (store_up_xfcp_int_to_temp) begin
temp_xfcp_usp_us_tdata_reg <= xfcp_usp_us_tdata_int;
temp_xfcp_usp_us_tlast_reg <= xfcp_usp_us_tlast_int;
temp_xfcp_usp_us_tuser_reg <= xfcp_usp_us_tuser_int;
end
end
taxi_i2c_master
i2c_master_inst (
.clk(clk),
.rst(rst),
/*
* Host interface
*/
.s_axis_cmd(i2c_cmd),
.s_axis_data(i2c_wr_data),
.m_axis_data(i2c_rd_data),
/*
* I2C interface
*/
.scl_i(i2c_scl_i),
.scl_o(i2c_scl_o),
.sda_i(i2c_sda_i),
.sda_o(i2c_sda_o),
/*
* Status
*/
.busy(busy),
.bus_control(bus_control),
.bus_active(bus_active),
.missed_ack(missed_ack),
/*
* Configuration
*/
.prescale(prescale_reg),
.stop_on_idle(stop_on_idle_reg)
);
endmodule
`resetall

7
src/xfcp/rtl/taxi_xfcp_mod_stats.f Normal file
View File

@@ -0,0 +1,7 @@
taxi_xfcp_mod_stats.sv
taxi_xfcp_mod_axil.sv
taxi_xfcp_switch.f
../lib/taxi/src/stats/rtl/taxi_stats_counter.sv
../lib/taxi/src/stats/rtl/taxi_stats_strings_full.sv
../lib/taxi/src/axi/rtl/taxi_axil_if.sv
../lib/taxi/src/axis/rtl/taxi_axis_if.sv

188
src/xfcp/rtl/taxi_xfcp_mod_stats.sv Normal file
View File

@@ -0,0 +1,188 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP statistics counter module
*/
module taxi_xfcp_mod_stats #
(
parameter XFCP_ID_STR = "Statistics",
parameter logic [8*16-1:0] XFCP_EXT_ID = 0,
parameter XFCP_EXT_ID_STR = "",
parameter STAT_COUNT_W = 32,
parameter logic STAT_STR_EN = 1'b1,
parameter STAT_PIPELINE = 2
)
(
input wire logic clk,
input wire logic rst,
/*
* XFCP upstream port
*/
taxi_axis_if.snk xfcp_usp_ds,
taxi_axis_if.src xfcp_usp_us,
/*
* Statistics increment input
*/
taxi_axis_if.snk s_axis_stat
);
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[STAT_STR_EN ? 2 : 1](), xfcp_sw_us[STAT_STR_EN ? 2 : 1]();
taxi_xfcp_switch #(
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
.PORTS($size(xfcp_sw_us))
)
xfcp_sw_inst (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_usp_ds),
.xfcp_usp_us(xfcp_usp_us),
/*
* XFCP downstream ports
*/
.xfcp_dsp_ds(xfcp_sw_ds),
.xfcp_dsp_us(xfcp_sw_us)
);
taxi_axil_if #(
.DATA_W(32),
.ADDR_W(s_axis_stat.ID_W+$clog2(((STAT_COUNT_W+31)/32)*4))
) axil_if_stats();
taxi_stats_counter #(
.STAT_COUNT_W(STAT_COUNT_W),
.PIPELINE(STAT_PIPELINE)
)
stats_counter_inst (
.clk(clk),
.rst(rst),
/*
* Statistics increment input
*/
.s_axis_stat(s_axis_stat),
/*
* AXI Lite register interface
*/
.s_axil_wr(axil_if_stats),
.s_axil_rd(axil_if_stats)
);
taxi_xfcp_mod_axil #(
.XFCP_ID_TYPE(16'h8080),
.XFCP_ID_STR("Statistics"),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
.COUNT_SIZE(16)
)
xfcp_mod_axil_inst (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_sw_ds[0]),
.xfcp_usp_us(xfcp_sw_us[0]),
/*
* AXI lite master interface
*/
.m_axil_wr(axil_if_stats),
.m_axil_rd(axil_if_stats)
);
if (STAT_STR_EN) begin
taxi_axis_if #(
.DATA_W(s_axis_stat.DATA_W),
.KEEP_W(1),
.LAST_EN(0),
.ID_W(s_axis_stat.ID_W),
.ID_EN(s_axis_stat.ID_EN),
.USER_W(1),
.USER_EN(s_axis_stat.USER_EN)
)
axis_stat_int();
assign axis_stat_int.tdata = s_axis_stat.tdata;
assign axis_stat_int.tvalid = s_axis_stat.tvalid;
assign axis_stat_int.tready = s_axis_stat.tready;
assign axis_stat_int.tid = s_axis_stat.tid;
assign axis_stat_int.tuser = s_axis_stat.tuser;
taxi_axil_if #(
.DATA_W(32),
.ADDR_W(s_axis_stat.ID_W+4)
) axil_if_strings();
taxi_stats_strings_full #(
.PIPELINE(STAT_PIPELINE)
)
stats_strings_inst (
.clk(clk),
.rst(rst),
/*
* Statistics increment input
*/
.s_axis_stat(axis_stat_int),
/*
* AXI Lite register interface
*/
.s_axil_wr(axil_if_strings),
.s_axil_rd(axil_if_strings)
);
taxi_xfcp_mod_axil #(
.XFCP_ID_TYPE(16'h8081),
.XFCP_ID_STR("Stats Strings"),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
.COUNT_SIZE(16)
)
xfcp_mod_axil_inst (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_sw_ds[1]),
.xfcp_usp_us(xfcp_sw_us[1]),
/*
* AXI lite master interface
*/
.m_axil_wr(axil_if_strings),
.m_axil_rd(axil_if_strings)
);
end
endmodule
`resetall

4
src/xfcp/rtl/taxi_xfcp_switch.f Normal file
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@@ -0,0 +1,4 @@
taxi_xfcp_switch.sv
../lib/taxi/src/prim/rtl/taxi_arbiter.sv
../lib/taxi/src/prim/rtl/taxi_penc.sv
../lib/taxi/src/axis/rtl/taxi_axis_if.sv

677
src/xfcp/rtl/taxi_xfcp_switch.sv Normal file
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@@ -0,0 +1,677 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2017-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`timescale 1ns / 1ps
/*
* XFCP 1xN switch
*/
module taxi_xfcp_switch #
(
parameter PORTS = 4,
parameter logic [15:0] XFCP_ID_TYPE = 16'h0100,
parameter XFCP_ID_STR = "XFCP Switch",
parameter logic [8*16-1:0] XFCP_EXT_ID = 0,
parameter XFCP_EXT_ID_STR = ""
)
(
input wire logic clk,
input wire logic rst,
/*
* XFCP upstream port
*/
taxi_axis_if.snk xfcp_usp_ds,
taxi_axis_if.src xfcp_usp_us,
/*
* XFCP downstream ports
*/
taxi_axis_if.src xfcp_dsp_ds[PORTS],
taxi_axis_if.snk xfcp_dsp_us[PORTS]
);
localparam CL_PORTS = PORTS > 1 ? $clog2(PORTS) : 1;
localparam CL_PORTS_P1 = $clog2(PORTS+1);
// check configuration
if (PORTS < 1 || PORTS > 256)
$fatal(0, "Error: PORTS out of range; must be between 1 and 256");
localparam START_TAG = 8'hFF;
localparam RPATH_TAG = 8'hFE;
localparam ID_REQ = 8'hFE;
localparam ID_RESP = 8'hFF;
// ID ROM
localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5;
localparam ID_ROM_SIZE = 2**ID_PTR_W;
reg [7:0] id_rom[ID_ROM_SIZE];
reg [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next;
integer j;
initial begin
// init ID ROM
for (integer i = 0; i < ID_ROM_SIZE; i = i + 1) begin
id_rom[i] = 0;
end
// binary part
{id_rom[1], id_rom[0]} = 16'h0100 | (XFCP_ID_TYPE & 16'h00FF); // module type (switch)
id_rom[2] = 8'd1; // upstream port count
id_rom[3] = 8'(PORTS); // downstream port count
// string part
// find string length
j = 0;
for (integer i = 1; i <= 16; i = i + 1) begin
if (j == i-1 && (XFCP_ID_STR >> (i*8)) > 0) begin
j = i;
end
end
// pack string
for (integer i = 0; i <= j; i = i + 1) begin
id_rom[i+16] = XFCP_ID_STR[8*(j-i) +: 8];
end
if (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) begin
// extended ID
// binary part
for (integer i = 0; i < 16; i = i + 1) begin
id_rom[i+32] = XFCP_EXT_ID[8*i +: 8];
end
// string part
// find string length
j = 0;
for (integer i = 1; i <= 16; i = i + 1) begin
if (j == i-1 && (XFCP_EXT_ID_STR >> (i*8)) > 0) begin
j = i;
end
end
// pack string
for (integer i = 0; i <= j; i = i + 1) begin
id_rom[i+48] = XFCP_EXT_ID_STR[8*(j-i) +: 8];
end
end
end
localparam [2:0]
DN_STATE_IDLE = 3'd0,
DN_STATE_TRANSFER = 3'd1,
DN_STATE_HEADER = 3'd2,
DN_STATE_PKT = 3'd3,
DN_STATE_ID = 3'd4;
reg [2:0] dn_state_reg = DN_STATE_IDLE, dn_state_next;
localparam [0:0]
UP_STATE_IDLE = 1'd0,
UP_STATE_TRANSFER = 1'd1;
reg [0:0] up_state_reg = UP_STATE_IDLE, up_state_next;
reg [CL_PORTS-1:0] dn_select_reg = '0, dn_select_next;
reg dn_frame_reg = 1'b0, dn_frame_next;
reg dn_enable_reg = 1'b0, dn_enable_next;
reg [CL_PORTS_P1-1:0] up_select_reg = '0, up_select_next;
reg up_frame_reg = 1'b0, up_frame_next;
reg xfcp_usp_ds_tready_reg = 1'b0, xfcp_usp_ds_tready_next;
reg [PORTS-1:0] xfcp_dsp_us_tready_reg = '0, xfcp_dsp_us_tready_next;
wire [PORTS-1:0] xfcp_dsp_ds_tready;
wire [PORTS-1:0] xfcp_dsp_ds_tvalid;
// internal datapath
reg [7:0] xfcp_usp_us_tdata_int;
reg xfcp_usp_us_tvalid_int;
reg xfcp_usp_us_tready_int_reg = 1'b0;
reg xfcp_usp_us_tlast_int;
reg xfcp_usp_us_tuser_int;
wire xfcp_usp_us_tready_int_early;
reg [7:0] xfcp_dsp_ds_tdata_int;
reg [PORTS-1:0] xfcp_dsp_ds_tvalid_int;
reg xfcp_dsp_ds_tready_int_reg = 1'b0;
reg xfcp_dsp_ds_tlast_int;
reg xfcp_dsp_ds_tuser_int;
wire xfcp_dsp_ds_tready_int_early;
reg [7:0] int_loop_tdata_reg = 8'd0, int_loop_tdata_next;
reg int_loop_tvalid_reg = 1'b0, int_loop_tvalid_next;
reg int_loop_tready;
reg int_loop_tready_early;
reg int_loop_tlast_reg = 1'b0, int_loop_tlast_next;
reg int_loop_tuser_reg = 1'b0, int_loop_tuser_next;
assign xfcp_usp_ds.tready = xfcp_usp_ds_tready_reg;
// unpack interface array
wire [PORTS+1-1:0] xfcp_dsp_us_tready;
wire [7:0] xfcp_dsp_us_tdata[PORTS+1];
wire [PORTS+1-1:0] xfcp_dsp_us_tvalid;
wire [PORTS+1-1:0] xfcp_dsp_us_tlast;
wire xfcp_dsp_us_tuser[PORTS+1];
for (genvar n = 0; n < PORTS; n = n + 1) begin
assign xfcp_dsp_us_tdata[n] = xfcp_dsp_us[n].tdata;
assign xfcp_dsp_us_tvalid[n] = xfcp_dsp_us[n].tvalid;
assign xfcp_dsp_us[n].tready = xfcp_dsp_us_tready_reg[n];
assign xfcp_dsp_us_tlast[n] = xfcp_dsp_us[n].tlast;
assign xfcp_dsp_us_tuser[n] = xfcp_dsp_us[n].tuser;
assign xfcp_dsp_us_tready[n] = xfcp_dsp_us[n].tready;
end
assign xfcp_dsp_us_tdata[PORTS] = int_loop_tdata_reg;
assign xfcp_dsp_us_tvalid[PORTS] = int_loop_tvalid_reg;
assign xfcp_dsp_us_tlast[PORTS] = int_loop_tlast_reg;
assign xfcp_dsp_us_tuser[PORTS] = int_loop_tuser_reg;
assign xfcp_dsp_us_tready[PORTS] = int_loop_tready;
// mux for downstream output control signals
wire current_output_tvalid = xfcp_dsp_ds_tvalid[dn_select_reg];
wire current_output_tready = xfcp_dsp_ds_tready[dn_select_reg];
// mux for incoming downstream packet
wire [7:0] current_input_tdata = xfcp_dsp_us_tdata[up_select_reg];
wire current_input_tvalid = xfcp_dsp_us_tvalid[up_select_reg];
wire current_input_tready = xfcp_dsp_us_tready[up_select_reg];
wire current_input_tlast = xfcp_dsp_us_tlast[up_select_reg];
wire current_input_tuser = xfcp_dsp_us_tuser[up_select_reg];
// downstream control logic
always_comb begin
dn_state_next = DN_STATE_IDLE;
dn_select_next = dn_select_reg;
dn_frame_next = dn_frame_reg;
dn_enable_next = dn_enable_reg;
id_ptr_next = id_ptr_reg;
xfcp_usp_ds_tready_next = 1'b0;
xfcp_dsp_ds_tdata_int = xfcp_usp_ds.tdata;
xfcp_dsp_ds_tvalid_int = PORTS'(xfcp_usp_ds.tvalid && xfcp_usp_ds.tready && dn_enable_reg) << dn_select_reg;
xfcp_dsp_ds_tlast_int = xfcp_usp_ds.tlast;
xfcp_dsp_ds_tuser_int = xfcp_usp_ds.tuser;
int_loop_tdata_next = int_loop_tdata_reg;
int_loop_tvalid_next = int_loop_tvalid_reg && !int_loop_tready;
int_loop_tlast_next = int_loop_tlast_reg;
int_loop_tuser_next = int_loop_tuser_reg;
if (xfcp_usp_ds.tready & xfcp_usp_ds.tvalid) begin
// end of frame detection
if (xfcp_usp_ds.tlast) begin
dn_frame_next = 1'b0;
dn_enable_next = 1'b0;
end
end
case (dn_state_reg)
DN_STATE_IDLE: begin
// wait for incoming upstream packet
xfcp_usp_ds_tready_next = 1'b1;
id_ptr_next = '0;
if (!dn_frame_reg && xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
// start of frame
dn_frame_next = 1'b1;
if (xfcp_usp_ds.tdata == RPATH_TAG || xfcp_usp_ds.tdata == START_TAG) begin
// packet for us
int_loop_tdata_next = xfcp_usp_ds.tdata;
int_loop_tvalid_next = xfcp_usp_ds.tvalid;
int_loop_tlast_next = xfcp_usp_ds.tlast;
int_loop_tuser_next = xfcp_usp_ds.tuser;
xfcp_usp_ds_tready_next = int_loop_tready_early;
if (xfcp_usp_ds.tdata == RPATH_TAG) begin
// has rpath
dn_state_next = DN_STATE_HEADER;
end else begin
// no rpath
dn_state_next = DN_STATE_PKT;
end
end else begin
// route packet
dn_enable_next = 1'b1;
dn_select_next = CL_PORTS'(xfcp_usp_ds.tdata);
xfcp_usp_ds_tready_next = xfcp_dsp_ds_tready_int_early;
dn_state_next = DN_STATE_TRANSFER;
if (xfcp_usp_ds.tdata >= 8'(PORTS)) begin
// out of range
dn_enable_next = 1'b0;
end
end
end else begin
dn_state_next = DN_STATE_IDLE;
end
end
DN_STATE_TRANSFER: begin
// transfer upstream packet through proper downstream port
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
// end of frame detection
if (xfcp_usp_ds.tlast) begin
dn_frame_next = 1'b0;
dn_enable_next = 1'b0;
dn_state_next = DN_STATE_IDLE;
end else begin
dn_state_next = DN_STATE_TRANSFER;
end
end else begin
dn_state_next = DN_STATE_TRANSFER;
end
xfcp_usp_ds_tready_next = xfcp_dsp_ds_tready_int_early && dn_frame_next;
end
DN_STATE_HEADER: begin
// loop back header
xfcp_usp_ds_tready_next = int_loop_tready_early;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
int_loop_tdata_next = xfcp_usp_ds.tdata;
int_loop_tvalid_next = 1'b1;
int_loop_tlast_next = xfcp_usp_ds.tlast;
int_loop_tuser_next = xfcp_usp_ds.tuser;
// end of header detection
if (xfcp_usp_ds.tdata == START_TAG) begin
dn_state_next = DN_STATE_PKT;
end else begin
dn_state_next = DN_STATE_HEADER;
end
end else begin
dn_state_next = DN_STATE_HEADER;
end
end
DN_STATE_PKT: begin
// packet type
xfcp_usp_ds_tready_next = int_loop_tready_early;
if (xfcp_usp_ds.tready && xfcp_usp_ds.tvalid) begin
int_loop_tdata_next = xfcp_usp_ds.tdata;
int_loop_tvalid_next = 1'b1;
int_loop_tlast_next = xfcp_usp_ds.tlast;
int_loop_tuser_next = xfcp_usp_ds.tuser;
if (xfcp_usp_ds.tdata == ID_REQ) begin
// ID packet
int_loop_tdata_next = ID_RESP;
int_loop_tlast_next = 1'b0;
dn_state_next = DN_STATE_ID;
end else begin
// something else
int_loop_tlast_next = 1'b1;
int_loop_tuser_next = 1'b1;
dn_state_next = DN_STATE_IDLE;
end
end else begin
dn_state_next = DN_STATE_PKT;
end
end
DN_STATE_ID: begin
// send ID
xfcp_usp_ds_tready_next = dn_frame_next;
if (int_loop_tready) begin
int_loop_tdata_next = id_rom[id_ptr_reg];
int_loop_tvalid_next = 1'b1;
int_loop_tlast_next = 1'b0;
int_loop_tuser_next = 1'b0;
id_ptr_next = id_ptr_reg + 1;
if (id_ptr_reg == ID_ROM_SIZE-1) begin
int_loop_tlast_next = 1'b1;
dn_state_next = DN_STATE_IDLE;
end else begin
dn_state_next = DN_STATE_ID;
end
end else begin
dn_state_next = DN_STATE_ID;
end
end
default: begin
dn_state_next = DN_STATE_IDLE;
end
endcase
end
// upstream control logic
wire [PORTS+1-1:0] req;
wire [PORTS+1-1:0] ack;
wire [PORTS+1-1:0] grant;
wire grant_valid;
wire [CL_PORTS_P1-1:0] grant_index;
// arbiter instance
taxi_arbiter #(
.PORTS(PORTS+1),
.ARB_ROUND_ROBIN(1),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.LSB_HIGH_PRIO(1)
)
arb_inst (
.clk(clk),
.rst(rst),
.req(req),
.ack(ack),
.grant(grant),
.grant_valid(grant_valid),
.grant_index(grant_index)
);
assign req = xfcp_dsp_us_tvalid & ~grant;
assign ack = grant & xfcp_dsp_us_tvalid & xfcp_dsp_us_tready & xfcp_dsp_us_tlast;
always_comb begin
up_state_next = UP_STATE_IDLE;
up_select_next = up_select_reg;
up_frame_next = up_frame_reg;
xfcp_usp_us_tdata_int = current_input_tdata;
xfcp_usp_us_tvalid_int = current_input_tvalid && current_input_tready && up_frame_reg;
xfcp_usp_us_tlast_int = current_input_tlast;
xfcp_usp_us_tuser_int = current_input_tuser;
if (current_input_tready && current_input_tvalid) begin
if (current_input_tlast) begin
// end of frame detection
up_frame_next = 1'b0;
end
end
case (up_state_reg)
UP_STATE_IDLE: begin
// wait for incoming downstream packet
if (grant_valid && xfcp_usp_us_tready_int_reg) begin
up_frame_next = 1'b1;
up_select_next = grant_index;
up_state_next = UP_STATE_TRANSFER;
if (up_select_next == CL_PORTS_P1'(PORTS)) begin
// internal loop; don't add port
end else begin
// prepend port to packet
xfcp_usp_us_tdata_int = 8'(grant_index);
xfcp_usp_us_tvalid_int = 1'b1;
xfcp_usp_us_tlast_int = 1'b0;
xfcp_usp_us_tuser_int = 1'b0;
end
end else begin
up_state_next = UP_STATE_IDLE;
end
end
UP_STATE_TRANSFER: begin
// transfer downstream packet out through upstream port
if (current_input_tvalid && current_input_tready) begin
if (current_input_tlast) begin
up_frame_next = 1'b0;
up_state_next = UP_STATE_IDLE;
end else begin
up_state_next = UP_STATE_TRANSFER;
end
end else begin
up_state_next = UP_STATE_TRANSFER;
end
end
endcase
end
always_comb begin
xfcp_dsp_us_tready_next = '0;
// int_loop_tready_early = 1'b0;
// generate ready signal on selected port
if (up_select_next == CL_PORTS_P1'(PORTS)) begin
// int_loop_tready_early = xfcp_usp_us_tready_int_early && up_frame_next;
end else begin
xfcp_dsp_us_tready_next = PORTS'(xfcp_usp_us_tready_int_early && up_frame_next) << up_select_next;
end
end
always_comb begin
int_loop_tready_early = xfcp_usp_us_tready_int_early && up_frame_next;
end
always_comb begin
int_loop_tready = xfcp_usp_us_tready_int_reg && up_frame_reg;
end
always_ff @(posedge clk) begin
dn_state_reg <= dn_state_next;
up_state_reg <= up_state_next;
id_ptr_reg <= id_ptr_next;
dn_select_reg <= dn_select_next;
dn_frame_reg <= dn_frame_next;
dn_enable_reg <= dn_enable_next;
up_select_reg <= up_select_next;
up_frame_reg <= up_frame_next;
xfcp_usp_ds_tready_reg <= xfcp_usp_ds_tready_next;
xfcp_dsp_us_tready_reg <= xfcp_dsp_us_tready_next;
int_loop_tdata_reg <= int_loop_tdata_next;
int_loop_tvalid_reg <= int_loop_tvalid_next;
int_loop_tlast_reg <= int_loop_tlast_next;
int_loop_tuser_reg <= int_loop_tuser_next;
if (rst) begin
dn_state_reg <= DN_STATE_IDLE;
up_state_reg <= UP_STATE_IDLE;
dn_select_reg <= '0;
dn_frame_reg <= 1'b0;
dn_enable_reg <= 1'b0;
up_select_reg <= '0;
up_frame_reg <= 1'b0;
xfcp_usp_ds_tready_reg <= 1'b0;
xfcp_dsp_us_tready_reg <= '0;
int_loop_tvalid_reg <= 1'b0;
end
end
// upstream output datapath logic
reg [7:0] xfcp_usp_us_tdata_reg = 8'd0;
reg xfcp_usp_us_tvalid_reg = 1'b0, xfcp_usp_us_tvalid_next;
reg xfcp_usp_us_tlast_reg = 1'b0;
reg xfcp_usp_us_tuser_reg = 1'b0;
reg [7:0] temp_xfcp_usp_us_tdata_reg = 8'd0;
reg temp_xfcp_usp_us_tvalid_reg = 1'b0, temp_xfcp_usp_us_tvalid_next;
reg temp_xfcp_usp_us_tlast_reg = 1'b0;
reg temp_xfcp_usp_us_tuser_reg = 1'b0;
// datapath control
reg store_xfcp_usp_us_int_to_output;
reg store_xfcp_usp_us_int_to_temp;
reg store_xfcp_usp_us_temp_to_output;
assign xfcp_usp_us.tdata = xfcp_usp_us_tdata_reg;
assign xfcp_usp_us.tkeep = '1;
assign xfcp_usp_us.tstrb = xfcp_usp_us.tkeep;
assign xfcp_usp_us.tvalid = xfcp_usp_us_tvalid_reg;
assign xfcp_usp_us.tlast = xfcp_usp_us_tlast_reg;
assign xfcp_usp_us.tid = '0;
assign xfcp_usp_us.tdest = '0;
assign xfcp_usp_us.tuser = xfcp_usp_us_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign xfcp_usp_us_tready_int_early = xfcp_usp_us.tready || (!temp_xfcp_usp_us_tvalid_reg && (!xfcp_usp_us_tvalid_reg || !xfcp_usp_us_tvalid_int));
always_comb begin
// transfer sink ready state to source
xfcp_usp_us_tvalid_next = xfcp_usp_us_tvalid_reg;
temp_xfcp_usp_us_tvalid_next = temp_xfcp_usp_us_tvalid_reg;
store_xfcp_usp_us_int_to_output = 1'b0;
store_xfcp_usp_us_int_to_temp = 1'b0;
store_xfcp_usp_us_temp_to_output = 1'b0;
if (xfcp_usp_us_tready_int_reg) begin
// input is ready
if (xfcp_usp_us.tready || !xfcp_usp_us_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
xfcp_usp_us_tvalid_next = xfcp_usp_us_tvalid_int;
store_xfcp_usp_us_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_xfcp_usp_us_tvalid_next = xfcp_usp_us_tvalid_int;
store_xfcp_usp_us_int_to_temp = 1'b1;
end
end else if (xfcp_usp_us.tready) begin
// input is not ready, but output is ready
xfcp_usp_us_tvalid_next = temp_xfcp_usp_us_tvalid_reg;
temp_xfcp_usp_us_tvalid_next = 1'b0;
store_xfcp_usp_us_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
if (rst) begin
xfcp_usp_us_tvalid_reg <= 1'b0;
xfcp_usp_us_tready_int_reg <= 1'b0;
temp_xfcp_usp_us_tvalid_reg <= 1'b0;
end else begin
xfcp_usp_us_tvalid_reg <= xfcp_usp_us_tvalid_next;
xfcp_usp_us_tready_int_reg <= xfcp_usp_us_tready_int_early;
temp_xfcp_usp_us_tvalid_reg <= temp_xfcp_usp_us_tvalid_next;
end
// datapath
if (store_xfcp_usp_us_int_to_output) begin
xfcp_usp_us_tdata_reg <= xfcp_usp_us_tdata_int;
xfcp_usp_us_tlast_reg <= xfcp_usp_us_tlast_int;
xfcp_usp_us_tuser_reg <= xfcp_usp_us_tuser_int;
end else if (store_xfcp_usp_us_temp_to_output) begin
xfcp_usp_us_tdata_reg <= temp_xfcp_usp_us_tdata_reg;
xfcp_usp_us_tlast_reg <= temp_xfcp_usp_us_tlast_reg;
xfcp_usp_us_tuser_reg <= temp_xfcp_usp_us_tuser_reg;
end
if (store_xfcp_usp_us_int_to_temp) begin
temp_xfcp_usp_us_tdata_reg <= xfcp_usp_us_tdata_int;
temp_xfcp_usp_us_tlast_reg <= xfcp_usp_us_tlast_int;
temp_xfcp_usp_us_tuser_reg <= xfcp_usp_us_tuser_int;
end
end
// downstream output datapath logic
reg [7:0] xfcp_dsp_ds_tdata_reg = 8'd0;
reg [PORTS-1:0] xfcp_dsp_ds_tvalid_reg = '0, xfcp_dsp_ds_tvalid_next;
reg xfcp_dsp_ds_tlast_reg = 1'b0;
reg xfcp_dsp_ds_tuser_reg = 1'b0;
reg [7:0] temp_xfcp_dsp_ds_tdata_reg = 8'd0;
reg [PORTS-1:0] temp_xfcp_dsp_ds_tvalid_reg = '0, temp_xfcp_dsp_ds_tvalid_next;
reg temp_xfcp_dsp_ds_tlast_reg = 1'b0;
reg temp_xfcp_dsp_ds_tuser_reg = 1'b0;
// datapath control
reg store_xfcp_dsp_ds_to_output;
reg store_xfcp_dsp_ds_to_temp;
reg store_xfcp_dsp_ds_temp_to_output;
assign xfcp_dsp_ds_tvalid = xfcp_dsp_ds_tvalid_reg;
for (genvar k = 0; k < PORTS; k = k + 1) begin
assign xfcp_dsp_ds[k].tdata = xfcp_dsp_ds_tdata_reg;
assign xfcp_dsp_ds[k].tkeep = '1;
assign xfcp_dsp_ds[k].tstrb = xfcp_dsp_ds[k].tkeep;
assign xfcp_dsp_ds[k].tvalid = xfcp_dsp_ds_tvalid_reg[k];
assign xfcp_dsp_ds[k].tlast = xfcp_dsp_ds_tlast_reg;
assign xfcp_dsp_ds[k].tid = '0;
assign xfcp_dsp_ds[k].tdest = '0;
assign xfcp_dsp_ds[k].tuser = xfcp_dsp_ds_tuser_reg;
assign xfcp_dsp_ds_tready[k] = xfcp_dsp_ds[k].tready;
end
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign xfcp_dsp_ds_tready_int_early = ((xfcp_dsp_ds_tready & xfcp_dsp_ds_tvalid) != 0) || ((temp_xfcp_dsp_ds_tvalid_reg == 0) && ((xfcp_dsp_ds_tvalid == 0) || (xfcp_dsp_ds_tvalid_int == 0)));
always_comb begin
// transfer sink ready state to source
xfcp_dsp_ds_tvalid_next = xfcp_dsp_ds_tvalid_reg;
temp_xfcp_dsp_ds_tvalid_next = temp_xfcp_dsp_ds_tvalid_reg;
store_xfcp_dsp_ds_to_output = 1'b0;
store_xfcp_dsp_ds_to_temp = 1'b0;
store_xfcp_dsp_ds_temp_to_output = 1'b0;
if (xfcp_dsp_ds_tready_int_reg) begin
// input is ready
if (((xfcp_dsp_ds_tready & xfcp_dsp_ds_tvalid) != 0) || (xfcp_dsp_ds_tvalid == 0)) begin
// output is ready or currently not valid, transfer data to output
xfcp_dsp_ds_tvalid_next = xfcp_dsp_ds_tvalid_int;
store_xfcp_dsp_ds_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_xfcp_dsp_ds_tvalid_next = xfcp_dsp_ds_tvalid_int;
store_xfcp_dsp_ds_to_temp = 1'b1;
end
end else if ((xfcp_dsp_ds_tready & xfcp_dsp_ds_tvalid) != 0) begin
// input is not ready, but output is ready
xfcp_dsp_ds_tvalid_next = temp_xfcp_dsp_ds_tvalid_reg;
temp_xfcp_dsp_ds_tvalid_next = '0;
store_xfcp_dsp_ds_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
if (rst) begin
xfcp_dsp_ds_tvalid_reg <= '0;
xfcp_dsp_ds_tready_int_reg <= 1'b0;
temp_xfcp_dsp_ds_tvalid_reg <= '0;
end else begin
xfcp_dsp_ds_tvalid_reg <= xfcp_dsp_ds_tvalid_next;
xfcp_dsp_ds_tready_int_reg <= xfcp_dsp_ds_tready_int_early;
temp_xfcp_dsp_ds_tvalid_reg <= temp_xfcp_dsp_ds_tvalid_next;
end
// datapath
if (store_xfcp_dsp_ds_to_output) begin
xfcp_dsp_ds_tdata_reg <= xfcp_dsp_ds_tdata_int;
xfcp_dsp_ds_tlast_reg <= xfcp_dsp_ds_tlast_int;
xfcp_dsp_ds_tuser_reg <= xfcp_dsp_ds_tuser_int;
end else if (store_xfcp_dsp_ds_temp_to_output) begin
xfcp_dsp_ds_tdata_reg <= temp_xfcp_dsp_ds_tdata_reg;
xfcp_dsp_ds_tlast_reg <= temp_xfcp_dsp_ds_tlast_reg;
xfcp_dsp_ds_tuser_reg <= temp_xfcp_dsp_ds_tuser_reg;
end
if (store_xfcp_dsp_ds_to_temp) begin
temp_xfcp_dsp_ds_tdata_reg <= xfcp_dsp_ds_tdata_int;
temp_xfcp_dsp_ds_tlast_reg <= xfcp_dsp_ds_tlast_int;
temp_xfcp_dsp_ds_tuser_reg <= xfcp_dsp_ds_tuser_int;
end
end
endmodule

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src/xfcp/tb/taxi_xfcp_if_uart/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_xfcp_if_uart
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_PRE_W := 16
export PARAM_TX_FIFO_DEPTH := 512
export PARAM_RX_FIFO_DEPTH := 512
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

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src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import sys
import cocotb_test.simulator
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
from cocotbext.uart import UartSource, UartSink
try:
from xfcp import XfcpFrame
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
from xfcp import XfcpFrame
finally:
del sys.path[0]
class TB(object):
def __init__(self, dut, baud=3e6):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
self.uart_source = UartSource(dut.uart_rxd, baud=baud, bits=8, stop_bits=1)
self.uart_sink = UartSink(dut.uart_txd, baud=baud, bits=8, stop_bits=1)
self.dsp_source = AxiStreamSource(AxiStreamBus.from_entity(dut.xfcp_dsp_us), dut.clk, dut.rst)
self.dsp_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.xfcp_dsp_ds), dut.clk, dut.rst)
dut.prescale.setimmediatevalue(int(1/8e-9/baud))
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test_tx(dut, payload_lengths=None, payload_data=None):
tb = TB(dut)
await tb.reset()
for test_data in [payload_data(x) for x in payload_lengths()]:
pkt = XfcpFrame()
pkt.path = [1, 2, 3]
pkt.rpath = [4]
pkt.ptype = 1
pkt.payload = test_data
await tb.dsp_source.write(pkt.build())
rx_data = bytearray()
while True:
b = await tb.uart_sink.read(1)
if b[0] == 0:
break
rx_data.extend(b)
rx_pkt = XfcpFrame.parse_cobs(rx_data)
print(rx_pkt)
assert rx_pkt == pkt
assert tb.uart_sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_rx(dut, payload_lengths=None, payload_data=None):
tb = TB(dut)
await tb.reset()
for test_data in [payload_data(x) for x in payload_lengths()]:
pkt = XfcpFrame()
pkt.path = [1, 2, 3]
pkt.rpath = [4]
pkt.ptype = 1
pkt.payload = test_data
await tb.uart_source.write(pkt.build_cobs())
rx_frame = await tb.dsp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
print(rx_pkt)
assert rx_pkt == pkt
assert tb.dsp_sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
return list(range(1, 16)) + [128]
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
for test in [run_test_tx, run_test_rx]:
factory = TestFactory(test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
def test_taxi_xfcp_if_uart(request):
dut = "taxi_xfcp_if_uart"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['PRE_W'] = 16
parameters['TX_FIFO_DEPTH'] = 512
parameters['RX_FIFO_DEPTH'] = 512
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

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src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP Interface (UART) testbench
*/
module test_taxi_xfcp_if_uart #
(
/* verilator lint_off WIDTHTRUNC */
parameter PRE_W = 16,
parameter TX_FIFO_DEPTH = 512,
parameter RX_FIFO_DEPTH = 512
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
logic uart_rxd;
logic uart_txd;
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_dsp_ds(), xfcp_dsp_us();
logic [PRE_W-1:0] prescale;
taxi_xfcp_if_uart #(
.PRE_W(PRE_W),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH)
)
uut (
.clk(clk),
.rst(rst),
/*
* UART interface
*/
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
/*
* XFCP downstream port
*/
.xfcp_dsp_ds(xfcp_dsp_ds),
.xfcp_dsp_us(xfcp_dsp_us),
/*
* Configuration
*/
.prescale(prescale)
);
endmodule
`resetall

1
src/xfcp/tb/taxi_xfcp_if_uart/xfcp.py Symbolic link
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../xfcp.py

53
src/xfcp/tb/taxi_xfcp_mod_axi/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_xfcp_mod_axi
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_COUNT_SIZE := 16
export PARAM_AXI_DATA_W := 32
export PARAM_AXI_ADDR_W := 32
export PARAM_AXI_STRB_W := $(shell expr $(PARAM_AXI_DATA_W) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

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src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import struct
import sys
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
from cocotbext.axi import AxiBus, AxiRam
try:
from xfcp import XfcpFrame
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
from xfcp import XfcpFrame
finally:
del sys.path[0]
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
self.usp_source = AxiStreamSource(AxiStreamBus.from_entity(dut.xfcp_usp_ds), dut.clk, dut.rst)
self.usp_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.xfcp_usp_us), dut.clk, dut.rst)
self.axi_ram = AxiRam(AxiBus.from_entity(dut.m_axi), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None):
if generator:
self.usp_source.set_pause_generator(generator())
self.axi_ram.write_if.b_channel.set_pause_generator(generator())
self.axi_ram.read_if.r_channel.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.usp_sink.set_pause_generator(generator())
self.axi_ram.write_if.aw_channel.set_pause_generator(generator())
self.axi_ram.write_if.w_channel.set_pause_generator(generator())
self.axi_ram.read_if.ar_channel.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.axi_ram.write_if.byte_lanes
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_lanes*4):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axi_ram.write(addr-128, b'\xaa'*(length+256))
pkt = XfcpFrame()
pkt.ptype = 0x12
pkt.payload = bytearray(struct.pack('<IH', addr, length)+test_data)
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
for k in range(100):
await RisingEdge(dut.clk)
tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
assert tb.axi_ram.read(addr, length) == test_data
assert tb.axi_ram.read(addr-1, 1) == b'\xaa'
assert tb.axi_ram.read(addr+length, 1) == b'\xaa'
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.axi_ram.write_if.byte_lanes
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_lanes*4):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axi_ram.write(addr, test_data)
pkt = XfcpFrame()
pkt.ptype = 0x10
pkt.payload = bytearray(struct.pack('<IH', addr, length))
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
assert rx_pkt.payload[6:] == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_id(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
pkt = XfcpFrame()
pkt.ptype = 0xFE
pkt.payload = b''
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
assert len(rx_pkt.payload) == 32
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
for test in [run_test_write, run_test_read, run_test_id]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("data_w", [8, 16, 32])
def test_taxi_xfcp_mod_axi(request, data_w):
dut = "taxi_xfcp_mod_axi"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['COUNT_SIZE'] = 16
parameters['AXI_DATA_W'] = data_w
parameters['AXI_ADDR_W'] = 32
parameters['AXI_STRB_W'] = parameters['AXI_DATA_W'] // 8
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

62
src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP AXI module testbench
*/
module test_taxi_xfcp_mod_axi #
(
/* verilator lint_off WIDTHTRUNC */
parameter COUNT_SIZE = 16,
parameter AXI_DATA_W = 32,
parameter AXI_ADDR_W = 32,
parameter AXI_STRB_W = (AXI_DATA_W/8)
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_usp_ds(), xfcp_usp_us();
taxi_axi_if #(
.DATA_W(AXI_DATA_W),
.ADDR_W(AXI_ADDR_W),
.STRB_W(AXI_STRB_W)
) m_axi();
taxi_xfcp_mod_axi #(
.COUNT_SIZE(COUNT_SIZE)
)
uut (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_usp_ds),
.xfcp_usp_us(xfcp_usp_us),
/*
* AXI master interface
*/
.m_axi_wr(m_axi),
.m_axi_rd(m_axi)
);
endmodule
`resetall

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src/xfcp/tb/taxi_xfcp_mod_axi/xfcp.py Normal file
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# SPDX-License-Identifier: MIT
"""
Copyright (c) 2017-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import struct
def cobs_encode(block):
block = bytes(block)
enc = bytearray()
seg = bytearray()
code = 1
new_data = True
for b in block:
if b == 0:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = True
else:
code += 1
seg.append(b)
new_data = True
if code == 255:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = False
if new_data:
enc.append(code)
enc.extend(seg)
return bytes(enc)
def cobs_decode(block):
block = bytes(block)
dec = bytearray()
code = 0
i = 0
if 0 in block:
return None
while i < len(block):
code = block[i]
i += 1
if i+code-1 > len(block):
return None
dec.extend(block[i:i+code-1])
i += code-1
if code < 255 and i < len(block):
dec.append(0)
return bytes(dec)
class XfcpFrame(object):
def __init__(self, payload=b'', path=[], rpath=[], ptype=0):
self._payload = b''
self.path = path
self.rpath = rpath
self.ptype = ptype
if type(payload) is bytes:
self.payload = payload
if type(payload) is XfcpFrame:
self.payload = payload.payload
self.path = list(payload.path)
self.rpath = list(payload.rpath)
self.ptype = payload.ptype
@property
def payload(self):
return self._payload
@payload.setter
def payload(self, value):
self._payload = bytes(value)
def build(self):
data = bytearray()
for p in self.path:
data.extend(struct.pack('B', p))
if self.rpath:
data.extend(struct.pack('B', 0xFE))
for p in self.rpath:
data.extend(struct.pack('B', p))
data.extend(struct.pack('B', 0xFF))
data.extend(struct.pack('B', self.ptype))
data.extend(self.payload)
return data
def build_cobs(self):
return cobs_encode(self.build())+b'\x00'
@classmethod
def parse(cls, data):
data = bytes(data)
i = 0
path = []
rpath = []
while i < len(data) and data[i] < 0xFE:
path.append(data[i])
i += 1
if data[i] == 0xFE:
i += 1
while i < len(data) and data[i] < 0xFE:
rpath.append(data[i])
i += 1
assert data[i] == 0xFF
i += 1
ptype = data[i]
i += 1
payload = data[i:]
return cls(payload, path, rpath, ptype)
@classmethod
def parse_cobs(cls, data):
return cls.parse(cobs_decode(bytes(data)))
def __eq__(self, other):
if type(other) is XfcpFrame:
return (self.path == other.path and
self.rpath == other.rpath and
self.ptype == other.ptype and
self.payload == other.payload)
return False
def __repr__(self):
return f"XfcpFrame(payload={self.payload!r}, path={self.path!r}, rpath={self.rpath!r}, ptype={self.ptype})"

55
src/xfcp/tb/taxi_xfcp_mod_axil/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_xfcp_mod_axil
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_COUNT_SIZE := 16
export PARAM_AXIL_DATA_W := 32
export PARAM_AXIL_ADDR_W := 32
export PARAM_AXIL_STRB_W := $(shell expr $(PARAM_AXIL_DATA_W) / 8 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

262
src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import struct
import sys
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
from cocotbext.axi import AxiLiteBus, AxiLiteRam
try:
from xfcp import XfcpFrame
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
from xfcp import XfcpFrame
finally:
del sys.path[0]
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
self.usp_source = AxiStreamSource(AxiStreamBus.from_entity(dut.xfcp_usp_ds), dut.clk, dut.rst)
self.usp_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.xfcp_usp_us), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None):
if generator:
self.usp_source.set_pause_generator(generator())
self.axil_ram.write_if.b_channel.set_pause_generator(generator())
self.axil_ram.read_if.r_channel.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.usp_sink.set_pause_generator(generator())
self.axil_ram.write_if.aw_channel.set_pause_generator(generator())
self.axil_ram.write_if.w_channel.set_pause_generator(generator())
self.axil_ram.read_if.ar_channel.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.axil_ram.write_if.byte_lanes
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_lanes*4):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axil_ram.write(addr-128, b'\xaa'*(length+256))
pkt = XfcpFrame()
pkt.ptype = 0x12
pkt.payload = bytearray(struct.pack('<IH', addr, length)+test_data)
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
for k in range(100):
await RisingEdge(dut.clk)
tb.log.debug("%s", tb.axil_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
assert tb.axil_ram.read(addr, length) == test_data
assert tb.axil_ram.read(addr-1, 1) == b'\xaa'
assert tb.axil_ram.read(addr+length, 1) == b'\xaa'
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = tb.axil_ram.write_if.byte_lanes
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_lanes*4):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axil_ram.write(addr, test_data)
pkt = XfcpFrame()
pkt.ptype = 0x10
pkt.payload = bytearray(struct.pack('<IH', addr, length))
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
assert rx_pkt.payload[6:] == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_id(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
pkt = XfcpFrame()
pkt.ptype = 0xFE
pkt.payload = b''
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
assert len(rx_pkt.payload) == 32
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
for test in [run_test_write, run_test_read, run_test_id]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("data_w", [8, 16, 32])
def test_taxi_xfcp_mod_axil(request, data_w):
dut = "taxi_xfcp_mod_axil"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(taxi_src_dir, "axi", "rtl", "taxi_axil_if.sv"),
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['COUNT_SIZE'] = 16
parameters['AXIL_DATA_W'] = data_w
parameters['AXIL_ADDR_W'] = 32
parameters['AXIL_STRB_W'] = parameters['AXIL_DATA_W'] // 8
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

62
src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP AXI lite module testbench
*/
module test_taxi_xfcp_mod_axil #
(
/* verilator lint_off WIDTHTRUNC */
parameter COUNT_SIZE = 16,
parameter AXIL_DATA_W = 32,
parameter AXIL_ADDR_W = 32,
parameter AXIL_STRB_W = (AXIL_DATA_W/8)
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_usp_ds(), xfcp_usp_us();
taxi_axil_if #(
.DATA_W(AXIL_DATA_W),
.ADDR_W(AXIL_ADDR_W),
.STRB_W(AXIL_STRB_W)
) m_axil();
taxi_xfcp_mod_axil #(
.COUNT_SIZE(COUNT_SIZE)
)
uut (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_usp_ds),
.xfcp_usp_us(xfcp_usp_us),
/*
* AXI lite master interface
*/
.m_axil_wr(m_axil),
.m_axil_rd(m_axil)
);
endmodule
`resetall

159
src/xfcp/tb/taxi_xfcp_mod_axil/xfcp.py Normal file
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# SPDX-License-Identifier: MIT
"""
Copyright (c) 2017-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import struct
def cobs_encode(block):
block = bytes(block)
enc = bytearray()
seg = bytearray()
code = 1
new_data = True
for b in block:
if b == 0:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = True
else:
code += 1
seg.append(b)
new_data = True
if code == 255:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = False
if new_data:
enc.append(code)
enc.extend(seg)
return bytes(enc)
def cobs_decode(block):
block = bytes(block)
dec = bytearray()
code = 0
i = 0
if 0 in block:
return None
while i < len(block):
code = block[i]
i += 1
if i+code-1 > len(block):
return None
dec.extend(block[i:i+code-1])
i += code-1
if code < 255 and i < len(block):
dec.append(0)
return bytes(dec)
class XfcpFrame(object):
def __init__(self, payload=b'', path=[], rpath=[], ptype=0):
self._payload = b''
self.path = path
self.rpath = rpath
self.ptype = ptype
if type(payload) is bytes:
self.payload = payload
if type(payload) is XfcpFrame:
self.payload = payload.payload
self.path = list(payload.path)
self.rpath = list(payload.rpath)
self.ptype = payload.ptype
@property
def payload(self):
return self._payload
@payload.setter
def payload(self, value):
self._payload = bytes(value)
def build(self):
data = bytearray()
for p in self.path:
data.extend(struct.pack('B', p))
if self.rpath:
data.extend(struct.pack('B', 0xFE))
for p in self.rpath:
data.extend(struct.pack('B', p))
data.extend(struct.pack('B', 0xFF))
data.extend(struct.pack('B', self.ptype))
data.extend(self.payload)
return data
def build_cobs(self):
return cobs_encode(self.build())+b'\x00'
@classmethod
def parse(cls, data):
data = bytes(data)
i = 0
path = []
rpath = []
while i < len(data) and data[i] < 0xFE:
path.append(data[i])
i += 1
if data[i] == 0xFE:
i += 1
while i < len(data) and data[i] < 0xFE:
rpath.append(data[i])
i += 1
assert data[i] == 0xFF
i += 1
ptype = data[i]
i += 1
payload = data[i:]
return cls(payload, path, rpath, ptype)
@classmethod
def parse_cobs(cls, data):
return cls.parse(cobs_decode(bytes(data)))
def __eq__(self, other):
if type(other) is XfcpFrame:
return (self.path == other.path and
self.rpath == other.rpath and
self.ptype == other.ptype and
self.payload == other.payload)
return False
def __repr__(self):
return f"XfcpFrame(payload={self.payload!r}, path={self.path!r}, rpath={self.rpath!r}, ptype={self.ptype})"

50
src/xfcp/tb/taxi_xfcp_mod_i2c_master/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_xfcp_mod_i2c_master
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DEFAULT_PRESCALE := $(shell expr 125000000 / 400000 / 4 )
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

367
src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import struct
import sys
import cocotb_test.simulator
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
from cocotbext.i2c import I2cMemory
try:
from xfcp import XfcpFrame
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
from xfcp import XfcpFrame
finally:
del sys.path[0]
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
self.usp_source = AxiStreamSource(AxiStreamBus.from_entity(dut.xfcp_usp_ds), dut.clk, dut.rst)
self.usp_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.xfcp_usp_us), dut.clk, dut.rst)
self.i2c_mem = []
self.i2c_mem.append(I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x50, size=1024))
self.i2c_mem.append(I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x51, size=1024))
def set_idle_generator(self, generator=None):
if generator:
self.usp_source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.usp_sink.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def get_status(self):
self.log.debug("Get status")
pkt = XfcpFrame()
pkt.ptype = 0x2C
pkt.payload = b'\x40'
self.log.debug("TX packet: %s", pkt)
await self.usp_source.send(pkt.build())
rx_frame = await self.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
self.log.debug("RX packet: %s", rx_pkt)
status = rx_pkt.payload[-1]
self.log.debug("Status: 0x%x", status)
return status
async def set_prescale(self, val):
self.log.debug("Set prescale: %s", val)
payload = bytearray()
payload.append(0x60) # set prescale
payload.extend(struct.pack('<H', val)) # prescale
pkt = XfcpFrame()
pkt.ptype = 0x2C
pkt.payload = payload
self.log.debug("TX packet: %s", pkt)
await self.usp_source.send(pkt.build())
rx_frame = await self.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
self.log.debug("RX packet: %s", rx_pkt)
async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
# change prescale setting
await tb.set_prescale(125000000//4000000//4)
test_data = b'\x11\x22\x33\x44'
for mem in tb.i2c_mem:
data = struct.pack('>H', 0x0004)+test_data
payload = bytearray()
payload.append(0x80 | mem.addr) # set address
payload.append(0x1C) # start write
payload.append(len(data)) # length
payload.extend(data) # data
pkt = XfcpFrame()
pkt.ptype = 0x2C
pkt.payload = payload
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
for k in range(1000):
await RisingEdge(dut.clk)
data = mem.read_mem(4, 4)
tb.log.info("Read data: %s", data)
assert data == test_data
status = await tb.get_status()
# no missed ACKs
assert not (status & 8)
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
# change prescale setting
await tb.set_prescale(125000000//4000000//4)
test_data = b'\x11\x22\x33\x44'
for mem in tb.i2c_mem:
mem.write_mem(4, test_data)
payload = bytearray()
payload.append(0x80 | mem.addr) # set address
payload.append(0x14) # start write
payload.append(2) # length
payload.extend(struct.pack('>H', 0x0004)) # address
payload.append(0x1A) # start read
payload.append(4) # length
pkt = XfcpFrame()
pkt.ptype = 0x2C
pkt.payload = payload
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
data = rx_pkt.payload[-4:]
tb.log.info("Read data: %s", data)
assert data == test_data
status = await tb.get_status()
# no missed ACKs
assert not (status & 8)
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_nack(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
# change prescale setting
await tb.set_prescale(125000000//4000000//4)
payload = bytearray()
payload.append(0x80 | 0x55) # set address
payload.append(0x14) # start write
payload.append(2) # length
payload.extend(struct.pack('>H', 0x0004)) # address
pkt = XfcpFrame()
pkt.ptype = 0x2C
pkt.payload = payload
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
status = await tb.get_status()
# no missed ACKs
assert (status & 8)
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_id(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
pkt = XfcpFrame()
pkt.ptype = 0xFE
pkt.payload = b''
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
assert len(rx_pkt.payload) == 32
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
for test in [
run_test_write,
run_test_read,
run_test_nack,
run_test_id,
]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
def test_taxi_xfcp_mod_i2c_master(request):
dut = "taxi_xfcp_mod_i2c_master"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DEFAULT_PRESCALE'] = 125000000//400000//4
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

60
src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP I2C master module testbench
*/
module test_taxi_xfcp_mod_i2c_master #
(
/* verilator lint_off WIDTHTRUNC */
parameter logic [15:0] DEFAULT_PRESCALE = 125000000/400000/4
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_usp_ds(), xfcp_usp_us();
logic i2c_scl_i;
logic i2c_scl_o;
logic i2c_sda_i;
logic i2c_sda_o;
taxi_xfcp_mod_i2c_master #(
.DEFAULT_PRESCALE(DEFAULT_PRESCALE)
)
uut (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_usp_ds),
.xfcp_usp_us(xfcp_usp_us),
/*
* I2C interface
*/
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o)
);
endmodule
`resetall

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src/xfcp/tb/taxi_xfcp_mod_i2c_master/xfcp.py Normal file
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# SPDX-License-Identifier: MIT
"""
Copyright (c) 2017-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import struct
def cobs_encode(block):
block = bytes(block)
enc = bytearray()
seg = bytearray()
code = 1
new_data = True
for b in block:
if b == 0:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = True
else:
code += 1
seg.append(b)
new_data = True
if code == 255:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = False
if new_data:
enc.append(code)
enc.extend(seg)
return bytes(enc)
def cobs_decode(block):
block = bytes(block)
dec = bytearray()
code = 0
i = 0
if 0 in block:
return None
while i < len(block):
code = block[i]
i += 1
if i+code-1 > len(block):
return None
dec.extend(block[i:i+code-1])
i += code-1
if code < 255 and i < len(block):
dec.append(0)
return bytes(dec)
class XfcpFrame(object):
def __init__(self, payload=b'', path=[], rpath=[], ptype=0):
self._payload = b''
self.path = path
self.rpath = rpath
self.ptype = ptype
if type(payload) is bytes:
self.payload = payload
if type(payload) is XfcpFrame:
self.payload = payload.payload
self.path = list(payload.path)
self.rpath = list(payload.rpath)
self.ptype = payload.ptype
@property
def payload(self):
return self._payload
@payload.setter
def payload(self, value):
self._payload = bytes(value)
def build(self):
data = bytearray()
for p in self.path:
data.extend(struct.pack('B', p))
if self.rpath:
data.extend(struct.pack('B', 0xFE))
for p in self.rpath:
data.extend(struct.pack('B', p))
data.extend(struct.pack('B', 0xFF))
data.extend(struct.pack('B', self.ptype))
data.extend(self.payload)
return data
def build_cobs(self):
return cobs_encode(self.build())+b'\x00'
@classmethod
def parse(cls, data):
data = bytes(data)
i = 0
path = []
rpath = []
while i < len(data) and data[i] < 0xFE:
path.append(data[i])
i += 1
if data[i] == 0xFE:
i += 1
while i < len(data) and data[i] < 0xFE:
rpath.append(data[i])
i += 1
assert data[i] == 0xFF
i += 1
ptype = data[i]
i += 1
payload = data[i:]
return cls(payload, path, rpath, ptype)
@classmethod
def parse_cobs(cls, data):
return cls.parse(cobs_decode(bytes(data)))
def __eq__(self, other):
if type(other) is XfcpFrame:
return (self.path == other.path and
self.rpath == other.rpath and
self.ptype == other.ptype and
self.payload == other.payload)
return False
def __repr__(self):
return f"XfcpFrame(payload={self.payload!r}, path={self.path!r}, rpath={self.rpath!r}, ptype={self.ptype})"

50
src/xfcp/tb/taxi_xfcp_switch/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_xfcp_switch
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_PORTS := 4
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

244
src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import struct
import sys
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
try:
from xfcp import XfcpFrame
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
from xfcp import XfcpFrame
finally:
del sys.path[0]
class TB(object):
def __init__(self, dut, baud=3e6):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
self.usp_source = AxiStreamSource(AxiStreamBus.from_entity(dut.xfcp_usp_ds), dut.clk, dut.rst)
self.usp_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.xfcp_usp_us), dut.clk, dut.rst)
self.dsp_sources = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.xfcp_dsp_us]
self.dsp_sinks = [AxiStreamSink(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.xfcp_dsp_ds]
def set_idle_generator(self, generator=None):
if generator:
self.usp_source.set_pause_generator(generator())
for src in self.dsp_sources:
src.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.usp_sink.set_pause_generator(generator())
for snk in self.dsp_sinks:
snk.set_pause_generator(generator())
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test_downstream(dut, idle_inserter=None, backpressure_inserter=None, port=0):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
pkt = XfcpFrame()
pkt.path = [port]
pkt.ptype = 0x01
pkt.payload = bytearray(range(8))
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.dsp_sinks[port].recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
assert rx_pkt.path == []
assert rx_pkt.ptype == 0x01
assert rx_pkt.payload == bytearray(range(8))
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_upstream(dut, idle_inserter=None, backpressure_inserter=None, port=0):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
pkt = XfcpFrame()
pkt.ptype = 0x01
pkt.payload = bytearray(range(8))
tb.log.debug("TX packet: %s", pkt)
await tb.dsp_sources[port].send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
assert rx_pkt.path == [port]
assert rx_pkt.ptype == 0x01
assert rx_pkt.payload == bytearray(range(8))
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_id(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
pkt = XfcpFrame()
pkt.ptype = 0xFE
pkt.payload = b''
tb.log.debug("TX packet: %s", pkt)
await tb.usp_source.send(pkt.build())
rx_frame = await tb.usp_sink.recv()
rx_pkt = XfcpFrame.parse(rx_frame.tdata)
tb.log.debug("RX packet: %s", rx_pkt)
assert len(rx_pkt.payload) == 32
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
ports = len(cocotb.top.xfcp_dsp_us)
for test in [run_test_downstream, run_test_upstream]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.add_option("port", list(range(ports)))
factory.generate_tests()
for test in [run_test_id]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("ports", [1, 4])
def test_taxi_xfcp_switch(request, ports):
dut = "taxi_xfcp_switch"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['PORTS'] = ports
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

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src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* XFCP switch testbench
*/
module test_taxi_xfcp_switch #
(
/* verilator lint_off WIDTHTRUNC */
parameter PORTS = 4
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_usp_ds(), xfcp_usp_us();
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_dsp_ds[PORTS](), xfcp_dsp_us[PORTS]();
taxi_xfcp_switch #(
.PORTS(PORTS)
)
uut (
.clk(clk),
.rst(rst),
/*
* XFCP upstream port
*/
.xfcp_usp_ds(xfcp_usp_ds),
.xfcp_usp_us(xfcp_usp_us),
/*
* XFCP downstream ports
*/
.xfcp_dsp_ds(xfcp_dsp_ds),
.xfcp_dsp_us(xfcp_dsp_us)
);
endmodule
`resetall

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src/xfcp/tb/taxi_xfcp_switch/xfcp.py Normal file
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# SPDX-License-Identifier: MIT
"""
Copyright (c) 2017-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import struct
def cobs_encode(block):
block = bytes(block)
enc = bytearray()
seg = bytearray()
code = 1
new_data = True
for b in block:
if b == 0:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = True
else:
code += 1
seg.append(b)
new_data = True
if code == 255:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = False
if new_data:
enc.append(code)
enc.extend(seg)
return bytes(enc)
def cobs_decode(block):
block = bytes(block)
dec = bytearray()
code = 0
i = 0
if 0 in block:
return None
while i < len(block):
code = block[i]
i += 1
if i+code-1 > len(block):
return None
dec.extend(block[i:i+code-1])
i += code-1
if code < 255 and i < len(block):
dec.append(0)
return bytes(dec)
class XfcpFrame(object):
def __init__(self, payload=b'', path=[], rpath=[], ptype=0):
self._payload = b''
self.path = path
self.rpath = rpath
self.ptype = ptype
if type(payload) is bytes:
self.payload = payload
if type(payload) is XfcpFrame:
self.payload = payload.payload
self.path = list(payload.path)
self.rpath = list(payload.rpath)
self.ptype = payload.ptype
@property
def payload(self):
return self._payload
@payload.setter
def payload(self, value):
self._payload = bytes(value)
def build(self):
data = bytearray()
for p in self.path:
data.extend(struct.pack('B', p))
if self.rpath:
data.extend(struct.pack('B', 0xFE))
for p in self.rpath:
data.extend(struct.pack('B', p))
data.extend(struct.pack('B', 0xFF))
data.extend(struct.pack('B', self.ptype))
data.extend(self.payload)
return data
def build_cobs(self):
return cobs_encode(self.build())+b'\x00'
@classmethod
def parse(cls, data):
data = bytes(data)
i = 0
path = []
rpath = []
while i < len(data) and data[i] < 0xFE:
path.append(data[i])
i += 1
if data[i] == 0xFE:
i += 1
while i < len(data) and data[i] < 0xFE:
rpath.append(data[i])
i += 1
assert data[i] == 0xFF
i += 1
ptype = data[i]
i += 1
payload = data[i:]
return cls(payload, path, rpath, ptype)
@classmethod
def parse_cobs(cls, data):
return cls.parse(cobs_decode(bytes(data)))
def __eq__(self, other):
if type(other) is XfcpFrame:
return (self.path == other.path and
self.rpath == other.rpath and
self.ptype == other.ptype and
self.payload == other.payload)
return False
def __repr__(self):
return f"XfcpFrame(payload={self.payload!r}, path={self.path!r}, rpath={self.rpath!r}, ptype={self.ptype})"

159
src/xfcp/tb/xfcp.py Normal file
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# SPDX-License-Identifier: MIT
"""
Copyright (c) 2017-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import struct
def cobs_encode(block):
block = bytes(block)
enc = bytearray()
seg = bytearray()
code = 1
new_data = True
for b in block:
if b == 0:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = True
else:
code += 1
seg.append(b)
new_data = True
if code == 255:
enc.append(code)
enc.extend(seg)
code = 1
seg = bytearray()
new_data = False
if new_data:
enc.append(code)
enc.extend(seg)
return bytes(enc)
def cobs_decode(block):
block = bytes(block)
dec = bytearray()
code = 0
i = 0
if 0 in block:
return None
while i < len(block):
code = block[i]
i += 1
if i+code-1 > len(block):
return None
dec.extend(block[i:i+code-1])
i += code-1
if code < 255 and i < len(block):
dec.append(0)
return bytes(dec)
class XfcpFrame(object):
def __init__(self, payload=b'', path=[], rpath=[], ptype=0):
self._payload = b''
self.path = path
self.rpath = rpath
self.ptype = ptype
if type(payload) is bytes:
self.payload = payload
if type(payload) is XfcpFrame:
self.payload = payload.payload
self.path = list(payload.path)
self.rpath = list(payload.rpath)
self.ptype = payload.ptype
@property
def payload(self):
return self._payload
@payload.setter
def payload(self, value):
self._payload = bytes(value)
def build(self):
data = bytearray()
for p in self.path:
data.extend(struct.pack('B', p))
if self.rpath:
data.extend(struct.pack('B', 0xFE))
for p in self.rpath:
data.extend(struct.pack('B', p))
data.extend(struct.pack('B', 0xFF))
data.extend(struct.pack('B', self.ptype))
data.extend(self.payload)
return data
def build_cobs(self):
return cobs_encode(self.build())+b'\x00'
@classmethod
def parse(cls, data):
data = bytes(data)
i = 0
path = []
rpath = []
while i < len(data) and data[i] < 0xFE:
path.append(data[i])
i += 1
if data[i] == 0xFE:
i += 1
while i < len(data) and data[i] < 0xFE:
rpath.append(data[i])
i += 1
assert data[i] == 0xFF
i += 1
ptype = data[i]
i += 1
payload = data[i:]
return cls(payload, path, rpath, ptype)
@classmethod
def parse_cobs(cls, data):
return cls.parse(cobs_decode(bytes(data)))
def __eq__(self, other):
if type(other) is XfcpFrame:
return (self.path == other.path and
self.rpath == other.rpath and
self.ptype == other.ptype and
self.payload == other.payload)
return False
def __repr__(self):
return f"XfcpFrame(payload={self.payload!r}, path={self.path!r}, rpath={self.rpath!r}, ptype={self.ptype})"