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syn: Add timing constraints for signal synchronizer

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-25 15:39:00 -08:00
parent eae85cb8c7
commit 6e90f4f0a0
1 changed files with 16 additions and 0 deletions
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syn/vivado/taxi_sync_signal.tcl Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2020-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
#
# signal synchronizer timing constraints
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_sync_signal || REF_NAME == taxi_sync_signal)}] {
puts "Inserting timing constraints for taxi_sync_signal instance $inst"
set_property ASYNC_REG TRUE [get_cells -hier "sync_reg_reg[*][*]" -filter "PARENT == $inst"]
set_false_path -to [get_cells -hier "sync_reg_reg[0][*]" -filter "PARENT == $inst"]
}