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lss: Remove redundant tristate control outputs on I2C modules

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-19 12:41:39 -07:00
parent fa2385aedb
commit 79e0bf6976
4 changed files with 1 additions and 26 deletions
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15
rtl/lss/taxi_i2c_master.sv
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@@ -31,10 +31,8 @@ module taxi_i2c_master (
*/ */
input wire logic scl_i, input wire logic scl_i,
output wire logic scl_o, output wire logic scl_o,
output wire logic scl_t,
input wire logic sda_i, input wire logic sda_i,
output wire logic sda_o, output wire logic sda_o,
output wire logic sda_t,
/* /*
* Status * Status
@@ -124,22 +122,13 @@ stop_on_idle
automatically issue stop when command input is not valid automatically issue stop when command input is not valid
Example of interfacing with tristate pins: Example of interfacing with tristate pins:
(this will work for any tristate bus)
assign scl_i = scl_pin;
assign scl_pin = scl_t ? 1'bz : scl_o;
assign sda_i = sda_pin;
assign sda_pin = sda_t ? 1'bz : sda_o;
Equivalent code that does not use *_t connections:
(we can get away with this because I2C is open-drain)
assign scl_i = scl_pin; assign scl_i = scl_pin;
assign scl_pin = scl_o ? 1'bz : 1'b0; assign scl_pin = scl_o ? 1'bz : 1'b0;
assign sda_i = sda_pin; assign sda_i = sda_pin;
assign sda_pin = sda_o ? 1'bz : 1'b0; assign sda_pin = sda_o ? 1'bz : 1'b0;
Example of two interconnected I2C devices: Example of two interconnected internal I2C devices:
assign scl_1_i = scl_1_o & scl_2_o; assign scl_1_i = scl_1_o & scl_2_o;
assign scl_2_i = scl_1_o & scl_2_o; assign scl_2_i = scl_1_o & scl_2_o;
@@ -265,9 +254,7 @@ assign m_axis_data.tdest = '0;
assign m_axis_data.tuser = '0; assign m_axis_data.tuser = '0;
assign scl_o = scl_o_reg; assign scl_o = scl_o_reg;
assign scl_t = scl_o_reg;
assign sda_o = sda_o_reg; assign sda_o = sda_o_reg;
assign sda_t = sda_o_reg;
assign busy = busy_reg; assign busy = busy_reg;
assign bus_active = bus_active_reg; assign bus_active = bus_active_reg;

4
rtl/lss/taxi_i2c_single_reg.sv
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@@ -28,10 +28,8 @@ module taxi_i2c_single_reg #(
*/ */
input wire logic scl_i, input wire logic scl_i,
output wire logic scl_o, output wire logic scl_o,
output wire logic scl_t,
input wire logic sda_i, input wire logic sda_i,
output wire logic sda_o, output wire logic sda_o,
output wire logic sda_t,
/* /*
* Data register * Data register
@@ -72,9 +70,7 @@ logic last_scl_i_reg = 1'b1;
logic last_sda_i_reg = 1'b1; logic last_sda_i_reg = 1'b1;
assign scl_o = 1'b1; assign scl_o = 1'b1;
assign scl_t = 1'b1;
assign sda_o = sda_o_reg; assign sda_o = sda_o_reg;
assign sda_t = sda_o_reg;
assign data_out = data_reg; assign data_out = data_reg;

4
tb/lss/taxi_i2c_master/test_taxi_i2c_master.sv
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@@ -27,10 +27,8 @@ taxi_axis_if #(.DATA_W(8)) m_axis_data();
logic scl_i; logic scl_i;
logic scl_o; logic scl_o;
logic scl_t;
logic sda_i; logic sda_i;
logic sda_o; logic sda_o;
logic sda_t;
logic busy; logic busy;
logic bus_control; logic bus_control;
@@ -57,10 +55,8 @@ uut (
*/ */
.scl_i(scl_i), .scl_i(scl_i),
.scl_o(scl_o), .scl_o(scl_o),
.scl_t(scl_t),
.sda_i(sda_i), .sda_i(sda_i),
.sda_o(sda_o), .sda_o(sda_o),
.sda_t(sda_t),
/* /*
* Status * Status

4
tb/lss/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv
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@@ -29,10 +29,8 @@ logic rst;
logic scl_i; logic scl_i;
logic scl_o; logic scl_o;
logic scl_t;
logic sda_i; logic sda_i;
logic sda_o; logic sda_o;
logic sda_t;
logic [7:0] data_in; logic [7:0] data_in;
logic data_latch; logic data_latch;
@@ -51,10 +49,8 @@ uut (
*/ */
.scl_i(scl_i), .scl_i(scl_i),
.scl_o(scl_o), .scl_o(scl_o),
.scl_t(scl_t),
.sda_i(sda_i), .sda_i(sda_i),
.sda_o(sda_o), .sda_o(sda_o),
.sda_t(sda_t),
/* /*
* Data register * Data register