mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-07 16:28:40 -08:00
example: Add example design for BittWare XUP-P3R/XUSP3S
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -118,6 +118,8 @@ To facilitate the dual-license model, contributions to the project can only be a
|
||||
Example designs are provided for several different FPGA boards, showcasing many of the capabilities of this library. Building the example designs will require the appropriate vendor toolchain and may also require tool and IP licenses.
|
||||
|
||||
* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex UltraScale+ XCVU3P)
|
||||
* BittWare XUSP3S (Xilinx Virtex UltraScale XCVU095)
|
||||
* BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P)
|
||||
* Cisco Nexus K35-S/ExaNIC X10 (Xilinx Kintex UltraScale XCKU035)
|
||||
* Cisco Nexus K3P-S/ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P)
|
||||
* Cisco Nexus K3P-Q/ExaNIC X100 (Xilinx Kintex UltraScale+ XCKU3P)
|
||||
|
||||
37
example/XUPP3R/fpga/README.md
Normal file
37
example/XUPP3R/fpga/README.md
Normal file
@@ -0,0 +1,37 @@
|
||||
# Taxi Example Design for XUP-P3R/XUSP3S
|
||||
|
||||
## Introduction
|
||||
|
||||
This example design targets the BittWare XUP-P3R/XUSP3S FPGA board.
|
||||
|
||||
The design places looped-back MACs on the QSFP28 ports, as well as XFCP on the USB UART for monitoring and control.
|
||||
|
||||
* USB UART
|
||||
* XFCP (3 Mbaud)
|
||||
* QSFP28
|
||||
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
|
||||
|
||||
## Board details
|
||||
|
||||
* FPGA: xcvu9p-flga2104-2L-e
|
||||
* XUP-P3R: xcvu9p-flgb2104-2-e
|
||||
* XUSP3S: xcvu095-ffvb2104-2-e
|
||||
* USB UART: FTDI FT232R
|
||||
* 25GBASE-R PHY: Soft PCS with GTY transceivers
|
||||
|
||||
## Licensing
|
||||
|
||||
* Toolchain
|
||||
* Vivado Enterprise (requires license)
|
||||
* IP
|
||||
* No licensed vendor IP or 3rd party IP
|
||||
|
||||
## How to build
|
||||
|
||||
Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
|
||||
|
||||
## How to test
|
||||
|
||||
Run `make program` to program the board with Vivado.
|
||||
|
||||
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
|
||||
153
example/XUPP3R/fpga/common/vivado.mk
Normal file
153
example/XUPP3R/fpga/common/vivado.mk
Normal file
@@ -0,0 +1,153 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016-2025 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - list of source files
|
||||
# INC_FILES - list of include files
|
||||
# XDC_FILES - list of timing constraint files
|
||||
# XCI_FILES - list of IP XCI files
|
||||
# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
|
||||
# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
|
||||
#
|
||||
# Note: both SYN_FILES and INC_FILES support file list files. File list
|
||||
# files are files with a .f extension that contain a list of additional
|
||||
# files to include, one path relative to the .f file location per line.
|
||||
# The .f files are processed recursively, and then the complete file list
|
||||
# is de-duplicated, with later files in the list taking precedence.
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: fpga vivado tmpclean clean distclean
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include $(CONFIG)
|
||||
|
||||
FPGA_TOP ?= fpga
|
||||
PROJECT ?= $(FPGA_TOP)
|
||||
XDC_FILES ?= $(PROJECT).xdc
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
|
||||
INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything (fpga)
|
||||
# fpga: build FPGA config
|
||||
# vivado: open project in Vivado
|
||||
# tmpclean: remove intermediate files
|
||||
# clean: remove output files and project files
|
||||
# distclean: remove archived output files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(PROJECT).bit
|
||||
|
||||
vivado: $(PROJECT).xpr
|
||||
vivado $(PROJECT).xpr
|
||||
|
||||
tmpclean::
|
||||
-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean:: tmpclean
|
||||
-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
|
||||
|
||||
distclean:: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
|
||||
# create fresh project if Makefile or IP files have changed
|
||||
create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
|
||||
echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
|
||||
echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
|
||||
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
|
||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
# source config TCL scripts if any source file has changed
|
||||
update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
|
||||
echo "open_project -quiet $(PROJECT).xpr" > $@
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
$(PROJECT).xpr: create_project.tcl update_config.tcl
|
||||
vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
|
||||
|
||||
# synthesis run
|
||||
$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
|
||||
echo "open_project $(PROJECT).xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
|
||||
echo "open_project $(PROJECT).xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "open_run impl_1" >> run_impl.tcl
|
||||
echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
|
||||
echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# output files (including potentially bit, bin, ltx, and xsa)
|
||||
$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
|
||||
echo "open_project $(PROJECT).xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
|
||||
echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
|
||||
echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
|
||||
ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
|
||||
cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
|
||||
if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
|
||||
if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
|
||||
154
example/XUPP3R/fpga/fpga_XUPP3R/Makefile
Normal file
154
example/XUPP3R/fpga/fpga_XUPP3R/Makefile
Normal file
@@ -0,0 +1,154 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu9p-flgb2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = ../rtl/fpga_xupp3r.sv
|
||||
SYN_FILES += ../rtl/fpga_core.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_xupp3r.xdc
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
%_fallback.bit: %.bit
|
||||
echo "open_project $*.xpr" > generate_fallback_bit.tcl
|
||||
echo "open_run impl_1" >> generate_fallback_bit.tcl
|
||||
echo "startgroup" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "endgroup" >> generate_fallback_bit.tcl
|
||||
echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
|
||||
echo "undo" >> generate_fallback_bit.tcl
|
||||
echo "exit" >> generate_fallback_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
|
||||
mkdir -p rev
|
||||
EXT=bit; COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
%_fallback.mcs %_fallback.prm: %_fallback.bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x0C000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
|
||||
echo "exit" >> generate_fallback_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||
|
||||
%_full.mcs %_full.prm: %_fallback.bit %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x0C000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||
echo "exit" >> generate_full_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
|
||||
echo "open_hw" > flash$*.tcl
|
||||
echo "connect_hw_server" >> flash$*.tcl
|
||||
echo "open_hw_target" >> flash$*.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "exit" >> flash$*.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||
154
example/XUPP3R/fpga/fpga_XUPP3R_10g/Makefile
Normal file
154
example/XUPP3R/fpga/fpga_XUPP3R_10g/Makefile
Normal file
@@ -0,0 +1,154 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu9p-flgb2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = ../rtl/fpga_xupp3r.sv
|
||||
SYN_FILES += ../rtl/fpga_core.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_xupp3r.xdc
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_322.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
%_fallback.bit: %.bit
|
||||
echo "open_project $*.xpr" > generate_fallback_bit.tcl
|
||||
echo "open_run impl_1" >> generate_fallback_bit.tcl
|
||||
echo "startgroup" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "endgroup" >> generate_fallback_bit.tcl
|
||||
echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
|
||||
echo "undo" >> generate_fallback_bit.tcl
|
||||
echo "exit" >> generate_fallback_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
|
||||
mkdir -p rev
|
||||
EXT=bit; COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
%_fallback.mcs %_fallback.prm: %_fallback.bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x0C000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
|
||||
echo "exit" >> generate_fallback_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||
|
||||
%_full.mcs %_full.prm: %_fallback.bit %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x0C000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||
echo "exit" >> generate_full_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
|
||||
echo "open_hw" > flash$*.tcl
|
||||
echo "connect_hw_server" >> flash$*.tcl
|
||||
echo "open_hw_target" >> flash$*.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "exit" >> flash$*.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||
155
example/XUPP3R/fpga/fpga_XUSP3S/Makefile
Normal file
155
example/XUPP3R/fpga/fpga_XUSP3S/Makefile
Normal file
@@ -0,0 +1,155 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu095-ffvb2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexu
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = ../rtl/fpga_xusp3s.sv
|
||||
SYN_FILES += ../rtl/fpga_core.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_xusp3s.xdc
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
%_fallback.bit: %.bit
|
||||
echo "open_project $*.xpr" > generate_fallback_bit.tcl
|
||||
echo "open_run impl_1" >> generate_fallback_bit.tcl
|
||||
echo "startgroup" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "endgroup" >> generate_fallback_bit.tcl
|
||||
echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
|
||||
echo "undo" >> generate_fallback_bit.tcl
|
||||
echo "exit" >> generate_fallback_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
|
||||
mkdir -p rev
|
||||
EXT=bit; COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
%_fallback.mcs %_fallback.prm: %_fallback.bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
|
||||
echo "exit" >> generate_fallback_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||
|
||||
%_full.mcs %_full.prm: %_fallback.bit %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||
echo "exit" >> generate_full_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
|
||||
echo "open_hw" > flash$*.tcl
|
||||
echo "connect_hw_server" >> flash$*.tcl
|
||||
echo "open_hw_target" >> flash$*.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "exit" >> flash$*.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||
|
||||
155
example/XUPP3R/fpga/fpga_XUSP3S_10g/Makefile
Normal file
155
example/XUPP3R/fpga/fpga_XUSP3S_10g/Makefile
Normal file
@@ -0,0 +1,155 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu095-ffvb2104-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexu
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = ../rtl/fpga_xusp3s.sv
|
||||
SYN_FILES += ../rtl/fpga_core.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga_xusp3s.xdc
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_phy_25g_us_gty_10g_322.tcl
|
||||
|
||||
# Configuration
|
||||
#CONFIG_TCL_FILES = config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
%_fallback.bit: %.bit
|
||||
echo "open_project $*.xpr" > generate_fallback_bit.tcl
|
||||
echo "open_run impl_1" >> generate_fallback_bit.tcl
|
||||
echo "startgroup" >> generate_fallback_bit.tcl
|
||||
echo "set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]" >> generate_fallback_bit.tcl
|
||||
echo "endgroup" >> generate_fallback_bit.tcl
|
||||
echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl
|
||||
echo "undo" >> generate_fallback_bit.tcl
|
||||
echo "exit" >> generate_fallback_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl
|
||||
mkdir -p rev
|
||||
EXT=bit; COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT";
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
%_fallback.mcs %_fallback.prm: %_fallback.bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x03000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl
|
||||
echo "exit" >> generate_fallback_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done;
|
||||
|
||||
%_full.mcs %_full.prm: %_fallback.bit %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x00000000 $*.bit up 0x03000000 $*_fallback.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl
|
||||
echo "exit" >> generate_full_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_full_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
flash%: $(FPGA_TOP)%.mcs $(FPGA_TOP)%.prm
|
||||
echo "open_hw" > flash$*.tcl
|
||||
echo "connect_hw_server" >> flash$*.tcl
|
||||
echo "open_hw_target" >> flash$*.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]" >> flash$*.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash$*.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash$*.tcl
|
||||
echo "exit" >> flash$*.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash$*.tcl
|
||||
|
||||
994
example/XUPP3R/fpga/fpga_xupp3r.xdc
Normal file
994
example/XUPP3R/fpga/fpga_xupp3r.xdc
Normal file
@@ -0,0 +1,994 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the BittWare XUP-P3R board
|
||||
# part: xcvu9p-flgb2104-2-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
# System clocks
|
||||
# 48 MHz system clock
|
||||
set_property -dict {LOC AV23 IOSTANDARD LVCMOS18} [get_ports clk_48mhz]
|
||||
create_clock -period 20.833 -name clk_48mhz [get_ports clk_48mhz]
|
||||
|
||||
# 322.265625 MHz clock from Si5338 B ch 1
|
||||
#set_property -dict {LOC AY23 IOSTANDARD DIFF_SSTL18_I} [get_ports clk_b1_p]
|
||||
#set_property -dict {LOC BA23 IOSTANDARD DIFF_SSTL18_I} [get_ports clk_b1_n]
|
||||
#create_clock -period 3.103 -name clk_b1 [get_ports clk_b1_p]
|
||||
|
||||
# 322.265625 MHz clock from Si5338 B ch 2
|
||||
#set_property -dict {LOC BB9 IOSTANDARD DIFF_SSTL15_DCI ODT RTT_48} [get_ports clk_b2_p]
|
||||
#set_property -dict {LOC BC9 IOSTANDARD DIFF_SSTL15_DCI ODT RTT_48} [get_ports clk_b2_n]
|
||||
#create_clock -period 3.103 -name clk_b2 [get_ports clk_b2_p]
|
||||
|
||||
# 100 MHz DDR4 module 1 clock from Si5338 A ch 0
|
||||
#set_property -dict {LOC AV18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_p]
|
||||
#set_property -dict {LOC AW18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_n]
|
||||
#create_clock -period 10.000 -name clk_ddr_1 [get_ports clk_ddr_1_p]
|
||||
|
||||
# 100 MHz DDR4 module 2 clock from Si5338 A ch 1
|
||||
#set_property -dict {LOC BB36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_p]
|
||||
#set_property -dict {LOC BC36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_n]
|
||||
#create_clock -period 10.000 -name clk_ddr_2 [get_ports clk_ddr_2_p]
|
||||
|
||||
# 100 MHz DDR4 module 3 clock from Si5338 A ch 2
|
||||
#set_property -dict {LOC E38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_p]
|
||||
#set_property -dict {LOC D38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_n]
|
||||
#create_clock -period 10.000 -name clk_ddr_3 [get_ports clk_ddr_3_p]
|
||||
|
||||
# 100 MHz DDR4 module 4 clock from Si5338 A ch 3
|
||||
#set_property -dict {LOC K18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_p]
|
||||
#set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_n]
|
||||
#create_clock -period 10.000 -name clk_ddr_4 [get_ports clk_ddr_4_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AR22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
|
||||
set_property -dict {LOC AT22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
|
||||
set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
|
||||
set_property -dict {LOC AV22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
|
||||
|
||||
set_false_path -to [get_ports {led[*]}]
|
||||
set_output_delay 0 [get_ports {led[*]}]
|
||||
|
||||
# Timing
|
||||
#set_property -dict {LOC AU22 IOSTANDARD LVCMOS18} [get_ports ext_pps_in] ;# from J1
|
||||
#set_property -dict {LOC AV24 IOSTANDARD LVCMOS18} [get_ports ext_clk_in] ;# from J2
|
||||
|
||||
#create_clock -period 100.000 -name ext_clk_in [get_ports ext_clk_in]
|
||||
|
||||
#set_false_path -from [get_ports {ext_pps_in ext_clk_in}]
|
||||
#set_input_delay 0 [get_ports {ext_pps_in ext_clk_in}]
|
||||
|
||||
# Reset
|
||||
set_property -dict {LOC AT23 IOSTANDARD LVCMOS18} [get_ports sys_rst_l]
|
||||
|
||||
set_false_path -from [get_ports {sys_rst_l}]
|
||||
set_input_delay 0 [get_ports {sys_rst_l}]
|
||||
|
||||
# UART
|
||||
set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
|
||||
set_property -dict {LOC AL24 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
|
||||
|
||||
set_false_path -to [get_ports {uart_txd}]
|
||||
set_output_delay 0 [get_ports {uart_txd}]
|
||||
set_false_path -from [get_ports {uart_rxd}]
|
||||
set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# EEPROM I2C interface
|
||||
set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports eeprom_i2c_scl]
|
||||
set_property -dict {LOC AP23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports eeprom_i2c_sda]
|
||||
|
||||
set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
|
||||
# I2C-related signals
|
||||
set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports fpga_i2c_master_l]
|
||||
set_property -dict {LOC AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_ctl_en]
|
||||
|
||||
set_false_path -to [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
set_output_delay 0 [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC BC45} [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC46} [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF42} [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF43} [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA45} [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA46} [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD42} [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD43} [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW45} [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW46} [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB42} [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB43} [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV43} [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV44} [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW40} [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW41} [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA40} [get_ports qsfp0_mgt_refclk_b0_p] ;# MGTREFCLK0P_120 from Si5338 B ch 0
|
||||
set_property -dict {LOC BA41} [get_ports qsfp0_mgt_refclk_b0_n] ;# MGTREFCLK0N_120 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AY38} [get_ports qsfp0_mgt_refclk_b1_p] ;# MGTREFCLK1P_120 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AY39} [get_ports qsfp0_mgt_refclk_b1_n] ;# MGTREFCLK1N_120 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AU36} [get_ports qsfp0_mgt_refclk_c0_p] ;# MGTREFCLK0P_121 from Si5338 C ch 0
|
||||
#set_property -dict {LOC AU37} [get_ports qsfp0_mgt_refclk_c0_n] ;# MGTREFCLK0N_121 from Si5338 C ch 0
|
||||
#set_property -dict {LOC AV38} [get_ports qsfp0_mgt_refclk_c1_p] ;# MGTREFCLK1P_121 from Si5338 C ch 1
|
||||
#set_property -dict {LOC AV39} [get_ports qsfp0_mgt_refclk_c1_n] ;# MGTREFCLK1N_121 from Si5338 C ch 1
|
||||
set_property -dict {LOC BD24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
|
||||
set_property -dict {LOC BD23 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_modprsl]
|
||||
set_property -dict {LOC BE23 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp0_intl]
|
||||
set_property -dict {LOC BC24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
|
||||
set_property -dict {LOC BF24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_scl]
|
||||
set_property -dict {LOC BF23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_sda]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 0)
|
||||
create_clock -period 3.103 -name qsfp0_mgt_refclk_b0 [get_ports qsfp0_mgt_refclk_b0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 1)
|
||||
#create_clock -period 3.103 -name qsfp0_mgt_refclk_b1 [get_ports qsfp0_mgt_refclk_b1_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 C ch 0)
|
||||
#create_clock -period 3.103 -name qsfp0_mgt_refclk_c0 [get_ports qsfp0_mgt_refclk_c0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 C ch 1)
|
||||
#create_clock -period 3.103 -name qsfp0_mgt_refclk_c1 [get_ports qsfp0_mgt_refclk_c1_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AN45} [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN46} [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN40} [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN41} [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM43} [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM44} [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM38} [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM39} [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL45} [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL46} [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL40} [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL41} [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK44} [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK38} [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK39} [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AR36} [get_ports qsfp1_mgt_refclk_b0_p] ;# MGTREFCLK0P_122 from Si5338 B ch 0
|
||||
set_property -dict {LOC AR37} [get_ports qsfp1_mgt_refclk_b0_n] ;# MGTREFCLK0N_122 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AN36} [get_ports qsfp1_mgt_refclk_b1_p] ;# MGTREFCLK1P_122 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AN37} [get_ports qsfp1_mgt_refclk_b1_n] ;# MGTREFCLK1N_122 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AL36} [get_ports qsfp1_mgt_refclk_c2_p] ;# MGTREFCLK0P_123 from Si5338 C ch 2
|
||||
#set_property -dict {LOC AL37} [get_ports qsfp1_mgt_refclk_c2_n] ;# MGTREFCLK0N_123 from Si5338 C ch 2
|
||||
#set_property -dict {LOC AJ36} [get_ports qsfp1_mgt_refclk_c3_p] ;# MGTREFCLK1P_123 from Si5338 C ch 3
|
||||
#set_property -dict {LOC AJ37} [get_ports qsfp1_mgt_refclk_c3_n] ;# MGTREFCLK1N_123 from Si5338 C ch 3
|
||||
set_property -dict {LOC BE20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
|
||||
set_property -dict {LOC BD21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl]
|
||||
set_property -dict {LOC BE21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl]
|
||||
set_property -dict {LOC BD20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
|
||||
set_property -dict {LOC BE22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_scl]
|
||||
set_property -dict {LOC BF22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_sda]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 0)
|
||||
create_clock -period 3.103 -name qsfp1_mgt_refclk_b0 [get_ports qsfp1_mgt_refclk_b0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 1)
|
||||
#create_clock -period 3.103 -name qsfp1_mgt_refclk_b1 [get_ports qsfp1_mgt_refclk_b1_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 C ch 2)
|
||||
#create_clock -period 3.103 -name qsfp1_mgt_refclk_c2 [get_ports qsfp1_mgt_refclk_c2_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 C ch 3)
|
||||
#create_clock -period 3.103 -name qsfp1_mgt_refclk_c3 [get_ports qsfp1_mgt_refclk_c3_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AA45} [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AC36} [get_ports qsfp2_mgt_refclk_b0_p] ;# MGTREFCLK0P_125 from Si5338 B ch 0
|
||||
set_property -dict {LOC AC37} [get_ports qsfp2_mgt_refclk_b0_n] ;# MGTREFCLK0N_125 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AA36} [get_ports qsfp2_mgt_refclk_b2_p] ;# MGTREFCLK1P_125 from Si5338 B ch 2
|
||||
#set_property -dict {LOC AA37} [get_ports qsfp2_mgt_refclk_b2_n] ;# MGTREFCLK1N_125 from Si5338 B ch 2
|
||||
#set_property -dict {LOC W36 } [get_ports qsfp2_mgt_refclk_d0_p] ;# MGTREFCLK0P_126 from Si5338 D ch 0
|
||||
#set_property -dict {LOC W37 } [get_ports qsfp2_mgt_refclk_d0_n] ;# MGTREFCLK0N_126 from Si5338 D ch 0
|
||||
#set_property -dict {LOC U36 } [get_ports qsfp2_mgt_refclk_d1_p] ;# MGTREFCLK1P_126 from Si5338 D ch 1
|
||||
#set_property -dict {LOC U37 } [get_ports qsfp2_mgt_refclk_d1_n] ;# MGTREFCLK1N_126 from Si5338 D ch 1
|
||||
set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_resetl]
|
||||
set_property -dict {LOC BB20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_modprsl]
|
||||
set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_intl]
|
||||
set_property -dict {LOC BC21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode]
|
||||
set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp2_i2c_scl]
|
||||
set_property -dict {LOC BA20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp2_i2c_sda]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 0)
|
||||
create_clock -period 3.103 -name qsfp2_mgt_refclk_b0 [get_ports qsfp2_mgt_refclk_b0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 2)
|
||||
#create_clock -period 3.103 -name qsfp2_mgt_refclk_b2 [get_ports qsfp2_mgt_refclk_b2_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 D ch 0)
|
||||
#create_clock -period 3.103 -name qsfp2_mgt_refclk_d0 [get_ports qsfp2_mgt_refclk_d0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 D ch 1)
|
||||
#create_clock -period 3.103 -name qsfp2_mgt_refclk_d1 [get_ports qsfp2_mgt_refclk_d1_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp2_resetl qsfp2_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp2_resetl qsfp2_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp2_modprsl qsfp2_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp2_modprsl qsfp2_intl}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_output_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC N45 } [get_ports {qsfp3_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports {qsfp3_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports {qsfp3_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports {qsfp3_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports {qsfp3_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports {qsfp3_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports {qsfp3_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp3_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp3_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports {qsfp3_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports {qsfp3_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp3_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports {qsfp3_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports {qsfp3_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports {qsfp3_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp3_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC R36 } [get_ports qsfp3_mgt_refclk_b0_p] ;# MGTREFCLK0P_127 from Si5338 B ch 0
|
||||
set_property -dict {LOC R37 } [get_ports qsfp3_mgt_refclk_b0_n] ;# MGTREFCLK0N_127 from Si5338 B ch 0
|
||||
#set_property -dict {LOC N36 } [get_ports qsfp3_mgt_refclk_b3_p] ;# MGTREFCLK1P_127 from Si5338 B ch 3
|
||||
#set_property -dict {LOC N37 } [get_ports qsfp3_mgt_refclk_b3_n] ;# MGTREFCLK1N_127 from Si5338 B ch 3
|
||||
#set_property -dict {LOC L36 } [get_ports qsfp3_mgt_refclk_d2_p] ;# MGTREFCLK0P_128 from Si5338 D ch 2
|
||||
#set_property -dict {LOC L37 } [get_ports qsfp3_mgt_refclk_d2_n] ;# MGTREFCLK0N_128 from Si5338 D ch 2
|
||||
#set_property -dict {LOC K38 } [get_ports qsfp3_mgt_refclk_d3_p] ;# MGTREFCLK1P_128 from Si5338 D ch 3
|
||||
#set_property -dict {LOC K39 } [get_ports qsfp3_mgt_refclk_d3_n] ;# MGTREFCLK1N_128 from Si5338 D ch 3
|
||||
set_property -dict {LOC BC23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp3_resetl]
|
||||
set_property -dict {LOC BB24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp3_modprsl]
|
||||
set_property -dict {LOC AY22 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp3_intl]
|
||||
set_property -dict {LOC BA22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp3_lpmode]
|
||||
set_property -dict {LOC BC22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp3_i2c_scl]
|
||||
set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp3_i2c_sda]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 0)
|
||||
create_clock -period 3.103 -name qsfp3_mgt_refclk_b0 [get_ports qsfp3_mgt_refclk_b0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 2)
|
||||
#create_clock -period 3.103 -name qsfp3_mgt_refclk_b3 [get_ports qsfp3_mgt_refclk_b3_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 D ch 2)
|
||||
#create_clock -period 3.103 -name qsfp3_mgt_refclk_d2 [get_ports qsfp3_mgt_refclk_d2_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 D ch 3)
|
||||
#create_clock -period 3.103 -name qsfp3_mgt_refclk_d3 [get_ports qsfp3_mgt_refclk_d3_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp3_resetl qsfp3_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp3_resetl qsfp3_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp3_modprsl qsfp3_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp3_modprsl qsfp3_intl}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}]
|
||||
set_output_delay 0 [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AT11 } [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_225
|
||||
#set_property -dict {LOC AT10 } [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_225
|
||||
#set_property -dict {LOC AM11 } [get_ports pcie_refclk_b1_p] ;# MGTREFCLK0P_226 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AM10 } [get_ports pcie_refclk_b1_n] ;# MGTREFCLK0N_226 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AH11 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227
|
||||
#set_property -dict {LOC AH10 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227
|
||||
#set_property -dict {LOC AR26 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
#set_property -dict {LOC AT18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
#set_property -dict {LOC AU17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
#set_property -dict {LOC AP18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
#set_property -dict {LOC AR18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
#set_property -dict {LOC AP20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
#set_property -dict {LOC AR20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
#set_property -dict {LOC AU21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
#set_property -dict {LOC AN18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
#set_property -dict {LOC AN17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
#set_property -dict {LOC AN19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
#set_property -dict {LOC AP19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
#set_property -dict {LOC AM16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
#set_property -dict {LOC AN16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
#set_property -dict {LOC AL19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
#set_property -dict {LOC AM19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
#set_property -dict {LOC AL20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
#set_property -dict {LOC AM20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
#set_property -dict {LOC AP16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}]
|
||||
#set_property -dict {LOC AT19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
#set_property -dict {LOC AU19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
#set_property -dict {LOC AT20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
#set_property -dict {LOC AU20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
#set_property -dict {LOC AR17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t[0]}]
|
||||
#set_property -dict {LOC AT17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c[0]}]
|
||||
#set_property -dict {LOC AY20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}]
|
||||
#set_property -dict {LOC AV21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}]
|
||||
#set_property -dict {LOC BA18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}]
|
||||
#set_property -dict {LOC AW20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}]
|
||||
#set_property -dict {LOC BA17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}]
|
||||
#set_property -dict {LOC AY18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}]
|
||||
#set_property -dict {LOC AM17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}]
|
||||
#set_property -dict {LOC AU25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}]
|
||||
#set_property -dict {LOC AT14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}]
|
||||
#set_property -dict {LOC AV17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
#set_property -dict {LOC AW21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}]
|
||||
#set_property -dict {LOC AV19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
#set_property -dict {LOC AY17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
#set_property -dict {LOC AL28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
#set_property -dict {LOC AL27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
#set_property -dict {LOC AM25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
#set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
#set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
#set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
#set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
#set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
#set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
#set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
#set_property -dict {LOC AU26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
#set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
#set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
#set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
#set_property -dict {LOC AY26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
#set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
#set_property -dict {LOC BB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
#set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
#set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
#set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
#set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
#set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
#set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
#set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
#set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
#set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
#set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
#set_property -dict {LOC AW15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
#set_property -dict {LOC AW16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
#set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
#set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
#set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
#set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
#set_property -dict {LOC AY15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
#set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
#set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
#set_property -dict {LOC AY12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
#set_property -dict {LOC BC13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
#set_property -dict {LOC BC14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
#set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
#set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
#set_property -dict {LOC BE16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
#set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
#set_property -dict {LOC BF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
#set_property -dict {LOC BE15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
#set_property -dict {LOC BC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
#set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
#set_property -dict {LOC BC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
#set_property -dict {LOC BE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
#set_property -dict {LOC BD18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
#set_property -dict {LOC BF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
#set_property -dict {LOC BF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
#set_property -dict {LOC AM26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
#set_property -dict {LOC AN26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
#set_property -dict {LOC AP25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
#set_property -dict {LOC AP26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
#set_property -dict {LOC AR25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
#set_property -dict {LOC AT25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
#set_property -dict {LOC AV26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
#set_property -dict {LOC AW26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
#set_property -dict {LOC AW25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
#set_property -dict {LOC AY25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
#set_property -dict {LOC BA25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
#set_property -dict {LOC BB25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
#set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
#set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
#set_property -dict {LOC BF28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
#set_property -dict {LOC BF29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
#set_property -dict {LOC AP13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
#set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
#set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
#set_property -dict {LOC AR15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
#set_property -dict {LOC AU14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
#set_property -dict {LOC AV14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
#set_property -dict {LOC AW14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
#set_property -dict {LOC AW13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
#set_property -dict {LOC BB15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
#set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
#set_property -dict {LOC BA12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
#set_property -dict {LOC BB12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
#set_property -dict {LOC BD13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
#set_property -dict {LOC BE13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
#set_property -dict {LOC BF14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
#set_property -dict {LOC BF13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
#set_property -dict {LOC BC19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
#set_property -dict {LOC BD19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
#set_property -dict {LOC BE17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
#set_property -dict {LOC BF17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
#set_property -dict {LOC AY33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
#set_property -dict {LOC BA33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
#set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
#set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
#set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
#set_property -dict {LOC AW33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
#set_property -dict {LOC AU34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
#set_property -dict {LOC AT33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
#set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
#set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
#set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
#set_property -dict {LOC AL32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
#set_property -dict {LOC AM32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
#set_property -dict {LOC AL34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
#set_property -dict {LOC AL33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}]
|
||||
#set_property -dict {LOC BA34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
#set_property -dict {LOC BB34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
#set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
#set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
#set_property -dict {LOC AW35 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t[0]}]
|
||||
#set_property -dict {LOC AW36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c[0]}]
|
||||
#set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}]
|
||||
#set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}]
|
||||
#set_property -dict {LOC BE35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}]
|
||||
#set_property -dict {LOC BD36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}]
|
||||
#set_property -dict {LOC BD34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}]
|
||||
#set_property -dict {LOC BD35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}]
|
||||
#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}]
|
||||
#set_property -dict {LOC AD30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}]
|
||||
#set_property -dict {LOC AT32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}]
|
||||
#set_property -dict {LOC BF35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
#set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}]
|
||||
#set_property -dict {LOC BA35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}]
|
||||
#set_property -dict {LOC BB35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
#set_property -dict {LOC BC34 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
#set_property -dict {LOC W34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
#set_property -dict {LOC W33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
#set_property -dict {LOC Y33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
#set_property -dict {LOC Y32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
#set_property -dict {LOC Y30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
#set_property -dict {LOC W30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
#set_property -dict {LOC AB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
#set_property -dict {LOC AA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
#set_property -dict {LOC AD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
#set_property -dict {LOC AC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
#set_property -dict {LOC AC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
#set_property -dict {LOC AC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
#set_property -dict {LOC AF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
#set_property -dict {LOC AE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
#set_property -dict {LOC AE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
#set_property -dict {LOC AD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
#set_property -dict {LOC AF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
#set_property -dict {LOC AF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
#set_property -dict {LOC AG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
#set_property -dict {LOC AG31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
#set_property -dict {LOC AG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
#set_property -dict {LOC AF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
#set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
#set_property -dict {LOC AH33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
#set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
#set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
#set_property -dict {LOC AG30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
#set_property -dict {LOC AG29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
#set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
#set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
#set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
#set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
#set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
#set_property -dict {LOC AM31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
#set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
#set_property -dict {LOC AU30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
#set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
#set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
#set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
#set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
#set_property -dict {LOC BB30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
#set_property -dict {LOC BD29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
#set_property -dict {LOC BC29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
#set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
#set_property -dict {LOC BE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
#set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
#set_property -dict {LOC BF38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
#set_property -dict {LOC W31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
#set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
#set_property -dict {LOC AA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
#set_property -dict {LOC AA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
#set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
#set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
#set_property -dict {LOC AE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
#set_property -dict {LOC AE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
#set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
#set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
#set_property -dict {LOC AH34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
#set_property -dict {LOC AJ34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
#set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
#set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
#set_property -dict {LOC AJ27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
#set_property -dict {LOC AK27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
#set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
#set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
#set_property -dict {LOC AR31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
#set_property -dict {LOC AW29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
#set_property -dict {LOC AW30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
#set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
#set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
#set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
#set_property -dict {LOC BC32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
#set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
#set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
#set_property -dict {LOC BF32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
#set_property -dict {LOC BF33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
#set_property -dict {LOC BD40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
#set_property -dict {LOC BE40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
#set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
|
||||
# DDR4 C2
|
||||
#set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||
#set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||
#set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||
#set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||
#set_property -dict {LOC E35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||
#set_property -dict {LOC D35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||
#set_property -dict {LOC E37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||
#set_property -dict {LOC B34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||
#set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||
#set_property -dict {LOC D34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||
#set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||
#set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||
#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||
#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||
#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||
#set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||
#set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||
#set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[17]}]
|
||||
#set_property -dict {LOC C36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||
#set_property -dict {LOC C37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||
#set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||
#set_property -dict {LOC D36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}]
|
||||
#set_property -dict {LOC B36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c2_ck_t[0]}]
|
||||
#set_property -dict {LOC B37 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c2_ck_c[0]}]
|
||||
#set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}]
|
||||
#set_property -dict {LOC B39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}]
|
||||
#set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}]
|
||||
#set_property -dict {LOC B40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}]
|
||||
#set_property -dict {LOC D40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}]
|
||||
#set_property -dict {LOC E39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}]
|
||||
#set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_c[0]}]
|
||||
#set_property -dict {LOC K34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_c[1]}]
|
||||
#set_property -dict {LOC E26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_c[2]}]
|
||||
#set_property -dict {LOC F38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||
#set_property -dict {LOC A39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}]
|
||||
#set_property -dict {LOC C38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}]
|
||||
#set_property -dict {LOC C39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||
#set_property -dict {LOC E40 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c2_reset_n}]
|
||||
|
||||
#set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}]
|
||||
#set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}]
|
||||
#set_property -dict {LOC E32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}]
|
||||
#set_property -dict {LOC F32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}]
|
||||
#set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}]
|
||||
#set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}]
|
||||
#set_property -dict {LOC G31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}]
|
||||
#set_property -dict {LOC H31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}]
|
||||
#set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}]
|
||||
#set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}]
|
||||
#set_property -dict {LOC J31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}]
|
||||
#set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}]
|
||||
#set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}]
|
||||
#set_property -dict {LOC M30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}]
|
||||
#set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}]
|
||||
#set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}]
|
||||
#set_property -dict {LOC N33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}]
|
||||
#set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}]
|
||||
#set_property -dict {LOC N31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}]
|
||||
#set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}]
|
||||
#set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}]
|
||||
#set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}]
|
||||
#set_property -dict {LOC R32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}]
|
||||
#set_property -dict {LOC R31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}]
|
||||
#set_property -dict {LOC T30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}]
|
||||
#set_property -dict {LOC U30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}]
|
||||
#set_property -dict {LOC U31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}]
|
||||
#set_property -dict {LOC V31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}]
|
||||
#set_property -dict {LOC T32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}]
|
||||
#set_property -dict {LOC U32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}]
|
||||
#set_property -dict {LOC R33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}]
|
||||
#set_property -dict {LOC T33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}]
|
||||
#set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}]
|
||||
#set_property -dict {LOC B30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}]
|
||||
#set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}]
|
||||
#set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}]
|
||||
#set_property -dict {LOC D30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}]
|
||||
#set_property -dict {LOC E30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}]
|
||||
#set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}]
|
||||
#set_property -dict {LOC D29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}]
|
||||
#set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}]
|
||||
#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}]
|
||||
#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}]
|
||||
#set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}]
|
||||
#set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}]
|
||||
#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}]
|
||||
#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}]
|
||||
#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}]
|
||||
#set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}]
|
||||
#set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}]
|
||||
#set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}]
|
||||
#set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}]
|
||||
#set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}]
|
||||
#set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}]
|
||||
#set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}]
|
||||
#set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}]
|
||||
#set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}]
|
||||
#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}]
|
||||
#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}]
|
||||
#set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}]
|
||||
#set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}]
|
||||
#set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}]
|
||||
#set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}]
|
||||
#set_property -dict {LOC T27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}]
|
||||
#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}]
|
||||
#set_property -dict {LOC F34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}]
|
||||
#set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}]
|
||||
#set_property -dict {LOC H34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}]
|
||||
#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}]
|
||||
#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}]
|
||||
#set_property -dict {LOC F37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}]
|
||||
#set_property -dict {LOC G37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}]
|
||||
#set_property -dict {LOC J33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}]
|
||||
#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}]
|
||||
#set_property -dict {LOC G30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}]
|
||||
#set_property -dict {LOC F30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}]
|
||||
#set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}]
|
||||
#set_property -dict {LOC J30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}]
|
||||
#set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}]
|
||||
#set_property -dict {LOC M32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}]
|
||||
#set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}]
|
||||
#set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}]
|
||||
#set_property -dict {LOC R30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}]
|
||||
#set_property -dict {LOC P30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}]
|
||||
#set_property -dict {LOC V32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}]
|
||||
#set_property -dict {LOC V33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}]
|
||||
#set_property -dict {LOC U34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}]
|
||||
#set_property -dict {LOC T34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}]
|
||||
#set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}]
|
||||
#set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}]
|
||||
#set_property -dict {LOC C27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}]
|
||||
#set_property -dict {LOC B27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}]
|
||||
#set_property -dict {LOC F28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}]
|
||||
#set_property -dict {LOC F29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}]
|
||||
#set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}]
|
||||
#set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}]
|
||||
#set_property -dict {LOC K26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}]
|
||||
#set_property -dict {LOC K27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}]
|
||||
#set_property -dict {LOC M29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}]
|
||||
#set_property -dict {LOC L29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}]
|
||||
#set_property -dict {LOC P29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}]
|
||||
#set_property -dict {LOC N29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}]
|
||||
#set_property -dict {LOC T28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}]
|
||||
#set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}]
|
||||
#set_property -dict {LOC H36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}]
|
||||
#set_property -dict {LOC G36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}]
|
||||
#set_property -dict {LOC H37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}]
|
||||
#set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}]
|
||||
|
||||
# DDR4 C3
|
||||
#set_property -dict {LOC F20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}]
|
||||
#set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}]
|
||||
#set_property -dict {LOC E21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}]
|
||||
#set_property -dict {LOC E20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}]
|
||||
#set_property -dict {LOC F18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}]
|
||||
#set_property -dict {LOC F17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}]
|
||||
#set_property -dict {LOC G21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}]
|
||||
#set_property -dict {LOC D19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}]
|
||||
#set_property -dict {LOC C19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}]
|
||||
#set_property -dict {LOC D21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}]
|
||||
#set_property -dict {LOC D20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}]
|
||||
#set_property -dict {LOC C21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}]
|
||||
#set_property -dict {LOC B21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}]
|
||||
#set_property -dict {LOC B19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}]
|
||||
#set_property -dict {LOC A19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}]
|
||||
#set_property -dict {LOC B20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}]
|
||||
#set_property -dict {LOC A20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}]
|
||||
#set_property -dict {LOC A18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[17]}]
|
||||
#set_property -dict {LOC H19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}]
|
||||
#set_property -dict {LOC H18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}]
|
||||
#set_property -dict {LOC G20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}]
|
||||
#set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}]
|
||||
#set_property -dict {LOC E18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c3_ck_t[0]}]
|
||||
#set_property -dict {LOC E17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c3_ck_c[0]}]
|
||||
#set_property -dict {LOC K20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}]
|
||||
#set_property -dict {LOC J21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}]
|
||||
#set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}]
|
||||
#set_property -dict {LOC L20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}]
|
||||
#set_property -dict {LOC K17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}]
|
||||
#set_property -dict {LOC L19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}]
|
||||
#set_property -dict {LOC C18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_c[0]}]
|
||||
#set_property -dict {LOC F25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_c[1]}]
|
||||
#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_c[2]}]
|
||||
#set_property -dict {LOC K21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}]
|
||||
#set_property -dict {LOC H21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}]
|
||||
#set_property -dict {LOC J20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}]
|
||||
#set_property -dict {LOC J19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}]
|
||||
#set_property -dict {LOC L17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c3_reset_n}]
|
||||
|
||||
#set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}]
|
||||
#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}]
|
||||
#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}]
|
||||
#set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}]
|
||||
#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}]
|
||||
#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}]
|
||||
#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}]
|
||||
#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}]
|
||||
#set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}]
|
||||
#set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}]
|
||||
#set_property -dict {LOC D23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}]
|
||||
#set_property -dict {LOC D24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}]
|
||||
#set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}]
|
||||
#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}]
|
||||
#set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}]
|
||||
#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}]
|
||||
#set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}]
|
||||
#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}]
|
||||
#set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}]
|
||||
#set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}]
|
||||
#set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}]
|
||||
#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}]
|
||||
#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}]
|
||||
#set_property -dict {LOC L22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}]
|
||||
#set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}]
|
||||
#set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}]
|
||||
#set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}]
|
||||
#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}]
|
||||
#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}]
|
||||
#set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}]
|
||||
#set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}]
|
||||
#set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}]
|
||||
#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}]
|
||||
#set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}]
|
||||
#set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}]
|
||||
#set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}]
|
||||
#set_property -dict {LOC A13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}]
|
||||
#set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}]
|
||||
#set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}]
|
||||
#set_property -dict {LOC C14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}]
|
||||
#set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}]
|
||||
#set_property -dict {LOC E13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}]
|
||||
#set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}]
|
||||
#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}]
|
||||
#set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}]
|
||||
#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}]
|
||||
#set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}]
|
||||
#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}]
|
||||
#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}]
|
||||
#set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}]
|
||||
#set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}]
|
||||
#set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}]
|
||||
#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}]
|
||||
#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}]
|
||||
#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}]
|
||||
#set_property -dict {LOC L14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}]
|
||||
#set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}]
|
||||
#set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}]
|
||||
#set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}]
|
||||
#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}]
|
||||
#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}]
|
||||
#set_property -dict {LOC N21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}]
|
||||
#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}]
|
||||
#set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}]
|
||||
#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}]
|
||||
#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}]
|
||||
#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}]
|
||||
#set_property -dict {LOC P18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}]
|
||||
#set_property -dict {LOC A23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}]
|
||||
#set_property -dict {LOC A22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}]
|
||||
#set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}]
|
||||
#set_property -dict {LOC B22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}]
|
||||
#set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}]
|
||||
#set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}]
|
||||
#set_property -dict {LOC G25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}]
|
||||
#set_property -dict {LOC G24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}]
|
||||
#set_property -dict {LOC K25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}]
|
||||
#set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}]
|
||||
#set_property -dict {LOC L25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}]
|
||||
#set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}]
|
||||
#set_property -dict {LOC P24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}]
|
||||
#set_property -dict {LOC N24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}]
|
||||
#set_property -dict {LOC R21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}]
|
||||
#set_property -dict {LOC P21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}]
|
||||
#set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}]
|
||||
#set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}]
|
||||
#set_property -dict {LOC D13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}]
|
||||
#set_property -dict {LOC C13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}]
|
||||
#set_property -dict {LOC G17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}]
|
||||
#set_property -dict {LOC G16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}]
|
||||
#set_property -dict {LOC G14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}]
|
||||
#set_property -dict {LOC F14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}]
|
||||
#set_property -dict {LOC H17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}]
|
||||
#set_property -dict {LOC H16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}]
|
||||
#set_property -dict {LOC L13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}]
|
||||
#set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}]
|
||||
#set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}]
|
||||
#set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}]
|
||||
#set_property -dict {LOC P13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}]
|
||||
#set_property -dict {LOC N13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}]
|
||||
#set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}]
|
||||
#set_property -dict {LOC N19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}]
|
||||
#set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}]
|
||||
#set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}]
|
||||
902
example/XUPP3R/fpga/fpga_xusp3s.xdc
Normal file
902
example/XUPP3R/fpga/fpga_xusp3s.xdc
Normal file
@@ -0,0 +1,902 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# XDC constraints for the BittWare XUSP3S board
|
||||
# part: xcvu095-ffvb2104-2-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 90 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
# System clocks
|
||||
# 48 MHz system clock
|
||||
set_property -dict {LOC AV23 IOSTANDARD LVCMOS33} [get_ports clk_48mhz]
|
||||
create_clock -period 20.833 -name clk_48mhz [get_ports clk_48mhz]
|
||||
|
||||
# 322.265625 MHz clock from Si5338 B ch 1
|
||||
#set_property -dict {LOC AY23 IOSTANDARD LVPECL} [get_ports clk_b1_p]
|
||||
#set_property -dict {LOC BA23 IOSTANDARD LVPECL} [get_ports clk_b1_n]
|
||||
#create_clock -period 3.103 -name clk_b1 [get_ports clk_b1_p]
|
||||
|
||||
# 322.265625 MHz clock from Si5338 B ch 2
|
||||
#set_property -dict {LOC BB9 IOSTANDARD DIFF_SSTL15_DCI ODT RTT_48} [get_ports clk_b2_p]
|
||||
#set_property -dict {LOC BC9 IOSTANDARD DIFF_SSTL15_DCI ODT RTT_48} [get_ports clk_b2_n]
|
||||
#create_clock -period 3.103 -name clk_b2 [get_ports clk_b2_p]
|
||||
|
||||
# 100 MHz DDR4 SODIMM 1 clock from Si5338 A ch 0
|
||||
#set_property -dict {LOC AV18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_sodimm1_p]
|
||||
#set_property -dict {LOC AW18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_sodimm1_n]
|
||||
#create_clock -period 10.000 -name clk_ddr_sodimm1 [get_ports clk_ddr_sodimm1_p]
|
||||
|
||||
# 100 MHz DDR4 A clock from Si5338 A ch 1
|
||||
#set_property -dict {LOC BB36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_a_p]
|
||||
#set_property -dict {LOC BC36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_a_n]
|
||||
#create_clock -period 10.000 -name clk_ddr_a [get_ports clk_ddr_a_p]
|
||||
|
||||
# 100 MHz DDR4 B clock from Si5338 A ch 2
|
||||
#set_property -dict {LOC E38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_b_p]
|
||||
#set_property -dict {LOC D38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_b_n]
|
||||
#create_clock -period 10.000 -name clk_ddr_b [get_ports clk_ddr_b_p]
|
||||
|
||||
# 100 MHz DDR4 SODIMM 2 clock from Si5338 A ch 3
|
||||
#set_property -dict {LOC K18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_sodimm2_p]
|
||||
#set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_sodimm2_n]
|
||||
#create_clock -period 10.000 -name clk_ddr_sodimm2 [get_ports clk_ddr_sodimm2_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AR22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
|
||||
set_property -dict {LOC AT22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
|
||||
set_property -dict {LOC AR23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
|
||||
set_property -dict {LOC AV22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
|
||||
|
||||
set_false_path -to [get_ports {led[*]}]
|
||||
set_output_delay 0 [get_ports {led[*]}]
|
||||
|
||||
# Timing
|
||||
#set_property -dict {LOC AU22 IOSTANDARD LVCMOS33} [get_ports ext_pps_in] ;# from J1
|
||||
#set_property -dict {LOC AV24 IOSTANDARD LVCMOS33} [get_ports ext_clk_in] ;# from J2
|
||||
|
||||
#create_clock -period 100.000 -name ext_clk_in [get_ports ext_clk_in]
|
||||
|
||||
#set_false_path -from [get_ports {ext_pps_in ext_clk_in}]
|
||||
#set_input_delay 0 [get_ports {ext_pps_in ext_clk_in}]
|
||||
|
||||
# Reset
|
||||
set_property -dict {LOC AT23 IOSTANDARD LVCMOS33} [get_ports sys_rst_l]
|
||||
|
||||
set_false_path -from [get_ports {sys_rst_l}]
|
||||
set_input_delay 0 [get_ports {sys_rst_l}]
|
||||
|
||||
# UART
|
||||
set_property -dict {LOC AM24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports uart_txd]
|
||||
set_property -dict {LOC AL24 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
|
||||
|
||||
set_false_path -to [get_ports {uart_txd}]
|
||||
set_output_delay 0 [get_ports {uart_txd}]
|
||||
set_false_path -from [get_ports {uart_rxd}]
|
||||
set_input_delay 0 [get_ports {uart_rxd}]
|
||||
|
||||
# EEPROM I2C interface
|
||||
set_property -dict {LOC AN24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports eeprom_i2c_scl]
|
||||
set_property -dict {LOC AP23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports eeprom_i2c_sda]
|
||||
|
||||
set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
|
||||
# I2C-related signals
|
||||
set_property -dict {LOC AT24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports fpga_i2c_master_l]
|
||||
set_property -dict {LOC AN23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_ctl_en]
|
||||
|
||||
set_false_path -to [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
set_output_delay 0 [get_ports {fpga_i2c_master_l qsfp_ctl_en}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC BC45} [get_ports {qsfp0_rx_p[0]}] ;# MGTHRXP0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BC46} [get_ports {qsfp0_rx_n[0]}] ;# MGTHRXN0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF42} [get_ports {qsfp0_tx_p[0]}] ;# MGTHTXP0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BF43} [get_ports {qsfp0_tx_n[0]}] ;# MGTHTXN0_124 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA45} [get_ports {qsfp0_rx_p[1]}] ;# MGTHRXP1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA46} [get_ports {qsfp0_rx_n[1]}] ;# MGTHRXN1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD42} [get_ports {qsfp0_tx_p[1]}] ;# MGTHTXP1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BD43} [get_ports {qsfp0_tx_n[1]}] ;# MGTHTXN1_124 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW45} [get_ports {qsfp0_rx_p[2]}] ;# MGTHRXP2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW46} [get_ports {qsfp0_rx_n[2]}] ;# MGTHRXN2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB42} [get_ports {qsfp0_tx_p[2]}] ;# MGTHTXP2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BB43} [get_ports {qsfp0_tx_n[2]}] ;# MGTHTXN2_124 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV43} [get_ports {qsfp0_rx_p[3]}] ;# MGTHRXP3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AV44} [get_ports {qsfp0_rx_n[3]}] ;# MGTHRXN3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW40} [get_ports {qsfp0_tx_p[3]}] ;# MGTHTXP3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AW41} [get_ports {qsfp0_tx_n[3]}] ;# MGTHTXN3_124 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC BA40} [get_ports qsfp0_mgt_refclk_b0_p] ;# MGTREFCLK0P_124 from Si5338 B ch 0
|
||||
set_property -dict {LOC BA41} [get_ports qsfp0_mgt_refclk_b0_n] ;# MGTREFCLK0N_124 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AY38} [get_ports qsfp0_mgt_refclk_b1_p] ;# MGTREFCLK1P_124 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AY39} [get_ports qsfp0_mgt_refclk_b1_n] ;# MGTREFCLK1N_124 from Si5338 B ch 1
|
||||
set_property -dict {LOC BD24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
|
||||
set_property -dict {LOC BD23 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp0_modprsl]
|
||||
set_property -dict {LOC BE23 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp0_intl]
|
||||
set_property -dict {LOC BC24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
|
||||
set_property -dict {LOC BF24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_scl]
|
||||
set_property -dict {LOC BF23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp0_i2c_sda]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 0)
|
||||
create_clock -period 3.103 -name qsfp0_mgt_refclk_b0 [get_ports qsfp0_mgt_refclk_b0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 1)
|
||||
#create_clock -period 3.103 -name qsfp0_mgt_refclk_b1 [get_ports qsfp0_mgt_refclk_b1_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_output_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp0_i2c_scl qsfp0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AN45} [get_ports {qsfp1_rx_p[0]}] ;# MGTHRXP0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN46} [get_ports {qsfp1_rx_n[0]}] ;# MGTHRXN0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN40} [get_ports {qsfp1_tx_p[0]}] ;# MGTHTXP0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AN41} [get_ports {qsfp1_tx_n[0]}] ;# MGTHTXN0_126 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM43} [get_ports {qsfp1_rx_p[1]}] ;# MGTHRXP1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM44} [get_ports {qsfp1_rx_n[1]}] ;# MGTHRXN1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM38} [get_ports {qsfp1_tx_p[1]}] ;# MGTHTXP1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AM39} [get_ports {qsfp1_tx_n[1]}] ;# MGTHTXN1_126 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL45} [get_ports {qsfp1_rx_p[2]}] ;# MGTHRXP2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL46} [get_ports {qsfp1_rx_n[2]}] ;# MGTHRXN2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL40} [get_ports {qsfp1_tx_p[2]}] ;# MGTHTXP2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AL41} [get_ports {qsfp1_tx_n[2]}] ;# MGTHTXN2_126 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK43} [get_ports {qsfp1_rx_p[3]}] ;# MGTHRXP3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK44} [get_ports {qsfp1_rx_n[3]}] ;# MGTHRXN3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK38} [get_ports {qsfp1_tx_p[3]}] ;# MGTHTXP3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AK39} [get_ports {qsfp1_tx_n[3]}] ;# MGTHTXN3_126 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AR36} [get_ports qsfp1_mgt_refclk_b0_p] ;# MGTREFCLK0P_126 from Si5338 B ch 0
|
||||
set_property -dict {LOC AR37} [get_ports qsfp1_mgt_refclk_b0_n] ;# MGTREFCLK0N_126 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AN36} [get_ports qsfp1_mgt_refclk_b1_p] ;# MGTREFCLK1P_126 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AN37} [get_ports qsfp1_mgt_refclk_b1_n] ;# MGTREFCLK1N_126 from Si5338 B ch 1
|
||||
set_property -dict {LOC BE20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
|
||||
set_property -dict {LOC BD21 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp1_modprsl]
|
||||
set_property -dict {LOC BE21 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp1_intl]
|
||||
set_property -dict {LOC BD20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
|
||||
set_property -dict {LOC BE22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_scl]
|
||||
set_property -dict {LOC BF22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp1_i2c_sda]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 0)
|
||||
create_clock -period 3.103 -name qsfp1_mgt_refclk_b0 [get_ports qsfp1_mgt_refclk_b0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 1)
|
||||
#create_clock -period 3.103 -name qsfp1_mgt_refclk_b1 [get_ports qsfp1_mgt_refclk_b1_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_output_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp1_i2c_scl qsfp1_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC AA45} [get_ports {qsfp2_rx_p[0]}] ;# MGTHRXP0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA46} [get_ports {qsfp2_rx_n[0]}] ;# MGTHRXN0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA40} [get_ports {qsfp2_tx_p[0]}] ;# MGTHTXP0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AA41} [get_ports {qsfp2_tx_n[0]}] ;# MGTHTXN0_129 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y43 } [get_ports {qsfp2_rx_p[1]}] ;# MGTHRXP1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y44 } [get_ports {qsfp2_rx_n[1]}] ;# MGTHRXN1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y38 } [get_ports {qsfp2_tx_p[1]}] ;# MGTHTXP1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC Y39 } [get_ports {qsfp2_tx_n[1]}] ;# MGTHTXN1_129 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W45 } [get_ports {qsfp2_rx_p[2]}] ;# MGTHRXP2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W46 } [get_ports {qsfp2_rx_n[2]}] ;# MGTHRXN2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W40 } [get_ports {qsfp2_tx_p[2]}] ;# MGTHTXP2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC W41 } [get_ports {qsfp2_tx_n[2]}] ;# MGTHTXN2_129 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V43 } [get_ports {qsfp2_rx_p[3]}] ;# MGTHRXP3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V44 } [get_ports {qsfp2_rx_n[3]}] ;# MGTHRXN3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V38 } [get_ports {qsfp2_tx_p[3]}] ;# MGTHTXP3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC V39 } [get_ports {qsfp2_tx_n[3]}] ;# MGTHTXN3_129 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
|
||||
set_property -dict {LOC AC36} [get_ports qsfp2_mgt_refclk_b0_p] ;# MGTREFCLK0P_129 from Si5338 B ch 0
|
||||
set_property -dict {LOC AC37} [get_ports qsfp2_mgt_refclk_b0_n] ;# MGTREFCLK0N_129 from Si5338 B ch 0
|
||||
#set_property -dict {LOC AA36} [get_ports qsfp2_mgt_refclk_b2_p] ;# MGTREFCLK1P_129 from Si5338 B ch 2
|
||||
#set_property -dict {LOC AA37} [get_ports qsfp2_mgt_refclk_b2_n] ;# MGTREFCLK1N_129 from Si5338 B ch 2
|
||||
set_property -dict {LOC BB22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp2_resetl]
|
||||
set_property -dict {LOC BB20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp2_modprsl]
|
||||
set_property -dict {LOC BB21 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp2_intl]
|
||||
set_property -dict {LOC BC21 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode]
|
||||
set_property -dict {LOC BF20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp2_i2c_scl]
|
||||
set_property -dict {LOC BA20 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp2_i2c_sda]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 0)
|
||||
create_clock -period 3.103 -name qsfp2_mgt_refclk_b0 [get_ports qsfp2_mgt_refclk_b0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 2)
|
||||
#create_clock -period 3.103 -name qsfp2_mgt_refclk_b2 [get_ports qsfp2_mgt_refclk_b2_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp2_resetl qsfp2_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp2_resetl qsfp2_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp2_modprsl qsfp2_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp2_modprsl qsfp2_intl}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_output_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp2_i2c_scl qsfp2_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC N45 } [get_ports {qsfp3_rx_p[0]}] ;# MGTHRXP0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N46 } [get_ports {qsfp3_rx_n[0]}] ;# MGTHRXN0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N40 } [get_ports {qsfp3_tx_p[0]}] ;# MGTHTXP0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC N41 } [get_ports {qsfp3_tx_n[0]}] ;# MGTHTXN0_131 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M43 } [get_ports {qsfp3_rx_p[1]}] ;# MGTHRXP1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M44 } [get_ports {qsfp3_rx_n[1]}] ;# MGTHRXN1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M38 } [get_ports {qsfp3_tx_p[1]}] ;# MGTHTXP1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp3_tx_n[1]}] ;# MGTHTXN1_131 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L45 } [get_ports {qsfp3_rx_p[2]}] ;# MGTHRXP2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L46 } [get_ports {qsfp3_rx_n[2]}] ;# MGTHRXN2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L40 } [get_ports {qsfp3_tx_p[2]}] ;# MGTHTXP2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp3_tx_n[2]}] ;# MGTHTXN2_131 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K43 } [get_ports {qsfp3_rx_p[3]}] ;# MGTHRXP3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC K44 } [get_ports {qsfp3_rx_n[3]}] ;# MGTHRXN3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J40 } [get_ports {qsfp3_tx_p[3]}] ;# MGTHTXP3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp3_tx_n[3]}] ;# MGTHTXN3_131 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8
|
||||
set_property -dict {LOC R36 } [get_ports qsfp3_mgt_refclk_b0_p] ;# MGTREFCLK0P_131 from Si5338 B ch 0
|
||||
set_property -dict {LOC R37 } [get_ports qsfp3_mgt_refclk_b0_n] ;# MGTREFCLK0N_131 from Si5338 B ch 0
|
||||
#set_property -dict {LOC N36 } [get_ports qsfp3_mgt_refclk_b3_p] ;# MGTREFCLK1P_131 from Si5338 B ch 3
|
||||
#set_property -dict {LOC N37 } [get_ports qsfp3_mgt_refclk_b3_n] ;# MGTREFCLK1N_131 from Si5338 B ch 3
|
||||
set_property -dict {LOC BC23 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp3_resetl]
|
||||
set_property -dict {LOC BB24 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp3_modprsl]
|
||||
set_property -dict {LOC AY22 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp3_intl]
|
||||
set_property -dict {LOC BA22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp3_lpmode]
|
||||
set_property -dict {LOC BC22 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp3_i2c_scl]
|
||||
set_property -dict {LOC BA24 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8 PULLUP true} [get_ports qsfp3_i2c_sda]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 0)
|
||||
create_clock -period 3.103 -name qsfp3_mgt_refclk_b0 [get_ports qsfp3_mgt_refclk_b0_p]
|
||||
|
||||
# 322.265625 MHz MGT reference clock (from Si5338 B ch 2)
|
||||
#create_clock -period 3.103 -name qsfp3_mgt_refclk_b3 [get_ports qsfp3_mgt_refclk_b3_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp3_resetl qsfp3_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp3_resetl qsfp3_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp3_modprsl qsfp3_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp3_modprsl qsfp3_intl}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}]
|
||||
set_output_delay 0 [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}]
|
||||
set_false_path -from [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}]
|
||||
set_input_delay 0 [get_ports {qsfp3_i2c_scl qsfp3_i2c_sda}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTHRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTHRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTHTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTHTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTHRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTHRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTHTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTHTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTHRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTHRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTHTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTHTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTHRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTHRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTHTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTHTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTHRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTHRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTHTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTHTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTHRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTHRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTHTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTHTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTHRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTHRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTHTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTHTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTHRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTHRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTHTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTHTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AT11 } [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_225
|
||||
#set_property -dict {LOC AT10 } [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_225
|
||||
#set_property -dict {LOC AM11 } [get_ports pcie_refclk_b1_p] ;# MGTREFCLK0P_226 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AM10 } [get_ports pcie_refclk_b1_n] ;# MGTREFCLK0N_226 from Si5338 B ch 1
|
||||
#set_property -dict {LOC AH11 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227
|
||||
#set_property -dict {LOC AH10 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227
|
||||
#set_property -dict {LOC AR26 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_b1 [get_ports pcie_refclk_b1_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 A (U5, U6, U7, U8, U9, U32, U33, U34, U35)
|
||||
# 9x MT40A512M8RH-083E
|
||||
#set_property -dict {LOC AY33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[0]}]
|
||||
#set_property -dict {LOC BA33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[1]}]
|
||||
#set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[2]}]
|
||||
#set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[3]}]
|
||||
#set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[4]}]
|
||||
#set_property -dict {LOC AW33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[5]}]
|
||||
#set_property -dict {LOC AU34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[6]}]
|
||||
#set_property -dict {LOC AT33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[7]}]
|
||||
#set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[8]}]
|
||||
#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[9]}]
|
||||
#set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[10]}]
|
||||
#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[11]}]
|
||||
#set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[12]}]
|
||||
#set_property -dict {LOC AL32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[13]}]
|
||||
#set_property -dict {LOC AM32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[14]}]
|
||||
#set_property -dict {LOC AL34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[15]}]
|
||||
#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[16]}]
|
||||
#set_property -dict {LOC BA34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_ba[0]}]
|
||||
#set_property -dict {LOC BB34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_ba[1]}]
|
||||
#set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_bg[0]}]
|
||||
#set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_bg[1]}]
|
||||
#set_property -dict {LOC AW35 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_a_ck_t[0]}]
|
||||
#set_property -dict {LOC AW36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_a_ck_c[0]}]
|
||||
#set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_cke[0]}]
|
||||
#set_property -dict {LOC BE35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_cs_n[0]}]
|
||||
#set_property -dict {LOC BF35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_act_n}]
|
||||
#set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_odt[0]}]
|
||||
#set_property -dict {LOC BB35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_par}]
|
||||
#set_property -dict {LOC BC34 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_a_reset_n}]
|
||||
|
||||
#set_property -dict {LOC W34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[0]}]
|
||||
#set_property -dict {LOC W33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[1]}]
|
||||
#set_property -dict {LOC Y33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[2]}]
|
||||
#set_property -dict {LOC Y32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[3]}]
|
||||
#set_property -dict {LOC Y30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[4]}]
|
||||
#set_property -dict {LOC W30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[5]}]
|
||||
#set_property -dict {LOC AB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[6]}]
|
||||
#set_property -dict {LOC AA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[7]}]
|
||||
#set_property -dict {LOC AD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[8]}]
|
||||
#set_property -dict {LOC AC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[9]}]
|
||||
#set_property -dict {LOC AC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[10]}]
|
||||
#set_property -dict {LOC AC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[11]}]
|
||||
#set_property -dict {LOC AF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[12]}]
|
||||
#set_property -dict {LOC AE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[13]}]
|
||||
#set_property -dict {LOC AE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[14]}]
|
||||
#set_property -dict {LOC AD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[15]}]
|
||||
#set_property -dict {LOC AF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[16]}]
|
||||
#set_property -dict {LOC AF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[17]}]
|
||||
#set_property -dict {LOC AG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[18]}]
|
||||
#set_property -dict {LOC AG31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[19]}]
|
||||
#set_property -dict {LOC AG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[20]}]
|
||||
#set_property -dict {LOC AF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[21]}]
|
||||
#set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[22]}]
|
||||
#set_property -dict {LOC AH33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[23]}]
|
||||
#set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[24]}]
|
||||
#set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[25]}]
|
||||
#set_property -dict {LOC AG30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[26]}]
|
||||
#set_property -dict {LOC AG29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[27]}]
|
||||
#set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[28]}]
|
||||
#set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[29]}]
|
||||
#set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[30]}]
|
||||
#set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[31]}]
|
||||
#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[32]}]
|
||||
#set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[33]}]
|
||||
#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[34]}]
|
||||
#set_property -dict {LOC AM31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[35]}]
|
||||
#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[36]}]
|
||||
#set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[37]}]
|
||||
#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[38]}]
|
||||
#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[39]}]
|
||||
#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[40]}]
|
||||
#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[41]}]
|
||||
#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[42]}]
|
||||
#set_property -dict {LOC AU30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[43]}]
|
||||
#set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[44]}]
|
||||
#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[45]}]
|
||||
#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[46]}]
|
||||
#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[47]}]
|
||||
#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[48]}]
|
||||
#set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[49]}]
|
||||
#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[50]}]
|
||||
#set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[51]}]
|
||||
#set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[52]}]
|
||||
#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[53]}]
|
||||
#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[54]}]
|
||||
#set_property -dict {LOC BB30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[55]}]
|
||||
#set_property -dict {LOC BD29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[56]}]
|
||||
#set_property -dict {LOC BC29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[57]}]
|
||||
#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[58]}]
|
||||
#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[59]}]
|
||||
#set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[60]}]
|
||||
#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[61]}]
|
||||
#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[62]}]
|
||||
#set_property -dict {LOC BE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[63]}]
|
||||
#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[64]}]
|
||||
#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[65]}]
|
||||
#set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[66]}]
|
||||
#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[67]}]
|
||||
#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[68]}]
|
||||
#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[69]}]
|
||||
#set_property -dict {LOC BF38 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[70]}]
|
||||
#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[71]}]
|
||||
#set_property -dict {LOC W31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[0]}]
|
||||
#set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[0]}]
|
||||
#set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[1]}]
|
||||
#set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[1]}]
|
||||
#set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[2]}]
|
||||
#set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[2]}]
|
||||
#set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[3]}]
|
||||
#set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[3]}]
|
||||
#set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[4]}]
|
||||
#set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[4]}]
|
||||
#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[5]}]
|
||||
#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[5]}]
|
||||
#set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[6]}]
|
||||
#set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[6]}]
|
||||
#set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[7]}]
|
||||
#set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[7]}]
|
||||
#set_property -dict {LOC BD40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[8]}]
|
||||
#set_property -dict {LOC BE40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[8]}]
|
||||
#set_property -dict {LOC AA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC AE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC AH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC AJ27 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC AP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC BF39 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 B (U22, U23, U24, U25, U26, U79, U80, U81, U82)
|
||||
# 9x MT40A512M8RH-083E
|
||||
#set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[0]}]
|
||||
#set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[1]}]
|
||||
#set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[2]}]
|
||||
#set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[3]}]
|
||||
#set_property -dict {LOC E35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[4]}]
|
||||
#set_property -dict {LOC D35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[5]}]
|
||||
#set_property -dict {LOC E37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[6]}]
|
||||
#set_property -dict {LOC B34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[7]}]
|
||||
#set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[8]}]
|
||||
#set_property -dict {LOC D34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[9]}]
|
||||
#set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[10]}]
|
||||
#set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[11]}]
|
||||
#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[12]}]
|
||||
#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[13]}]
|
||||
#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[14]}]
|
||||
#set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[15]}]
|
||||
#set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[16]}]
|
||||
#set_property -dict {LOC C36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_ba[0]}]
|
||||
#set_property -dict {LOC C37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_ba[1]}]
|
||||
#set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_bg[0]}]
|
||||
#set_property -dict {LOC D36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_bg[1]}]
|
||||
#set_property -dict {LOC B36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_b_ck_t[0]}]
|
||||
#set_property -dict {LOC B37 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_b_ck_c[0]}]
|
||||
#set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_cke[0]}]
|
||||
#set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_cs_n[0]}]
|
||||
#set_property -dict {LOC F38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_act_n}]
|
||||
#set_property -dict {LOC A39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_odt[0]}]
|
||||
#set_property -dict {LOC C39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_par}]
|
||||
#set_property -dict {LOC E40 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_b_reset_n}]
|
||||
|
||||
#set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[0]}]
|
||||
#set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[1]}]
|
||||
#set_property -dict {LOC E32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[2]}]
|
||||
#set_property -dict {LOC F32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[3]}]
|
||||
#set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[4]}]
|
||||
#set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[5]}]
|
||||
#set_property -dict {LOC G31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[6]}]
|
||||
#set_property -dict {LOC H31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[7]}]
|
||||
#set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[8]}]
|
||||
#set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[9]}]
|
||||
#set_property -dict {LOC J31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[10]}]
|
||||
#set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[11]}]
|
||||
#set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[12]}]
|
||||
#set_property -dict {LOC M30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[13]}]
|
||||
#set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[14]}]
|
||||
#set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[15]}]
|
||||
#set_property -dict {LOC N33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[16]}]
|
||||
#set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[17]}]
|
||||
#set_property -dict {LOC N31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[18]}]
|
||||
#set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[19]}]
|
||||
#set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[20]}]
|
||||
#set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[21]}]
|
||||
#set_property -dict {LOC R32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[22]}]
|
||||
#set_property -dict {LOC R31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[23]}]
|
||||
#set_property -dict {LOC T30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[24]}]
|
||||
#set_property -dict {LOC U30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[25]}]
|
||||
#set_property -dict {LOC U31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[26]}]
|
||||
#set_property -dict {LOC V31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[27]}]
|
||||
#set_property -dict {LOC T32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[28]}]
|
||||
#set_property -dict {LOC U32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[29]}]
|
||||
#set_property -dict {LOC R33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[30]}]
|
||||
#set_property -dict {LOC T33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[31]}]
|
||||
#set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[32]}]
|
||||
#set_property -dict {LOC B30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[33]}]
|
||||
#set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[34]}]
|
||||
#set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[35]}]
|
||||
#set_property -dict {LOC D30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[36]}]
|
||||
#set_property -dict {LOC E30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[37]}]
|
||||
#set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[38]}]
|
||||
#set_property -dict {LOC D29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[39]}]
|
||||
#set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[40]}]
|
||||
#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[41]}]
|
||||
#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[42]}]
|
||||
#set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[43]}]
|
||||
#set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[44]}]
|
||||
#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[45]}]
|
||||
#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[46]}]
|
||||
#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[47]}]
|
||||
#set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[48]}]
|
||||
#set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[49]}]
|
||||
#set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[50]}]
|
||||
#set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[51]}]
|
||||
#set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[52]}]
|
||||
#set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[53]}]
|
||||
#set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[54]}]
|
||||
#set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[55]}]
|
||||
#set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[56]}]
|
||||
#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[57]}]
|
||||
#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[58]}]
|
||||
#set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[59]}]
|
||||
#set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[60]}]
|
||||
#set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[61]}]
|
||||
#set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[62]}]
|
||||
#set_property -dict {LOC T27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[63]}]
|
||||
#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[64]}]
|
||||
#set_property -dict {LOC F34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[65]}]
|
||||
#set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[66]}]
|
||||
#set_property -dict {LOC H34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[67]}]
|
||||
#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[68]}]
|
||||
#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[69]}]
|
||||
#set_property -dict {LOC F37 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[70]}]
|
||||
#set_property -dict {LOC G37 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[71]}]
|
||||
#set_property -dict {LOC J33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[0]}]
|
||||
#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[0]}]
|
||||
#set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[1]}]
|
||||
#set_property -dict {LOC J30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[1]}]
|
||||
#set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[2]}]
|
||||
#set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[2]}]
|
||||
#set_property -dict {LOC V32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[3]}]
|
||||
#set_property -dict {LOC V33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[3]}]
|
||||
#set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[4]}]
|
||||
#set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[4]}]
|
||||
#set_property -dict {LOC F28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[5]}]
|
||||
#set_property -dict {LOC F29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[5]}]
|
||||
#set_property -dict {LOC K26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[6]}]
|
||||
#set_property -dict {LOC K27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[6]}]
|
||||
#set_property -dict {LOC P29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[7]}]
|
||||
#set_property -dict {LOC N29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[7]}]
|
||||
#set_property -dict {LOC H36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[8]}]
|
||||
#set_property -dict {LOC G36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[8]}]
|
||||
#set_property -dict {LOC G30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC M31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC U34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC M29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC T28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 SODIMM 1
|
||||
#set_property -dict {LOC AT18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[0]}]
|
||||
#set_property -dict {LOC AU17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[1]}]
|
||||
#set_property -dict {LOC AP18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[2]}]
|
||||
#set_property -dict {LOC AR18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[3]}]
|
||||
#set_property -dict {LOC AP20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[4]}]
|
||||
#set_property -dict {LOC AR20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[5]}]
|
||||
#set_property -dict {LOC AU21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[6]}]
|
||||
#set_property -dict {LOC AN18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[7]}]
|
||||
#set_property -dict {LOC AN17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[8]}]
|
||||
#set_property -dict {LOC AN19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[9]}]
|
||||
#set_property -dict {LOC AP19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[10]}]
|
||||
#set_property -dict {LOC AM16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[11]}]
|
||||
#set_property -dict {LOC AN16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[12]}]
|
||||
#set_property -dict {LOC AL19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[13]}]
|
||||
#set_property -dict {LOC AM19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[14]}]
|
||||
#set_property -dict {LOC AL20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[15]}]
|
||||
#set_property -dict {LOC AM20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_adr[16]}]
|
||||
#set_property -dict {LOC AT19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_ba[0]}]
|
||||
#set_property -dict {LOC AU19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_ba[1]}]
|
||||
#set_property -dict {LOC AT20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_bg[0]}]
|
||||
#set_property -dict {LOC AU20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_bg[1]}]
|
||||
#set_property -dict {LOC AR17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm1_ck_t[0]}]
|
||||
#set_property -dict {LOC AT17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm1_ck_c[0]}]
|
||||
#set_property -dict {LOC AM17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm1_ck_t[1]}]
|
||||
#set_property -dict {LOC AL17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm1_ck_c[1]}]
|
||||
#set_property -dict {LOC AY20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cke[0]}]
|
||||
#set_property -dict {LOC AV21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cke[1]}]
|
||||
#set_property -dict {LOC BA18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cs_n[0]}]
|
||||
#set_property -dict {LOC AW20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cs_n[1]}]
|
||||
#set_property -dict {LOC AP16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cs_n[2]}]
|
||||
#set_property -dict {LOC AY17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_cs_n[3]}]
|
||||
#set_property -dict {LOC AV17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_act_n}]
|
||||
#set_property -dict {LOC AW21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_odt[0]}]
|
||||
#set_property -dict {LOC AV19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_odt[1]}]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm1_par}]
|
||||
#set_property -dict {LOC BA17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_sodimm1_reset_n}]
|
||||
#set_property -dict {LOC AY18 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm1_alert_n}]
|
||||
|
||||
#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[0]}]
|
||||
#set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[1]}]
|
||||
#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[2]}]
|
||||
#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[3]}]
|
||||
#set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[4]}]
|
||||
#set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[5]}]
|
||||
#set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[6]}]
|
||||
#set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[7]}]
|
||||
#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[8]}]
|
||||
#set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[9]}]
|
||||
#set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[10]}]
|
||||
#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[11]}]
|
||||
#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[12]}]
|
||||
#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[13]}]
|
||||
#set_property -dict {LOC AW15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[14]}]
|
||||
#set_property -dict {LOC AW16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[15]}]
|
||||
#set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[16]}]
|
||||
#set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[17]}]
|
||||
#set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[18]}]
|
||||
#set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[19]}]
|
||||
#set_property -dict {LOC AY15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[20]}]
|
||||
#set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[21]}]
|
||||
#set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[22]}]
|
||||
#set_property -dict {LOC AY12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[23]}]
|
||||
#set_property -dict {LOC BC13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[24]}]
|
||||
#set_property -dict {LOC BC14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[25]}]
|
||||
#set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[26]}]
|
||||
#set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[27]}]
|
||||
#set_property -dict {LOC BE16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[28]}]
|
||||
#set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[29]}]
|
||||
#set_property -dict {LOC BF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[30]}]
|
||||
#set_property -dict {LOC BE15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[31]}]
|
||||
#set_property -dict {LOC AL28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[32]}]
|
||||
#set_property -dict {LOC AL27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[33]}]
|
||||
#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[34]}]
|
||||
#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[35]}]
|
||||
#set_property -dict {LOC AM25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[36]}]
|
||||
#set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[37]}]
|
||||
#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[38]}]
|
||||
#set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[39]}]
|
||||
#set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[40]}]
|
||||
#set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[41]}]
|
||||
#set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[42]}]
|
||||
#set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[43]}]
|
||||
#set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[44]}]
|
||||
#set_property -dict {LOC AU26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[45]}]
|
||||
#set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[46]}]
|
||||
#set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[47]}]
|
||||
#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[48]}]
|
||||
#set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[49]}]
|
||||
#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[50]}]
|
||||
#set_property -dict {LOC AY26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[51]}]
|
||||
#set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[52]}]
|
||||
#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[53]}]
|
||||
#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[54]}]
|
||||
#set_property -dict {LOC BB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[55]}]
|
||||
#set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[56]}]
|
||||
#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[57]}]
|
||||
#set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[58]}]
|
||||
#set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[59]}]
|
||||
#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[60]}]
|
||||
#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[61]}]
|
||||
#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[62]}]
|
||||
#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[63]}]
|
||||
#set_property -dict {LOC BC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[64]}]
|
||||
#set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[65]}]
|
||||
#set_property -dict {LOC BC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[66]}]
|
||||
#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[67]}]
|
||||
#set_property -dict {LOC BE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[68]}]
|
||||
#set_property -dict {LOC BD18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[69]}]
|
||||
#set_property -dict {LOC BF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[70]}]
|
||||
#set_property -dict {LOC BF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dq[71]}]
|
||||
#set_property -dict {LOC AP13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[0]}]
|
||||
#set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[0]}]
|
||||
#set_property -dict {LOC AU14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[1]}]
|
||||
#set_property -dict {LOC AV14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[1]}]
|
||||
#set_property -dict {LOC BB15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[2]}]
|
||||
#set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[2]}]
|
||||
#set_property -dict {LOC BD13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[3]}]
|
||||
#set_property -dict {LOC BE13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[3]}]
|
||||
#set_property -dict {LOC AM26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[4]}]
|
||||
#set_property -dict {LOC AN26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[4]}]
|
||||
#set_property -dict {LOC AR25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[5]}]
|
||||
#set_property -dict {LOC AT25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[5]}]
|
||||
#set_property -dict {LOC AW25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[6]}]
|
||||
#set_property -dict {LOC AY25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[6]}]
|
||||
#set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[7]}]
|
||||
#set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[7]}]
|
||||
#set_property -dict {LOC BC19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_t[8]}]
|
||||
#set_property -dict {LOC BD19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm1_dqs_c[8]}]
|
||||
#set_property -dict {LOC AR16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC AV26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC BA25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC BE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm1_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 SODIMM 2 (J10)
|
||||
#set_property -dict {LOC F20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[0]}]
|
||||
#set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[1]}]
|
||||
#set_property -dict {LOC E21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[2]}]
|
||||
#set_property -dict {LOC E20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[3]}]
|
||||
#set_property -dict {LOC F18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[4]}]
|
||||
#set_property -dict {LOC F17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[5]}]
|
||||
#set_property -dict {LOC G21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[6]}]
|
||||
#set_property -dict {LOC D19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[7]}]
|
||||
#set_property -dict {LOC C19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[8]}]
|
||||
#set_property -dict {LOC D21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[9]}]
|
||||
#set_property -dict {LOC D20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[10]}]
|
||||
#set_property -dict {LOC C21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[11]}]
|
||||
#set_property -dict {LOC B21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[12]}]
|
||||
#set_property -dict {LOC B19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[13]}]
|
||||
#set_property -dict {LOC A19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[14]}]
|
||||
#set_property -dict {LOC B20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[15]}]
|
||||
#set_property -dict {LOC A20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_adr[16]}]
|
||||
#set_property -dict {LOC H19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_ba[0]}]
|
||||
#set_property -dict {LOC H18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_ba[1]}]
|
||||
#set_property -dict {LOC G20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_bg[0]}]
|
||||
#set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_bg[1]}]
|
||||
#set_property -dict {LOC E18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm2_ck_t[0]}]
|
||||
#set_property -dict {LOC E17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm2_ck_c[0]}]
|
||||
#set_property -dict {LOC C18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm2_ck_t[1]}]
|
||||
#set_property -dict {LOC D18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm2_ck_c[1]}]
|
||||
#set_property -dict {LOC K20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cke[0]}]
|
||||
#set_property -dict {LOC J21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cke[1]}]
|
||||
#set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cs_n[0]}]
|
||||
#set_property -dict {LOC L20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cs_n[1]}]
|
||||
#set_property -dict {LOC A18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cs_n[2]}]
|
||||
#set_property -dict {LOC L17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_cs_n[3]}]
|
||||
#set_property -dict {LOC K21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_act_n}]
|
||||
#set_property -dict {LOC H21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_odt[0]}]
|
||||
#set_property -dict {LOC J20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_odt[1]}]
|
||||
#set_property -dict {LOC J19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm2_par}]
|
||||
#set_property -dict {LOC K17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_sodimm2_reset_n}]
|
||||
#set_property -dict {LOC L19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm2_alert_n}]
|
||||
|
||||
#set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[0]}]
|
||||
#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[1]}]
|
||||
#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[2]}]
|
||||
#set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[3]}]
|
||||
#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[4]}]
|
||||
#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[5]}]
|
||||
#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[6]}]
|
||||
#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[7]}]
|
||||
#set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[8]}]
|
||||
#set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[9]}]
|
||||
#set_property -dict {LOC D23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[10]}]
|
||||
#set_property -dict {LOC D24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[11]}]
|
||||
#set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[12]}]
|
||||
#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[13]}]
|
||||
#set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[14]}]
|
||||
#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[15]}]
|
||||
#set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[16]}]
|
||||
#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[17]}]
|
||||
#set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[18]}]
|
||||
#set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[19]}]
|
||||
#set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[20]}]
|
||||
#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[21]}]
|
||||
#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[22]}]
|
||||
#set_property -dict {LOC L22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[23]}]
|
||||
#set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[24]}]
|
||||
#set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[25]}]
|
||||
#set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[26]}]
|
||||
#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[27]}]
|
||||
#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[28]}]
|
||||
#set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[29]}]
|
||||
#set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[30]}]
|
||||
#set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[31]}]
|
||||
#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[32]}]
|
||||
#set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[33]}]
|
||||
#set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[34]}]
|
||||
#set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[35]}]
|
||||
#set_property -dict {LOC A13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[36]}]
|
||||
#set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[37]}]
|
||||
#set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[38]}]
|
||||
#set_property -dict {LOC C14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[39]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[40]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[41]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[42]}]
|
||||
#set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[43]}]
|
||||
#set_property -dict {LOC E13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[44]}]
|
||||
#set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[45]}]
|
||||
#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[46]}]
|
||||
#set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[47]}]
|
||||
#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[48]}]
|
||||
#set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[49]}]
|
||||
#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[50]}]
|
||||
#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[51]}]
|
||||
#set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[52]}]
|
||||
#set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[53]}]
|
||||
#set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[54]}]
|
||||
#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[55]}]
|
||||
#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[56]}]
|
||||
#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[57]}]
|
||||
#set_property -dict {LOC L14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[58]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[59]}]
|
||||
#set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[60]}]
|
||||
#set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[61]}]
|
||||
#set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[62]}]
|
||||
#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[63]}]
|
||||
#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[64]}]
|
||||
#set_property -dict {LOC N21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[65]}]
|
||||
#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[66]}]
|
||||
#set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[67]}]
|
||||
#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[68]}]
|
||||
#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[69]}]
|
||||
#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[70]}]
|
||||
#set_property -dict {LOC P18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dq[71]}]
|
||||
#set_property -dict {LOC A23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[0]}]
|
||||
#set_property -dict {LOC A22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[0]}]
|
||||
#set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[1]}]
|
||||
#set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[1]}]
|
||||
#set_property -dict {LOC K25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[2]}]
|
||||
#set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[2]}]
|
||||
#set_property -dict {LOC P24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[3]}]
|
||||
#set_property -dict {LOC N24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[3]}]
|
||||
#set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[4]}]
|
||||
#set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[4]}]
|
||||
#set_property -dict {LOC G17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[5]}]
|
||||
#set_property -dict {LOC G16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[5]}]
|
||||
#set_property -dict {LOC H17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[6]}]
|
||||
#set_property -dict {LOC H16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[6]}]
|
||||
#set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[7]}]
|
||||
#set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[7]}]
|
||||
#set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_t[8]}]
|
||||
#set_property -dict {LOC N19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm2_dqs_c[8]}]
|
||||
#set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC D13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC G14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm2_dm_dbi_n[8]}]
|
||||
1
example/XUPP3R/fpga/lib/taxi
Symbolic link
1
example/XUPP3R/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../
|
||||
619
example/XUPP3R/fpga/rtl/fpga_core.sv
Normal file
619
example/XUPP3R/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,619 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk_125mhz,
|
||||
input wire logic rst_125mhz,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic led,
|
||||
|
||||
/*
|
||||
* UART: 3000000 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
input wire logic eeprom_i2c_scl_i,
|
||||
output wire logic eeprom_i2c_scl_o,
|
||||
input wire logic eeprom_i2c_sda_i,
|
||||
output wire logic eeprom_i2c_sda_o,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp0_tx_p,
|
||||
output wire logic [3:0] qsfp0_tx_n,
|
||||
input wire logic [3:0] qsfp0_rx_p,
|
||||
input wire logic [3:0] qsfp0_rx_n,
|
||||
input wire logic qsfp0_mgt_refclk_b0_p,
|
||||
input wire logic qsfp0_mgt_refclk_b0_n,
|
||||
|
||||
output wire logic qsfp0_resetl,
|
||||
input wire logic qsfp0_modprsl,
|
||||
input wire logic qsfp0_intl,
|
||||
output wire logic qsfp0_lpmode,
|
||||
|
||||
input wire logic qsfp0_i2c_scl_i,
|
||||
output wire logic qsfp0_i2c_scl_o,
|
||||
input wire logic qsfp0_i2c_sda_i,
|
||||
output wire logic qsfp0_i2c_sda_o,
|
||||
|
||||
output wire logic [3:0] qsfp1_tx_p,
|
||||
output wire logic [3:0] qsfp1_tx_n,
|
||||
input wire logic [3:0] qsfp1_rx_p,
|
||||
input wire logic [3:0] qsfp1_rx_n,
|
||||
input wire logic qsfp1_mgt_refclk_b0_p,
|
||||
input wire logic qsfp1_mgt_refclk_b0_n,
|
||||
|
||||
output wire logic qsfp1_resetl,
|
||||
input wire logic qsfp1_modprsl,
|
||||
input wire logic qsfp1_intl,
|
||||
output wire logic qsfp1_lpmode,
|
||||
|
||||
input wire logic qsfp1_i2c_scl_i,
|
||||
output wire logic qsfp1_i2c_scl_o,
|
||||
input wire logic qsfp1_i2c_sda_i,
|
||||
output wire logic qsfp1_i2c_sda_o,
|
||||
|
||||
output wire logic [3:0] qsfp2_tx_p,
|
||||
output wire logic [3:0] qsfp2_tx_n,
|
||||
input wire logic [3:0] qsfp2_rx_p,
|
||||
input wire logic [3:0] qsfp2_rx_n,
|
||||
input wire logic qsfp2_mgt_refclk_b0_p,
|
||||
input wire logic qsfp2_mgt_refclk_b0_n,
|
||||
|
||||
output wire logic qsfp2_resetl,
|
||||
input wire logic qsfp2_modprsl,
|
||||
input wire logic qsfp2_intl,
|
||||
output wire logic qsfp2_lpmode,
|
||||
|
||||
input wire logic qsfp2_i2c_scl_i,
|
||||
output wire logic qsfp2_i2c_scl_o,
|
||||
input wire logic qsfp2_i2c_sda_i,
|
||||
output wire logic qsfp2_i2c_sda_o,
|
||||
|
||||
output wire logic [3:0] qsfp3_tx_p,
|
||||
output wire logic [3:0] qsfp3_tx_n,
|
||||
input wire logic [3:0] qsfp3_rx_p,
|
||||
input wire logic [3:0] qsfp3_rx_n,
|
||||
input wire logic qsfp3_mgt_refclk_b0_p,
|
||||
input wire logic qsfp3_mgt_refclk_b0_n,
|
||||
|
||||
output wire logic qsfp3_resetl,
|
||||
input wire logic qsfp3_modprsl,
|
||||
input wire logic qsfp3_intl,
|
||||
output wire logic qsfp3_lpmode,
|
||||
|
||||
input wire logic qsfp3_i2c_scl_i,
|
||||
output wire logic qsfp3_i2c_scl_o,
|
||||
input wire logic qsfp3_i2c_sda_i,
|
||||
output wire logic qsfp3_i2c_sda_o
|
||||
);
|
||||
|
||||
assign eeprom_i2c_scl_o = 1'b1;
|
||||
assign eeprom_i2c_sda_o = 1'b1;
|
||||
|
||||
assign qsfp0_i2c_scl_o = 1'b1;
|
||||
assign qsfp0_i2c_sda_o = 1'b1;
|
||||
assign qsfp1_i2c_scl_o = 1'b1;
|
||||
assign qsfp1_i2c_sda_o = 1'b1;
|
||||
assign qsfp2_i2c_scl_o = 1'b1;
|
||||
assign qsfp2_i2c_sda_o = 1'b1;
|
||||
assign qsfp3_i2c_scl_o = 1'b1;
|
||||
assign qsfp3_i2c_sda_o = 1'b1;
|
||||
|
||||
// XFCP
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
|
||||
|
||||
taxi_xfcp_if_uart #(
|
||||
.TX_FIFO_DEPTH(512),
|
||||
.RX_FIFO_DEPTH(512)
|
||||
)
|
||||
xfcp_if_uart_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.uart_rxd(uart_rxd),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* XFCP downstream interface
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_ds),
|
||||
.xfcp_dsp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/3000000))
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1]();
|
||||
|
||||
taxi_xfcp_switch #(
|
||||
.XFCP_ID_STR(FAMILY == "virtexuplus" ? "XUPP3R" : "XUSP3S"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR("Taxi example"),
|
||||
.PORTS($size(xfcp_sw_us))
|
||||
)
|
||||
xfcp_sw_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_ds),
|
||||
.xfcp_usp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* XFCP downstream ports
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_sw_ds),
|
||||
.xfcp_dsp_us(xfcp_sw_us)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
|
||||
|
||||
taxi_xfcp_mod_stats #(
|
||||
.XFCP_ID_STR("Statistics"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR(""),
|
||||
.STAT_COUNT_W(64),
|
||||
.STAT_PIPELINE(2)
|
||||
)
|
||||
xfcp_stats_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_sw_ds[0]),
|
||||
.xfcp_usp_us(xfcp_sw_us[0]),
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
.s_axis_stat(axis_stat)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[4]();
|
||||
|
||||
taxi_axis_arb_mux #(
|
||||
.S_COUNT($size(axis_eth_stat)),
|
||||
.UPDATE_TID(1'b0),
|
||||
.ARB_ROUND_ROBIN(1'b1),
|
||||
.ARB_LSB_HIGH_PRIO(1'b0)
|
||||
)
|
||||
stat_mux_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* AXI4-Stream inputs (sink)
|
||||
*/
|
||||
.s_axis(axis_eth_stat),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(axis_stat)
|
||||
);
|
||||
|
||||
// QSFP28
|
||||
assign qsfp0_resetl = 1'b1;
|
||||
assign qsfp0_lpmode = 1'b0;
|
||||
assign qsfp1_resetl = 1'b1;
|
||||
assign qsfp1_lpmode = 1'b0;
|
||||
assign qsfp2_resetl = 1'b1;
|
||||
assign qsfp2_lpmode = 1'b0;
|
||||
assign qsfp3_resetl = 1'b1;
|
||||
assign qsfp3_lpmode = 1'b0;
|
||||
|
||||
localparam GTY_QUAD_CNT = 4;
|
||||
localparam GTY_CNT = GTY_QUAD_CNT*4;
|
||||
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_tx_p;
|
||||
wire [GTY_CNT-1:0] eth_gty_tx_n;
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_p = {qsfp3_rx_p, qsfp2_rx_p, qsfp1_rx_p, qsfp0_rx_p};
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_n = {qsfp3_rx_n, qsfp2_rx_n, qsfp1_rx_n, qsfp0_rx_n};
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p = {qsfp3_mgt_refclk_b0_p, qsfp2_mgt_refclk_b0_p, qsfp1_mgt_refclk_b0_p, qsfp0_mgt_refclk_b0_p};
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n = {qsfp3_mgt_refclk_b0_n, qsfp2_mgt_refclk_b0_n, qsfp1_mgt_refclk_b0_n, qsfp0_mgt_refclk_b0_n};
|
||||
|
||||
assign qsfp0_tx_p = eth_gty_tx_p[3:0];
|
||||
assign qsfp0_tx_n = eth_gty_tx_n[3:0];
|
||||
assign qsfp1_tx_p = eth_gty_tx_p[7:4];
|
||||
assign qsfp1_tx_n = eth_gty_tx_n[7:4];
|
||||
assign qsfp2_tx_p = eth_gty_tx_p[11:8];
|
||||
assign qsfp2_tx_n = eth_gty_tx_n[11:8];
|
||||
assign qsfp3_tx_p = eth_gty_tx_p[15:12];
|
||||
assign qsfp3_tx_n = eth_gty_tx_n[15:12];
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_tx_clk;
|
||||
wire [GTY_CNT-1:0] eth_gty_tx_rst;
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_clk;
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_rst;
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
|
||||
|
||||
wire [GTY_CNT-1:0] eth_gty_rx_status;
|
||||
|
||||
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
|
||||
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
|
||||
|
||||
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
|
||||
|
||||
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
|
||||
|
||||
wire eth_gty_mgt_refclk_int;
|
||||
|
||||
if (SIM) begin
|
||||
|
||||
assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n];
|
||||
assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n];
|
||||
assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int;
|
||||
|
||||
end else begin
|
||||
|
||||
if (FAMILY == "virtexuplus") begin
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst (
|
||||
.I (eth_gty_mgt_refclk_p[n]),
|
||||
.IB (eth_gty_mgt_refclk_n[n]),
|
||||
.CEB (1'b0),
|
||||
.O (eth_gty_mgt_refclk[n]),
|
||||
.ODIV2 (eth_gty_mgt_refclk_int)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
IBUFDS_GTE3 ibufds_gte4_eth_gty_mgt_refclk_inst (
|
||||
.I (eth_gty_mgt_refclk_p[n]),
|
||||
.IB (eth_gty_mgt_refclk_n[n]),
|
||||
.CEB (1'b0),
|
||||
.O (eth_gty_mgt_refclk[n]),
|
||||
.ODIV2 (eth_gty_mgt_refclk_int)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst (
|
||||
.CE (ð_gty_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (eth_gty_mgt_refclk_int),
|
||||
.O (eth_gty_mgt_refclk_bufg[n])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_sync_reset_inst (
|
||||
.clk(eth_gty_mgt_refclk_bufg[n]),
|
||||
.rst(rst_125mhz),
|
||||
.out(eth_gty_rst[n])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP0[4] = '{"QSFP0.1", "QSFP0.2", "QSFP0.3", "QSFP0.4"};
|
||||
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"};
|
||||
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"};
|
||||
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP3[4] = '{"QSFP3.1", "QSFP3.2", "QSFP3.3", "QSFP3.4"};
|
||||
|
||||
for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
|
||||
|
||||
localparam CNT = 4;
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(4),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(n*CNT*(16+16)),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP0 :
|
||||
n == 1 ? STAT_PREFIX_STR_QSFP1 :
|
||||
n == 2 ? STAT_PREFIX_STR_QSFP2 : STAT_PREFIX_STR_QSFP3)
|
||||
)
|
||||
mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(eth_gty_rst[n]),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
|
||||
.xcvr_gtrefclk00_in(eth_gty_mgt_refclk[n]),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]),
|
||||
.xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]),
|
||||
.xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]),
|
||||
.xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
|
||||
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]),
|
||||
.m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('{CNT{'0}}),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('{CNT{'0}}),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('{CNT{'0}}),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('{CNT{'0}}),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('{CNT{'0}}),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk_125mhz),
|
||||
.stat_rst(rst_125mhz),
|
||||
.m_axis_stat(axis_eth_stat[n]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(eth_gty_rx_status[n*CNT +: CNT]),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(),
|
||||
.stat_rx_err_bad_block(),
|
||||
.stat_rx_err_framing(),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop('0),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
|
||||
.cfg_tx_ifg('{CNT{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
for (genvar n = 0; n < GTY_CNT; n = n + 1) begin : qsfp_ch
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(16384),
|
||||
.RAM_PIPELINE(2),
|
||||
.FRAME_FIFO(1),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(1),
|
||||
.DROP_BAD_FRAME(1),
|
||||
.DROP_WHEN_FULL(1)
|
||||
)
|
||||
ch_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(eth_gty_rx_clk[n]),
|
||||
.s_rst(eth_gty_rx_rst[n]),
|
||||
.s_axis(eth_gty_axis_rx[n]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(eth_gty_tx_clk[n]),
|
||||
.m_rst(eth_gty_tx_rst[n]),
|
||||
.m_axis(eth_gty_axis_tx[n]),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
445
example/XUPP3R/fpga/rtl/fpga_xupp3r.sv
Normal file
445
example/XUPP3R/fpga/rtl/fpga_xupp3r.sv
Normal file
@@ -0,0 +1,445 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 48MHz
|
||||
*/
|
||||
input wire logic clk_48mhz,
|
||||
input wire logic sys_rst_l,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [3:0] led,
|
||||
|
||||
/*
|
||||
* UART: 3000000 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
|
||||
/*
|
||||
* I2C and related signals
|
||||
*/
|
||||
inout wire logic eeprom_i2c_scl,
|
||||
inout wire logic eeprom_i2c_sda,
|
||||
output wire logic fpga_i2c_master_l,
|
||||
output wire logic qsfp_ctl_en,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp0_tx_p,
|
||||
output wire logic [3:0] qsfp0_tx_n,
|
||||
input wire logic [3:0] qsfp0_rx_p,
|
||||
input wire logic [3:0] qsfp0_rx_n,
|
||||
input wire logic qsfp0_mgt_refclk_b0_p,
|
||||
input wire logic qsfp0_mgt_refclk_b0_n,
|
||||
// input wire logic qsfp0_mgt_refclk_b1_p,
|
||||
// input wire logic qsfp0_mgt_refclk_b1_n,
|
||||
// input wire logic qsfp0_mgt_refclk_c0_p,
|
||||
// input wire logic qsfp0_mgt_refclk_c0_n,
|
||||
// input wire logic qsfp0_mgt_refclk_c1_p,
|
||||
// input wire logic qsfp0_mgt_refclk_c1_n,
|
||||
output wire logic qsfp0_resetl,
|
||||
input wire logic qsfp0_modprsl,
|
||||
input wire logic qsfp0_intl,
|
||||
output wire logic qsfp0_lpmode,
|
||||
inout wire logic qsfp0_i2c_scl,
|
||||
inout wire logic qsfp0_i2c_sda,
|
||||
|
||||
output wire logic [3:0] qsfp1_tx_p,
|
||||
output wire logic [3:0] qsfp1_tx_n,
|
||||
input wire logic [3:0] qsfp1_rx_p,
|
||||
input wire logic [3:0] qsfp1_rx_n,
|
||||
input wire logic qsfp1_mgt_refclk_b0_p,
|
||||
input wire logic qsfp1_mgt_refclk_b0_n,
|
||||
// input wire logic qsfp1_mgt_refclk_b1_p,
|
||||
// input wire logic qsfp1_mgt_refclk_b1_n,
|
||||
// input wire logic qsfp1_mgt_refclk_c2_p,
|
||||
// input wire logic qsfp1_mgt_refclk_c2_n,
|
||||
// input wire logic qsfp1_mgt_refclk_c3_p,
|
||||
// input wire logic qsfp1_mgt_refclk_c3_n,
|
||||
output wire logic qsfp1_resetl,
|
||||
input wire logic qsfp1_modprsl,
|
||||
input wire logic qsfp1_intl,
|
||||
output wire logic qsfp1_lpmode,
|
||||
inout wire logic qsfp1_i2c_scl,
|
||||
inout wire logic qsfp1_i2c_sda,
|
||||
|
||||
output wire logic [3:0] qsfp2_tx_p,
|
||||
output wire logic [3:0] qsfp2_tx_n,
|
||||
input wire logic [3:0] qsfp2_rx_p,
|
||||
input wire logic [3:0] qsfp2_rx_n,
|
||||
input wire logic qsfp2_mgt_refclk_b0_p,
|
||||
input wire logic qsfp2_mgt_refclk_b0_n,
|
||||
// input wire logic qsfp2_mgt_refclk_b2_p,
|
||||
// input wire logic qsfp2_mgt_refclk_b2_n,
|
||||
// input wire logic qsfp2_mgt_refclk_d0_p,
|
||||
// input wire logic qsfp2_mgt_refclk_d0_n,
|
||||
// input wire logic qsfp2_mgt_refclk_d1_p,
|
||||
// input wire logic qsfp2_mgt_refclk_d1_n,
|
||||
output wire logic qsfp2_resetl,
|
||||
input wire logic qsfp2_modprsl,
|
||||
input wire logic qsfp2_intl,
|
||||
output wire logic qsfp2_lpmode,
|
||||
inout wire logic qsfp2_i2c_scl,
|
||||
inout wire logic qsfp2_i2c_sda,
|
||||
|
||||
output wire logic [3:0] qsfp3_tx_p,
|
||||
output wire logic [3:0] qsfp3_tx_n,
|
||||
input wire logic [3:0] qsfp3_rx_p,
|
||||
input wire logic [3:0] qsfp3_rx_n,
|
||||
input wire logic qsfp3_mgt_refclk_b0_p,
|
||||
input wire logic qsfp3_mgt_refclk_b0_n,
|
||||
// input wire logic qsfp3_mgt_refclk_b3_p,
|
||||
// input wire logic qsfp3_mgt_refclk_b3_n,
|
||||
// input wire logic qsfp3_mgt_refclk_d2_p,
|
||||
// input wire logic qsfp3_mgt_refclk_d2_n,
|
||||
// input wire logic qsfp3_mgt_refclk_d3_p,
|
||||
// input wire logic qsfp3_mgt_refclk_d3_n,
|
||||
output wire logic qsfp3_resetl,
|
||||
input wire logic qsfp3_modprsl,
|
||||
input wire logic qsfp3_intl,
|
||||
output wire logic qsfp3_lpmode,
|
||||
inout wire logic qsfp3_i2c_scl,
|
||||
inout wire logic qsfp3_i2c_sda
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_125mhz_mmcm_out;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = !sys_rst_l;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 48 MHz input
|
||||
.CLKIN1_PERIOD(20.833),
|
||||
.REF_JITTER1(0.010),
|
||||
// 48 MHz input / 4 = 12 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(4),
|
||||
// 12 MHz PFD * 125 = 1500 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(125),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1500 MHz / 12 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(12),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 48 MHz input
|
||||
.CLKIN1(clk_48mhz),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign qsfp_ctl_en = 1'b1;
|
||||
assign fpga_i2c_master_l = 1'b0;
|
||||
|
||||
wire uart_rxd_int;
|
||||
|
||||
wire eeprom_i2c_scl_i;
|
||||
wire eeprom_i2c_scl_o;
|
||||
wire eeprom_i2c_sda_i;
|
||||
wire eeprom_i2c_sda_o;
|
||||
|
||||
wire qsfp0_modprsl_int;
|
||||
wire qsfp0_intl_int;
|
||||
wire qsfp0_i2c_scl_i;
|
||||
wire qsfp0_i2c_scl_o;
|
||||
wire qsfp0_i2c_sda_i;
|
||||
wire qsfp0_i2c_sda_o;
|
||||
|
||||
wire qsfp1_modprsl_int;
|
||||
wire qsfp1_intl_int;
|
||||
wire qsfp1_i2c_scl_i;
|
||||
wire qsfp1_i2c_scl_o;
|
||||
wire qsfp1_i2c_sda_i;
|
||||
wire qsfp1_i2c_sda_o;
|
||||
|
||||
wire qsfp2_modprsl_int;
|
||||
wire qsfp2_intl_int;
|
||||
wire qsfp2_i2c_scl_i;
|
||||
wire qsfp2_i2c_scl_o;
|
||||
wire qsfp2_i2c_sda_i;
|
||||
wire qsfp2_i2c_sda_o;
|
||||
|
||||
wire qsfp3_modprsl_int;
|
||||
wire qsfp3_intl_int;
|
||||
wire qsfp3_i2c_scl_i;
|
||||
wire qsfp3_i2c_scl_o;
|
||||
wire qsfp3_i2c_sda_i;
|
||||
wire qsfp3_i2c_sda_o;
|
||||
|
||||
logic eeprom_i2c_scl_o_reg;
|
||||
logic eeprom_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp0_i2c_scl_o_reg;
|
||||
logic qsfp0_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp1_i2c_scl_o_reg;
|
||||
logic qsfp1_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp2_i2c_scl_o_reg;
|
||||
logic qsfp2_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp3_i2c_scl_o_reg;
|
||||
logic qsfp3_i2c_sda_o_reg;
|
||||
|
||||
always_ff @(posedge clk_125mhz_int) begin
|
||||
eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
|
||||
eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
|
||||
|
||||
qsfp0_i2c_scl_o_reg <= qsfp0_i2c_scl_o;
|
||||
qsfp0_i2c_sda_o_reg <= qsfp0_i2c_sda_o;
|
||||
|
||||
qsfp1_i2c_scl_o_reg <= qsfp1_i2c_scl_o;
|
||||
qsfp1_i2c_sda_o_reg <= qsfp1_i2c_sda_o;
|
||||
|
||||
qsfp2_i2c_scl_o_reg <= qsfp2_i2c_scl_o;
|
||||
qsfp2_i2c_sda_o_reg <= qsfp2_i2c_sda_o;
|
||||
|
||||
qsfp3_i2c_scl_o_reg <= qsfp3_i2c_scl_o;
|
||||
qsfp3_i2c_sda_o_reg <= qsfp3_i2c_sda_o;
|
||||
end
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(19),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.in({uart_rxd, eeprom_i2c_scl, eeprom_i2c_sda,
|
||||
qsfp0_modprsl, qsfp0_intl, qsfp0_i2c_scl, qsfp0_i2c_sda,
|
||||
qsfp1_modprsl, qsfp1_intl, qsfp1_i2c_scl, qsfp1_i2c_sda,
|
||||
qsfp2_modprsl, qsfp2_intl, qsfp2_i2c_scl, qsfp2_i2c_sda,
|
||||
qsfp3_modprsl, qsfp3_intl, qsfp3_i2c_scl, qsfp3_i2c_sda}),
|
||||
.out({uart_rxd_int, eeprom_i2c_scl_i, eeprom_i2c_sda_i,
|
||||
qsfp0_modprsl_int, qsfp0_intl_int, qsfp0_i2c_scl_i, qsfp0_i2c_sda_i,
|
||||
qsfp1_modprsl_int, qsfp1_intl_int, qsfp1_i2c_scl_i, qsfp1_i2c_sda_i,
|
||||
qsfp2_modprsl_int, qsfp2_intl_int, qsfp2_i2c_scl_i, qsfp2_i2c_sda_i,
|
||||
qsfp3_modprsl_int, qsfp3_intl_int, qsfp3_i2c_scl_i, qsfp3_i2c_sda_i})
|
||||
);
|
||||
|
||||
assign eeprom_i2c_scl = eeprom_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign eeprom_i2c_sda = eeprom_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp0_i2c_scl = qsfp0_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp0_i2c_sda = qsfp0_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp1_i2c_scl = qsfp1_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp1_i2c_sda = qsfp1_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp2_i2c_scl = qsfp2_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp2_i2c_sda = qsfp2_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp3_i2c_scl = qsfp3_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp3_i2c_sda = qsfp3_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.led(led),
|
||||
|
||||
/*
|
||||
* UART: 3000000 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd_int),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
.eeprom_i2c_scl_i(eeprom_i2c_scl_i),
|
||||
.eeprom_i2c_scl_o(eeprom_i2c_scl_o),
|
||||
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
|
||||
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.qsfp0_tx_p(qsfp0_tx_p),
|
||||
.qsfp0_tx_n(qsfp0_tx_n),
|
||||
.qsfp0_rx_p(qsfp0_rx_p),
|
||||
.qsfp0_rx_n(qsfp0_rx_n),
|
||||
.qsfp0_mgt_refclk_b0_p(qsfp0_mgt_refclk_b0_p),
|
||||
.qsfp0_mgt_refclk_b0_n(qsfp0_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp0_modprsl(qsfp0_modprsl_int),
|
||||
.qsfp0_resetl(qsfp0_resetl),
|
||||
.qsfp0_intl(qsfp0_intl_int),
|
||||
.qsfp0_lpmode(qsfp0_lpmode),
|
||||
|
||||
.qsfp0_i2c_scl_i(qsfp0_i2c_scl_i),
|
||||
.qsfp0_i2c_scl_o(qsfp0_i2c_scl_o),
|
||||
.qsfp0_i2c_sda_i(qsfp0_i2c_sda_i),
|
||||
.qsfp0_i2c_sda_o(qsfp0_i2c_sda_o),
|
||||
|
||||
.qsfp1_tx_p(qsfp1_tx_p),
|
||||
.qsfp1_tx_n(qsfp1_tx_n),
|
||||
.qsfp1_rx_p(qsfp1_rx_p),
|
||||
.qsfp1_rx_n(qsfp1_rx_n),
|
||||
.qsfp1_mgt_refclk_b0_p(qsfp1_mgt_refclk_b0_p),
|
||||
.qsfp1_mgt_refclk_b0_n(qsfp1_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp1_modprsl(qsfp1_modprsl_int),
|
||||
.qsfp1_resetl(qsfp1_resetl),
|
||||
.qsfp1_intl(qsfp1_intl_int),
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
.qsfp1_i2c_scl_i(qsfp1_i2c_scl_i),
|
||||
.qsfp1_i2c_scl_o(qsfp1_i2c_scl_o),
|
||||
.qsfp1_i2c_sda_i(qsfp1_i2c_sda_i),
|
||||
.qsfp1_i2c_sda_o(qsfp1_i2c_sda_o),
|
||||
|
||||
.qsfp2_tx_p(qsfp2_tx_p),
|
||||
.qsfp2_tx_n(qsfp2_tx_n),
|
||||
.qsfp2_rx_p(qsfp2_rx_p),
|
||||
.qsfp2_rx_n(qsfp2_rx_n),
|
||||
.qsfp2_mgt_refclk_b0_p(qsfp2_mgt_refclk_b0_p),
|
||||
.qsfp2_mgt_refclk_b0_n(qsfp2_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp2_modprsl(qsfp2_modprsl_int),
|
||||
.qsfp2_resetl(qsfp2_resetl),
|
||||
.qsfp2_intl(qsfp2_intl_int),
|
||||
.qsfp2_lpmode(qsfp2_lpmode),
|
||||
|
||||
.qsfp2_i2c_scl_i(qsfp2_i2c_scl_i),
|
||||
.qsfp2_i2c_scl_o(qsfp2_i2c_scl_o),
|
||||
.qsfp2_i2c_sda_i(qsfp2_i2c_sda_i),
|
||||
.qsfp2_i2c_sda_o(qsfp2_i2c_sda_o),
|
||||
|
||||
.qsfp3_tx_p(qsfp3_tx_p),
|
||||
.qsfp3_tx_n(qsfp3_tx_n),
|
||||
.qsfp3_rx_p(qsfp3_rx_p),
|
||||
.qsfp3_rx_n(qsfp3_rx_n),
|
||||
.qsfp3_mgt_refclk_b0_p(qsfp3_mgt_refclk_b0_p),
|
||||
.qsfp3_mgt_refclk_b0_n(qsfp3_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp3_modprsl(qsfp3_modprsl_int),
|
||||
.qsfp3_resetl(qsfp3_resetl),
|
||||
.qsfp3_intl(qsfp3_intl_int),
|
||||
.qsfp3_lpmode(qsfp3_lpmode),
|
||||
|
||||
.qsfp3_i2c_scl_i(qsfp3_i2c_scl_i),
|
||||
.qsfp3_i2c_scl_o(qsfp3_i2c_scl_o),
|
||||
.qsfp3_i2c_sda_i(qsfp3_i2c_sda_i),
|
||||
.qsfp3_i2c_sda_o(qsfp3_i2c_sda_o)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
445
example/XUPP3R/fpga/rtl/fpga_xusp3s.sv
Normal file
445
example/XUPP3R/fpga/rtl/fpga_xusp3s.sv
Normal file
@@ -0,0 +1,445 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexu"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 48MHz
|
||||
*/
|
||||
input wire logic clk_48mhz,
|
||||
input wire logic sys_rst_l,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [3:0] led,
|
||||
|
||||
/*
|
||||
* UART: 3000000 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
|
||||
/*
|
||||
* I2C and related signals
|
||||
*/
|
||||
inout wire logic eeprom_i2c_scl,
|
||||
inout wire logic eeprom_i2c_sda,
|
||||
output wire logic fpga_i2c_master_l,
|
||||
output wire logic qsfp_ctl_en,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp0_tx_p,
|
||||
output wire logic [3:0] qsfp0_tx_n,
|
||||
input wire logic [3:0] qsfp0_rx_p,
|
||||
input wire logic [3:0] qsfp0_rx_n,
|
||||
input wire logic qsfp0_mgt_refclk_b0_p,
|
||||
input wire logic qsfp0_mgt_refclk_b0_n,
|
||||
// input wire logic qsfp0_mgt_refclk_b1_p,
|
||||
// input wire logic qsfp0_mgt_refclk_b1_n,
|
||||
// input wire logic qsfp0_mgt_refclk_c0_p,
|
||||
// input wire logic qsfp0_mgt_refclk_c0_n,
|
||||
// input wire logic qsfp0_mgt_refclk_c1_p,
|
||||
// input wire logic qsfp0_mgt_refclk_c1_n,
|
||||
output wire logic qsfp0_resetl,
|
||||
input wire logic qsfp0_modprsl,
|
||||
input wire logic qsfp0_intl,
|
||||
output wire logic qsfp0_lpmode,
|
||||
inout wire logic qsfp0_i2c_scl,
|
||||
inout wire logic qsfp0_i2c_sda,
|
||||
|
||||
output wire logic [3:0] qsfp1_tx_p,
|
||||
output wire logic [3:0] qsfp1_tx_n,
|
||||
input wire logic [3:0] qsfp1_rx_p,
|
||||
input wire logic [3:0] qsfp1_rx_n,
|
||||
input wire logic qsfp1_mgt_refclk_b0_p,
|
||||
input wire logic qsfp1_mgt_refclk_b0_n,
|
||||
// input wire logic qsfp1_mgt_refclk_b1_p,
|
||||
// input wire logic qsfp1_mgt_refclk_b1_n,
|
||||
// input wire logic qsfp1_mgt_refclk_c2_p,
|
||||
// input wire logic qsfp1_mgt_refclk_c2_n,
|
||||
// input wire logic qsfp1_mgt_refclk_c3_p,
|
||||
// input wire logic qsfp1_mgt_refclk_c3_n,
|
||||
output wire logic qsfp1_resetl,
|
||||
input wire logic qsfp1_modprsl,
|
||||
input wire logic qsfp1_intl,
|
||||
output wire logic qsfp1_lpmode,
|
||||
inout wire logic qsfp1_i2c_scl,
|
||||
inout wire logic qsfp1_i2c_sda,
|
||||
|
||||
output wire logic [3:0] qsfp2_tx_p,
|
||||
output wire logic [3:0] qsfp2_tx_n,
|
||||
input wire logic [3:0] qsfp2_rx_p,
|
||||
input wire logic [3:0] qsfp2_rx_n,
|
||||
input wire logic qsfp2_mgt_refclk_b0_p,
|
||||
input wire logic qsfp2_mgt_refclk_b0_n,
|
||||
// input wire logic qsfp2_mgt_refclk_b2_p,
|
||||
// input wire logic qsfp2_mgt_refclk_b2_n,
|
||||
// input wire logic qsfp2_mgt_refclk_d0_p,
|
||||
// input wire logic qsfp2_mgt_refclk_d0_n,
|
||||
// input wire logic qsfp2_mgt_refclk_d1_p,
|
||||
// input wire logic qsfp2_mgt_refclk_d1_n,
|
||||
output wire logic qsfp2_resetl,
|
||||
input wire logic qsfp2_modprsl,
|
||||
input wire logic qsfp2_intl,
|
||||
output wire logic qsfp2_lpmode,
|
||||
inout wire logic qsfp2_i2c_scl,
|
||||
inout wire logic qsfp2_i2c_sda,
|
||||
|
||||
output wire logic [3:0] qsfp3_tx_p,
|
||||
output wire logic [3:0] qsfp3_tx_n,
|
||||
input wire logic [3:0] qsfp3_rx_p,
|
||||
input wire logic [3:0] qsfp3_rx_n,
|
||||
input wire logic qsfp3_mgt_refclk_b0_p,
|
||||
input wire logic qsfp3_mgt_refclk_b0_n,
|
||||
// input wire logic qsfp3_mgt_refclk_b3_p,
|
||||
// input wire logic qsfp3_mgt_refclk_b3_n,
|
||||
// input wire logic qsfp3_mgt_refclk_d2_p,
|
||||
// input wire logic qsfp3_mgt_refclk_d2_n,
|
||||
// input wire logic qsfp3_mgt_refclk_d3_p,
|
||||
// input wire logic qsfp3_mgt_refclk_d3_n,
|
||||
output wire logic qsfp3_resetl,
|
||||
input wire logic qsfp3_modprsl,
|
||||
input wire logic qsfp3_intl,
|
||||
output wire logic qsfp3_lpmode,
|
||||
inout wire logic qsfp3_i2c_scl,
|
||||
inout wire logic qsfp3_i2c_sda
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_125mhz_mmcm_out;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = !sys_rst_l;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME3_BASE #(
|
||||
// 48 MHz input
|
||||
.CLKIN1_PERIOD(20.833),
|
||||
.REF_JITTER1(0.010),
|
||||
// 48 MHz input / 3 = 16 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(3),
|
||||
// 16 MHz PFD * 62.5 = 1000 MHz VCO (range 600 MHz to 1440 MHz)
|
||||
.CLKFBOUT_MULT_F(62.5),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1000 MHz / 8 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(8),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 48 MHz input
|
||||
.CLKIN1(clk_48mhz),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign qsfp_ctl_en = 1'b1;
|
||||
assign fpga_i2c_master_l = 1'b0;
|
||||
|
||||
wire uart_rxd_int;
|
||||
|
||||
wire eeprom_i2c_scl_i;
|
||||
wire eeprom_i2c_scl_o;
|
||||
wire eeprom_i2c_sda_i;
|
||||
wire eeprom_i2c_sda_o;
|
||||
|
||||
wire qsfp0_modprsl_int;
|
||||
wire qsfp0_intl_int;
|
||||
wire qsfp0_i2c_scl_i;
|
||||
wire qsfp0_i2c_scl_o;
|
||||
wire qsfp0_i2c_sda_i;
|
||||
wire qsfp0_i2c_sda_o;
|
||||
|
||||
wire qsfp1_modprsl_int;
|
||||
wire qsfp1_intl_int;
|
||||
wire qsfp1_i2c_scl_i;
|
||||
wire qsfp1_i2c_scl_o;
|
||||
wire qsfp1_i2c_sda_i;
|
||||
wire qsfp1_i2c_sda_o;
|
||||
|
||||
wire qsfp2_modprsl_int;
|
||||
wire qsfp2_intl_int;
|
||||
wire qsfp2_i2c_scl_i;
|
||||
wire qsfp2_i2c_scl_o;
|
||||
wire qsfp2_i2c_sda_i;
|
||||
wire qsfp2_i2c_sda_o;
|
||||
|
||||
wire qsfp3_modprsl_int;
|
||||
wire qsfp3_intl_int;
|
||||
wire qsfp3_i2c_scl_i;
|
||||
wire qsfp3_i2c_scl_o;
|
||||
wire qsfp3_i2c_sda_i;
|
||||
wire qsfp3_i2c_sda_o;
|
||||
|
||||
logic eeprom_i2c_scl_o_reg;
|
||||
logic eeprom_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp0_i2c_scl_o_reg;
|
||||
logic qsfp0_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp1_i2c_scl_o_reg;
|
||||
logic qsfp1_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp2_i2c_scl_o_reg;
|
||||
logic qsfp2_i2c_sda_o_reg;
|
||||
|
||||
logic qsfp3_i2c_scl_o_reg;
|
||||
logic qsfp3_i2c_sda_o_reg;
|
||||
|
||||
always_ff @(posedge clk_125mhz_int) begin
|
||||
eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
|
||||
eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
|
||||
|
||||
qsfp0_i2c_scl_o_reg <= qsfp0_i2c_scl_o;
|
||||
qsfp0_i2c_sda_o_reg <= qsfp0_i2c_sda_o;
|
||||
|
||||
qsfp1_i2c_scl_o_reg <= qsfp1_i2c_scl_o;
|
||||
qsfp1_i2c_sda_o_reg <= qsfp1_i2c_sda_o;
|
||||
|
||||
qsfp2_i2c_scl_o_reg <= qsfp2_i2c_scl_o;
|
||||
qsfp2_i2c_sda_o_reg <= qsfp2_i2c_sda_o;
|
||||
|
||||
qsfp3_i2c_scl_o_reg <= qsfp3_i2c_scl_o;
|
||||
qsfp3_i2c_sda_o_reg <= qsfp3_i2c_sda_o;
|
||||
end
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(19),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.in({uart_rxd, eeprom_i2c_scl, eeprom_i2c_sda,
|
||||
qsfp0_modprsl, qsfp0_intl, qsfp0_i2c_scl, qsfp0_i2c_sda,
|
||||
qsfp1_modprsl, qsfp1_intl, qsfp1_i2c_scl, qsfp1_i2c_sda,
|
||||
qsfp2_modprsl, qsfp2_intl, qsfp2_i2c_scl, qsfp2_i2c_sda,
|
||||
qsfp3_modprsl, qsfp3_intl, qsfp3_i2c_scl, qsfp3_i2c_sda}),
|
||||
.out({uart_rxd_int, eeprom_i2c_scl_i, eeprom_i2c_sda_i,
|
||||
qsfp0_modprsl_int, qsfp0_intl_int, qsfp0_i2c_scl_i, qsfp0_i2c_sda_i,
|
||||
qsfp1_modprsl_int, qsfp1_intl_int, qsfp1_i2c_scl_i, qsfp1_i2c_sda_i,
|
||||
qsfp2_modprsl_int, qsfp2_intl_int, qsfp2_i2c_scl_i, qsfp2_i2c_sda_i,
|
||||
qsfp3_modprsl_int, qsfp3_intl_int, qsfp3_i2c_scl_i, qsfp3_i2c_sda_i})
|
||||
);
|
||||
|
||||
assign eeprom_i2c_scl = eeprom_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign eeprom_i2c_sda = eeprom_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp0_i2c_scl = qsfp0_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp0_i2c_sda = qsfp0_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp1_i2c_scl = qsfp1_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp1_i2c_sda = qsfp1_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp2_i2c_scl = qsfp2_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp2_i2c_sda = qsfp2_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
assign qsfp3_i2c_scl = qsfp3_i2c_scl_o_reg ? 1'bz : 1'b0;
|
||||
assign qsfp3_i2c_sda = qsfp3_i2c_sda_o_reg ? 1'bz : 1'b0;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.led(led),
|
||||
|
||||
/*
|
||||
* UART: 3000000 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd_int),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
.eeprom_i2c_scl_i(eeprom_i2c_scl_i),
|
||||
.eeprom_i2c_scl_o(eeprom_i2c_scl_o),
|
||||
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
|
||||
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.qsfp0_tx_p(qsfp0_tx_p),
|
||||
.qsfp0_tx_n(qsfp0_tx_n),
|
||||
.qsfp0_rx_p(qsfp0_rx_p),
|
||||
.qsfp0_rx_n(qsfp0_rx_n),
|
||||
.qsfp0_mgt_refclk_b0_p(qsfp0_mgt_refclk_b0_p),
|
||||
.qsfp0_mgt_refclk_b0_n(qsfp0_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp0_modprsl(qsfp0_modprsl_int),
|
||||
.qsfp0_resetl(qsfp0_resetl),
|
||||
.qsfp0_intl(qsfp0_intl_int),
|
||||
.qsfp0_lpmode(qsfp0_lpmode),
|
||||
|
||||
.qsfp0_i2c_scl_i(qsfp0_i2c_scl_i),
|
||||
.qsfp0_i2c_scl_o(qsfp0_i2c_scl_o),
|
||||
.qsfp0_i2c_sda_i(qsfp0_i2c_sda_i),
|
||||
.qsfp0_i2c_sda_o(qsfp0_i2c_sda_o),
|
||||
|
||||
.qsfp1_tx_p(qsfp1_tx_p),
|
||||
.qsfp1_tx_n(qsfp1_tx_n),
|
||||
.qsfp1_rx_p(qsfp1_rx_p),
|
||||
.qsfp1_rx_n(qsfp1_rx_n),
|
||||
.qsfp1_mgt_refclk_b0_p(qsfp1_mgt_refclk_b0_p),
|
||||
.qsfp1_mgt_refclk_b0_n(qsfp1_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp1_modprsl(qsfp1_modprsl_int),
|
||||
.qsfp1_resetl(qsfp1_resetl),
|
||||
.qsfp1_intl(qsfp1_intl_int),
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
.qsfp1_i2c_scl_i(qsfp1_i2c_scl_i),
|
||||
.qsfp1_i2c_scl_o(qsfp1_i2c_scl_o),
|
||||
.qsfp1_i2c_sda_i(qsfp1_i2c_sda_i),
|
||||
.qsfp1_i2c_sda_o(qsfp1_i2c_sda_o),
|
||||
|
||||
.qsfp2_tx_p(qsfp2_tx_p),
|
||||
.qsfp2_tx_n(qsfp2_tx_n),
|
||||
.qsfp2_rx_p(qsfp2_rx_p),
|
||||
.qsfp2_rx_n(qsfp2_rx_n),
|
||||
.qsfp2_mgt_refclk_b0_p(qsfp2_mgt_refclk_b0_p),
|
||||
.qsfp2_mgt_refclk_b0_n(qsfp2_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp2_modprsl(qsfp2_modprsl_int),
|
||||
.qsfp2_resetl(qsfp2_resetl),
|
||||
.qsfp2_intl(qsfp2_intl_int),
|
||||
.qsfp2_lpmode(qsfp2_lpmode),
|
||||
|
||||
.qsfp2_i2c_scl_i(qsfp2_i2c_scl_i),
|
||||
.qsfp2_i2c_scl_o(qsfp2_i2c_scl_o),
|
||||
.qsfp2_i2c_sda_i(qsfp2_i2c_sda_i),
|
||||
.qsfp2_i2c_sda_o(qsfp2_i2c_sda_o),
|
||||
|
||||
.qsfp3_tx_p(qsfp3_tx_p),
|
||||
.qsfp3_tx_n(qsfp3_tx_n),
|
||||
.qsfp3_rx_p(qsfp3_rx_p),
|
||||
.qsfp3_rx_n(qsfp3_rx_n),
|
||||
.qsfp3_mgt_refclk_b0_p(qsfp3_mgt_refclk_b0_p),
|
||||
.qsfp3_mgt_refclk_b0_n(qsfp3_mgt_refclk_b0_n),
|
||||
|
||||
.qsfp3_modprsl(qsfp3_modprsl_int),
|
||||
.qsfp3_resetl(qsfp3_resetl),
|
||||
.qsfp3_intl(qsfp3_intl_int),
|
||||
.qsfp3_lpmode(qsfp3_lpmode),
|
||||
|
||||
.qsfp3_i2c_scl_i(qsfp3_i2c_scl_i),
|
||||
.qsfp3_i2c_scl_o(qsfp3_i2c_scl_o),
|
||||
.qsfp3_i2c_sda_i(qsfp3_i2c_sda_i),
|
||||
.qsfp3_i2c_sda_o(qsfp3_i2c_sda_o)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
54
example/XUPP3R/fpga/tb/fpga_core/Makefile
Normal file
54
example/XUPP3R/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).sv
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"virtexuplus\""
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
example/XUPP3R/fpga/tb/fpga_core/baser.py
Symbolic link
1
example/XUPP3R/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/tb/eth/baser.py
|
||||
202
example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
Normal file
202
example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,202 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Combine
|
||||
|
||||
from cocotbext.eth import XgmiiFrame
|
||||
from cocotbext.uart import UartSource, UartSink
|
||||
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut, speed=1000e6):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp0_mgt_refclk_b0_p, 3.102, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp1_mgt_refclk_b0_p, 3.102, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp2_mgt_refclk_b0_p, 3.102, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp3_mgt_refclk_b0_p, 3.102, units="ns").start())
|
||||
|
||||
self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
|
||||
self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)
|
||||
|
||||
self.qsfp_sources = []
|
||||
self.qsfp_sinks = []
|
||||
|
||||
for inst in dut.gty_quad:
|
||||
for ch in inst.mac_inst.ch:
|
||||
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.tx_clk, 2.56, units="ns").start())
|
||||
cocotb.start_soon(Clock(ch.ch_inst.gt_inst.rx_clk, 2.56, units="ns").start())
|
||||
|
||||
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.gt_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
|
||||
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.gt_inst.tx_clk, reverse=True))
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst_125mhz.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 0
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
|
||||
async def mac_test(tb, source, sink):
|
||||
tb.log.info("Test MAC")
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 32
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("MAC test done")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tests = []
|
||||
|
||||
tb.log.info("Start BASE-T MAC loopback test")
|
||||
|
||||
for k in range(len(tb.qsfp_sources)):
|
||||
tb.log.info("Start QSFP %d MAC loopback test", k)
|
||||
|
||||
tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
|
||||
|
||||
await Combine(*tests)
|
||||
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = "1'b1"
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"virtexuplus\""
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Reference in New Issue
Block a user