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hip: Integrate usrclk active logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-08-07 23:20:27 -07:00
parent 7132d1817a
commit 89bb672524
2 changed files with 33 additions and 9 deletions
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22
src/hip/rtl/us/taxi_gt_rx_reset.sv
View File

@@ -17,9 +17,9 @@ Authors:
*/
module taxi_gt_rx_reset #
(
parameter GT_RX_PD = 1'b0,
parameter GT_RX_QPLL_SEL = 1'b0,
parameter GT_RX_LPM_EN = 1'b0,
parameter logic GT_RX_PD = 1'b0,
parameter logic GT_RX_QPLL_SEL = 1'b0,
parameter logic GT_RX_LPM_EN = 1'b0,
parameter CNT_W = 8,
parameter CDR_CNT_W = 20
)
@@ -34,7 +34,7 @@ module taxi_gt_rx_reset #
output wire logic gt_rx_pd_out,
output wire logic gt_rx_reset_out,
input wire logic gt_rx_reset_done_in,
input wire logic gt_userclk_rx_active_in,
output wire logic gt_userclk_rx_active_out,
output wire logic gt_rx_pma_reset_out,
output wire logic gt_rx_dfe_lpm_reset_out,
output wire logic gt_rx_eyescan_reset_out,
@@ -79,6 +79,18 @@ logic gt_rx_pd_reg = GT_RX_PD;
logic gt_rx_qpll_sel_reg = GT_RX_QPLL_SEL;
logic gt_rx_lpm_en_reg = GT_RX_LPM_EN;
wire gt_userclk_rx_active_n;
assign gt_userclk_rx_active_out = !gt_userclk_rx_active_n;
taxi_sync_reset #(
.N(4)
)
gt_userclk_rx_active_sync_inst (
.clk(gt_rxusrclk2),
.rst(gt_rx_reset_reg),
.out(gt_userclk_rx_active_n)
);
wire gt_rx_reset_done_sync;
wire gt_rx_pma_reset_done_sync;
wire gt_rx_prgdiv_reset_done_sync;
@@ -91,7 +103,7 @@ taxi_sync_signal #(
)
gt_status_sync_inst (
.clk(clk),
.in({gt_rx_reset_done_in, gt_rx_pma_reset_done_in, gt_rx_prgdiv_reset_done_in, gt_userclk_rx_active_in, gt_rx_cdr_lock_in}),
.in({gt_rx_reset_done_in, gt_rx_pma_reset_done_in, gt_rx_prgdiv_reset_done_in, gt_userclk_rx_active_out, gt_rx_cdr_lock_in}),
.out({gt_rx_reset_done_sync, gt_rx_pma_reset_done_sync, gt_rx_prgdiv_reset_done_sync, gt_userclk_rx_active_sync, gt_rx_cdr_lock_sync})
);

20
src/hip/rtl/us/taxi_gt_tx_reset.sv
View File

@@ -17,8 +17,8 @@ Authors:
*/
module taxi_gt_tx_reset #
(
parameter GT_TX_PD = 1'b0,
parameter GT_TX_QPLL_SEL = 1'b0,
parameter logic GT_TX_PD = 1'b0,
parameter logic GT_TX_QPLL_SEL = 1'b0,
parameter CNT_W = 8
)
(
@@ -32,7 +32,7 @@ module taxi_gt_tx_reset #
output wire logic gt_tx_pd_out,
output wire logic gt_tx_reset_out,
input wire logic gt_tx_reset_done_in,
input wire logic gt_userclk_tx_active_in,
output wire logic gt_userclk_tx_active_out,
output wire logic gt_tx_pma_reset_out,
output wire logic gt_tx_pcs_reset_out,
input wire logic gt_tx_pma_reset_done_in,
@@ -67,6 +67,18 @@ logic gt_tx_pd_reg = GT_TX_PD;
logic gt_tx_qpll_sel_reg = GT_TX_QPLL_SEL;
wire gt_userclk_tx_active_n;
assign gt_userclk_tx_active_out = !gt_userclk_tx_active_n;
taxi_sync_reset #(
.N(4)
)
gt_userclk_tx_active_sync_inst (
.clk(gt_txusrclk2),
.rst(gt_tx_reset_reg),
.out(gt_userclk_tx_active_n)
);
wire gt_tx_reset_done_sync;
wire gt_tx_pma_reset_done_sync;
wire gt_tx_prgdiv_reset_done_sync;
@@ -78,7 +90,7 @@ taxi_sync_signal #(
)
gt_status_sync_inst (
.clk(clk),
.in({gt_tx_reset_done_in, gt_tx_pma_reset_done_in, gt_tx_prgdiv_reset_done_in, gt_userclk_tx_active_in}),
.in({gt_tx_reset_done_in, gt_tx_pma_reset_done_in, gt_tx_prgdiv_reset_done_in, gt_userclk_tx_active_out}),
.out({gt_tx_reset_done_sync, gt_tx_pma_reset_done_sync, gt_tx_prgdiv_reset_done_sync, gt_userclk_tx_active_sync})
);