eth: Add reset logic, QPLL control signals, and additional configuration parameters for US/US+ GTH/GTY transceivers

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv

@@ -170,9 +170,19 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
          */
         .xcvr_gtpowergood_out(qsfp_gtpowergood[n]),
         .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(qsfp_0_mgt_refclk),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py

@@ -77,6 +77,10 @@ class TB:
 async def mac_test(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64

src/eth/example/Alveo/fpga/rtl/fpga_core.sv

@@ -330,9 +330,19 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
          */
         .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
         .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py

@@ -93,6 +93,10 @@ class TB:
 async def mac_test(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64

src/eth/example/KCU105/fpga/rtl/fpga_core.sv

@@ -567,9 +567,19 @@ end else begin : sfp_mac
          */
         .xcvr_gtpowergood_out(sfp_gtpowergood),
         .xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(sfp_mgt_refclk_0),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py

@@ -159,9 +159,13 @@ async def mac_test(tb, source, sink):
     tb.log.info("MAC test done")
 
 
-async def mac_test_25g(tb, source, sink):
+async def mac_test_10g(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk)
+
     tb.log.info("Multiple small packets")
 
     count = 64
@@ -218,7 +222,7 @@ async def run_test(dut):
             tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
         else:
             tb.log.info("Start SFP %d 10G MAC loopback test", k)
-            tests.append(cocotb.start_soon(mac_test_25g(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
+            tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
 
     await Combine(*tests)
 

src/eth/example/KR260/fpga/rtl/fpga_core.sv

@@ -427,9 +427,19 @@ end else begin : sfp_mac
          */
         .xcvr_gtpowergood_out(sfp_gtpowergood),
         .xcvr_gtrefclk00_in(sfp_mgt_refclk),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(sfp_mgt_refclk),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py

@@ -143,9 +143,13 @@ async def mac_test(tb, source, sink):
     tb.log.info("MAC test done")
 
 
-async def mac_test_25g(tb, source, sink):
+async def mac_test_10g(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk)
+
     tb.log.info("Multiple small packets")
 
     count = 64
@@ -205,7 +209,7 @@ async def run_test(dut):
         tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_source, tb.sfp_sink)))
     else:
         tb.log.info("Start 10G SFP MAC loopback test")
-        tests.append(cocotb.start_soon(mac_test_25g(tb, tb.sfp_source, tb.sfp_sink)))
+        tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_source, tb.sfp_sink)))
 
     await Combine(*tests)
 

src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv

@@ -189,9 +189,19 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
          */
         .xcvr_gtpowergood_out(qsfp_gtpowergood[n]),
         .xcvr_gtrefclk00_in(qsfp_mgt_refclk),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(qsfp_mgt_refclk),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py

@@ -80,6 +80,10 @@ class TB:
 async def mac_test(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64

src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv

@@ -170,9 +170,19 @@ sfp_mac_inst (
      */
     .xcvr_gtpowergood_out(sfp_gtpowergood),
     .xcvr_gtrefclk00_in(sfp_mgt_refclk),
+    .xcvr_qpll0pd_in(1'b0),
+    .xcvr_qpll0reset_in(1'b0),
+    .xcvr_qpll0pcierate_in(3'd0),
     .xcvr_qpll0lock_out(),
     .xcvr_qpll0clk_out(),
     .xcvr_qpll0refclk_out(),
+    .xcvr_gtrefclk01_in(sfp_mgt_refclk),
+    .xcvr_qpll1pd_in(1'b0),
+    .xcvr_qpll1reset_in(1'b0),
+    .xcvr_qpll1pcierate_in(3'd0),
+    .xcvr_qpll1lock_out(),
+    .xcvr_qpll1clk_out(),
+    .xcvr_qpll1refclk_out(),
 
     /*
      * Serial data

src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py

@@ -77,6 +77,10 @@ class TB:
 async def mac_test(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64

src/eth/example/VCU108/fpga/rtl/fpga_core.sv

@@ -379,9 +379,19 @@ qsfp_mac_inst (
      */
     .xcvr_gtpowergood_out(qsfp_gtpowergood),
     .xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
+    .xcvr_qpll0pd_in(1'b0),
+    .xcvr_qpll0reset_in(1'b0),
+    .xcvr_qpll0pcierate_in(3'd0),
     .xcvr_qpll0lock_out(),
     .xcvr_qpll0clk_out(),
     .xcvr_qpll0refclk_out(),
+    .xcvr_gtrefclk01_in(qsfp_mgt_refclk_0),
+    .xcvr_qpll1pd_in(1'b0),
+    .xcvr_qpll1reset_in(1'b0),
+    .xcvr_qpll1pcierate_in(3'd0),
+    .xcvr_qpll1lock_out(),
+    .xcvr_qpll1clk_out(),
+    .xcvr_qpll1refclk_out(),
 
     /*
      * Serial data

src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py

@@ -140,6 +140,10 @@ async def mac_test(tb, source, sink):
 async def mac_test_25g(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk)
+
     tb.log.info("Multiple small packets")
 
     count = 64

src/eth/example/VCU118/fpga/rtl/fpga_core.sv

@@ -575,9 +575,19 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
          */
         .xcvr_gtpowergood_out(qsfp_gtpowergood[n]),
         .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(qsfp1_mgt_refclk_0),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py

@@ -141,6 +141,10 @@ async def mac_test(tb, source, sink):
 async def mac_test_25g(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64

src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv

@@ -388,9 +388,19 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
          */
         .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
         .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[n]),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[n]),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py

@@ -82,6 +82,10 @@ class TB:
 async def mac_test(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64

src/eth/example/ZCU102/fpga/rtl/fpga_core.sv

@@ -653,9 +653,19 @@ end else begin : sfp_mac
          */
         .xcvr_gtpowergood_out(sfp_gtpowergood),
         .xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(sfp_mgt_refclk_0),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py

@@ -166,9 +166,13 @@ async def mac_test(tb, source, sink):
     tb.log.info("MAC test done")
 
 
-async def mac_test_25g(tb, source, sink):
+async def mac_test_10g(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64
@@ -221,7 +225,7 @@ async def run_test(dut):
             tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
         else:
             tb.log.info("Start SFP %d 10G MAC loopback test", k)
-            tests.append(cocotb.start_soon(mac_test_25g(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
+            tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
 
     await Combine(*tests)
 

src/eth/example/ZCU106/fpga/rtl/fpga_core.sv

@@ -464,9 +464,19 @@ end else begin : sfp_mac
          */
         .xcvr_gtpowergood_out(sfp_gtpowergood),
         .xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(sfp_mgt_refclk_0),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py

@@ -148,9 +148,13 @@ async def mac_test(tb, source, sink):
     tb.log.info("MAC test done")
 
 
-async def mac_test_25g(tb, source, sink):
+async def mac_test_10g(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64
@@ -203,7 +207,7 @@ async def run_test(dut):
             tests.append(cocotb.start_soon(mac_test(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
         else:
             tb.log.info("Start SFP %d 10G MAC loopback test", k)
-            tests.append(cocotb.start_soon(mac_test_25g(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
+            tests.append(cocotb.start_soon(mac_test_10g(tb, tb.sfp_sources[k], tb.sfp_sinks[k])))
 
     await Combine(*tests)
 

src/eth/example/ZCU111/fpga/rtl/fpga_core.sv

@@ -267,9 +267,19 @@ sfp_mac_inst (
      */
     .xcvr_gtpowergood_out(sfp_gtpowergood),
     .xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
+    .xcvr_qpll0pd_in(1'b0),
+    .xcvr_qpll0reset_in(1'b0),
+    .xcvr_qpll0pcierate_in(3'd0),
     .xcvr_qpll0lock_out(),
     .xcvr_qpll0clk_out(),
     .xcvr_qpll0refclk_out(),
+    .xcvr_gtrefclk01_in(sfp_mgt_refclk_0),
+    .xcvr_qpll1pd_in(1'b0),
+    .xcvr_qpll1reset_in(1'b0),
+    .xcvr_qpll1pcierate_in(3'd0),
+    .xcvr_qpll1lock_out(),
+    .xcvr_qpll1clk_out(),
+    .xcvr_qpll1refclk_out(),
 
     /*
      * Serial data

src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py

@@ -87,6 +87,10 @@ class TB:
 async def mac_test(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64

src/eth/example/fb2CG/fpga/rtl/fpga_core.sv

@@ -210,9 +210,19 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
          */
         .xcvr_gtpowergood_out(qsfp_gtpowergood[n]),
         .xcvr_gtrefclk00_in(qsfp_mgt_refclk[CLK]),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(qsfp_mgt_refclk[CLK]),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py

@@ -81,6 +81,10 @@ class TB:
 async def mac_test(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64