eth: Add reset logic, QPLL control signals, and additional configuration parameters for US/US+ GTH/GTY transceivers

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/example/Alveo/fpga/rtl/fpga_core.sv

@@ -330,9 +330,19 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
          */
         .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]),
         .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]),
+        .xcvr_qpll0pd_in(1'b0),
+        .xcvr_qpll0reset_in(1'b0),
+        .xcvr_qpll0pcierate_in(3'd0),
         .xcvr_qpll0lock_out(),
         .xcvr_qpll0clk_out(),
         .xcvr_qpll0refclk_out(),
+        .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]),
+        .xcvr_qpll1pd_in(1'b0),
+        .xcvr_qpll1reset_in(1'b0),
+        .xcvr_qpll1pcierate_in(3'd0),
+        .xcvr_qpll1lock_out(),
+        .xcvr_qpll1clk_out(),
+        .xcvr_qpll1refclk_out(),
 
         /*
          * Serial data

src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py

@@ -93,6 +93,10 @@ class TB:
 async def mac_test(tb, source, sink):
     tb.log.info("Test MAC")
 
+    tb.log.info("Wait for block lock")
+    for k in range(1200):
+        await RisingEdge(tb.dut.clk_125mhz)
+
     tb.log.info("Multiple small packets")
 
     count = 64