mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-09 17:08:38 -08:00
eth: Add reset logic, QPLL control signals, and additional configuration parameters for US/US+ GTH/GTY transceivers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
83
src/hip/rtl/us/taxi_gt_qpll_reset.sv
Normal file
83
src/hip/rtl/us/taxi_gt_qpll_reset.sv
Normal file
@@ -0,0 +1,83 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* GT QPLL reset controller for UltraScale/UltraScale+ GTH/GTY
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*/
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module taxi_gt_qpll_reset #
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(
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parameter logic QPLL_PD = 1'b0,
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parameter CNT_W = 8
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* GT
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*/
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output wire logic gt_qpll_reset_out,
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output wire logic gt_qpll_pd_out,
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input wire logic gt_qpll_lock_in,
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/*
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* Control/status
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*/
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input wire logic qpll_reset_in = 1'b0,
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input wire logic qpll_pd_in = QPLL_PD,
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output wire logic qpll_lock_out
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);
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logic qpll_reset_reg = 1'b1;
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logic qpll_pd_reg = QPLL_PD;
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logic [CNT_W-1:0] qpll_reset_cnt_reg = '0;
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assign gt_qpll_reset_out = qpll_reset_reg;
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assign gt_qpll_pd_out = qpll_pd_reg;
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always_ff @(posedge clk) begin
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qpll_pd_reg <= qpll_pd_in;
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if (&qpll_reset_cnt_reg) begin
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qpll_reset_reg <= 1'b0;
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end else begin
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qpll_reset_cnt_reg <= qpll_reset_cnt_reg + 1;
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qpll_reset_reg <= 1'b1;
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end
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if (qpll_reset_in || qpll_pd_reg) begin
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qpll_reset_cnt_reg <= 0;
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end
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if (rst) begin
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qpll_reset_reg <= 1'b1;
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qpll_pd_reg <= QPLL_PD;
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qpll_reset_cnt_reg <= '0;
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end
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end
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taxi_sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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qpll_lock_sync_inst (
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.clk(clk),
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.in(gt_qpll_lock_in),
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.out(qpll_lock_out)
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);
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endmodule
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`resetall
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253
src/hip/rtl/us/taxi_gt_rx_reset.sv
Normal file
253
src/hip/rtl/us/taxi_gt_rx_reset.sv
Normal file
@@ -0,0 +1,253 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* GT RX reset controller for UltraScale/UltraScale+ GTH/GTY
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*/
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module taxi_gt_rx_reset #
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(
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parameter GT_RX_PD = 1'b0,
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parameter GT_RX_QPLL_SEL = 1'b0,
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parameter GT_RX_LPM_EN = 1'b0,
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parameter CNT_W = 8,
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parameter CDR_CNT_W = 20
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* GT
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*/
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output wire logic gt_rx_pd_out,
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output wire logic gt_rx_reset_out,
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input wire logic gt_rx_reset_done_in,
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input wire logic gt_userclk_rx_active_in,
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output wire logic gt_rx_pma_reset_out,
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output wire logic gt_rx_dfe_lpm_reset_out,
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output wire logic gt_rx_eyescan_reset_out,
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output wire logic gt_rx_pcs_reset_out,
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input wire logic gt_rx_pma_reset_done_in,
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output wire logic gt_rx_prgdiv_reset_out,
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input wire logic gt_rx_prgdiv_reset_done_in,
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output wire logic gt_rx_qpll_sel_out,
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output wire logic gt_rx_userrdy_out,
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input wire logic gt_rx_cdr_lock_in,
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output wire logic gt_rx_lpm_en_out,
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/*
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* Control/status
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*/
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input wire logic qpll0_lock_in,
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input wire logic qpll1_lock_in,
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input wire logic rx_reset_in = 1'b0,
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output wire logic rx_reset_done_out,
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input wire logic rx_pma_reset_in = 1'b0,
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output wire logic rx_pma_reset_done_out,
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output wire logic rx_prgdiv_reset_done_out,
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input wire logic rx_pcs_reset_in = 1'b0,
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input wire logic rx_dfe_lpm_reset_in = 1'b0,
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input wire logic eyescan_reset_in = 1'b0,
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input wire logic rx_pd_in = GT_RX_PD,
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input wire logic rx_qpll_sel_in = GT_RX_QPLL_SEL,
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input wire logic rx_lpm_en_in = GT_RX_LPM_EN
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);
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logic gt_rx_reset_reg = 1'b1;
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logic gt_rx_pma_reset_reg = 1'b0;
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logic gt_rx_pcs_reset_reg = 1'b0;
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logic gt_rx_dfe_lpm_reset_reg = 1'b0;
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logic gt_eyescan_reset_reg = 1'b0;
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logic gt_rx_prgdiv_reset_reg = 1'b0;
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logic gt_rx_userrdy_reg = 1'b0;
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logic gt_rx_pd_reg = GT_RX_PD;
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logic gt_rx_qpll_sel_reg = GT_RX_QPLL_SEL;
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logic gt_rx_lpm_en_reg = GT_RX_LPM_EN;
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wire gt_rx_reset_done_sync;
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wire gt_rx_pma_reset_done_sync;
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wire gt_rx_prgdiv_reset_done_sync;
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wire gt_userclk_rx_active_sync;
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wire gt_rx_cdr_lock_sync;
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taxi_sync_signal #(
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.WIDTH(5),
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.N(2)
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)
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gt_status_sync_inst (
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.clk(clk),
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.in({gt_rx_reset_done_in, gt_rx_pma_reset_done_in, gt_rx_prgdiv_reset_done_in, gt_userclk_rx_active_in, gt_rx_cdr_lock_in}),
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.out({gt_rx_reset_done_sync, gt_rx_pma_reset_done_sync, gt_rx_prgdiv_reset_done_sync, gt_userclk_rx_active_sync, gt_rx_cdr_lock_sync})
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);
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wire rx_reset_sync;
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taxi_sync_reset #(
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.N(4)
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)
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reset_sync_inst (
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.clk(clk),
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.rst(rx_reset_in),
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.out(rx_reset_sync)
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);
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localparam [2:0]
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STATE_RESET = 3'd0,
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STATE_WAIT_LOCK = 3'd1,
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STATE_WAIT_CDR = 3'd2,
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STATE_WAIT_USRCLK = 3'd3,
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STATE_DONE = 3'd4;
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logic [2:0] state_reg = STATE_RESET;
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logic [CNT_W-1:0] rx_reset_cnt_reg = '0;
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logic [CDR_CNT_W-1:0] rx_reset_cdr_cnt_reg = '0;
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logic rx_reset_done_reg = 1'b0;
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assign rx_reset_done_out = rx_reset_done_reg;
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assign gt_rx_pd_out = gt_rx_pd_reg;
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assign gt_rx_reset_out = gt_rx_reset_reg;
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assign gt_rx_pma_reset_out = gt_rx_pma_reset_reg;
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assign gt_rx_dfe_lpm_reset_out = gt_rx_dfe_lpm_reset_reg;
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assign gt_rx_eyescan_reset_out = gt_eyescan_reset_reg;
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assign gt_rx_pcs_reset_out = gt_rx_pcs_reset_reg;
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assign gt_rx_prgdiv_reset_out = gt_rx_prgdiv_reset_reg;
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assign gt_rx_qpll_sel_out = gt_rx_qpll_sel_reg;
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assign gt_rx_userrdy_out = gt_rx_userrdy_reg;
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assign gt_rx_lpm_en_out = gt_rx_lpm_en_reg;
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assign rx_reset_done_out = rx_reset_done_reg;
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assign rx_pma_reset_done_out = gt_rx_pma_reset_done_sync;
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assign rx_prgdiv_reset_done_out = gt_rx_prgdiv_reset_done_sync;
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wire rx_sel_pll_lock = gt_rx_qpll_sel_reg ? qpll1_lock_in : qpll0_lock_in;
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always_ff @(posedge clk) begin
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gt_rx_reset_reg <= 1'b1;
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gt_rx_pma_reset_reg <= rx_pma_reset_in;
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gt_rx_pcs_reset_reg <= rx_pcs_reset_in;
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gt_rx_dfe_lpm_reset_reg <= rx_dfe_lpm_reset_in;
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gt_eyescan_reset_reg <= eyescan_reset_in;
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gt_rx_prgdiv_reset_reg <= 1'b1;
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gt_rx_userrdy_reg <= 1'b0;
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state_reg <= STATE_RESET;
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rx_reset_cnt_reg <= '0;
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rx_reset_cdr_cnt_reg <= '0;
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rx_reset_done_reg <= 1'b0;
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case (state_reg)
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STATE_RESET: begin
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gt_rx_reset_reg <= 1'b1;
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gt_rx_prgdiv_reset_reg <= 1'b1;
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gt_rx_userrdy_reg <= 1'b0;
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gt_rx_pd_reg <= rx_pd_in;
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gt_rx_qpll_sel_reg <= rx_qpll_sel_in;
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gt_rx_lpm_en_reg <= rx_lpm_en_in;
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state_reg <= STATE_WAIT_LOCK;
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end
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STATE_WAIT_LOCK: begin
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gt_rx_reset_reg <= 1'b1;
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gt_rx_prgdiv_reset_reg <= 1'b1;
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gt_rx_userrdy_reg <= 1'b0;
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state_reg <= STATE_WAIT_LOCK;
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if (rx_sel_pll_lock) begin
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// QPLL locked
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rx_reset_cnt_reg <= rx_reset_cnt_reg + 1;
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if (&rx_reset_cnt_reg) begin
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state_reg <= STATE_WAIT_CDR;
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end
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end
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end
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STATE_WAIT_CDR: begin
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gt_rx_reset_reg <= 1'b0;
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gt_rx_prgdiv_reset_reg <= 1'b1;
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gt_rx_userrdy_reg <= 1'b0;
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state_reg <= STATE_WAIT_CDR;
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rx_reset_cdr_cnt_reg <= rx_reset_cdr_cnt_reg + 1;
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if (&rx_reset_cdr_cnt_reg) begin
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state_reg <= STATE_WAIT_USRCLK;
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end
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if (gt_rx_cdr_lock_sync) begin
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// CDR locked
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rx_reset_cnt_reg <= rx_reset_cnt_reg + 1;
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if (&rx_reset_cnt_reg) begin
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state_reg <= STATE_WAIT_USRCLK;
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end
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end
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end
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STATE_WAIT_USRCLK: begin
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gt_rx_reset_reg <= 1'b0;
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gt_rx_prgdiv_reset_reg <= 1'b0;
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gt_rx_userrdy_reg <= 1'b0;
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state_reg <= STATE_WAIT_USRCLK;
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if (gt_userclk_rx_active_sync) begin
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// user clock running
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rx_reset_cnt_reg <= rx_reset_cnt_reg + 1;
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if (&rx_reset_cnt_reg) begin
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state_reg <= STATE_DONE;
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end
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end
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end
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STATE_DONE: begin
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gt_rx_reset_reg <= 1'b0;
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gt_rx_prgdiv_reset_reg <= 1'b0;
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gt_rx_userrdy_reg <= 1'b1;
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rx_reset_done_reg <= gt_rx_reset_done_sync && gt_rx_prgdiv_reset_done_sync;
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state_reg <= STATE_DONE;
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end
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default: begin
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state_reg <= STATE_RESET;
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end
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endcase
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if (rx_reset_sync || rx_pd_in || !rx_sel_pll_lock || (gt_rx_qpll_sel_reg != rx_qpll_sel_in) || (gt_rx_lpm_en_reg != rx_lpm_en_in)) begin
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state_reg <= STATE_RESET;
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end
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if (rst) begin
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gt_rx_reset_reg <= 1'b1;
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gt_rx_pma_reset_reg <= 1'b0;
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gt_rx_pcs_reset_reg <= 1'b0;
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gt_rx_dfe_lpm_reset_reg <= 1'b0;
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gt_eyescan_reset_reg <= 1'b0;
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gt_rx_prgdiv_reset_reg <= 1'b1;
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gt_rx_userrdy_reg <= 1'b0;
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gt_rx_pd_reg <= GT_RX_PD;
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gt_rx_qpll_sel_reg <= GT_RX_QPLL_SEL;
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state_reg <= STATE_RESET;
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rx_reset_done_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
|
||||
206
src/hip/rtl/us/taxi_gt_tx_reset.sv
Normal file
206
src/hip/rtl/us/taxi_gt_tx_reset.sv
Normal file
@@ -0,0 +1,206 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* GT TX reset controller for UltraScale/UltraScale+ GTH/GTY
|
||||
*/
|
||||
module taxi_gt_tx_reset #
|
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(
|
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parameter GT_TX_PD = 1'b0,
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parameter GT_TX_QPLL_SEL = 1'b0,
|
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parameter CNT_W = 8
|
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)
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(
|
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input wire logic clk,
|
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input wire logic rst,
|
||||
|
||||
/*
|
||||
* GT
|
||||
*/
|
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output wire logic gt_tx_pd_out,
|
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output wire logic gt_tx_reset_out,
|
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input wire logic gt_tx_reset_done_in,
|
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input wire logic gt_userclk_tx_active_in,
|
||||
output wire logic gt_tx_pma_reset_out,
|
||||
output wire logic gt_tx_pcs_reset_out,
|
||||
input wire logic gt_tx_pma_reset_done_in,
|
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output wire logic gt_tx_prgdiv_reset_out,
|
||||
input wire logic gt_tx_prgdiv_reset_done_in,
|
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output wire logic gt_tx_qpll_sel_out,
|
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output wire logic gt_tx_userrdy_out,
|
||||
|
||||
/*
|
||||
* Control/status
|
||||
*/
|
||||
input wire logic qpll0_lock_in,
|
||||
input wire logic qpll1_lock_in,
|
||||
input wire logic tx_reset_in = 1'b0,
|
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output wire logic tx_reset_done_out,
|
||||
input wire logic tx_pma_reset_in = 1'b0,
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output wire logic tx_pma_reset_done_out,
|
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output wire logic tx_prgdiv_reset_done_out,
|
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input wire logic tx_pcs_reset_in = 1'b0,
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input wire logic tx_pd_in = GT_TX_PD,
|
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input wire logic tx_qpll_sel_in = GT_TX_QPLL_SEL
|
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);
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|
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logic gt_tx_reset_reg = 1'b1;
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logic gt_tx_pma_reset_reg = 1'b0;
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logic gt_tx_pcs_reset_reg = 1'b0;
|
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logic gt_tx_prgdiv_reset_reg = 1'b0;
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logic gt_tx_userrdy_reg = 1'b0;
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|
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logic gt_tx_pd_reg = GT_TX_PD;
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logic gt_tx_qpll_sel_reg = GT_TX_QPLL_SEL;
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wire gt_tx_reset_done_sync;
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wire gt_tx_pma_reset_done_sync;
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wire gt_tx_prgdiv_reset_done_sync;
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wire gt_userclk_tx_active_sync;
|
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|
||||
taxi_sync_signal #(
|
||||
.WIDTH(4),
|
||||
.N(2)
|
||||
)
|
||||
gt_status_sync_inst (
|
||||
.clk(clk),
|
||||
.in({gt_tx_reset_done_in, gt_tx_pma_reset_done_in, gt_tx_prgdiv_reset_done_in, gt_userclk_tx_active_in}),
|
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.out({gt_tx_reset_done_sync, gt_tx_pma_reset_done_sync, gt_tx_prgdiv_reset_done_sync, gt_userclk_tx_active_sync})
|
||||
);
|
||||
|
||||
wire tx_reset_sync;
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
reset_sync_inst (
|
||||
.clk(clk),
|
||||
.rst(tx_reset_in),
|
||||
.out(tx_reset_sync)
|
||||
);
|
||||
|
||||
localparam [1:0]
|
||||
STATE_RESET = 2'd0,
|
||||
STATE_WAIT_LOCK = 2'd1,
|
||||
STATE_WAIT_USRCLK = 2'd2,
|
||||
STATE_DONE = 2'd3;
|
||||
|
||||
logic [1:0] state_reg = STATE_RESET;
|
||||
logic [CNT_W-1:0] tx_reset_cnt_reg = '0;
|
||||
logic tx_reset_done_reg = 1'b0;
|
||||
|
||||
assign gt_tx_pd_out = gt_tx_pd_reg;
|
||||
assign gt_tx_reset_out = gt_tx_reset_reg;
|
||||
assign gt_tx_pma_reset_out = gt_tx_pma_reset_reg;
|
||||
assign gt_tx_pcs_reset_out = gt_tx_pcs_reset_reg;
|
||||
assign gt_tx_prgdiv_reset_out = gt_tx_prgdiv_reset_reg;
|
||||
assign gt_tx_qpll_sel_out = gt_tx_qpll_sel_reg;
|
||||
assign gt_tx_userrdy_out = gt_tx_userrdy_reg;
|
||||
|
||||
assign tx_reset_done_out = tx_reset_done_reg;
|
||||
assign tx_pma_reset_done_out = gt_tx_pma_reset_done_sync;
|
||||
assign tx_prgdiv_reset_done_out = gt_tx_prgdiv_reset_done_sync;
|
||||
|
||||
wire tx_sel_pll_lock = gt_tx_qpll_sel_reg ? qpll1_lock_in : qpll0_lock_in;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
gt_tx_reset_reg <= 1'b1;
|
||||
gt_tx_pma_reset_reg <= tx_pma_reset_in;
|
||||
gt_tx_pcs_reset_reg <= tx_pcs_reset_in;
|
||||
|
||||
gt_tx_prgdiv_reset_reg <= 1'b1;
|
||||
gt_tx_userrdy_reg <= 1'b0;
|
||||
|
||||
state_reg <= STATE_RESET;
|
||||
tx_reset_cnt_reg <= '0;
|
||||
tx_reset_done_reg <= 1'b0;
|
||||
|
||||
case (state_reg)
|
||||
STATE_RESET: begin
|
||||
gt_tx_reset_reg <= 1'b1;
|
||||
gt_tx_prgdiv_reset_reg <= 1'b1;
|
||||
gt_tx_userrdy_reg <= 1'b0;
|
||||
|
||||
gt_tx_pd_reg <= tx_pd_in;
|
||||
gt_tx_qpll_sel_reg <= tx_qpll_sel_in;
|
||||
|
||||
state_reg <= STATE_WAIT_LOCK;
|
||||
end
|
||||
STATE_WAIT_LOCK: begin
|
||||
gt_tx_reset_reg <= 1'b1;
|
||||
gt_tx_prgdiv_reset_reg <= 1'b1;
|
||||
gt_tx_userrdy_reg <= 1'b0;
|
||||
|
||||
state_reg <= STATE_WAIT_LOCK;
|
||||
if (tx_sel_pll_lock) begin
|
||||
// QPLL locked
|
||||
tx_reset_cnt_reg <= tx_reset_cnt_reg + 1;
|
||||
if (&tx_reset_cnt_reg) begin
|
||||
state_reg <= STATE_WAIT_USRCLK;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_WAIT_USRCLK: begin
|
||||
gt_tx_reset_reg <= 1'b0;
|
||||
gt_tx_prgdiv_reset_reg <= 1'b0;
|
||||
gt_tx_userrdy_reg <= 1'b0;
|
||||
|
||||
state_reg <= STATE_WAIT_USRCLK;
|
||||
if (gt_userclk_tx_active_sync) begin
|
||||
// user clock running
|
||||
tx_reset_cnt_reg <= tx_reset_cnt_reg + 1;
|
||||
if (&tx_reset_cnt_reg) begin
|
||||
state_reg <= STATE_DONE;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_DONE: begin
|
||||
gt_tx_reset_reg <= 1'b0;
|
||||
gt_tx_prgdiv_reset_reg <= 1'b0;
|
||||
gt_tx_userrdy_reg <= 1'b1;
|
||||
|
||||
tx_reset_done_reg <= gt_tx_reset_done_sync && gt_tx_prgdiv_reset_done_sync;
|
||||
|
||||
state_reg <= STATE_DONE;
|
||||
end
|
||||
default: begin
|
||||
state_reg <= STATE_RESET;
|
||||
end
|
||||
endcase
|
||||
|
||||
if (tx_reset_sync || tx_pd_in || !tx_sel_pll_lock || (gt_tx_qpll_sel_reg != tx_qpll_sel_in)) begin
|
||||
state_reg <= STATE_RESET;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
gt_tx_reset_reg <= 1'b1;
|
||||
gt_tx_pma_reset_reg <= 1'b0;
|
||||
gt_tx_pcs_reset_reg <= 1'b0;
|
||||
|
||||
gt_tx_prgdiv_reset_reg <= 1'b1;
|
||||
gt_tx_userrdy_reg <= 1'b0;
|
||||
|
||||
gt_tx_pd_reg <= GT_TX_PD;
|
||||
gt_tx_qpll_sel_reg <= GT_TX_QPLL_SEL;
|
||||
|
||||
state_reg <= STATE_RESET;
|
||||
tx_reset_done_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user