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eth: Avoid hardcoding clock period

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-06-13 10:28:53 -07:00
parent 4e66dd0f98
commit 98d06954cc
5 changed files with 8 additions and 8 deletions
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8
src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py
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@@ -145,7 +145,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= 3.2
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
@@ -155,7 +155,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
if gbx_cfg is None:
assert abs(rx_frame_sfd_ns - ptp_ts_ns - 12.8) < 0.01
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01
assert tb.sink.empty()
@@ -222,7 +222,7 @@ async def run_test_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= 3.2
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
@@ -232,7 +232,7 @@ async def run_test_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
if gbx_cfg is None:
assert abs(rx_frame_sfd_ns - ptp_ts_ns - 12.8) < 0.01
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01
start_lane.append(rx_frame.start_lane)

2
src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py
View File

@@ -252,7 +252,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= 3.2
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)

2
src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py
View File

@@ -227,7 +227,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= 3.2
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)

2
src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py
View File

@@ -297,7 +297,7 @@ async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= 3.2
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)

2
src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py
View File

@@ -273,7 +273,7 @@ async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= 3.2
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)