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eth: Avoid hardcoding clock period

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-06-13 10:28:53 -07:00
parent 4e66dd0f98
commit 98d06954cc
5 changed files with 8 additions and 8 deletions
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2
src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py
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@@ -227,7 +227,7 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= 3.2
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)