examples: Add notes on required licenses

Signed-off-by: Alex Forencich <alex@alexforencich.com>

example/Arty/fpga/README.md

@@ -16,6 +16,13 @@ The design places a looped-back MAC on the BASE-T port, as well as a looped-back
 *  FPGA: XC7A35TICSG324-1L
 *  PHY: TI DP83848J via MII
 
+## Licensing
+
+*  Toolchain
+    *  Vivado Standard (enterprise license not required)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
 ## How to build
 
 Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.

example/KC705/fpga/README.md

@@ -21,6 +21,13 @@ The design places looped-back MACs on both the BASE-T port as well as the SFP+ c
 *  1000BASE-T PHY: Marvell 88E1111 via GMII, RGMII, or SGMII
 *  1000BASE-X PHY: Xilinx PCS/PMA core via GTX transceiver
 
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
 ## How to build
 
 Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.

example/KCU105/fpga/README.md

@@ -18,6 +18,13 @@ The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as
 *  FPGA: xcku040-ffva1156-2-e
 *  1000BASE-T PHY: Marvell 88E1111 via SGMII
 
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
 ## How to build
 
 Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.

example/KR260/fpga/README.md

@@ -18,6 +18,13 @@ The design places looped-back MACs on the BASE-T ports and SFP+ cage, as well as
 *  FPGA: xck26-sfvc784-2LV-c
 *  1000BASE-T PHY: Marvell 88E1111 via SGMII
 
+## Licensing
+
+*  Toolchain
+    *  Vivado Standard (enterprise license not required)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
 ## How to build
 
 Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.

example/VCU108/fpga/README.md

@@ -16,6 +16,13 @@ The design places a looped-back MAC on the BASE-T port as well as a looped-back
 *  FPGA: xcvu095-ffva2104-2-e
 *  1000BASE-T PHY: Marvell 88E1111 via SGMII
 
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
 ## How to build
 
 Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.