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examples: Add notes on required licenses
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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@@ -16,6 +16,13 @@ The design places a looped-back MAC on the BASE-T port as well as a looped-back
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* FPGA: xcvu095-ffva2104-2-e
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* 1000BASE-T PHY: Marvell 88E1111 via SGMII
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## Licensing
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* Toolchain
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* Vivado Enterprise (requires license)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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