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example/Alveo: Add XFCP to Alveo example design for monitoring and control

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-04-09 16:05:10 -07:00
parent ecfb50641d
commit a5b7b8031b
22 changed files with 174 additions and 55 deletions
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example/Alveo/fpga/README.md
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@@ -4,10 +4,10 @@
This example design targets the Xilinx Alveo series.
The design places looped-back MACs on the Ethernet ports as well as a looped-back UART on on the USB UART connections.
The design places looped-back MACs on the Ethernet ports, as well as XFCP on the USB UART for monitoring and control.
* USB UART
* Looped-back UART
* XFCP (3 Mbaud)
* DSFP/QSFP28
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
@@ -50,6 +50,4 @@ Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensu
Run `make program` to program the board with Vivado.
To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification.
To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.