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axis: Fix async FIFO timing constraints when using distributed RAM

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-04-09 14:24:12 -07:00
parent 04718790ae
commit ecfb50641d
1 changed files with 1 additions and 1 deletions
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2
syn/vivado/taxi_axis_async_fifo.tcl
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@@ -49,7 +49,7 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_axis_async_fi
}
# output register (needed for distributed RAM sync write/async read)
set output_reg_ffs [get_cells -quiet "$fifo_inst/m_axis_pipe_reg_reg[0][*]"]
set output_reg_ffs [get_cells -quiet "$fifo_inst/mem_rd_data_pipe_reg_reg[0][*]"]
if {[llength $output_reg_ffs]} {
if {[llength $write_clk]} {