bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 00:48:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

axi: Add AXI register module and testbench

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-26 21:08:39 -08:00
parent 1075896ecc
commit ae26b61200
7 changed files with 1609 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
rtl/axi/taxi_axi_register.f Normal file
View File

@@ -0,0 +1,4 @@
taxi_axi_register.sv
taxi_axi_register_wr.sv
taxi_axi_register_rd.sv
taxi_axi_if.sv

94
rtl/axi/taxi_axi_register.sv Normal file
View File

@@ -0,0 +1,94 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 register
*/
module taxi_axi_register #
(
// AW channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter AW_REG_TYPE = 1,
// W channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter W_REG_TYPE = 2,
// B channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter B_REG_TYPE = 1,
// AR channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter AR_REG_TYPE = 1,
// R channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter R_REG_TYPE = 2
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4 slave interface
*/
taxi_axi_if.wr_slv s_axi_wr,
taxi_axi_if.rd_slv s_axi_rd,
/*
* AXI4 master interface
*/
taxi_axi_if.wr_mst m_axi_wr,
taxi_axi_if.rd_mst m_axi_rd
);
taxi_axi_register_wr #(
.AW_REG_TYPE(AW_REG_TYPE),
.W_REG_TYPE(W_REG_TYPE),
.B_REG_TYPE(B_REG_TYPE)
)
axi_register_wr_inst (
.clk(clk),
.rst(rst),
/*
* AXI4 slave interface
*/
.s_axi_wr(s_axi_wr),
/*
* AXI4 master interface
*/
.m_axi_wr(m_axi_wr)
);
taxi_axi_register_rd #(
.AR_REG_TYPE(AR_REG_TYPE),
.R_REG_TYPE(R_REG_TYPE)
)
axi_register_rd_inst (
.clk(clk),
.rst(rst),
/*
* AXI4 slave interface
*/
.s_axi_rd(s_axi_rd),
/*
* AXI4 master interface
*/
.m_axi_rd(m_axi_rd)
);
endmodule
`resetall

472
rtl/axi/taxi_axi_register_rd.sv Normal file
View File

@@ -0,0 +1,472 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 register (read)
*/
module taxi_axi_register_rd #
(
// AR channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter AR_REG_TYPE = 1,
// R channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter R_REG_TYPE = 2
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4 slave interface
*/
taxi_axi_if.rd_slv s_axi_rd,
/*
* AXI4 master interface
*/
taxi_axi_if.rd_mst m_axi_rd
);
// extract parameters
localparam DATA_W = s_axi_rd.DATA_W;
localparam ADDR_W = s_axi_rd.ADDR_W;
localparam STRB_W = s_axi_rd.STRB_W;
localparam ID_W = s_axi_rd.ID_W;
localparam logic ARUSER_EN = s_axi_rd.ARUSER_EN && m_axi_rd.ARUSER_EN;
localparam ARUSER_W = s_axi_rd.ARUSER_W;
localparam logic RUSER_EN = s_axi_rd.RUSER_EN && m_axi_rd.RUSER_EN;
localparam RUSER_W = s_axi_rd.RUSER_W;
if (m_axi_rd.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (m_axi_rd.STRB_W != STRB_W)
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
// AR channel
if (AR_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
logic s_axi_arready_reg = 1'b0;
logic [ID_W-1:0] m_axi_arid_reg = '0;
logic [ADDR_W-1:0] m_axi_araddr_reg = '0;
logic [7:0] m_axi_arlen_reg = '0;
logic [2:0] m_axi_arsize_reg = '0;
logic [1:0] m_axi_arburst_reg = '0;
logic m_axi_arlock_reg = '0;
logic [3:0] m_axi_arcache_reg = '0;
logic [2:0] m_axi_arprot_reg = '0;
logic [3:0] m_axi_arqos_reg = '0;
logic [3:0] m_axi_arregion_reg = '0;
logic [ARUSER_W-1:0] m_axi_aruser_reg = '0;
logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
logic [ID_W-1:0] temp_m_axi_arid_reg = '0;
logic [ADDR_W-1:0] temp_m_axi_araddr_reg = '0;
logic [7:0] temp_m_axi_arlen_reg = '0;
logic [2:0] temp_m_axi_arsize_reg = '0;
logic [1:0] temp_m_axi_arburst_reg = '0;
logic temp_m_axi_arlock_reg = '0;
logic [3:0] temp_m_axi_arcache_reg = '0;
logic [2:0] temp_m_axi_arprot_reg = '0;
logic [3:0] temp_m_axi_arqos_reg = '0;
logic [3:0] temp_m_axi_arregion_reg = '0;
logic [ARUSER_W-1:0] temp_m_axi_aruser_reg = '0;
logic temp_m_axi_arvalid_reg = 1'b0, temp_m_axi_arvalid_next;
// datapath control
logic store_axi_ar_input_to_output;
logic store_axi_ar_input_to_temp;
logic store_axi_ar_temp_to_output;
assign s_axi_rd.arready = s_axi_arready_reg;
assign m_axi_rd.arid = m_axi_arid_reg;
assign m_axi_rd.araddr = m_axi_araddr_reg;
assign m_axi_rd.arlen = m_axi_arlen_reg;
assign m_axi_rd.arsize = m_axi_arsize_reg;
assign m_axi_rd.arburst = m_axi_arburst_reg;
assign m_axi_rd.arlock = m_axi_arlock_reg;
assign m_axi_rd.arcache = m_axi_arcache_reg;
assign m_axi_rd.arprot = m_axi_arprot_reg;
assign m_axi_rd.arqos = m_axi_arqos_reg;
assign m_axi_rd.arregion = m_axi_arregion_reg;
assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0;
assign m_axi_rd.arvalid = m_axi_arvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axi_arready_early = m_axi_rd.arready || (!temp_m_axi_arvalid_reg && (!m_axi_arvalid_reg || !s_axi_rd.arvalid));
always_comb begin
// transfer sink ready state to source
m_axi_arvalid_next = m_axi_arvalid_reg;
temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg;
store_axi_ar_input_to_output = 1'b0;
store_axi_ar_input_to_temp = 1'b0;
store_axi_ar_temp_to_output = 1'b0;
if (s_axi_arready_reg) begin
// input is ready
if (m_axi_rd.arready || !m_axi_arvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axi_arvalid_next = s_axi_rd.arvalid;
store_axi_ar_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axi_arvalid_next = s_axi_rd.arvalid;
store_axi_ar_input_to_temp = 1'b1;
end
end else if (m_axi_rd.arready) begin
// input is not ready, but output is ready
m_axi_arvalid_next = temp_m_axi_arvalid_reg;
temp_m_axi_arvalid_next = 1'b0;
store_axi_ar_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
s_axi_arready_reg <= s_axi_arready_early;
m_axi_arvalid_reg <= m_axi_arvalid_next;
temp_m_axi_arvalid_reg <= temp_m_axi_arvalid_next;
// datapath
if (store_axi_ar_input_to_output) begin
m_axi_arid_reg <= s_axi_rd.arid;
m_axi_araddr_reg <= s_axi_rd.araddr;
m_axi_arlen_reg <= s_axi_rd.arlen;
m_axi_arsize_reg <= s_axi_rd.arsize;
m_axi_arburst_reg <= s_axi_rd.arburst;
m_axi_arlock_reg <= s_axi_rd.arlock;
m_axi_arcache_reg <= s_axi_rd.arcache;
m_axi_arprot_reg <= s_axi_rd.arprot;
m_axi_arqos_reg <= s_axi_rd.arqos;
m_axi_arregion_reg <= s_axi_rd.arregion;
m_axi_aruser_reg <= s_axi_rd.aruser;
end else if (store_axi_ar_temp_to_output) begin
m_axi_arid_reg <= temp_m_axi_arid_reg;
m_axi_araddr_reg <= temp_m_axi_araddr_reg;
m_axi_arlen_reg <= temp_m_axi_arlen_reg;
m_axi_arsize_reg <= temp_m_axi_arsize_reg;
m_axi_arburst_reg <= temp_m_axi_arburst_reg;
m_axi_arlock_reg <= temp_m_axi_arlock_reg;
m_axi_arcache_reg <= temp_m_axi_arcache_reg;
m_axi_arprot_reg <= temp_m_axi_arprot_reg;
m_axi_arqos_reg <= temp_m_axi_arqos_reg;
m_axi_arregion_reg <= temp_m_axi_arregion_reg;
m_axi_aruser_reg <= temp_m_axi_aruser_reg;
end
if (store_axi_ar_input_to_temp) begin
temp_m_axi_arid_reg <= s_axi_rd.arid;
temp_m_axi_araddr_reg <= s_axi_rd.araddr;
temp_m_axi_arlen_reg <= s_axi_rd.arlen;
temp_m_axi_arsize_reg <= s_axi_rd.arsize;
temp_m_axi_arburst_reg <= s_axi_rd.arburst;
temp_m_axi_arlock_reg <= s_axi_rd.arlock;
temp_m_axi_arcache_reg <= s_axi_rd.arcache;
temp_m_axi_arprot_reg <= s_axi_rd.arprot;
temp_m_axi_arqos_reg <= s_axi_rd.arqos;
temp_m_axi_arregion_reg <= s_axi_rd.arregion;
temp_m_axi_aruser_reg <= s_axi_rd.aruser;
end
if (rst) begin
s_axi_arready_reg <= 1'b0;
m_axi_arvalid_reg <= 1'b0;
temp_m_axi_arvalid_reg <= 1'b0;
end
end
end else if (AR_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
logic s_axi_arready_reg = 1'b0;
logic [ID_W-1:0] m_axi_arid_reg = '0;
logic [ADDR_W-1:0] m_axi_araddr_reg = '0;
logic [7:0] m_axi_arlen_reg = '0;
logic [2:0] m_axi_arsize_reg = '0;
logic [1:0] m_axi_arburst_reg = '0;
logic m_axi_arlock_reg = '0;
logic [3:0] m_axi_arcache_reg = '0;
logic [2:0] m_axi_arprot_reg = '0;
logic [3:0] m_axi_arqos_reg = '0;
logic [3:0] m_axi_arregion_reg = '0;
logic [ARUSER_W-1:0] m_axi_aruser_reg = '0;
logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;
// datapath control
logic store_axi_ar_input_to_output;
assign s_axi_rd.arready = s_axi_arready_reg;
assign m_axi_rd.arid = m_axi_arid_reg;
assign m_axi_rd.araddr = m_axi_araddr_reg;
assign m_axi_rd.arlen = m_axi_arlen_reg;
assign m_axi_rd.arsize = m_axi_arsize_reg;
assign m_axi_rd.arburst = m_axi_arburst_reg;
assign m_axi_rd.arlock = m_axi_arlock_reg;
assign m_axi_rd.arcache = m_axi_arcache_reg;
assign m_axi_rd.arprot = m_axi_arprot_reg;
assign m_axi_rd.arqos = m_axi_arqos_reg;
assign m_axi_rd.arregion = m_axi_arregion_reg;
assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0;
assign m_axi_rd.arvalid = m_axi_arvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axi_arready_early = !m_axi_arvalid_next;
always_comb begin
// transfer sink ready state to source
m_axi_arvalid_next = m_axi_arvalid_reg;
store_axi_ar_input_to_output = 1'b0;
if (s_axi_arready_reg) begin
m_axi_arvalid_next = s_axi_rd.arvalid;
store_axi_ar_input_to_output = 1'b1;
end else if (m_axi_rd.arready) begin
m_axi_arvalid_next = 1'b0;
end
end
always_ff @(posedge clk) begin
s_axi_arready_reg <= s_axi_arready_early;
m_axi_arvalid_reg <= m_axi_arvalid_next;
// datapath
if (store_axi_ar_input_to_output) begin
m_axi_arid_reg <= s_axi_rd.arid;
m_axi_araddr_reg <= s_axi_rd.araddr;
m_axi_arlen_reg <= s_axi_rd.arlen;
m_axi_arsize_reg <= s_axi_rd.arsize;
m_axi_arburst_reg <= s_axi_rd.arburst;
m_axi_arlock_reg <= s_axi_rd.arlock;
m_axi_arcache_reg <= s_axi_rd.arcache;
m_axi_arprot_reg <= s_axi_rd.arprot;
m_axi_arqos_reg <= s_axi_rd.arqos;
m_axi_arregion_reg <= s_axi_rd.arregion;
m_axi_aruser_reg <= s_axi_rd.aruser;
end
if (rst) begin
s_axi_arready_reg <= 1'b0;
m_axi_arvalid_reg <= 1'b0;
end
end
end else begin
// bypass AR channel
assign m_axi_rd.arid = s_axi_rd.arid;
assign m_axi_rd.araddr = s_axi_rd.araddr;
assign m_axi_rd.arlen = s_axi_rd.arlen;
assign m_axi_rd.arsize = s_axi_rd.arsize;
assign m_axi_rd.arburst = s_axi_rd.arburst;
assign m_axi_rd.arlock = s_axi_rd.arlock;
assign m_axi_rd.arcache = s_axi_rd.arcache;
assign m_axi_rd.arprot = s_axi_rd.arprot;
assign m_axi_rd.arqos = s_axi_rd.arqos;
assign m_axi_rd.arregion = s_axi_rd.arregion;
assign m_axi_rd.aruser = ARUSER_EN ? s_axi_rd.aruser : '0;
assign m_axi_rd.arvalid = s_axi_rd.arvalid;
assign s_axi_rd.arready = m_axi_rd.arready;
end
// R channel
if (R_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
logic m_axi_rready_reg = 1'b0;
logic [ID_W-1:0] s_axi_rid_reg = '0;
logic [DATA_W-1:0] s_axi_rdata_reg = '0;
logic [1:0] s_axi_rresp_reg = 2'b0;
logic s_axi_rlast_reg = 1'b0;
logic [RUSER_W-1:0] s_axi_ruser_reg = '0;
logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
logic [ID_W-1:0] temp_s_axi_rid_reg = '0;
logic [DATA_W-1:0] temp_s_axi_rdata_reg = '0;
logic [1:0] temp_s_axi_rresp_reg = 2'b0;
logic temp_s_axi_rlast_reg = 1'b0;
logic [RUSER_W-1:0] temp_s_axi_ruser_reg = '0;
logic temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next;
// datapath control
logic store_axi_r_input_to_output;
logic store_axi_r_input_to_temp;
logic store_axi_r_temp_to_output;
assign m_axi_rd.rready = m_axi_rready_reg;
assign s_axi_rd.rid = s_axi_rid_reg;
assign s_axi_rd.rdata = s_axi_rdata_reg;
assign s_axi_rd.rresp = s_axi_rresp_reg;
assign s_axi_rd.rlast = s_axi_rlast_reg;
assign s_axi_rd.ruser = RUSER_EN ? s_axi_ruser_reg : '0;
assign s_axi_rd.rvalid = s_axi_rvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire m_axi_rready_early = s_axi_rd.rready || (!temp_s_axi_rvalid_reg && (!s_axi_rvalid_reg || !m_axi_rd.rvalid));
always_comb begin
// transfer sink ready state to source
s_axi_rvalid_next = s_axi_rvalid_reg;
temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;
store_axi_r_input_to_output = 1'b0;
store_axi_r_input_to_temp = 1'b0;
store_axi_r_temp_to_output = 1'b0;
if (m_axi_rready_reg) begin
// input is ready
if (s_axi_rd.rready || !s_axi_rvalid_reg) begin
// output is ready or currently not valid, transfer data to output
s_axi_rvalid_next = m_axi_rd.rvalid;
store_axi_r_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_s_axi_rvalid_next = m_axi_rd.rvalid;
store_axi_r_input_to_temp = 1'b1;
end
end else if (s_axi_rd.rready) begin
// input is not ready, but output is ready
s_axi_rvalid_next = temp_s_axi_rvalid_reg;
temp_s_axi_rvalid_next = 1'b0;
store_axi_r_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
m_axi_rready_reg <= m_axi_rready_early;
s_axi_rvalid_reg <= s_axi_rvalid_next;
temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;
// datapath
if (store_axi_r_input_to_output) begin
s_axi_rid_reg <= m_axi_rd.rid;
s_axi_rdata_reg <= m_axi_rd.rdata;
s_axi_rresp_reg <= m_axi_rd.rresp;
s_axi_rlast_reg <= m_axi_rd.rlast;
s_axi_ruser_reg <= m_axi_rd.ruser;
end else if (store_axi_r_temp_to_output) begin
s_axi_rid_reg <= temp_s_axi_rid_reg;
s_axi_rdata_reg <= temp_s_axi_rdata_reg;
s_axi_rresp_reg <= temp_s_axi_rresp_reg;
s_axi_rlast_reg <= temp_s_axi_rlast_reg;
s_axi_ruser_reg <= temp_s_axi_ruser_reg;
end
if (store_axi_r_input_to_temp) begin
temp_s_axi_rid_reg <= m_axi_rd.rid;
temp_s_axi_rdata_reg <= m_axi_rd.rdata;
temp_s_axi_rresp_reg <= m_axi_rd.rresp;
temp_s_axi_rlast_reg <= m_axi_rd.rlast;
temp_s_axi_ruser_reg <= m_axi_rd.ruser;
end
if (rst) begin
m_axi_rready_reg <= 1'b0;
s_axi_rvalid_reg <= 1'b0;
temp_s_axi_rvalid_reg <= 1'b0;
end
end
end else if (R_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
logic m_axi_rready_reg = 1'b0;
logic [ID_W-1:0] s_axi_rid_reg = '0;
logic [DATA_W-1:0] s_axi_rdata_reg = '0;
logic [1:0] s_axi_rresp_reg = 2'b0;
logic s_axi_rlast_reg = 1'b0;
logic [RUSER_W-1:0] s_axi_ruser_reg = '0;
logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
// datapath control
logic store_axi_r_input_to_output;
assign m_axi_rd.rready = m_axi_rready_reg;
assign s_axi_rd.rid = s_axi_rid_reg;
assign s_axi_rd.rdata = s_axi_rdata_reg;
assign s_axi_rd.rresp = s_axi_rresp_reg;
assign s_axi_rd.rlast = s_axi_rlast_reg;
assign s_axi_rd.ruser = RUSER_EN ? s_axi_ruser_reg : '0;
assign s_axi_rd.rvalid = s_axi_rvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire m_axi_rready_early = !s_axi_rvalid_next;
always_comb begin
// transfer sink ready state to source
s_axi_rvalid_next = s_axi_rvalid_reg;
store_axi_r_input_to_output = 1'b0;
if (m_axi_rready_reg) begin
s_axi_rvalid_next = m_axi_rd.rvalid;
store_axi_r_input_to_output = 1'b1;
end else if (s_axi_rd.rready) begin
s_axi_rvalid_next = 1'b0;
end
end
always_ff @(posedge clk) begin
m_axi_rready_reg <= m_axi_rready_early;
s_axi_rvalid_reg <= s_axi_rvalid_next;
// datapath
if (store_axi_r_input_to_output) begin
s_axi_rid_reg <= m_axi_rd.rid;
s_axi_rdata_reg <= m_axi_rd.rdata;
s_axi_rresp_reg <= m_axi_rd.rresp;
s_axi_rlast_reg <= m_axi_rd.rlast;
s_axi_ruser_reg <= m_axi_rd.ruser;
end
if (rst) begin
m_axi_rready_reg <= 1'b0;
s_axi_rvalid_reg <= 1'b0;
end
end
end else begin
// bypass R channel
assign s_axi_rd.rid = m_axi_rd.rid;
assign s_axi_rd.rdata = m_axi_rd.rdata;
assign s_axi_rd.rresp = m_axi_rd.rresp;
assign s_axi_rd.rlast = m_axi_rd.rlast;
assign s_axi_rd.ruser = RUSER_EN ? m_axi_rd.ruser : '0;
assign s_axi_rd.rvalid = m_axi_rd.rvalid;
assign m_axi_rd.rready = s_axi_rd.rready;
end
endmodule
`resetall

623
rtl/axi/taxi_axi_register_wr.sv Normal file
View File

@@ -0,0 +1,623 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 register (write)
*/
module taxi_axi_register_wr #
(
// AW channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter AW_REG_TYPE = 1,
// W channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter W_REG_TYPE = 2,
// B channel register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter B_REG_TYPE = 1
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4 slave interface
*/
taxi_axi_if.wr_slv s_axi_wr,
/*
* AXI4 master interface
*/
taxi_axi_if.wr_mst m_axi_wr
);
// extract parameters
localparam DATA_W = s_axi_wr.DATA_W;
localparam ADDR_W = s_axi_wr.ADDR_W;
localparam STRB_W = s_axi_wr.STRB_W;
localparam ID_W = s_axi_wr.ID_W;
localparam logic AWUSER_EN = s_axi_wr.AWUSER_EN && m_axi_wr.AWUSER_EN;
localparam AWUSER_W = s_axi_wr.AWUSER_W;
localparam logic WUSER_EN = s_axi_wr.WUSER_EN && m_axi_wr.WUSER_EN;
localparam WUSER_W = s_axi_wr.WUSER_W;
localparam logic BUSER_EN = s_axi_wr.BUSER_EN && m_axi_wr.BUSER_EN;
localparam BUSER_W = s_axi_wr.BUSER_W;
if (m_axi_wr.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (m_axi_wr.STRB_W != STRB_W)
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
// AW channel
if (AW_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
logic s_axi_awready_reg = 1'b0;
logic [ID_W-1:0] m_axi_awid_reg = '0;
logic [ADDR_W-1:0] m_axi_awaddr_reg = '0;
logic [7:0] m_axi_awlen_reg = '0;
logic [2:0] m_axi_awsize_reg = '0;
logic [1:0] m_axi_awburst_reg = '0;
logic m_axi_awlock_reg = '0;
logic [3:0] m_axi_awcache_reg = '0;
logic [2:0] m_axi_awprot_reg = '0;
logic [3:0] m_axi_awqos_reg = '0;
logic [3:0] m_axi_awregion_reg = '0;
logic [AWUSER_W-1:0] m_axi_awuser_reg = '0;
logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
logic [ID_W-1:0] temp_m_axi_awid_reg = '0;
logic [ADDR_W-1:0] temp_m_axi_awaddr_reg = '0;
logic [7:0] temp_m_axi_awlen_reg = '0;
logic [2:0] temp_m_axi_awsize_reg = '0;
logic [1:0] temp_m_axi_awburst_reg = '0;
logic temp_m_axi_awlock_reg = '0;
logic [3:0] temp_m_axi_awcache_reg = '0;
logic [2:0] temp_m_axi_awprot_reg = '0;
logic [3:0] temp_m_axi_awqos_reg = '0;
logic [3:0] temp_m_axi_awregion_reg = '0;
logic [AWUSER_W-1:0] temp_m_axi_awuser_reg = '0;
logic temp_m_axi_awvalid_reg = 1'b0, temp_m_axi_awvalid_next;
// datapath control
logic store_axi_aw_input_to_output;
logic store_axi_aw_input_to_temp;
logic store_axi_aw_temp_to_output;
assign s_axi_wr.awready = s_axi_awready_reg;
assign m_axi_wr.awid = m_axi_awid_reg;
assign m_axi_wr.awaddr = m_axi_awaddr_reg;
assign m_axi_wr.awlen = m_axi_awlen_reg;
assign m_axi_wr.awsize = m_axi_awsize_reg;
assign m_axi_wr.awburst = m_axi_awburst_reg;
assign m_axi_wr.awlock = m_axi_awlock_reg;
assign m_axi_wr.awcache = m_axi_awcache_reg;
assign m_axi_wr.awprot = m_axi_awprot_reg;
assign m_axi_wr.awqos = m_axi_awqos_reg;
assign m_axi_wr.awregion = m_axi_awregion_reg;
assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0;
assign m_axi_wr.awvalid = m_axi_awvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axi_awready_early = m_axi_wr.awready || (!temp_m_axi_awvalid_reg && (!m_axi_awvalid_reg || !s_axi_wr.awvalid));
always_comb begin
// transfer sink ready state to source
m_axi_awvalid_next = m_axi_awvalid_reg;
temp_m_axi_awvalid_next = temp_m_axi_awvalid_reg;
store_axi_aw_input_to_output = 1'b0;
store_axi_aw_input_to_temp = 1'b0;
store_axi_aw_temp_to_output = 1'b0;
if (s_axi_awready_reg) begin
// input is ready
if (m_axi_wr.awready || !m_axi_awvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axi_awvalid_next = s_axi_wr.awvalid;
store_axi_aw_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axi_awvalid_next = s_axi_wr.awvalid;
store_axi_aw_input_to_temp = 1'b1;
end
end else if (m_axi_wr.awready) begin
// input is not ready, but output is ready
m_axi_awvalid_next = temp_m_axi_awvalid_reg;
temp_m_axi_awvalid_next = 1'b0;
store_axi_aw_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
s_axi_awready_reg <= s_axi_awready_early;
m_axi_awvalid_reg <= m_axi_awvalid_next;
temp_m_axi_awvalid_reg <= temp_m_axi_awvalid_next;
// datapath
if (store_axi_aw_input_to_output) begin
m_axi_awid_reg <= s_axi_wr.awid;
m_axi_awaddr_reg <= s_axi_wr.awaddr;
m_axi_awlen_reg <= s_axi_wr.awlen;
m_axi_awsize_reg <= s_axi_wr.awsize;
m_axi_awburst_reg <= s_axi_wr.awburst;
m_axi_awlock_reg <= s_axi_wr.awlock;
m_axi_awcache_reg <= s_axi_wr.awcache;
m_axi_awprot_reg <= s_axi_wr.awprot;
m_axi_awqos_reg <= s_axi_wr.awqos;
m_axi_awregion_reg <= s_axi_wr.awregion;
m_axi_awuser_reg <= s_axi_wr.awuser;
end else if (store_axi_aw_temp_to_output) begin
m_axi_awid_reg <= temp_m_axi_awid_reg;
m_axi_awaddr_reg <= temp_m_axi_awaddr_reg;
m_axi_awlen_reg <= temp_m_axi_awlen_reg;
m_axi_awsize_reg <= temp_m_axi_awsize_reg;
m_axi_awburst_reg <= temp_m_axi_awburst_reg;
m_axi_awlock_reg <= temp_m_axi_awlock_reg;
m_axi_awcache_reg <= temp_m_axi_awcache_reg;
m_axi_awprot_reg <= temp_m_axi_awprot_reg;
m_axi_awqos_reg <= temp_m_axi_awqos_reg;
m_axi_awregion_reg <= temp_m_axi_awregion_reg;
m_axi_awuser_reg <= temp_m_axi_awuser_reg;
end
if (store_axi_aw_input_to_temp) begin
temp_m_axi_awid_reg <= s_axi_wr.awid;
temp_m_axi_awaddr_reg <= s_axi_wr.awaddr;
temp_m_axi_awlen_reg <= s_axi_wr.awlen;
temp_m_axi_awsize_reg <= s_axi_wr.awsize;
temp_m_axi_awburst_reg <= s_axi_wr.awburst;
temp_m_axi_awlock_reg <= s_axi_wr.awlock;
temp_m_axi_awcache_reg <= s_axi_wr.awcache;
temp_m_axi_awprot_reg <= s_axi_wr.awprot;
temp_m_axi_awqos_reg <= s_axi_wr.awqos;
temp_m_axi_awregion_reg <= s_axi_wr.awregion;
temp_m_axi_awuser_reg <= s_axi_wr.awuser;
end
if (rst) begin
s_axi_awready_reg <= 1'b0;
m_axi_awvalid_reg <= 1'b0;
temp_m_axi_awvalid_reg <= 1'b0;
end
end
end else if (AW_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
logic s_axi_awready_reg = 1'b0;
logic [ID_W-1:0] m_axi_awid_reg = '0;
logic [ADDR_W-1:0] m_axi_awaddr_reg = '0;
logic [7:0] m_axi_awlen_reg = '0;
logic [2:0] m_axi_awsize_reg = '0;
logic [1:0] m_axi_awburst_reg = '0;
logic m_axi_awlock_reg = '0;
logic [3:0] m_axi_awcache_reg = '0;
logic [2:0] m_axi_awprot_reg = '0;
logic [3:0] m_axi_awqos_reg = '0;
logic [3:0] m_axi_awregion_reg = '0;
logic [AWUSER_W-1:0] m_axi_awuser_reg = '0;
logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
// datapath control
logic store_axi_aw_input_to_output;
assign s_axi_wr.awready = s_axi_awready_reg;
assign m_axi_wr.awid = m_axi_awid_reg;
assign m_axi_wr.awaddr = m_axi_awaddr_reg;
assign m_axi_wr.awlen = m_axi_awlen_reg;
assign m_axi_wr.awsize = m_axi_awsize_reg;
assign m_axi_wr.awburst = m_axi_awburst_reg;
assign m_axi_wr.awlock = m_axi_awlock_reg;
assign m_axi_wr.awcache = m_axi_awcache_reg;
assign m_axi_wr.awprot = m_axi_awprot_reg;
assign m_axi_wr.awqos = m_axi_awqos_reg;
assign m_axi_wr.awregion = m_axi_awregion_reg;
assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0;
assign m_axi_wr.awvalid = m_axi_awvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axi_awready_eawly = !m_axi_awvalid_next;
always_comb begin
// transfer sink ready state to source
m_axi_awvalid_next = m_axi_awvalid_reg;
store_axi_aw_input_to_output = 1'b0;
if (s_axi_awready_reg) begin
m_axi_awvalid_next = s_axi_wr.awvalid;
store_axi_aw_input_to_output = 1'b1;
end else if (m_axi_wr.awready) begin
m_axi_awvalid_next = 1'b0;
end
end
always_ff @(posedge clk) begin
s_axi_awready_reg <= s_axi_awready_eawly;
m_axi_awvalid_reg <= m_axi_awvalid_next;
// datapath
if (store_axi_aw_input_to_output) begin
m_axi_awid_reg <= s_axi_wr.awid;
m_axi_awaddr_reg <= s_axi_wr.awaddr;
m_axi_awlen_reg <= s_axi_wr.awlen;
m_axi_awsize_reg <= s_axi_wr.awsize;
m_axi_awburst_reg <= s_axi_wr.awburst;
m_axi_awlock_reg <= s_axi_wr.awlock;
m_axi_awcache_reg <= s_axi_wr.awcache;
m_axi_awprot_reg <= s_axi_wr.awprot;
m_axi_awqos_reg <= s_axi_wr.awqos;
m_axi_awregion_reg <= s_axi_wr.awregion;
m_axi_awuser_reg <= s_axi_wr.awuser;
end
if (rst) begin
s_axi_awready_reg <= 1'b0;
m_axi_awvalid_reg <= 1'b0;
end
end
end else begin
// bypass AW channel
assign m_axi_wr.awid = s_axi_wr.awid;
assign m_axi_wr.awaddr = s_axi_wr.awaddr;
assign m_axi_wr.awlen = s_axi_wr.awlen;
assign m_axi_wr.awsize = s_axi_wr.awsize;
assign m_axi_wr.awburst = s_axi_wr.awburst;
assign m_axi_wr.awlock = s_axi_wr.awlock;
assign m_axi_wr.awcache = s_axi_wr.awcache;
assign m_axi_wr.awprot = s_axi_wr.awprot;
assign m_axi_wr.awqos = s_axi_wr.awqos;
assign m_axi_wr.awregion = s_axi_wr.awregion;
assign m_axi_wr.awuser = AWUSER_EN ? s_axi_wr.awuser : '0;
assign m_axi_wr.awvalid = s_axi_wr.awvalid;
assign s_axi_wr.awready = m_axi_wr.awready;
end
// W channel
if (W_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
logic s_axi_wready_reg = 1'b0;
logic [DATA_W-1:0] m_axi_wdata_reg = '0;
logic [STRB_W-1:0] m_axi_wstrb_reg = '0;
logic m_axi_wlast_reg = 1'b0;
logic [WUSER_W-1:0] m_axi_wuser_reg = '0;
logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
logic [DATA_W-1:0] temp_m_axi_wdata_reg = '0;
logic [STRB_W-1:0] temp_m_axi_wstrb_reg = '0;
logic temp_m_axi_wlast_reg = 1'b0;
logic [WUSER_W-1:0] temp_m_axi_wuser_reg = '0;
logic temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
// datapath control
logic store_axi_w_input_to_output;
logic store_axi_w_input_to_temp;
logic store_axi_w_temp_to_output;
assign s_axi_wr.wready = s_axi_wready_reg;
assign m_axi_wr.wdata = m_axi_wdata_reg;
assign m_axi_wr.wstrb = m_axi_wstrb_reg;
assign m_axi_wr.wlast = m_axi_wlast_reg;
assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0;
assign m_axi_wr.wvalid = m_axi_wvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire s_axi_wready_early = m_axi_wr.wready || (!temp_m_axi_wvalid_reg && (!m_axi_wvalid_reg || !s_axi_wr.wvalid));
always_comb begin
// transfer sink ready state to source
m_axi_wvalid_next = m_axi_wvalid_reg;
temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
store_axi_w_input_to_output = 1'b0;
store_axi_w_input_to_temp = 1'b0;
store_axi_w_temp_to_output = 1'b0;
if (s_axi_wready_reg) begin
// input is ready
if (m_axi_wr.wready || !m_axi_wvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axi_wvalid_next = s_axi_wr.wvalid;
store_axi_w_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axi_wvalid_next = s_axi_wr.wvalid;
store_axi_w_input_to_temp = 1'b1;
end
end else if (m_axi_wr.wready) begin
// input is not ready, but output is ready
m_axi_wvalid_next = temp_m_axi_wvalid_reg;
temp_m_axi_wvalid_next = 1'b0;
store_axi_w_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
s_axi_wready_reg <= s_axi_wready_early;
m_axi_wvalid_reg <= m_axi_wvalid_next;
temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
// datapath
if (store_axi_w_input_to_output) begin
m_axi_wdata_reg <= s_axi_wr.wdata;
m_axi_wstrb_reg <= s_axi_wr.wstrb;
m_axi_wlast_reg <= s_axi_wr.wlast;
m_axi_wuser_reg <= s_axi_wr.wuser;
end else if (store_axi_w_temp_to_output) begin
m_axi_wdata_reg <= temp_m_axi_wdata_reg;
m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
m_axi_wlast_reg <= temp_m_axi_wlast_reg;
m_axi_wuser_reg <= temp_m_axi_wuser_reg;
end
if (store_axi_w_input_to_temp) begin
temp_m_axi_wdata_reg <= s_axi_wr.wdata;
temp_m_axi_wstrb_reg <= s_axi_wr.wstrb;
temp_m_axi_wlast_reg <= s_axi_wr.wlast;
temp_m_axi_wuser_reg <= s_axi_wr.wuser;
end
if (rst) begin
s_axi_wready_reg <= 1'b0;
m_axi_wvalid_reg <= 1'b0;
temp_m_axi_wvalid_reg <= 1'b0;
end
end
end else if (W_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
logic s_axi_wready_reg = 1'b0;
logic [DATA_W-1:0] m_axi_wdata_reg = '0;
logic [STRB_W-1:0] m_axi_wstrb_reg = '0;
logic m_axi_wlast_reg = 1'b0;
logic [WUSER_W-1:0] m_axi_wuser_reg = '0;
logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
// datapath control
logic store_axi_w_input_to_output;
assign s_axi_wr.wready = s_axi_wready_reg;
assign m_axi_wr.wdata = m_axi_wdata_reg;
assign m_axi_wr.wstrb = m_axi_wstrb_reg;
assign m_axi_wr.wlast = m_axi_wlast_reg;
assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0;
assign m_axi_wr.wvalid = m_axi_wvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire s_axi_wready_ewly = !m_axi_wvalid_next;
always_comb begin
// transfer sink ready state to source
m_axi_wvalid_next = m_axi_wvalid_reg;
store_axi_w_input_to_output = 1'b0;
if (s_axi_wready_reg) begin
m_axi_wvalid_next = s_axi_wr.wvalid;
store_axi_w_input_to_output = 1'b1;
end else if (m_axi_wr.wready) begin
m_axi_wvalid_next = 1'b0;
end
end
always_ff @(posedge clk) begin
s_axi_wready_reg <= s_axi_wready_ewly;
m_axi_wvalid_reg <= m_axi_wvalid_next;
// datapath
if (store_axi_w_input_to_output) begin
m_axi_wdata_reg <= s_axi_wr.wdata;
m_axi_wstrb_reg <= s_axi_wr.wstrb;
m_axi_wlast_reg <= s_axi_wr.wlast;
m_axi_wuser_reg <= s_axi_wr.wuser;
end
if (rst) begin
s_axi_wready_reg <= 1'b0;
m_axi_wvalid_reg <= 1'b0;
end
end
end else begin
// bypass W channel
assign m_axi_wr.wdata = s_axi_wr.wdata;
assign m_axi_wr.wstrb = s_axi_wr.wstrb;
assign m_axi_wr.wlast = s_axi_wr.wlast;
assign m_axi_wr.wuser = WUSER_EN ? s_axi_wr.wuser : '0;
assign m_axi_wr.wvalid = s_axi_wr.wvalid;
assign s_axi_wr.wready = m_axi_wr.wready;
end
// B channel
if (B_REG_TYPE > 1) begin
// skid buffer, no bubble cycles
// datapath registers
logic m_axi_bready_reg = 1'b0;
logic [ID_W-1:0] s_axi_bid_reg = '0;
logic [1:0] s_axi_bresp_reg = 2'b0;
logic [BUSER_W-1:0] s_axi_buser_reg = '0;
logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
logic [ID_W-1:0] temp_s_axi_bid_reg = '0;
logic [1:0] temp_s_axi_bresp_reg = 2'b0;
logic [BUSER_W-1:0] temp_s_axi_buser_reg = '0;
logic temp_s_axi_bvalid_reg = 1'b0, temp_s_axi_bvalid_next;
// datapath control
logic store_axi_b_input_to_output;
logic store_axi_b_input_to_temp;
logic store_axi_b_temp_to_output;
assign m_axi_wr.bready = m_axi_bready_reg;
assign s_axi_wr.bid = s_axi_bid_reg;
assign s_axi_wr.bresp = s_axi_bresp_reg;
assign s_axi_wr.buser = BUSER_EN ? s_axi_buser_reg : '0;
assign s_axi_wr.bvalid = s_axi_bvalid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
wire m_axi_bready_early = s_axi_wr.bready || (!temp_s_axi_bvalid_reg && (!s_axi_bvalid_reg || !m_axi_wr.bvalid));
always_comb begin
// transfer sink ready state to source
s_axi_bvalid_next = s_axi_bvalid_reg;
temp_s_axi_bvalid_next = temp_s_axi_bvalid_reg;
store_axi_b_input_to_output = 1'b0;
store_axi_b_input_to_temp = 1'b0;
store_axi_b_temp_to_output = 1'b0;
if (m_axi_bready_reg) begin
// input is ready
if (s_axi_wr.bready || !s_axi_bvalid_reg) begin
// output is ready or currently not valid, transfer data to output
s_axi_bvalid_next = m_axi_wr.bvalid;
store_axi_b_input_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_s_axi_bvalid_next = m_axi_wr.bvalid;
store_axi_b_input_to_temp = 1'b1;
end
end else if (s_axi_wr.bready) begin
// input is not ready, but output is ready
s_axi_bvalid_next = temp_s_axi_bvalid_reg;
temp_s_axi_bvalid_next = 1'b0;
store_axi_b_temp_to_output = 1'b1;
end
end
always_ff @(posedge clk) begin
m_axi_bready_reg <= m_axi_bready_early;
s_axi_bvalid_reg <= s_axi_bvalid_next;
temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next;
// datapath
if (store_axi_b_input_to_output) begin
s_axi_bid_reg <= m_axi_wr.bid;
s_axi_bresp_reg <= m_axi_wr.bresp;
s_axi_buser_reg <= m_axi_wr.buser;
end else if (store_axi_b_temp_to_output) begin
s_axi_bid_reg <= temp_s_axi_bid_reg;
s_axi_bresp_reg <= temp_s_axi_bresp_reg;
s_axi_buser_reg <= temp_s_axi_buser_reg;
end
if (store_axi_b_input_to_temp) begin
temp_s_axi_bid_reg <= m_axi_wr.bid;
temp_s_axi_bresp_reg <= m_axi_wr.bresp;
temp_s_axi_buser_reg <= m_axi_wr.buser;
end
if (rst) begin
m_axi_bready_reg <= 1'b0;
s_axi_bvalid_reg <= 1'b0;
temp_s_axi_bvalid_reg <= 1'b0;
end
end
end else if (B_REG_TYPE == 1) begin
// simple register, inserts bubble cycles
// datapath registers
logic m_axi_bready_reg = 1'b0;
logic [ID_W-1:0] s_axi_bid_reg = '0;
logic [1:0] s_axi_bresp_reg = 2'b0;
logic [BUSER_W-1:0] s_axi_buser_reg = '0;
logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
// datapath control
logic store_axi_b_input_to_output;
assign m_axi_wr.bready = m_axi_bready_reg;
assign s_axi_wr.bid = s_axi_bid_reg;
assign s_axi_wr.bresp = s_axi_bresp_reg;
assign s_axi_wr.buser = BUSER_EN ? s_axi_buser_reg : '0;
assign s_axi_wr.bvalid = s_axi_bvalid_reg;
// enable ready input next cycle if output buffer will be empty
wire m_axi_bready_early = !s_axi_bvalid_next;
always_comb begin
// transfer sink ready state to source
s_axi_bvalid_next = s_axi_bvalid_reg;
store_axi_b_input_to_output = 1'b0;
if (m_axi_bready_reg) begin
s_axi_bvalid_next = m_axi_wr.bvalid;
store_axi_b_input_to_output = 1'b1;
end else if (s_axi_wr.bready) begin
s_axi_bvalid_next = 1'b0;
end
end
always_ff @(posedge clk) begin
m_axi_bready_reg <= m_axi_bready_early;
s_axi_bvalid_reg <= s_axi_bvalid_next;
// datapath
if (store_axi_b_input_to_output) begin
s_axi_bid_reg <= m_axi_wr.bid;
s_axi_bresp_reg <= m_axi_wr.bresp;
s_axi_buser_reg <= m_axi_wr.buser;
end
if (rst) begin
m_axi_bready_reg <= 1'b0;
s_axi_bvalid_reg <= 1'b0;
end
end
end else begin
// bypass B channel
assign s_axi_wr.bid = m_axi_wr.bid;
assign s_axi_wr.bresp = m_axi_wr.bresp;
assign s_axi_wr.buser = BUSER_EN ? m_axi_wr.buser : '0;
assign s_axi_wr.bvalid = m_axi_wr.bvalid;
assign m_axi_wr.bready = s_axi_wr.bready;
end
endmodule
`resetall

66
tb/axi/taxi_axi_register/Makefile Normal file
View File

@@ -0,0 +1,66 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2020-2025
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = taxi_axi_register
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += ../../../rtl/axi/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
REG_TYPE ?= 1
# module parameters
export PARAM_DATA_W := 32
export PARAM_ADDR_W := 32
export PARAM_ID_W := 8
export PARAM_AWUSER_EN := 0
export PARAM_AWUSER_W := 1
export PARAM_WUSER_EN := 0
export PARAM_WUSER_W := 1
export PARAM_BUSER_EN := 0
export PARAM_BUSER_W := 1
export PARAM_ARUSER_EN := 0
export PARAM_ARUSER_W := 1
export PARAM_RUSER_EN := 0
export PARAM_RUSER_W := 1
export PARAM_AW_REG_TYPE := $(REG_TYPE)
export PARAM_W_REG_TYPE := $(REG_TYPE)
export PARAM_B_REG_TYPE := $(REG_TYPE)
export PARAM_AR_REG_TYPE := $(REG_TYPE)
export PARAM_R_REG_TYPE := $(REG_TYPE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-WIDTH
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

262
tb/axi/taxi_axi_register/test_taxi_axi_register.py Normal file
View File

@@ -0,0 +1,262 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2020-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory
from cocotbext.axi import AxiBus, AxiMaster, AxiRam
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_entity(dut.s_axi), dut.clk, dut.rst)
self.axi_ram = AxiRam(AxiBus.from_entity(dut.m_axi), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None):
if generator:
self.axi_master.write_if.aw_channel.set_pause_generator(generator())
self.axi_master.write_if.w_channel.set_pause_generator(generator())
self.axi_master.read_if.ar_channel.set_pause_generator(generator())
self.axi_ram.write_if.b_channel.set_pause_generator(generator())
self.axi_ram.read_if.r_channel.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.axi_master.write_if.b_channel.set_pause_generator(generator())
self.axi_master.read_if.r_channel.set_pause_generator(generator())
self.axi_ram.write_if.aw_channel.set_pause_generator(generator())
self.axi_ram.write_if.w_channel.set_pause_generator(generator())
self.axi_ram.read_if.ar_channel.set_pause_generator(generator())
async def cycle_reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
tb = TB(dut)
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
size = max_burst_size
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axi_ram.write(addr-128, b'\xaa'*(length+256))
await tb.axi_master.write(addr, test_data, size=size)
tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
assert tb.axi_ram.read(addr, length) == test_data
assert tb.axi_ram.read(addr-1, 1) == b'\xaa'
assert tb.axi_ram.read(addr+length, 1) == b'\xaa'
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
tb = TB(dut)
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
size = max_burst_size
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axi_ram.write(addr, test_data)
data = await tb.axi_master.read(addr, length, size=size)
assert data.data == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
async def worker(master, offset, aperture, count=16):
for k in range(count):
length = random.randint(1, min(512, aperture))
addr = offset+random.randint(0, aperture-length)
test_data = bytearray([x % 256 for x in range(length)])
await Timer(random.randint(1, 100), 'ns')
await master.write(addr, test_data)
await Timer(random.randint(1, 100), 'ns')
data = await master.read(addr, length)
assert data.data == test_data
workers = []
for k in range(16):
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0)
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
data_width = len(cocotb.top.s_axi.wdata)
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.add_option("size", [None]+list(range(max_burst_size)))
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("reg_type", [None, 0, 1, 2])
@pytest.mark.parametrize("data_w", [8, 16, 32])
def test_taxi_axi_register(request, data_w, reg_type):
dut = "taxi_axi_register"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, "axi", f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DATA_W'] = data_w
parameters['ADDR_W'] = 32
parameters['ID_W'] = 8
parameters['AWUSER_EN'] = 0
parameters['AWUSER_W'] = 1
parameters['WUSER_EN'] = 0
parameters['WUSER_W'] = 1
parameters['BUSER_EN'] = 0
parameters['BUSER_W'] = 1
parameters['ARUSER_EN'] = 0
parameters['ARUSER_W'] = 1
parameters['RUSER_EN'] = 0
parameters['RUSER_W'] = 1
parameters['AW_REG_TYPE'] = 1 if reg_type is None else reg_type
parameters['W_REG_TYPE'] = 2 if reg_type is None else reg_type
parameters['B_REG_TYPE'] = 1 if reg_type is None else reg_type
parameters['AR_REG_TYPE'] = 1 if reg_type is None else reg_type
parameters['R_REG_TYPE'] = 2 if reg_type is None else reg_type
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

88
tb/axi/taxi_axi_register/test_taxi_axi_register.sv Normal file
View File

@@ -0,0 +1,88 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 register testbench
*/
module test_taxi_axi_register #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter ADDR_W = 32,
parameter ID_W = 8,
parameter logic AWUSER_EN = 1'b0,
parameter AWUSER_W = 1,
parameter logic WUSER_EN = 1'b0,
parameter WUSER_W = 1,
parameter logic BUSER_EN = 1'b0,
parameter BUSER_W = 1,
parameter logic ARUSER_EN = 1'b0,
parameter ARUSER_W = 1,
parameter logic RUSER_EN = 1'b0,
parameter RUSER_W = 1,
parameter AW_REG_TYPE = 1,
parameter W_REG_TYPE = 2,
parameter B_REG_TYPE = 1,
parameter AR_REG_TYPE = 1,
parameter R_REG_TYPE = 2
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axi_if #(
.DATA_W(DATA_W),
.ADDR_W(ADDR_W),
.ID_W(ID_W),
.AWUSER_EN(AWUSER_EN),
.AWUSER_W(AWUSER_W),
.WUSER_EN(WUSER_EN),
.WUSER_W(WUSER_W),
.BUSER_EN(BUSER_EN),
.BUSER_W(BUSER_W),
.ARUSER_EN(ARUSER_EN),
.ARUSER_W(ARUSER_W),
.RUSER_EN(RUSER_EN),
.RUSER_W(RUSER_W)
) s_axi(), m_axi();
taxi_axi_register #(
.AW_REG_TYPE(AW_REG_TYPE),
.W_REG_TYPE(W_REG_TYPE),
.B_REG_TYPE(B_REG_TYPE),
.AR_REG_TYPE(AR_REG_TYPE),
.R_REG_TYPE(R_REG_TYPE)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4 slave interface
*/
.s_axi_wr(s_axi),
.s_axi_rd(s_axi),
/*
* AXI4 master interface
*/
.m_axi_wr(m_axi),
.m_axi_rd(m_axi)
);
endmodule
`resetall