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example/ADM_PCIE_9V3: Example design cleanup

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-26 14:16:18 -08:00
parent c6cbb57fe7
commit da3996cf5c
1 changed files with 6 additions and 6 deletions
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12
example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
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@@ -26,16 +26,16 @@ module fpga_core #
* Clock: 125 MHz * Clock: 125 MHz
* Synchronous reset * Synchronous reset
*/ */
input wire clk_125mhz, input wire logic clk_125mhz,
input wire rst_125mhz, input wire logic rst_125mhz,
/* /*
* GPIO * GPIO
*/ */
output wire [1:0] user_led_g, output wire logic [1:0] user_led_g,
output wire user_led_r, output wire logic user_led_r,
output wire [1:0] front_led, output wire logic [1:0] front_led,
input wire [1:0] user_sw, input wire logic [1:0] user_sw,
/* /*
* Ethernet: QSFP28 * Ethernet: QSFP28