bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 17:08:38 -08:00
Code Issues Packages Projects Releases Wiki Activity

eth: Add 10G PHY module and testbench

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-04 17:10:21 -08:00
parent c6ea4071eb
commit e35d2b2c03
16 changed files with 1553 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
rtl/eth/taxi_eth_phy_10g.f Normal file
View File

@@ -0,0 +1,3 @@
taxi_eth_phy_10g.sv
taxi_eth_phy_10g_rx.f
taxi_eth_phy_10g_tx.f

158
rtl/eth/taxi_eth_phy_10g.sv Normal file
View File

@@ -0,0 +1,158 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY
*/
module taxi_eth_phy_10g #
(
parameter DATA_W = 64,
parameter CTRL_W = (DATA_W/8),
parameter HDR_W = 2,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 7,
parameter COUNT_125US = 125000/6.4
)
(
input wire logic rx_clk,
input wire logic rx_rst,
input wire logic tx_clk,
input wire logic tx_rst,
/*
* XGMII interface
*/
input wire logic [DATA_W-1:0] xgmii_txd,
input wire logic [CTRL_W-1:0] xgmii_txc,
output wire logic [DATA_W-1:0] xgmii_rxd,
output wire logic [CTRL_W-1:0] xgmii_rxc,
/*
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
/*
* Status
*/
output wire logic tx_bad_block,
output wire logic [6:0] rx_error_count,
output wire logic rx_bad_block,
output wire logic rx_sequence_error,
output wire logic rx_block_lock,
output wire logic rx_high_ber,
output wire logic rx_status,
/*
* Configuration
*/
input wire logic cfg_tx_prbs31_enable = 1'b0,
input wire logic cfg_rx_prbs31_enable = 1'b0
);
taxi_eth_phy_10g_rx #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.HDR_W(HDR_W),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
/*
* XGMII interface
*/
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
/*
* SERDES interface
*/
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
/*
* Status
*/
.rx_error_count(rx_error_count),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status),
/*
* Configuration
*/
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
taxi_eth_phy_10g_tx #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.HDR_W(HDR_W),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
)
eth_phy_10g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
/*
* XGMII interface
*/
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
/*
* SERDES interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
/*
* Status
*/
.tx_bad_block(tx_bad_block),
/*
* Configuration
*/
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
);
endmodule
`resetall

3
rtl/eth/taxi_eth_phy_10g_rx.f Normal file
View File

@@ -0,0 +1,3 @@
taxi_eth_phy_10g_rx.sv
taxi_eth_phy_10g_rx_if.f
taxi_xgmii_baser_dec_64.sv

153
rtl/eth/taxi_eth_phy_10g_rx.sv Normal file
View File

@@ -0,0 +1,153 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY RX
*/
module taxi_eth_phy_10g_rx #
(
parameter DATA_W = 64,
parameter CTRL_W = (DATA_W/8),
parameter HDR_W = 2,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 7,
parameter COUNT_125US = 125000/6.4
)
(
input wire logic clk,
input wire logic rst,
/*
* XGMII interface
*/
output wire logic [DATA_W-1:0] xgmii_rxd,
output wire logic [CTRL_W-1:0] xgmii_rxc,
/*
* SERDES interface
*/
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
/*
* Status
*/
output wire logic [6:0] rx_error_count,
output wire logic rx_bad_block,
output wire logic rx_sequence_error,
output wire logic rx_block_lock,
output wire logic rx_high_ber,
output wire logic rx_status,
/*
* Configuration
*/
input wire logic cfg_rx_prbs31_enable
);
// check configuration
if (DATA_W != 64)
$fatal(0, "Error: Interface width must be 64");
if (CTRL_W * 8 != DATA_W)
$fatal(0, "Error: Interface requires byte (8-bit) granularity");
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
wire [DATA_W-1:0] encoded_rx_data;
wire [HDR_W-1:0] encoded_rx_hdr;
taxi_eth_phy_10g_rx_if #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
.SERDES_PIPELINE(SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_if_inst (
.clk(clk),
.rst(rst),
/*
* 10GBASE-R encoded interface
*/
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
/*
* SERDES interface
*/
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
/*
* Status
*/
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),
.rx_error_count(rx_error_count),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status),
/*
* Configuration
*/
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
);
taxi_xgmii_baser_dec_64 #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.HDR_W(HDR_W)
)
xgmii_baser_dec_inst (
.clk(clk),
.rst(rst),
/*
* 10GBASE-R encoded input
*/
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
/*
* XGMII interface
*/
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
/*
* Status
*/
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error)
);
endmodule
`resetall

105
rtl/eth/taxi_eth_phy_10g_rx_ber_mon.sv Normal file
View File

@@ -0,0 +1,105 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY BER monitor
*/
module taxi_eth_phy_10g_rx_ber_mon #
(
parameter HDR_W = 2,
parameter COUNT_125US = 125000/6.4
)
(
input wire logic clk,
input wire logic rst,
/*
* SERDES interface
*/
input wire logic [HDR_W-1:0] serdes_rx_hdr,
/*
* Status
*/
output wire logic rx_high_ber
);
// check configuration
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
localparam COUNT_W = $clog2($rtoi(COUNT_125US)+1);
localparam logic [COUNT_W-1:0] COUNT_125US_INT = COUNT_W'($rtoi(COUNT_125US));
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
logic [COUNT_W-1:0] time_count_reg = COUNT_125US_INT, time_count_next;
logic [3:0] ber_count_reg = 4'd0, ber_count_next;
logic rx_high_ber_reg = 1'b0, rx_high_ber_next;
assign rx_high_ber = rx_high_ber_reg;
always_comb begin
if (time_count_reg > 0) begin
time_count_next = time_count_reg-1;
end else begin
time_count_next = time_count_reg;
end
ber_count_next = ber_count_reg;
rx_high_ber_next = rx_high_ber_reg;
if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
if (ber_count_reg != 4'd15) begin
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end else begin
// invalid header
if (ber_count_reg == 4'd15) begin
rx_high_ber_next = 1'b1;
end else begin
ber_count_next = ber_count_reg + 1;
if (time_count_reg == 0) begin
rx_high_ber_next = 1'b0;
end
end
end
if (time_count_reg == 0) begin
// 125 us timer expired
ber_count_next = 4'd0;
time_count_next = COUNT_125US_INT;
end
end
always_ff @(posedge clk) begin
time_count_reg <= time_count_next;
ber_count_reg <= ber_count_next;
rx_high_ber_reg <= rx_high_ber_next;
if (rst) begin
time_count_reg <= COUNT_125US_INT;
ber_count_reg <= 4'd0;
rx_high_ber_reg <= 1'b0;
end
end
endmodule
`resetall

126
rtl/eth/taxi_eth_phy_10g_rx_frame_sync.sv Normal file
View File

@@ -0,0 +1,126 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY frame sync
*/
module taxi_eth_phy_10g_rx_frame_sync #
(
parameter HDR_W = 2,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 7
)
(
input wire logic clk,
input wire logic rst,
/*
* SERDES interface
*/
input wire logic [HDR_W-1:0] serdes_rx_hdr,
output wire logic serdes_rx_bitslip,
/*
* Status
*/
output wire logic rx_block_lock
);
localparam BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES;
localparam BITSLIP_COUNT_W = $clog2(BITSLIP_MAX_CYCLES);
// check configuration
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
logic [5:0] sh_count_reg = 6'd0, sh_count_next;
logic [3:0] sh_invalid_count_reg = 4'd0, sh_invalid_count_next;
logic [BITSLIP_COUNT_W-1:0] bitslip_count_reg = '0, bitslip_count_next;
logic serdes_rx_bitslip_reg = 1'b0, serdes_rx_bitslip_next;
logic rx_block_lock_reg = 1'b0, rx_block_lock_next;
assign serdes_rx_bitslip = serdes_rx_bitslip_reg;
assign rx_block_lock = rx_block_lock_reg;
always_comb begin
sh_count_next = sh_count_reg;
sh_invalid_count_next = sh_invalid_count_reg;
bitslip_count_next = bitslip_count_reg;
serdes_rx_bitslip_next = serdes_rx_bitslip_reg;
rx_block_lock_next = rx_block_lock_reg;
if (bitslip_count_reg != 0) begin
bitslip_count_next = bitslip_count_reg-1;
end else if (serdes_rx_bitslip_reg) begin
serdes_rx_bitslip_next = 1'b0;
bitslip_count_next = BITSLIP_COUNT_W'(BITSLIP_LOW_CYCLES);
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
sh_count_next = sh_count_reg + 1;
if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = '0;
sh_invalid_count_next = '0;
if (sh_invalid_count_reg == 0) begin
rx_block_lock_next = 1'b1;
end
end
end else begin
// invalid header
sh_count_next = sh_count_reg + 1;
sh_invalid_count_next = sh_invalid_count_reg + 1;
if (!rx_block_lock_reg || &sh_invalid_count_reg) begin
// invalid count overflow, lost block lock
sh_count_next = '0;
sh_invalid_count_next = '0;
rx_block_lock_next = 1'b0;
// slip one bit
serdes_rx_bitslip_next = 1'b1;
bitslip_count_next = BITSLIP_COUNT_W'(BITSLIP_HIGH_CYCLES);
end else if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = '0;
sh_invalid_count_next = '0;
end
end
end
always_ff @(posedge clk) begin
sh_count_reg <= sh_count_next;
sh_invalid_count_reg <= sh_invalid_count_next;
bitslip_count_reg <= bitslip_count_next;
serdes_rx_bitslip_reg <= serdes_rx_bitslip_next;
rx_block_lock_reg <= rx_block_lock_next;
if (rst) begin
sh_count_reg <= '0;
sh_invalid_count_reg <= '0;
bitslip_count_reg <= '0;
serdes_rx_bitslip_reg <= 1'b0;
rx_block_lock_reg <= 1'b0;
end
end
endmodule
`resetall

5
rtl/eth/taxi_eth_phy_10g_rx_if.f Normal file
View File

@@ -0,0 +1,5 @@
taxi_eth_phy_10g_rx_if.sv
taxi_eth_phy_10g_rx_ber_mon.sv
taxi_eth_phy_10g_rx_frame_sync.sv
taxi_eth_phy_10g_rx_watchdog.sv
../lfsr/taxi_lfsr.sv

247
rtl/eth/taxi_eth_phy_10g_rx_if.sv Normal file
View File

@@ -0,0 +1,247 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY RX IF
*/
module taxi_eth_phy_10g_rx_if #
(
parameter DATA_W = 64,
parameter HDR_W = 2,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 7,
parameter COUNT_125US = 125000/6.4
)
(
input wire logic clk,
input wire logic rst,
/*
* 10GBASE-R encoded interface
*/
output wire logic [DATA_W-1:0] encoded_rx_data,
output wire logic [HDR_W-1:0] encoded_rx_hdr,
/*
* SERDES interface
*/
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
/*
* Status
*/
input wire logic rx_bad_block,
input wire logic rx_sequence_error,
output wire logic [6:0] rx_error_count,
output wire logic rx_block_lock,
output wire logic rx_high_ber,
output wire logic rx_status,
/*
* Configuration
*/
input wire logic cfg_rx_prbs31_enable
);
// check configuration
if (DATA_W != 64)
$fatal(0, "Error: Interface width must be 64");
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
wire [DATA_W-1:0] serdes_rx_data_rev, serdes_rx_data_int;
wire [HDR_W-1:0] serdes_rx_hdr_rev, serdes_rx_hdr_int;
if (BIT_REVERSE) begin
for (genvar n = 0; n < DATA_W; n = n + 1) begin
assign serdes_rx_data_rev[n] = serdes_rx_data[DATA_W-n-1];
end
for (genvar n = 0; n < HDR_W; n = n + 1) begin
assign serdes_rx_hdr_rev[n] = serdes_rx_hdr[HDR_W-n-1];
end
end else begin
assign serdes_rx_data_rev = serdes_rx_data;
assign serdes_rx_hdr_rev = serdes_rx_hdr;
end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
logic [DATA_W-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
logic [HDR_W-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_rx_data_pipe_reg[n] = '0;
serdes_rx_hdr_pipe_reg[n] = '0;
end
always @(posedge clk) begin
serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1];
end
end
assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_hdr_int = serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1];
end else begin
assign serdes_rx_data_int = serdes_rx_data_rev;
assign serdes_rx_hdr_int = serdes_rx_hdr_rev;
end
wire [DATA_W-1:0] descrambled_rx_data;
logic [DATA_W-1:0] encoded_rx_data_reg = '0;
logic [HDR_W-1:0] encoded_rx_hdr_reg = '0;
logic [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
logic [30:0] prbs31_state_reg = 31'h7fffffff;
wire [30:0] prbs31_state;
wire [DATA_W+HDR_W-1:0] prbs31_data;
logic [DATA_W+HDR_W-1:0] prbs31_data_reg = '0;
logic [6:0] rx_error_count_reg = '0;
logic [5:0] rx_error_count_1_reg = '0;
logic [5:0] rx_error_count_2_reg = '0;
logic [5:0] rx_error_count_1_temp;
logic [5:0] rx_error_count_2_temp;
taxi_lfsr #(
.LFSR_W(58),
.LFSR_POLY(58'h8000000001),
.LFSR_GALOIS(0),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_W(DATA_W)
)
descrambler_inst (
.data_in(serdes_rx_data_int),
.state_in(scrambler_state_reg),
.data_out(descrambled_rx_data),
.state_out(scrambler_state)
);
taxi_lfsr #(
.LFSR_W(31),
.LFSR_POLY(31'h10000001),
.LFSR_GALOIS(0),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_W(DATA_W+HDR_W)
)
prbs31_check_inst (
.data_in(~{serdes_rx_data_int, serdes_rx_hdr_int}),
.state_in(prbs31_state_reg),
.data_out(prbs31_data),
.state_out(prbs31_state)
);
always_comb begin
rx_error_count_1_temp = '0;
rx_error_count_2_temp = '0;
for (integer i = 0; i < DATA_W+HDR_W; i = i + 1) begin
if (i[0]) begin
rx_error_count_1_temp = rx_error_count_1_temp + 6'(prbs31_data_reg[i]);
end else begin
rx_error_count_2_temp = rx_error_count_2_temp + 6'(prbs31_data_reg[i]);
end
end
end
always_ff @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
if (PRBS31_EN) begin
if (cfg_rx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
prbs31_data_reg <= prbs31_data;
end else begin
prbs31_data_reg <= '0;
end
rx_error_count_1_reg <= rx_error_count_1_temp;
rx_error_count_2_reg <= rx_error_count_2_temp;
rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg;
end else begin
rx_error_count_reg <= '0;
end
end
assign encoded_rx_data = encoded_rx_data_reg;
assign encoded_rx_hdr = encoded_rx_hdr_reg;
assign rx_error_count = rx_error_count_reg;
wire serdes_rx_bitslip_int;
wire serdes_rx_reset_req_int;
assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_EN && cfg_rx_prbs31_enable);
assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_EN && cfg_rx_prbs31_enable);
taxi_eth_phy_10g_rx_frame_sync #(
.HDR_W(HDR_W),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES)
)
eth_phy_10g_rx_frame_sync_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_bitslip(serdes_rx_bitslip_int),
.rx_block_lock(rx_block_lock)
);
taxi_eth_phy_10g_rx_ber_mon #(
.HDR_W(HDR_W),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_ber_mon_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.rx_high_ber(rx_high_ber)
);
taxi_eth_phy_10g_rx_watchdog #(
.HDR_W(HDR_W),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_watchdog_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_reset_req(serdes_rx_reset_req_int),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_status(rx_status)
);
endmodule
`resetall

153
rtl/eth/taxi_eth_phy_10g_rx_watchdog.sv Normal file
View File

@@ -0,0 +1,153 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY serdes watchdog
*/
module taxi_eth_phy_10g_rx_watchdog #
(
parameter HDR_W = 2,
parameter COUNT_125US = 125000/6.4
)
(
input wire logic clk,
input wire logic rst,
/*
* SERDES interface
*/
input wire logic [HDR_W-1:0] serdes_rx_hdr,
output wire logic serdes_rx_reset_req,
/*
* Monitor inputs
*/
input wire logic rx_bad_block,
input wire logic rx_sequence_error,
input wire logic rx_block_lock,
input wire logic rx_high_ber,
/*
* Status
*/
output wire logic rx_status
);
// check configuration
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
localparam COUNT_W = $clog2($rtoi(COUNT_125US)+1);
localparam logic [COUNT_W-1:0] COUNT_125US_INT = COUNT_W'($rtoi(COUNT_125US));
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
logic [COUNT_W-1:0] time_count_reg = '0, time_count_next;
logic [3:0] error_count_reg = '0, error_count_next;
logic [3:0] status_count_reg = '0, status_count_next;
logic saw_ctrl_sh_reg = 1'b0, saw_ctrl_sh_next;
logic [9:0] block_error_count_reg = '0, block_error_count_next;
logic serdes_rx_reset_req_reg = 1'b0, serdes_rx_reset_req_next;
logic rx_status_reg = 1'b0, rx_status_next;
assign serdes_rx_reset_req = serdes_rx_reset_req_reg;
assign rx_status = rx_status_reg;
always_comb begin
error_count_next = error_count_reg;
status_count_next = status_count_reg;
saw_ctrl_sh_next = saw_ctrl_sh_reg;
block_error_count_next = block_error_count_reg;
serdes_rx_reset_req_next = 1'b0;
rx_status_next = rx_status_reg;
if (rx_block_lock) begin
if (serdes_rx_hdr == SYNC_CTRL) begin
saw_ctrl_sh_next = 1'b1;
end
if ((rx_bad_block || rx_sequence_error) && !(&block_error_count_reg)) begin
block_error_count_next = block_error_count_reg + 1;
end
end else begin
rx_status_next = 1'b0;
status_count_next = '0;
end
if (time_count_reg != 0) begin
time_count_next = time_count_reg-1;
end else begin
time_count_next = COUNT_125US_INT;
if (!saw_ctrl_sh_reg || &block_error_count_reg) begin
error_count_next = error_count_reg + 1;
status_count_next = '0;
end else begin
error_count_next = '0;
if (!(&status_count_reg)) begin
status_count_next = status_count_reg + 1;
end
end
if (&error_count_reg) begin
error_count_next = '0;
serdes_rx_reset_req_next = 1'b1;
end
if (&status_count_reg) begin
rx_status_next = 1'b1;
end
saw_ctrl_sh_next = 1'b0;
block_error_count_next = '0;
end
end
always_ff @(posedge clk) begin
time_count_reg <= time_count_next;
error_count_reg <= error_count_next;
status_count_reg <= status_count_next;
saw_ctrl_sh_reg <= saw_ctrl_sh_next;
block_error_count_reg <= block_error_count_next;
rx_status_reg <= rx_status_next;
if (rst) begin
time_count_reg <= COUNT_125US_INT;
error_count_reg <= '0;
status_count_reg <= '0;
saw_ctrl_sh_reg <= 1'b0;
block_error_count_reg <= '0;
rx_status_reg <= 1'b0;
end
end
always_ff @(posedge clk or posedge rst) begin
if (rst) begin
serdes_rx_reset_req_reg <= 1'b0;
end else begin
serdes_rx_reset_req_reg <= serdes_rx_reset_req_next;
end
end
endmodule
`resetall

3
rtl/eth/taxi_eth_phy_10g_tx.f Normal file
View File

@@ -0,0 +1,3 @@
taxi_eth_phy_10g_tx.sv
taxi_eth_phy_10g_tx_if.f
taxi_xgmii_baser_enc_64.sv

127
rtl/eth/taxi_eth_phy_10g_tx.sv Normal file
View File

@@ -0,0 +1,127 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY TX
*/
module taxi_eth_phy_10g_tx #
(
parameter DATA_W = 64,
parameter CTRL_W = (DATA_W/8),
parameter HDR_W = 2,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
parameter SERDES_PIPELINE = 0
)
(
input wire logic clk,
input wire logic rst,
/*
* XGMII interface
*/
input wire logic [DATA_W-1:0] xgmii_txd,
input wire logic [CTRL_W-1:0] xgmii_txc,
/*
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
/*
* Status
*/
output wire logic tx_bad_block,
/*
* Configuration
*/
input wire logic cfg_tx_prbs31_enable
);
// check configuration
if (DATA_W != 64)
$fatal(0, "Error: Interface width must be 64");
if (CTRL_W * 8 != DATA_W)
$fatal(0, "Error: Interface requires byte (8-bit) granularity");
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
wire [DATA_W-1:0] encoded_tx_data;
wire [HDR_W-1:0] encoded_tx_hdr;
taxi_xgmii_baser_enc_64 #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.HDR_W(HDR_W)
)
xgmii_baser_enc_inst (
.clk(clk),
.rst(rst),
/*
* XGMII interface
*/
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
/*
* 10GBASE-R encoded interface
*/
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
/*
* Status
*/
.tx_bad_block(tx_bad_block)
);
taxi_eth_phy_10g_tx_if #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
.SERDES_PIPELINE(SERDES_PIPELINE)
)
eth_phy_10g_tx_if_inst (
.clk(clk),
.rst(rst),
/*
* 10GBASE-R encoded interface
*/
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
/*
* SERDES interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
/*
* Configuration
*/
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
);
endmodule
`resetall

2
rtl/eth/taxi_eth_phy_10g_tx_if.f Normal file
View File

@@ -0,0 +1,2 @@
taxi_eth_phy_10g_tx_if.sv
../lfsr/taxi_lfsr.sv

154
rtl/eth/taxi_eth_phy_10g_tx_if.sv Normal file
View File

@@ -0,0 +1,154 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY TX IF
*/
module taxi_eth_phy_10g_tx_if #
(
parameter DATA_W = 64,
parameter HDR_W = 2,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
parameter SERDES_PIPELINE = 0
)
(
input wire logic clk,
input wire logic rst,
/*
* 10GBASE-R encoded interface
*/
input wire logic [DATA_W-1:0] encoded_tx_data,
input wire logic [HDR_W-1:0] encoded_tx_hdr,
/*
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
/*
* Configuration
*/
input wire logic cfg_tx_prbs31_enable
);
// check configuration
if (DATA_W != 64)
$fatal(0, "Error: Interface width must be 64");
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
logic [57:0] scrambler_state_reg = '1;
wire [57:0] scrambler_state;
wire [DATA_W-1:0] scrambled_data;
logic [30:0] prbs31_state_reg = 31'h7fffffff;
wire [30:0] prbs31_state;
wire [DATA_W+HDR_W-1:0] prbs31_data;
logic [DATA_W-1:0] serdes_tx_data_reg = '0;
logic [HDR_W-1:0] serdes_tx_hdr_reg = '0;
wire [DATA_W-1:0] serdes_tx_data_int;
wire [HDR_W-1:0] serdes_tx_hdr_int;
if (BIT_REVERSE) begin
for (genvar n = 0; n < DATA_W; n = n + 1) begin
assign serdes_tx_data_int[n] = serdes_tx_data_reg[DATA_W-n-1];
end
for (genvar n = 0; n < HDR_W; n = n + 1) begin
assign serdes_tx_hdr_int[n] = serdes_tx_hdr_reg[HDR_W-n-1];
end
end else begin
assign serdes_tx_data_int = serdes_tx_data_reg;
assign serdes_tx_hdr_int = serdes_tx_hdr_reg;
end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_tx_data_pipe_reg[n] = '0;
serdes_tx_hdr_pipe_reg[n] = '0;
end
always @(posedge clk) begin
serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1];
serdes_tx_hdr_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_int : serdes_tx_hdr_pipe_reg[n-1];
end
end
assign serdes_tx_data = serdes_tx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_hdr = serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1];
end else begin
assign serdes_tx_data = serdes_tx_data_int;
assign serdes_tx_hdr = serdes_tx_hdr_int;
end
taxi_lfsr #(
.LFSR_W(58),
.LFSR_POLY(58'h8000000001),
.LFSR_GALOIS(0),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_W(DATA_W)
)
scrambler_inst (
.data_in(encoded_tx_data),
.state_in(scrambler_state_reg),
.data_out(scrambled_data),
.state_out(scrambler_state)
);
taxi_lfsr #(
.LFSR_W(31),
.LFSR_POLY(31'h10000001),
.LFSR_GALOIS(0),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_W(DATA_W+HDR_W)
)
prbs31_gen_inst (
.data_in('0),
.state_in(prbs31_state_reg),
.data_out(prbs31_data),
.state_out(prbs31_state)
);
always_ff @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
if (PRBS31_EN && cfg_tx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
serdes_tx_data_reg <= ~prbs31_data[DATA_W+HDR_W-1:HDR_W];
serdes_tx_hdr_reg <= ~prbs31_data[HDR_W-1:0];
end else begin
serdes_tx_data_reg <= SCRAMBLER_DISABLE ? encoded_tx_data : scrambled_data;
serdes_tx_hdr_reg <= encoded_tx_hdr;
end
end
endmodule
`resetall