mirror of
https://github.com/fpganinja/taxi.git
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io: Add source-synchronous IO modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
116
rtl/io/taxi_ssio_ddr_in.sv
Normal file
116
rtl/io/taxi_ssio_ddr_in.sv
Normal file
@@ -0,0 +1,116 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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||||
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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||||
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic source synchronous DDR input
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*/
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module taxi_ssio_ddr_in #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "virtex7",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire logic input_clk,
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input wire logic [WIDTH-1:0] input_d,
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output wire logic output_clk,
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output wire logic [WIDTH-1:0] output_q1,
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output wire logic [WIDTH-1:0] output_q2
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);
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wire clk_int;
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wire clk_io;
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if (!SIM && VENDOR == "XILINX") begin
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// Xilinx/AMD device support
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// use Xilinx clocking primitives
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if (FAMILY == "virtex6" || FAMILY == "virtex7" || FAMILY == "kintex7" || FAMILY == "artix7") begin
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// BUFIO + BUFR
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// virtex6, virtex7, kintex7, artix7, zynq
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assign clk_int = input_clk;
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// pass through RX clock to input buffers
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BUFIO
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clk_bufio (
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.I(clk_int),
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.O(clk_io)
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);
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// pass through RX clock to logic
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BUFR #(
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.BUFR_DIVIDE("BYPASS")
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)
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clk_bufr (
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.I(clk_int),
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.O(output_clk),
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.CE(1'b1),
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.CLR(1'b0)
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);
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end else begin
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// BUFG only
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// spartan6, virtexu, kintexu, virtexuplus, virtexuplusHBM, virtexuplus58g, kintexuplus, zynquplus, zynquplusRFSOC
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// buffer RX clock
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BUFG
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clk_bufg (
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.I(input_clk),
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.O(clk_int)
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);
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// pass through RX clock to logic and input buffers
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assign clk_io = clk_int;
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assign output_clk = clk_int;
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end
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end else begin
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// generic/simulation implementation (no vendor primitives)
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// pass through RX clock to input buffers
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assign clk_io = input_clk;
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// pass through RX clock to logic
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assign clk_int = input_clk;
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assign output_clk = clk_int;
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end
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taxi_iddr #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.WIDTH(WIDTH)
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)
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data_iddr_inst (
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.clk(clk_io),
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.d(input_d),
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.q1(output_q1),
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.q2(output_q2)
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);
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endmodule
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`resetall
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107
rtl/io/taxi_ssio_ddr_in_diff.sv
Normal file
107
rtl/io/taxi_ssio_ddr_in_diff.sv
Normal file
@@ -0,0 +1,107 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic source synchronous DDR input
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*/
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module taxi_ssio_ddr_in_diff #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "virtex7",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire logic input_clk_p,
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input wire logic input_clk_n,
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input wire logic [WIDTH-1:0] input_d_p,
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input wire logic [WIDTH-1:0] input_d_n,
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output wire logic output_clk,
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output wire logic [WIDTH-1:0] output_q1,
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output wire logic [WIDTH-1:0] output_q2
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);
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wire input_clk;
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wire [WIDTH-1:0] input_d;
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if (!SIM && VENDOR == "XILINX") begin
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// Xilinx/AMD device support
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IBUFDS
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clk_ibufds_inst (
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.I(input_clk_p),
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.IB(input_clk_n),
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.O(input_clk)
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);
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for (genvar n = 0; n < WIDTH; n = n + 1) begin
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IBUFDS
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data_ibufds_inst (
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.I(input_d_p[n]),
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.IB(input_d_n[n]),
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.O(input_d[n])
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);
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end
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end else if (!SIM && VENDOR == "ALTERA") begin
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// Altera/Intel/Altera device support
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ALT_INBUF_DIFF
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clk_inbuf_diff_inst (
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.i(input_clk_p),
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.ibar(input_clk_n),
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.o(input_clk)
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);
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for (genvar n = 0; n < WIDTH; n = n + 1) begin
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ALT_INBUF_DIFF
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data_inbuf_diff_inst (
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.i(input_d_p[n]),
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.ibar(input_d_n[n]),
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.o(input_d[n])
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);
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end
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end else begin
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// generic/simulation implementation (no vendor primitives)
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assign input_clk = input_clk_p;
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assign input_d = input_d_p;
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end
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taxi_ssio_ddr_in #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.WIDTH(WIDTH)
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)
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ssio_ddr_in_inst(
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.input_clk(input_clk),
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.input_d(input_d),
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.output_clk(output_clk),
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.output_q1(output_q1),
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.output_q2(output_q2)
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);
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endmodule
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`resetall
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72
rtl/io/taxi_ssio_ddr_out.sv
Normal file
72
rtl/io/taxi_ssio_ddr_out.sv
Normal file
@@ -0,0 +1,72 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
|
||||
|
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Copyright (c) 2016-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
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- Alex Forencich
|
||||
|
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*/
|
||||
|
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`resetall
|
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`timescale 1ns / 1ps
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`default_nettype none
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|
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/*
|
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* Generic source synchronous DDR output
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*/
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module taxi_ssio_ddr_out #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "virtex7",
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// Use 90 degree clock for transmit
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parameter logic USE_CLK90 = 1'b1,
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire logic clk,
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input wire logic clk90,
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input wire logic [WIDTH-1:0] input_d1,
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input wire logic [WIDTH-1:0] input_d2,
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output wire logic output_clk,
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output wire logic [WIDTH-1:0] output_q
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);
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wire ref_clk = USE_CLK90 ? clk90 : clk;
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taxi_oddr #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.WIDTH(1)
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)
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clk_oddr_inst (
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.clk(ref_clk),
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.d1(1'b1),
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.d2(1'b0),
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.q(output_clk)
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);
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taxi_oddr #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.WIDTH(WIDTH)
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)
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data_oddr_inst (
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.clk(clk),
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.d1(input_d1),
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.d2(input_d2),
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.q(output_q)
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);
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endmodule
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`resetall
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113
rtl/io/taxi_ssio_ddr_out_diff.sv
Normal file
113
rtl/io/taxi_ssio_ddr_out_diff.sv
Normal file
@@ -0,0 +1,113 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
|
||||
|
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Copyright (c) 2016-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Generic source synchronous DDR output
|
||||
*/
|
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module taxi_ssio_ddr_out_diff #
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(
|
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// simulation (set to avoid vendor primitives)
|
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
|
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// device family
|
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parameter FAMILY = "virtex7",
|
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// Use 90 degree clock for transmit
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parameter logic USE_CLK90 = 1'b1,
|
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// Width of register in bits
|
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parameter WIDTH = 1
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)
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(
|
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input wire logic clk,
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input wire logic clk90,
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input wire logic [WIDTH-1:0] input_d1,
|
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input wire logic [WIDTH-1:0] input_d2,
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output wire logic output_clk_p,
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output wire logic output_clk_n,
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output wire logic [WIDTH-1:0] output_q_p,
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output wire logic [WIDTH-1:0] output_q_n
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);
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wire output_clk;
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wire [WIDTH-1:0] output_q;
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taxi_ssio_ddr_out #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.USE_CLK90(USE_CLK90),
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.WIDTH(WIDTH)
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)
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ssio_ddr_out_inst(
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.clk(clk),
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.clk90(clk90),
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.input_d1(input_d1),
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.input_d2(input_d2),
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.output_clk(output_clk),
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.output_q(output_q)
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);
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if (!SIM && VENDOR == "XILINX") begin
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// Xilinx/AMD device support
|
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|
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OBUFDS
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clk_obufds_inst (
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.I(output_clk),
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.O(output_clk_p),
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.OB(output_clk_n)
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);
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for (genvar n = 0; n < WIDTH; n = n + 1) begin
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OBUFDS
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data_obufds_inst (
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.I(output_q[n]),
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.O(output_q_p[n]),
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.OB(output_q_n[n])
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);
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end
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end else if (!SIM && VENDOR == "ALTERA") begin
|
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// Altera/Intel/Altera device support
|
||||
|
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ALT_OUTBUF_DIFF
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clk_outbuf_diff_inst (
|
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.i(output_clk),
|
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.o(output_clk_p),
|
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.obar(output_clk_n)
|
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);
|
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|
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for (genvar n = 0; n < WIDTH; n = n + 1) begin
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ALT_OUTBUF_DIFF
|
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data_outbuf_diff_inst (
|
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.i(output_q[n]),
|
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.o(output_q_p[n]),
|
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.obar(output_q_n[n])
|
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);
|
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end
|
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|
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end else begin
|
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// generic/simulation implementation (no vendor primitives)
|
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|
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assign output_clk_p = output_clk;
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assign output_clk_n = ~output_clk;
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assign output_q_p = output_q;
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assign output_q_n = ~output_q;
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|
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end
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|
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endmodule
|
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|
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`resetall
|
||||
134
rtl/io/taxi_ssio_sdr_in.sv
Normal file
134
rtl/io/taxi_ssio_sdr_in.sv
Normal file
@@ -0,0 +1,134 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2016-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Generic source synchronous SDR input
|
||||
*/
|
||||
module taxi_ssio_sdr_in #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter FAMILY = "virtex7",
|
||||
// Width of register in bits
|
||||
parameter WIDTH = 1
|
||||
)
|
||||
(
|
||||
input wire logic input_clk,
|
||||
|
||||
input wire logic [WIDTH-1:0] input_d,
|
||||
|
||||
output wire logic output_clk,
|
||||
|
||||
output wire logic [WIDTH-1:0] output_q
|
||||
);
|
||||
|
||||
wire clk_int;
|
||||
wire clk_io;
|
||||
|
||||
if (!SIM && VENDOR == "XILINX") begin
|
||||
// Xilinx/AMD device support
|
||||
|
||||
if (FAMILY == "virtex6" || FAMILY == "virtex7" || FAMILY == "kintex7" || FAMILY == "artix7") begin
|
||||
// BUFIO + BUFR
|
||||
// virtex6, virtex7, kintex7, artix7, zynq
|
||||
|
||||
assign clk_int = input_clk;
|
||||
|
||||
// pass through RX clock to input buffers
|
||||
BUFIO
|
||||
clk_bufio (
|
||||
.I(clk_int),
|
||||
.O(clk_io)
|
||||
);
|
||||
|
||||
// pass through RX clock to logic
|
||||
BUFR #(
|
||||
.BUFR_DIVIDE("BYPASS")
|
||||
)
|
||||
clk_bufr (
|
||||
.I(clk_int),
|
||||
.O(output_clk),
|
||||
.CE(1'b1),
|
||||
.CLR(1'b0)
|
||||
);
|
||||
|
||||
end else if (FAMILY == "spartan6") begin
|
||||
// BUFIO2 + BUFG
|
||||
// spartan6
|
||||
|
||||
// pass through RX clock to input buffers
|
||||
BUFIO2 #(
|
||||
.DIVIDE(1),
|
||||
.DIVIDE_BYPASS("TRUE"),
|
||||
.I_INVERT("FALSE"),
|
||||
.USE_DOUBLER("FALSE")
|
||||
)
|
||||
clk_bufio (
|
||||
.I(input_clk),
|
||||
.DIVCLK(clk_int),
|
||||
.IOCLK(clk_io),
|
||||
.SERDESSTROBE()
|
||||
);
|
||||
|
||||
// pass through RX clock to MAC
|
||||
BUFG
|
||||
clk_bufg (
|
||||
.I(clk_int),
|
||||
.O(output_clk)
|
||||
);
|
||||
|
||||
end else begin
|
||||
// BUFG only
|
||||
// virtexu, kintexu, virtexuplus, virtexuplusHBM, virtexuplus58g, kintexuplus, zynquplus, zynquplusRFSOC
|
||||
|
||||
// buffer RX clock
|
||||
BUFG
|
||||
clk_bufg (
|
||||
.I(input_clk),
|
||||
.O(clk_int)
|
||||
);
|
||||
|
||||
// pass through RX clock to logic and input buffers
|
||||
assign clk_io = clk_int;
|
||||
assign output_clk = clk_int;
|
||||
|
||||
end
|
||||
|
||||
end else begin
|
||||
// generic/simulation implementation (no vendor primitives)
|
||||
|
||||
// pass through RX clock to input buffers
|
||||
assign clk_io = input_clk;
|
||||
|
||||
// pass through RX clock to logic
|
||||
assign clk_int = input_clk;
|
||||
assign output_clk = clk_int;
|
||||
|
||||
end
|
||||
|
||||
(* IOB = "TRUE" *)
|
||||
logic [WIDTH-1:0] output_q_reg = '0;
|
||||
|
||||
assign output_q = output_q_reg;
|
||||
|
||||
always_ff @(posedge clk_io) begin
|
||||
output_q_reg <= input_d;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
105
rtl/io/taxi_ssio_sdr_in_diff.sv
Normal file
105
rtl/io/taxi_ssio_sdr_in_diff.sv
Normal file
@@ -0,0 +1,105 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2016-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Generic source synchronous SDR input
|
||||
*/
|
||||
module ssio_sdr_in_diff #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter FAMILY = "virtex7",
|
||||
// Width of register in bits
|
||||
parameter WIDTH = 1
|
||||
)
|
||||
(
|
||||
input wire logic input_clk_p,
|
||||
input wire logic input_clk_n,
|
||||
|
||||
input wire logic [WIDTH-1:0] input_d_p,
|
||||
input wire logic [WIDTH-1:0] input_d_n,
|
||||
|
||||
output wire logic output_clk,
|
||||
|
||||
output wire logic [WIDTH-1:0] output_q
|
||||
);
|
||||
|
||||
wire input_clk;
|
||||
wire [WIDTH-1:0] input_d;
|
||||
|
||||
if (!SIM && VENDOR == "XILINX") begin
|
||||
// Xilinx/AMD device support
|
||||
|
||||
IBUFDS
|
||||
clk_ibufds_inst (
|
||||
.I(input_clk_p),
|
||||
.IB(input_clk_n),
|
||||
.O(input_clk)
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < WIDTH; n = n + 1) begin
|
||||
IBUFDS
|
||||
data_ibufds_inst (
|
||||
.I(input_d_p[n]),
|
||||
.IB(input_d_n[n]),
|
||||
.O(input_d[n])
|
||||
);
|
||||
end
|
||||
|
||||
end else if (!SIM && VENDOR == "ALTERA") begin
|
||||
// Altera/Intel/Altera device support
|
||||
|
||||
ALT_INBUF_DIFF
|
||||
clk_inbuf_diff_inst (
|
||||
.i(input_clk_p),
|
||||
.ibar(input_clk_n),
|
||||
.o(input_clk)
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < WIDTH; n = n + 1) begin
|
||||
ALT_INBUF_DIFF
|
||||
data_inbuf_diff_inst (
|
||||
.i(input_d_p[n]),
|
||||
.ibar(input_d_n[n]),
|
||||
.o(input_d[n])
|
||||
);
|
||||
end
|
||||
|
||||
end else begin
|
||||
// generic/simulation implementation (no vendor primitives)
|
||||
|
||||
assign input_clk = input_clk_p;
|
||||
assign input_d = input_d_p;
|
||||
|
||||
end
|
||||
|
||||
taxi_ssio_sdr_in #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.WIDTH(WIDTH)
|
||||
)
|
||||
ssio_ddr_in_inst(
|
||||
.input_clk(input_clk),
|
||||
.input_d(input_d),
|
||||
.output_clk(output_clk),
|
||||
.output_q(output_q)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
rtl/io/taxi_ssio_sdr_out.sv
Normal file
62
rtl/io/taxi_ssio_sdr_out.sv
Normal file
@@ -0,0 +1,62 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2016-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Generic source synchronous SDR output
|
||||
*/
|
||||
module taxi_ssio_sdr_out #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter FAMILY = "virtex7",
|
||||
// Width of register in bits
|
||||
parameter WIDTH = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
|
||||
input wire logic [WIDTH-1:0] input_d,
|
||||
|
||||
output wire logic output_clk,
|
||||
output wire logic [WIDTH-1:0] output_q
|
||||
);
|
||||
|
||||
taxi_oddr #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.WIDTH(1)
|
||||
)
|
||||
clk_oddr_inst (
|
||||
.clk(clk),
|
||||
.d1(1'b0),
|
||||
.d2(1'b1),
|
||||
.q(output_clk)
|
||||
);
|
||||
|
||||
(* IOB = "TRUE" *)
|
||||
logic [WIDTH-1:0] output_q_reg = '0;
|
||||
|
||||
assign output_q = output_q_reg;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
output_q_reg <= input_d;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
106
rtl/io/taxi_ssio_sdr_out_diff.sv
Normal file
106
rtl/io/taxi_ssio_sdr_out_diff.sv
Normal file
@@ -0,0 +1,106 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2016-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Generic source synchronous SDR output
|
||||
*/
|
||||
module taxi_ssio_sdr_out_diff #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter FAMILY = "virtex7",
|
||||
// Width of register in bits
|
||||
parameter WIDTH = 1
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
|
||||
input wire logic [WIDTH-1:0] input_d,
|
||||
|
||||
output wire logic output_clk_p,
|
||||
output wire logic output_clk_n,
|
||||
output wire logic [WIDTH-1:0] output_q_p,
|
||||
output wire logic [WIDTH-1:0] output_q_n
|
||||
);
|
||||
|
||||
wire output_clk;
|
||||
wire [WIDTH-1:0] output_q;
|
||||
|
||||
taxi_ssio_sdr_out #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.WIDTH(WIDTH)
|
||||
)
|
||||
ssio_ddr_out_inst(
|
||||
.clk(clk),
|
||||
.input_d(input_d),
|
||||
.output_clk(output_clk),
|
||||
.output_q(output_q)
|
||||
);
|
||||
|
||||
if (!SIM && VENDOR == "XILINX") begin
|
||||
// Xilinx/AMD device support
|
||||
|
||||
OBUFDS
|
||||
clk_obufds_inst (
|
||||
.I(output_clk),
|
||||
.O(output_clk_p),
|
||||
.OB(output_clk_n)
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < WIDTH; n = n + 1) begin
|
||||
OBUFDS
|
||||
data_obufds_inst (
|
||||
.I(output_q[n]),
|
||||
.O(output_q_p[n]),
|
||||
.OB(output_q_n[n])
|
||||
);
|
||||
end
|
||||
|
||||
end else if (!SIM && VENDOR == "ALTERA") begin
|
||||
// Altera/Intel/Altera device support
|
||||
|
||||
ALT_OUTBUF_DIFF
|
||||
clk_outbuf_diff_inst (
|
||||
.i(output_clk),
|
||||
.o(output_clk_p),
|
||||
.obar(output_clk_n)
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < WIDTH; n = n + 1) begin
|
||||
ALT_OUTBUF_DIFF
|
||||
data_outbuf_diff_inst (
|
||||
.i(output_q[n]),
|
||||
.o(output_q_p[n]),
|
||||
.obar(output_q_n[n])
|
||||
);
|
||||
end
|
||||
|
||||
end else begin
|
||||
// generic/simulation implementation (no vendor primitives)
|
||||
|
||||
assign output_clk_p = output_clk;
|
||||
assign output_clk_n = ~output_clk;
|
||||
assign output_q_p = output_q;
|
||||
assign output_q_n = ~output_q;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user