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apb: Remove extra idle cycles

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-12 15:35:03 -07:00
parent d799cddaa5
commit f5b7eb272d
5 changed files with 9 additions and 9 deletions
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4
src/apb/rtl/taxi_apb_adapter.sv
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@@ -162,7 +162,7 @@ end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
m_apb_pauser_next = s_apb.pauser;
m_apb_pwuser_next = s_apb.pwuser;
if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
if (s_apb.psel && !s_apb.pready) begin
m_apb_psel_next = 1'b1;
state_next = STATE_DATA;
end else begin
@@ -317,7 +317,7 @@ end else begin : downsize
s_apb_pslverr_next = 1'b0;
if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
if (s_apb.psel && !s_apb.pready) begin
m_apb_psel_next = 1'b1;
state_next = STATE_DATA;
end else begin

6
src/apb/rtl/taxi_apb_axil_adapter.sv
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@@ -168,7 +168,7 @@ if (AXIL_BYTE_LANES == APB_BYTE_LANES) begin : bypass
m_axil_auser_next = s_apb.pauser;
m_axil_wuser_next = s_apb.pwuser;
if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
if (s_apb.psel && !s_apb.pready) begin
if (s_apb.pwrite) begin
m_axil_awvalid_next = 1'b1;
m_axil_wvalid_next = 1'b1;
@@ -322,7 +322,7 @@ end else if (AXIL_BYTE_LANES > APB_BYTE_LANES) begin : upsize
m_axil_auser_next = s_apb.pauser;
m_axil_wuser_next = s_apb.pwuser;
if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
if (s_apb.psel && !s_apb.pready) begin
if (s_apb.pwrite) begin
m_axil_awvalid_next = 1'b1;
m_axil_wvalid_next = 1'b1;
@@ -501,7 +501,7 @@ end else begin : downsize
s_apb_pslverr_next = 1'b0;
if (s_apb.psel && s_apb.penable && !s_apb.pready) begin
if (s_apb.psel && !s_apb.pready) begin
if (s_apb.pwrite) begin
m_axil_awvalid_next = 1'b1;
m_axil_wvalid_next = 1'b1;

4
src/apb/rtl/taxi_apb_dp_ram.sv
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@@ -101,7 +101,7 @@ always_comb begin
s_apb_a_pready_next = 1'b0;
if (s_apb_a.psel && s_apb_a.penable && (!s_apb_a_pready_reg && (PIPELINE_OUTPUT || !s_apb_a_pready_pipe_reg))) begin
if (s_apb_a.psel && (!s_apb_a_pready_reg && (PIPELINE_OUTPUT || !s_apb_a_pready_pipe_reg))) begin
s_apb_a_pready_next = 1'b1;
if (s_apb_a.pwrite) begin
@@ -139,7 +139,7 @@ always_comb begin
s_apb_b_pready_next = 1'b0;
if (s_apb_b.psel && s_apb_b.penable && (!s_apb_b_pready_reg && (PIPELINE_OUTPUT || !s_apb_b_pready_pipe_reg))) begin
if (s_apb_b.psel && (!s_apb_b_pready_reg && (PIPELINE_OUTPUT || !s_apb_b_pready_pipe_reg))) begin
s_apb_b_pready_next = 1'b1;
if (s_apb_b.pwrite) begin

2
src/apb/rtl/taxi_apb_interconnect.sv
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@@ -249,7 +249,7 @@ always_ff @(posedge clk) begin
m_apb_psel_reg <= '0;
m_apb_penable_reg <= 1'b0;
if (s_apb.psel && s_apb.penable && !s_apb_pready_reg) begin
if (s_apb.psel && !s_apb_pready_reg) begin
act_reg <= 1'b1;
for (integer i = 0; i < M_CNT; i = i + 1) begin
for (integer j = 0; j < M_REGIONS; j = j + 1) begin

2
src/apb/rtl/taxi_apb_ram.sv
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@@ -75,7 +75,7 @@ always_comb begin
s_apb_pready_next = 1'b0;
if (s_apb.psel && s_apb.penable && (!s_apb_pready_reg && (PIPELINE_OUTPUT || !s_apb_pready_pipe_reg))) begin
if (s_apb.psel && (!s_apb_pready_reg && (PIPELINE_OUTPUT || !s_apb_pready_pipe_reg))) begin
s_apb_pready_next = 1'b1;
if (s_apb.pwrite) begin