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https://github.com/fpganinja/taxi.git
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stats: Add statistics collector module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
216
rtl/stats/taxi_stats_collect.sv
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216
rtl/stats/taxi_stats_collect.sv
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@@ -0,0 +1,216 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Statistics collector
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*/
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module taxi_stats_collect #
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(
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// Channel count
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parameter CNT = 8,
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// Increment width (bits)
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parameter INC_W = 8,
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// Base statistic ID
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parameter ID_BASE = 0,
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// Statistics counter update period (cycles)
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parameter UPDATE_PERIOD = 1024
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* Increment inputs
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*/
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input wire logic [INC_W-1:0] stat_inc[CNT],
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input wire logic stat_valid[CNT],
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/*
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* Statistics increment output
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*/
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taxi_axis_if.src m_axis_stat,
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/*
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* Control inputs
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*/
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input wire logic update
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);
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localparam STAT_INC_W = m_axis_stat.DATA_W;
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localparam STAT_ID_W = m_axis_stat.ID_W;
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localparam CNT_W = $clog2(CNT);
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localparam PERIOD_CNT_W = $clog2(UPDATE_PERIOD+1);
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localparam ACC_W = INC_W+CNT_W+1;
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localparam [0:0]
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STATE_READ = 1'd0,
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STATE_WRITE = 1'd1;
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logic [0:0] state_reg = STATE_READ, state_next;
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logic [STAT_INC_W-1:0] m_axis_stat_tdata_reg = '0, m_axis_stat_tdata_next;
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logic [STAT_ID_W-1:0] m_axis_stat_tid_reg = '0, m_axis_stat_tid_next;
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logic m_axis_stat_tvalid_reg = 0, m_axis_stat_tvalid_next;
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logic [CNT_W-1:0] count_reg = '0, count_next;
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logic [PERIOD_CNT_W-1:0] update_period_reg = PERIOD_CNT_W'(UPDATE_PERIOD), update_period_next;
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logic [CNT-1:0] zero_reg = '1, zero_next;
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logic [CNT-1:0] update_reg = '0, update_next;
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wire [ACC_W-1:0] acc_int[CNT];
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logic [CNT-1:0] acc_clear;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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logic [STAT_INC_W-1:0] mem_reg[CNT];
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logic [STAT_INC_W-1:0] mem_rd_data_reg = '0;
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logic mem_rd_en;
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logic mem_wr_en;
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logic [STAT_INC_W-1:0] mem_wr_data;
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assign m_axis_stat.tdata = m_axis_stat_tdata_reg;
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assign m_axis_stat.tkeep = 1'b1;
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assign m_axis_stat.tstrb = m_axis_stat.tkeep;
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assign m_axis_stat.tvalid = m_axis_stat_tvalid_reg;
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assign m_axis_stat.tlast = 1'b1;
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assign m_axis_stat.tid = m_axis_stat_tid_reg;
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assign m_axis_stat.tdest = '0;
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assign m_axis_stat.tuser = '0;
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for (genvar n = 0; n < CNT; n = n + 1) begin
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reg [ACC_W-1:0] acc_reg = '0;
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assign acc_int[n] = acc_reg;
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always_ff @(posedge clk) begin
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if (acc_clear[n]) begin
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if (stat_valid[n]) begin
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acc_reg <= ACC_W'(stat_inc[n]);
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end else begin
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acc_reg <= '0;
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end
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end else begin
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if (stat_valid[n]) begin
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acc_reg <= acc_reg + ACC_W'(stat_inc[n]);
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end
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end
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if (rst) begin
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acc_reg <= '0;
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end
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end
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end
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always_comb begin
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state_next = STATE_READ;
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m_axis_stat_tdata_next = m_axis_stat_tdata_reg;
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m_axis_stat_tid_next = m_axis_stat_tid_reg;
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m_axis_stat_tvalid_next = m_axis_stat_tvalid_reg && !m_axis_stat.tready;
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count_next = count_reg;
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update_period_next = update_period_reg;
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zero_next = zero_reg;
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update_next = update_reg;
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acc_clear = '0;
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mem_rd_en = 1'b0;
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mem_wr_en = 1'b0;
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mem_wr_data = '0;
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case (state_reg)
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STATE_READ: begin
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mem_rd_en = 1'b1;
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state_next = STATE_WRITE;
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end
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STATE_WRITE: begin
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mem_wr_en = 1'b1;
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acc_clear[count_reg] = 1'b1;
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if (!m_axis_stat_tvalid_reg && update_reg[count_reg]) begin
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update_next[count_reg] = 1'b0;
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mem_wr_data = '0;
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if (zero_reg[count_reg]) begin
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m_axis_stat_tdata_next = STAT_INC_W'(acc_int[count_reg]);
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m_axis_stat_tid_next = STAT_ID_W'(count_reg+ID_BASE);
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m_axis_stat_tvalid_next = acc_int[count_reg] != 0;
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end else begin
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m_axis_stat_tdata_next = STAT_INC_W'(mem_rd_data_reg + acc_int[count_reg]);
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m_axis_stat_tid_next = STAT_ID_W'(count_reg+ID_BASE);
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m_axis_stat_tvalid_next = mem_rd_data_reg != 0 || acc_int[count_reg] != 0;
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end
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end else begin
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if (zero_reg[count_reg]) begin
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mem_wr_data = STAT_INC_W'(acc_int[count_reg]);
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end else begin
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mem_wr_data = mem_rd_data_reg + STAT_INC_W'(acc_int[count_reg]);
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end
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end
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zero_next[count_reg] = 1'b0;
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if (count_reg == CNT_W'(CNT-1)) begin
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count_next = '0;
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end else begin
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count_next = count_reg + 1;
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end
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state_next = STATE_READ;
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end
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endcase
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if (update_period_reg == 0) begin
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update_next = '1;
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update_period_next = PERIOD_CNT_W'(UPDATE_PERIOD);
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end else begin
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update_period_next = update_period_reg - 1;
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end
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if (update) begin
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update_next = '1;
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end
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end
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always_ff @(posedge clk) begin
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state_reg <= state_next;
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m_axis_stat_tdata_reg <= m_axis_stat_tdata_next;
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m_axis_stat_tid_reg <= m_axis_stat_tid_next;
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m_axis_stat_tvalid_reg <= m_axis_stat_tvalid_next;
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count_reg <= count_next;
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update_period_reg <= update_period_next;
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zero_reg <= zero_next;
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update_reg <= update_next;
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if (mem_wr_en) begin
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mem_reg[count_reg] <= mem_wr_data;
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end else if (mem_rd_en) begin
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mem_rd_data_reg <= mem_reg[count_reg];
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end
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if (rst) begin
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state_reg <= STATE_READ;
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m_axis_stat_tvalid_reg <= 1'b0;
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count_reg <= '0;
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update_period_reg <= PERIOD_CNT_W'(UPDATE_PERIOD);
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zero_reg <= '1;
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update_reg <= '0;
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end
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end
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endmodule
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`resetall
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52
tb/stats/taxi_stats_collect/Makefile
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52
tb/stats/taxi_stats_collect/Makefile
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@@ -0,0 +1,52 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2021-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = taxi_stats_collect
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += ../../../rtl/stats/$(DUT).sv
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VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_CNT := 8
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export PARAM_INC_W := 8
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export PARAM_ID_BASE := 0
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export PARAM_UPDATE_PERIOD := 128
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export PARAM_STAT_INC_W := 16
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export PARAM_STAT_ID_W := $(shell python -c "print(($(PARAM_CNT)-1).bit_length())")
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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249
tb/stats/taxi_stats_collect/test_taxi_stats_collect.py
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249
tb/stats/taxi_stats_collect/test_taxi_stats_collect.py
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@@ -0,0 +1,249 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import random
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.queue import Queue
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from cocotb.triggers import RisingEdge, Timer
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiStreamBus, AxiStreamSink
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.clk, dut.rst)
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for k in range(len(dut.stat_inc)):
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dut.stat_inc[k].setimmediatevalue(0)
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dut.stat_valid[k].setimmediatevalue(0)
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dut.update.setimmediatevalue(0)
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.stat_sink.set_pause_generator(generator())
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async def cycle_reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test_acc(dut, backpressure_inserter=None):
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tb = TB(dut)
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stat_count = len(dut.stat_valid)
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await tb.cycle_reset()
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tb.set_backpressure_generator(backpressure_inserter)
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for n in range(10):
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await RisingEdge(dut.clk)
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dut.stat_inc.value = [k for k in range(stat_count)]
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dut.stat_valid.value = [1]*stat_count
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await RisingEdge(dut.clk)
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dut.stat_inc.value = [0]*stat_count
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dut.stat_valid.value = [0]*stat_count
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await Timer(1000, 'ns')
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await Timer(1000, 'ns')
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data = [0]*stat_count
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while not tb.stat_sink.empty():
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stat = await tb.stat_sink.recv()
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assert stat.tdata[0] != 0
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data[stat.tid] += stat.tdata[0]
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print(data)
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for n in range(stat_count):
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assert data[n] == n*10
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_stress_test(dut, backpressure_inserter=None):
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tb = TB(dut)
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stat_count = len(dut.stat_valid)
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stat_inc_width = len(dut.stat_inc) // stat_count
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await tb.cycle_reset()
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tb.set_backpressure_generator(backpressure_inserter)
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async def worker(num, queue_ref, queue_drive, count=1024):
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for k in range(count):
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count = random.randrange(1, 2**stat_inc_width)
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await queue_drive.put(count)
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await queue_ref.put((num, count))
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await Timer(random.randint(1, 100), 'ns')
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workers = []
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queue_ref = Queue()
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queue_drive = [Queue() for k in range(stat_count)]
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for k in range(stat_count):
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workers.append(cocotb.start_soon(worker(k, queue_ref, queue_drive[k], count=1024)))
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async def driver(dut, queues):
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while True:
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await RisingEdge(dut.clk)
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inc = [0]*stat_count
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valid = [0]*stat_count
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for num, queue in enumerate(queues):
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if not queue.empty():
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count = await queue.get()
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inc[num] += count
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valid[num] = 1
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dut.stat_inc.value = inc
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dut.stat_valid.value = valid
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driver = cocotb.start_soon(driver(dut, queue_drive))
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while workers:
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await workers.pop(0).join()
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await Timer(1000, 'ns')
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driver.kill()
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await Timer(1000, 'ns')
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data_ref = [0]*stat_count
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while not queue_ref.empty():
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num, count = await queue_ref.get()
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data_ref[num] += count
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print(data_ref)
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data = [0]*stat_count
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while not tb.stat_sink.empty():
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stat = await tb.stat_sink.recv()
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assert stat.tdata[0] != 0
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data[stat.tid] += stat.tdata[0]
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print(data)
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assert data == data_ref
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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if cocotb.SIM_NAME:
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for test in [run_test_acc]:
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factory = TestFactory(test)
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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factory = TestFactory(run_stress_test)
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.dirname(__file__)
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
|
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|
||||
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def process_f_files(files):
|
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
|
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_taxi_stats_collect(request):
|
||||
dut = "taxi_stats_collect"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, "stats", f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['CNT'] = 8
|
||||
parameters['INC_W'] = 8
|
||||
parameters['ID_BASE'] = 0
|
||||
parameters['UPDATE_PERIOD'] = 128
|
||||
parameters['STAT_INC_W'] = 16
|
||||
parameters['STAT_ID_W'] = (parameters['CNT']-1).bit_length()
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
76
tb/stats/taxi_stats_collect/test_taxi_stats_collect.sv
Normal file
76
tb/stats/taxi_stats_collect/test_taxi_stats_collect.sv
Normal file
@@ -0,0 +1,76 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Statistics collector testbench
|
||||
*/
|
||||
module test_taxi_stats_collect #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter CNT = 8,
|
||||
parameter INC_W = 8,
|
||||
parameter ID_BASE = 0,
|
||||
parameter UPDATE_PERIOD = 128,
|
||||
parameter STAT_INC_W = 16,
|
||||
parameter STAT_ID_W = $clog2(CNT)
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
logic [INC_W-1:0] stat_inc[CNT];
|
||||
logic [0:0] stat_valid[CNT];
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(STAT_INC_W),
|
||||
.KEEP_EN(0),
|
||||
.KEEP_W(1),
|
||||
.ID_EN(1),
|
||||
.ID_W(STAT_ID_W)
|
||||
) m_axis_stat();
|
||||
|
||||
logic update;
|
||||
|
||||
taxi_stats_collect #(
|
||||
.CNT(CNT),
|
||||
.INC_W(INC_W),
|
||||
.ID_BASE(ID_BASE),
|
||||
.UPDATE_PERIOD(UPDATE_PERIOD)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* Increment inputs
|
||||
*/
|
||||
.stat_inc(stat_inc),
|
||||
.stat_valid(stat_valid),
|
||||
|
||||
/*
|
||||
* Statistics increment output
|
||||
*/
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Control inputs
|
||||
*/
|
||||
.update(update)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user