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eth: Avoid hardcoding clock period

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-06-17 20:15:50 -07:00
parent 295dc2dd23
commit fd521a1511
1 changed files with 2 additions and 2 deletions
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4
src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py
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@@ -144,7 +144,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
if tx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
tx_frame_sfd_ns -= 3.2
tx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
@@ -153,7 +153,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
assert rx_frame.tdata == test_data
assert frame_error == 0
if gbx_cfg is None:
assert abs(ptp_ts_ns - tx_frame_sfd_ns - 6.4) < 0.01
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period) < 0.01
assert tb.sink.empty()