Alex Forencich
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44c811f82a
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lss: Add I2C master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 10:41:16 -07:00 |
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Alex Forencich
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ebeadee172
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lss: Implement fractional baud rate generation for UART
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-11 23:49:39 -07:00 |
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Alex Forencich
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1c686391ab
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lss: Refactor UART module to split out and share baud rate generation logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-11 23:09:19 -07:00 |
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Alex Forencich
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024353c68a
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lss: Add MDIO master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-06 23:48:57 -08:00 |
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Alex Forencich
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c6cbb57fe7
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lss: Extract UART data width setting from interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 14:15:42 -08:00 |
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Alex Forencich
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c4558a02f0
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lss: Add UART module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 15:02:48 -08:00 |
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